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target-xtensa: implement memory protection options
[qemu.git] / target-xtensa / translate.c
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2328826b
MF		 1/*
2 * Xtensa ISA:
3 * http://www.tensilica.com/products/literature-docs/documentation/xtensa-isa-databook.htm
4 *
5 * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions are met:
10 * * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * * Neither the name of the Open Source and Linux Lab nor the
16 * names of its contributors may be used to endorse or promote products
17 * derived from this software without specific prior written permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
23 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
26 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 */
30
31#include <stdio.h>
32
33#include "cpu.h"
34#include "exec-all.h"
35#include "disas.h"
36#include "tcg-op.h"
37#include "qemu-log.h"
1ddeaa5d 38#include "sysemu.h"
2328826b 39
dedc5eae
MF		 40#include "helpers.h"
41#define GEN_HELPER 1
42#include "helpers.h"
43
44typedef struct DisasContext {
45 const XtensaConfig *config;
46 TranslationBlock *tb;
47 uint32_t pc;
48 uint32_t next_pc;
f0a548b9
MF		 49 int cring;
50 int ring;
797d780b
MF		 51 uint32_t lbeg;
52 uint32_t lend;
6ad6dbf7 53 TCGv_i32 litbase;
dedc5eae
MF		 54 int is_jmp;
55 int singlestep_enabled;
3580ecad
MF		 56
57 bool sar_5bit;
58 bool sar_m32_5bit;
59 bool sar_m32_allocated;
60 TCGv_i32 sar_m32;
b994e91b
MF		 61
62 uint32_t ccount_delta;
772177c1 63 unsigned used_window;
dedc5eae
MF		 64} DisasContext;
65
66static TCGv_ptr cpu_env;
67static TCGv_i32 cpu_pc;
68static TCGv_i32 cpu_R[16];
2af3da91
MF		 69static TCGv_i32 cpu_SR[256];
70static TCGv_i32 cpu_UR[256];
dedc5eae
MF		 71
72#include "gen-icount.h"
2328826b 73
2af3da91 74static const char * const sregnames[256] = {
797d780b
MF		 75 [LBEG] = "LBEG",
76 [LEND] = "LEND",
77 [LCOUNT] = "LCOUNT",
3580ecad 78 [SAR] = "SAR",
6ad6dbf7 79 [LITBASE] = "LITBASE",
809377aa 80 [SCOMPARE1] = "SCOMPARE1",
553e44f9
MF		 81 [WINDOW_BASE] = "WINDOW_BASE",
82 [WINDOW_START] = "WINDOW_START",
b67ea0cd
MF		 83 [PTEVADDR] = "PTEVADDR",
84 [RASID] = "RASID",
85 [ITLBCFG] = "ITLBCFG",
86 [DTLBCFG] = "DTLBCFG",
40643d7c 87 [EPC1] = "EPC1",
b994e91b
MF		 88 [EPC1 + 1] = "EPC2",
89 [EPC1 + 2] = "EPC3",
90 [EPC1 + 3] = "EPC4",
91 [EPC1 + 4] = "EPC5",
92 [EPC1 + 5] = "EPC6",
93 [EPC1 + 6] = "EPC7",
40643d7c 94 [DEPC] = "DEPC",
b994e91b
MF		 95 [EPS2] = "EPS2",
96 [EPS2 + 1] = "EPS3",
97 [EPS2 + 2] = "EPS4",
98 [EPS2 + 3] = "EPS5",
99 [EPS2 + 4] = "EPS6",
100 [EPS2 + 5] = "EPS7",
40643d7c 101 [EXCSAVE1] = "EXCSAVE1",
b994e91b
MF		 102 [EXCSAVE1 + 1] = "EXCSAVE2",
103 [EXCSAVE1 + 2] = "EXCSAVE3",
104 [EXCSAVE1 + 3] = "EXCSAVE4",
105 [EXCSAVE1 + 4] = "EXCSAVE5",
106 [EXCSAVE1 + 5] = "EXCSAVE6",
107 [EXCSAVE1 + 6] = "EXCSAVE7",
f3df4c04 108 [CPENABLE] = "CPENABLE",
b994e91b
MF		 109 [INTSET] = "INTSET",
110 [INTCLEAR] = "INTCLEAR",
111 [INTENABLE] = "INTENABLE",
f0a548b9 112 [PS] = "PS",
97836cee 113 [VECBASE] = "VECBASE",
40643d7c 114 [EXCCAUSE] = "EXCCAUSE",
b994e91b 115 [CCOUNT] = "CCOUNT",
f3df4c04 116 [PRID] = "PRID",
40643d7c 117 [EXCVADDR] = "EXCVADDR",
b994e91b
MF		 118 [CCOMPARE] = "CCOMPARE0",
119 [CCOMPARE + 1] = "CCOMPARE1",
120 [CCOMPARE + 2] = "CCOMPARE2",
2af3da91
MF		 121};
122
123static const char * const uregnames[256] = {
124 [THREADPTR] = "THREADPTR",
125 [FCR] = "FCR",
126 [FSR] = "FSR",
127};
128
2328826b
MF		 129void xtensa_translate_init(void)
130{
dedc5eae
MF		 131 static const char * const regnames[] = {
132 "ar0", "ar1", "ar2", "ar3",
133 "ar4", "ar5", "ar6", "ar7",
134 "ar8", "ar9", "ar10", "ar11",
135 "ar12", "ar13", "ar14", "ar15",
136 };
137 int i;
138
139 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
140 cpu_pc = tcg_global_mem_new_i32(TCG_AREG0,
141 offsetof(CPUState, pc), "pc");
142
143 for (i = 0; i < 16; i++) {
144 cpu_R[i] = tcg_global_mem_new_i32(TCG_AREG0,
145 offsetof(CPUState, regs[i]),
146 regnames[i]);
147 }
2af3da91
MF		 148
149 for (i = 0; i < 256; ++i) {
150 if (sregnames[i]) {
151 cpu_SR[i] = tcg_global_mem_new_i32(TCG_AREG0,
152 offsetof(CPUState, sregs[i]),
153 sregnames[i]);
154 }
155 }
156
157 for (i = 0; i < 256; ++i) {
158 if (uregnames[i]) {
159 cpu_UR[i] = tcg_global_mem_new_i32(TCG_AREG0,
160 offsetof(CPUState, uregs[i]),
161 uregnames[i]);
162 }
163 }
dedc5eae
MF		 164#define GEN_HELPER 2
165#include "helpers.h"
166}
167
b67ea0cd
MF		 168static inline bool option_bits_enabled(DisasContext *dc, uint64_t opt)
169{
170 return xtensa_option_bits_enabled(dc->config, opt);
171}
172
dedc5eae
MF		 173static inline bool option_enabled(DisasContext *dc, int opt)
174{
175 return xtensa_option_enabled(dc->config, opt);
176}
177
6ad6dbf7
MF		 178static void init_litbase(DisasContext *dc)
179{
180 if (dc->tb->flags & XTENSA_TBFLAG_LITBASE) {
181 dc->litbase = tcg_temp_local_new_i32();
182 tcg_gen_andi_i32(dc->litbase, cpu_SR[LITBASE], 0xfffff000);
183 }
184}
185
186static void reset_litbase(DisasContext *dc)
187{
188 if (dc->tb->flags & XTENSA_TBFLAG_LITBASE) {
189 tcg_temp_free(dc->litbase);
190 }
191}
192
3580ecad
MF		 193static void init_sar_tracker(DisasContext *dc)
194{
195 dc->sar_5bit = false;
196 dc->sar_m32_5bit = false;
197 dc->sar_m32_allocated = false;
198}
199
200static void reset_sar_tracker(DisasContext *dc)
201{
202 if (dc->sar_m32_allocated) {
203 tcg_temp_free(dc->sar_m32);
204 }
205}
206
207static void gen_right_shift_sar(DisasContext *dc, TCGv_i32 sa)
208{
209 tcg_gen_andi_i32(cpu_SR[SAR], sa, 0x1f);
210 if (dc->sar_m32_5bit) {
211 tcg_gen_discard_i32(dc->sar_m32);
212 }
213 dc->sar_5bit = true;
214 dc->sar_m32_5bit = false;
215}
216
217static void gen_left_shift_sar(DisasContext *dc, TCGv_i32 sa)
218{
219 TCGv_i32 tmp = tcg_const_i32(32);
220 if (!dc->sar_m32_allocated) {
221 dc->sar_m32 = tcg_temp_local_new_i32();
222 dc->sar_m32_allocated = true;
223 }
224 tcg_gen_andi_i32(dc->sar_m32, sa, 0x1f);
225 tcg_gen_sub_i32(cpu_SR[SAR], tmp, dc->sar_m32);
226 dc->sar_5bit = false;
227 dc->sar_m32_5bit = true;
228 tcg_temp_free(tmp);
229}
230
b994e91b
MF		 231static void gen_advance_ccount(DisasContext *dc)
232{
233 if (dc->ccount_delta > 0) {
234 TCGv_i32 tmp = tcg_const_i32(dc->ccount_delta);
235 dc->ccount_delta = 0;
236 gen_helper_advance_ccount(tmp);
237 tcg_temp_free(tmp);
238 }
239}
240
772177c1
MF		 241static void reset_used_window(DisasContext *dc)
242{
243 dc->used_window = 0;
244}
245
b994e91b 246static void gen_exception(DisasContext *dc, int excp)
dedc5eae
MF		 247{
248 TCGv_i32 tmp = tcg_const_i32(excp);
b994e91b 249 gen_advance_ccount(dc);
dedc5eae
MF		 250 gen_helper_exception(tmp);
251 tcg_temp_free(tmp);
252}
253
40643d7c
MF		 254static void gen_exception_cause(DisasContext *dc, uint32_t cause)
255{
256 TCGv_i32 tpc = tcg_const_i32(dc->pc);
257 TCGv_i32 tcause = tcg_const_i32(cause);
b994e91b 258 gen_advance_ccount(dc);
40643d7c
MF		 259 gen_helper_exception_cause(tpc, tcause);
260 tcg_temp_free(tpc);
261 tcg_temp_free(tcause);
262}
263
5b4e481b
MF		 264static void gen_exception_cause_vaddr(DisasContext *dc, uint32_t cause,
265 TCGv_i32 vaddr)
266{
267 TCGv_i32 tpc = tcg_const_i32(dc->pc);
268 TCGv_i32 tcause = tcg_const_i32(cause);
b994e91b 269 gen_advance_ccount(dc);
5b4e481b
MF		 270 gen_helper_exception_cause_vaddr(tpc, tcause, vaddr);
271 tcg_temp_free(tpc);
272 tcg_temp_free(tcause);
273}
274
40643d7c
MF		 275static void gen_check_privilege(DisasContext *dc)
276{
277 if (dc->cring) {
278 gen_exception_cause(dc, PRIVILEGED_CAUSE);
279 }
280}
281
dedc5eae
MF		 282static void gen_jump_slot(DisasContext *dc, TCGv dest, int slot)
283{
284 tcg_gen_mov_i32(cpu_pc, dest);
285 if (dc->singlestep_enabled) {
b994e91b 286 gen_exception(dc, EXCP_DEBUG);
dedc5eae 287 } else {
b994e91b 288 gen_advance_ccount(dc);
dedc5eae
MF		 289 if (slot >= 0) {
290 tcg_gen_goto_tb(slot);
291 tcg_gen_exit_tb((tcg_target_long)dc->tb + slot);
292 } else {
293 tcg_gen_exit_tb(0);
294 }
295 }
296 dc->is_jmp = DISAS_UPDATE;
297}
298
67882fd1
MF		 299static void gen_jump(DisasContext *dc, TCGv dest)
300{
301 gen_jump_slot(dc, dest, -1);
302}
303
dedc5eae
MF		 304static void gen_jumpi(DisasContext *dc, uint32_t dest, int slot)
305{
306 TCGv_i32 tmp = tcg_const_i32(dest);
307 if (((dc->pc ^ dest) & TARGET_PAGE_MASK) != 0) {
308 slot = -1;
309 }
310 gen_jump_slot(dc, tmp, slot);
311 tcg_temp_free(tmp);
312}
313
553e44f9
MF		 314static void gen_callw_slot(DisasContext *dc, int callinc, TCGv_i32 dest,
315 int slot)
316{
317 TCGv_i32 tcallinc = tcg_const_i32(callinc);
318
319 tcg_gen_deposit_i32(cpu_SR[PS], cpu_SR[PS],
320 tcallinc, PS_CALLINC_SHIFT, PS_CALLINC_LEN);
321 tcg_temp_free(tcallinc);
322 tcg_gen_movi_i32(cpu_R[callinc << 2],
323 (callinc << 30) | (dc->next_pc & 0x3fffffff));
324 gen_jump_slot(dc, dest, slot);
325}
326
327static void gen_callw(DisasContext *dc, int callinc, TCGv_i32 dest)
328{
329 gen_callw_slot(dc, callinc, dest, -1);
330}
331
332static void gen_callwi(DisasContext *dc, int callinc, uint32_t dest, int slot)
333{
334 TCGv_i32 tmp = tcg_const_i32(dest);
335 if (((dc->pc ^ dest) & TARGET_PAGE_MASK) != 0) {
336 slot = -1;
337 }
338 gen_callw_slot(dc, callinc, tmp, slot);
339 tcg_temp_free(tmp);
340}
341
797d780b
MF		 342static bool gen_check_loop_end(DisasContext *dc, int slot)
343{
344 if (option_enabled(dc, XTENSA_OPTION_LOOP) &&
345 !(dc->tb->flags & XTENSA_TBFLAG_EXCM) &&
346 dc->next_pc == dc->lend) {
347 int label = gen_new_label();
348
349 tcg_gen_brcondi_i32(TCG_COND_EQ, cpu_SR[LCOUNT], 0, label);
350 tcg_gen_subi_i32(cpu_SR[LCOUNT], cpu_SR[LCOUNT], 1);
351 gen_jumpi(dc, dc->lbeg, slot);
352 gen_set_label(label);
353 gen_jumpi(dc, dc->next_pc, -1);
354 return true;
355 }
356 return false;
357}
358
359static void gen_jumpi_check_loop_end(DisasContext *dc, int slot)
360{
361 if (!gen_check_loop_end(dc, slot)) {
362 gen_jumpi(dc, dc->next_pc, slot);
363 }
364}
365
bd57fb91
MF		 366static void gen_brcond(DisasContext *dc, TCGCond cond,
367 TCGv_i32 t0, TCGv_i32 t1, uint32_t offset)
368{
369 int label = gen_new_label();
370
371 tcg_gen_brcond_i32(cond, t0, t1, label);
797d780b 372 gen_jumpi_check_loop_end(dc, 0);
bd57fb91
MF		 373 gen_set_label(label);
374 gen_jumpi(dc, dc->pc + offset, 1);
375}
376
377static void gen_brcondi(DisasContext *dc, TCGCond cond,
378 TCGv_i32 t0, uint32_t t1, uint32_t offset)
379{
380 TCGv_i32 tmp = tcg_const_i32(t1);
381 gen_brcond(dc, cond, t0, tmp, offset);
382 tcg_temp_free(tmp);
383}
384
b994e91b
MF		 385static void gen_rsr_ccount(DisasContext *dc, TCGv_i32 d, uint32_t sr)
386{
387 gen_advance_ccount(dc);
388 tcg_gen_mov_i32(d, cpu_SR[sr]);
389}
390
b67ea0cd
MF		 391static void gen_rsr_ptevaddr(DisasContext *dc, TCGv_i32 d, uint32_t sr)
392{
393 tcg_gen_shri_i32(d, cpu_SR[EXCVADDR], 10);
394 tcg_gen_or_i32(d, d, cpu_SR[sr]);
395 tcg_gen_andi_i32(d, d, 0xfffffffc);
396}
397
b8132eff
MF		 398static void gen_rsr(DisasContext *dc, TCGv_i32 d, uint32_t sr)
399{
400 static void (* const rsr_handler[256])(DisasContext *dc,
401 TCGv_i32 d, uint32_t sr) = {
b994e91b 402 [CCOUNT] = gen_rsr_ccount,
b67ea0cd 403 [PTEVADDR] = gen_rsr_ptevaddr,
b8132eff
MF		 404 };
405
406 if (sregnames[sr]) {
407 if (rsr_handler[sr]) {
408 rsr_handler[sr](dc, d, sr);
409 } else {
410 tcg_gen_mov_i32(d, cpu_SR[sr]);
411 }
412 } else {
413 qemu_log("RSR %d not implemented, ", sr);
414 }
415}
416
797d780b
MF		 417static void gen_wsr_lbeg(DisasContext *dc, uint32_t sr, TCGv_i32 s)
418{
419 gen_helper_wsr_lbeg(s);
420}
421
422static void gen_wsr_lend(DisasContext *dc, uint32_t sr, TCGv_i32 s)
423{
424 gen_helper_wsr_lend(s);
425}
426
3580ecad
MF		 427static void gen_wsr_sar(DisasContext *dc, uint32_t sr, TCGv_i32 s)
428{
429 tcg_gen_andi_i32(cpu_SR[sr], s, 0x3f);
430 if (dc->sar_m32_5bit) {
431 tcg_gen_discard_i32(dc->sar_m32);
432 }
433 dc->sar_5bit = false;
434 dc->sar_m32_5bit = false;
435}
436
6ad6dbf7
MF		 437static void gen_wsr_litbase(DisasContext *dc, uint32_t sr, TCGv_i32 s)
438{
439 tcg_gen_andi_i32(cpu_SR[sr], s, 0xfffff001);
440 /* This can change tb->flags, so exit tb */
441 gen_jumpi_check_loop_end(dc, -1);
442}
443
553e44f9
MF		 444static void gen_wsr_windowbase(DisasContext *dc, uint32_t sr, TCGv_i32 v)
445{
446 gen_helper_wsr_windowbase(v);
772177c1
MF		 447 reset_used_window(dc);
448}
449
450static void gen_wsr_windowstart(DisasContext *dc, uint32_t sr, TCGv_i32 v)
451{
452 tcg_gen_mov_i32(cpu_SR[sr], v);
453 reset_used_window(dc);
553e44f9
MF		 454}
455
b67ea0cd
MF		 456static void gen_wsr_ptevaddr(DisasContext *dc, uint32_t sr, TCGv_i32 v)
457{
458 tcg_gen_andi_i32(cpu_SR[sr], v, 0xffc00000);
459}
460
461static void gen_wsr_rasid(DisasContext *dc, uint32_t sr, TCGv_i32 v)
462{
463 gen_helper_wsr_rasid(v);
464 /* This can change tb->flags, so exit tb */
465 gen_jumpi_check_loop_end(dc, -1);
466}
467
468static void gen_wsr_tlbcfg(DisasContext *dc, uint32_t sr, TCGv_i32 v)
469{
470 tcg_gen_andi_i32(cpu_SR[sr], v, 0x01130000);
471}
472
b994e91b
MF		 473static void gen_wsr_intset(DisasContext *dc, uint32_t sr, TCGv_i32 v)
474{
475 tcg_gen_andi_i32(cpu_SR[sr], v,
476 dc->config->inttype_mask[INTTYPE_SOFTWARE]);
477 gen_helper_check_interrupts(cpu_env);
478 gen_jumpi_check_loop_end(dc, 0);
479}
480
481static void gen_wsr_intclear(DisasContext *dc, uint32_t sr, TCGv_i32 v)
482{
483 TCGv_i32 tmp = tcg_temp_new_i32();
484
485 tcg_gen_andi_i32(tmp, v,
486 dc->config->inttype_mask[INTTYPE_EDGE] |
487 dc->config->inttype_mask[INTTYPE_NMI] |
488 dc->config->inttype_mask[INTTYPE_SOFTWARE]);
489 tcg_gen_andc_i32(cpu_SR[INTSET], cpu_SR[INTSET], tmp);
490 tcg_temp_free(tmp);
491 gen_helper_check_interrupts(cpu_env);
492}
493
494static void gen_wsr_intenable(DisasContext *dc, uint32_t sr, TCGv_i32 v)
495{
496 tcg_gen_mov_i32(cpu_SR[sr], v);
497 gen_helper_check_interrupts(cpu_env);
498 gen_jumpi_check_loop_end(dc, 0);
499}
500
f0a548b9
MF		 501static void gen_wsr_ps(DisasContext *dc, uint32_t sr, TCGv_i32 v)
502{
503 uint32_t mask = PS_WOE | PS_CALLINC | PS_OWB |
504 PS_UM | PS_EXCM | PS_INTLEVEL;
505
506 if (option_enabled(dc, XTENSA_OPTION_MMU)) {
507 mask |= PS_RING;
508 }
509 tcg_gen_andi_i32(cpu_SR[sr], v, mask);
772177c1 510 reset_used_window(dc);
b994e91b
MF		 511 gen_helper_check_interrupts(cpu_env);
512 /* This can change mmu index and tb->flags, so exit tb */
797d780b 513 gen_jumpi_check_loop_end(dc, -1);
f0a548b9
MF		 514}
515
f3df4c04
MF		 516static void gen_wsr_prid(DisasContext *dc, uint32_t sr, TCGv_i32 v)
517{
518}
519
b994e91b
MF		 520static void gen_wsr_ccompare(DisasContext *dc, uint32_t sr, TCGv_i32 v)
521{
522 uint32_t id = sr - CCOMPARE;
523 if (id < dc->config->nccompare) {
524 uint32_t int_bit = 1 << dc->config->timerint[id];
525 gen_advance_ccount(dc);
526 tcg_gen_mov_i32(cpu_SR[sr], v);
527 tcg_gen_andi_i32(cpu_SR[INTSET], cpu_SR[INTSET], ~int_bit);
528 gen_helper_check_interrupts(cpu_env);
529 }
530}
531
b8132eff
MF		 532static void gen_wsr(DisasContext *dc, uint32_t sr, TCGv_i32 s)
533{
534 static void (* const wsr_handler[256])(DisasContext *dc,
535 uint32_t sr, TCGv_i32 v) = {
797d780b
MF		 536 [LBEG] = gen_wsr_lbeg,
537 [LEND] = gen_wsr_lend,
3580ecad 538 [SAR] = gen_wsr_sar,
6ad6dbf7 539 [LITBASE] = gen_wsr_litbase,
553e44f9 540 [WINDOW_BASE] = gen_wsr_windowbase,
772177c1 541 [WINDOW_START] = gen_wsr_windowstart,
b67ea0cd
MF		 542 [PTEVADDR] = gen_wsr_ptevaddr,
543 [RASID] = gen_wsr_rasid,
544 [ITLBCFG] = gen_wsr_tlbcfg,
545 [DTLBCFG] = gen_wsr_tlbcfg,
b994e91b
MF		 546 [INTSET] = gen_wsr_intset,
547 [INTCLEAR] = gen_wsr_intclear,
548 [INTENABLE] = gen_wsr_intenable,
f0a548b9 549 [PS] = gen_wsr_ps,
f3df4c04 550 [PRID] = gen_wsr_prid,
b994e91b
MF		 551 [CCOMPARE] = gen_wsr_ccompare,
552 [CCOMPARE + 1] = gen_wsr_ccompare,
553 [CCOMPARE + 2] = gen_wsr_ccompare,
b8132eff
MF		 554 };
555
556 if (sregnames[sr]) {
557 if (wsr_handler[sr]) {
558 wsr_handler[sr](dc, sr, s);
559 } else {
560 tcg_gen_mov_i32(cpu_SR[sr], s);
561 }
562 } else {
563 qemu_log("WSR %d not implemented, ", sr);
564 }
565}
566
5b4e481b
MF		 567static void gen_load_store_alignment(DisasContext *dc, int shift,
568 TCGv_i32 addr, bool no_hw_alignment)
569{
570 if (!option_enabled(dc, XTENSA_OPTION_UNALIGNED_EXCEPTION)) {
571 tcg_gen_andi_i32(addr, addr, ~0 << shift);
572 } else if (option_enabled(dc, XTENSA_OPTION_HW_ALIGNMENT) &&
573 no_hw_alignment) {
574 int label = gen_new_label();
575 TCGv_i32 tmp = tcg_temp_new_i32();
576 tcg_gen_andi_i32(tmp, addr, ~(~0 << shift));
577 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, label);
578 gen_exception_cause_vaddr(dc, LOAD_STORE_ALIGNMENT_CAUSE, addr);
579 gen_set_label(label);
580 tcg_temp_free(tmp);
581 }
582}
583
b994e91b
MF		 584static void gen_waiti(DisasContext *dc, uint32_t imm4)
585{
586 TCGv_i32 pc = tcg_const_i32(dc->next_pc);
587 TCGv_i32 intlevel = tcg_const_i32(imm4);
588 gen_advance_ccount(dc);
589 gen_helper_waiti(pc, intlevel);
590 tcg_temp_free(pc);
591 tcg_temp_free(intlevel);
592}
593
772177c1
MF		 594static void gen_window_check1(DisasContext *dc, unsigned r1)
595{
596 if (dc->tb->flags & XTENSA_TBFLAG_EXCM) {
597 return;
598 }
599 if (option_enabled(dc, XTENSA_OPTION_WINDOWED_REGISTER) &&
600 r1 / 4 > dc->used_window) {
601 TCGv_i32 pc = tcg_const_i32(dc->pc);
602 TCGv_i32 w = tcg_const_i32(r1 / 4);
603
604 dc->used_window = r1 / 4;
605 gen_advance_ccount(dc);
606 gen_helper_window_check(pc, w);
607
608 tcg_temp_free(w);
609 tcg_temp_free(pc);
610 }
611}
612
613static void gen_window_check2(DisasContext *dc, unsigned r1, unsigned r2)
614{
615 gen_window_check1(dc, r1 > r2 ? r1 : r2);
616}
617
618static void gen_window_check3(DisasContext *dc, unsigned r1, unsigned r2,
619 unsigned r3)
620{
621 gen_window_check2(dc, r1, r2 > r3 ? r2 : r3);
622}
623
dedc5eae
MF		 624static void disas_xtensa_insn(DisasContext *dc)
625{
b67ea0cd
MF		 626#define HAS_OPTION_BITS(opt) do { \
627 if (!option_bits_enabled(dc, opt)) { \
628 qemu_log("Option is not enabled %s:%d\n", \
629 __FILE__, __LINE__); \
dedc5eae
MF		 630 goto invalid_opcode; \
631 } \
632 } while (0)
633
b67ea0cd
MF		 634#define HAS_OPTION(opt) HAS_OPTION_BITS(XTENSA_OPTION_BIT(opt))
635
91a5bb76
MF		 636#define TBD() qemu_log("TBD(pc = %08x): %s:%d\n", dc->pc, __FILE__, __LINE__)
637#define RESERVED() do { \
638 qemu_log("RESERVED(pc = %08x, %02x%02x%02x): %s:%d\n", \
639 dc->pc, b0, b1, b2, __FILE__, __LINE__); \
640 goto invalid_opcode; \
641 } while (0)
642
643
dedc5eae
MF		 644#ifdef TARGET_WORDS_BIGENDIAN
645#define OP0 (((b0) & 0xf0) >> 4)
646#define OP1 (((b2) & 0xf0) >> 4)
647#define OP2 ((b2) & 0xf)
648#define RRR_R ((b1) & 0xf)
649#define RRR_S (((b1) & 0xf0) >> 4)
650#define RRR_T ((b0) & 0xf)
651#else
652#define OP0 (((b0) & 0xf))
653#define OP1 (((b2) & 0xf))
654#define OP2 (((b2) & 0xf0) >> 4)
655#define RRR_R (((b1) & 0xf0) >> 4)
656#define RRR_S (((b1) & 0xf))
657#define RRR_T (((b0) & 0xf0) >> 4)
658#endif
659
660#define RRRN_R RRR_R
661#define RRRN_S RRR_S
662#define RRRN_T RRR_T
663
664#define RRI8_R RRR_R
665#define RRI8_S RRR_S
666#define RRI8_T RRR_T
667#define RRI8_IMM8 (b2)
668#define RRI8_IMM8_SE ((((b2) & 0x80) ? 0xffffff00 : 0) | RRI8_IMM8)
669
670#ifdef TARGET_WORDS_BIGENDIAN
671#define RI16_IMM16 (((b1) << 8) | (b2))
672#else
673#define RI16_IMM16 (((b2) << 8) | (b1))
674#endif
675
676#ifdef TARGET_WORDS_BIGENDIAN
677#define CALL_N (((b0) & 0xc) >> 2)
678#define CALL_OFFSET ((((b0) & 0x3) << 16) | ((b1) << 8) | (b2))
679#else
680#define CALL_N (((b0) & 0x30) >> 4)
681#define CALL_OFFSET ((((b0) & 0xc0) >> 6) | ((b1) << 2) | ((b2) << 10))
682#endif
683#define CALL_OFFSET_SE \
684 (((CALL_OFFSET & 0x20000) ? 0xfffc0000 : 0) | CALL_OFFSET)
685
686#define CALLX_N CALL_N
687#ifdef TARGET_WORDS_BIGENDIAN
688#define CALLX_M ((b0) & 0x3)
689#else
690#define CALLX_M (((b0) & 0xc0) >> 6)
691#endif
692#define CALLX_S RRR_S
693
694#define BRI12_M CALLX_M
695#define BRI12_S RRR_S
696#ifdef TARGET_WORDS_BIGENDIAN
697#define BRI12_IMM12 ((((b1) & 0xf) << 8) | (b2))
698#else
699#define BRI12_IMM12 ((((b1) & 0xf0) >> 4) | ((b2) << 4))
700#endif
701#define BRI12_IMM12_SE (((BRI12_IMM12 & 0x800) ? 0xfffff000 : 0) | BRI12_IMM12)
702
703#define BRI8_M BRI12_M
704#define BRI8_R RRI8_R
705#define BRI8_S RRI8_S
706#define BRI8_IMM8 RRI8_IMM8
707#define BRI8_IMM8_SE RRI8_IMM8_SE
708
709#define RSR_SR (b1)
710
711 uint8_t b0 = ldub_code(dc->pc);
712 uint8_t b1 = ldub_code(dc->pc + 1);
713 uint8_t b2 = ldub_code(dc->pc + 2);
714
bd57fb91
MF		 715 static const uint32_t B4CONST[] = {
716 0xffffffff, 1, 2, 3, 4, 5, 6, 7, 8, 10, 12, 16, 32, 64, 128, 256
717 };
718
719 static const uint32_t B4CONSTU[] = {
720 32768, 65536, 2, 3, 4, 5, 6, 7, 8, 10, 12, 16, 32, 64, 128, 256
721 };
722
dedc5eae
MF		 723 if (OP0 >= 8) {
724 dc->next_pc = dc->pc + 2;
725 HAS_OPTION(XTENSA_OPTION_CODE_DENSITY);
726 } else {
727 dc->next_pc = dc->pc + 3;
728 }
729
730 switch (OP0) {
731 case 0: /*QRST*/
732 switch (OP1) {
733 case 0: /*RST0*/
734 switch (OP2) {
735 case 0: /*ST0*/
736 if ((RRR_R & 0xc) == 0x8) {
737 HAS_OPTION(XTENSA_OPTION_BOOLEAN);
738 }
739
740 switch (RRR_R) {
741 case 0: /*SNM0*/
5da4a6a8
MF		 742 switch (CALLX_M) {
743 case 0: /*ILL*/
40643d7c 744 gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);
5da4a6a8
MF		 745 break;
746
747 case 1: /*reserved*/
91a5bb76 748 RESERVED();
5da4a6a8
MF		 749 break;
750
751 case 2: /*JR*/
752 switch (CALLX_N) {
753 case 0: /*RET*/
754 case 2: /*JX*/
772177c1 755 gen_window_check1(dc, CALLX_S);
5da4a6a8
MF		 756 gen_jump(dc, cpu_R[CALLX_S]);
757 break;
758
759 case 1: /*RETWw*/
760 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
553e44f9
MF		 761 {
762 TCGv_i32 tmp = tcg_const_i32(dc->pc);
b994e91b 763 gen_advance_ccount(dc);
553e44f9
MF		 764 gen_helper_retw(tmp, tmp);
765 gen_jump(dc, tmp);
766 tcg_temp_free(tmp);
767 }
5da4a6a8
MF		 768 break;
769
770 case 3: /*reserved*/
91a5bb76 771 RESERVED();
5da4a6a8
MF		 772 break;
773 }
774 break;
775
776 case 3: /*CALLX*/
772177c1 777 gen_window_check2(dc, CALLX_S, CALLX_N << 2);
5da4a6a8
MF		 778 switch (CALLX_N) {
779 case 0: /*CALLX0*/
780 {
781 TCGv_i32 tmp = tcg_temp_new_i32();
782 tcg_gen_mov_i32(tmp, cpu_R[CALLX_S]);
783 tcg_gen_movi_i32(cpu_R[0], dc->next_pc);
784 gen_jump(dc, tmp);
785 tcg_temp_free(tmp);
786 }
787 break;
788
789 case 1: /*CALLX4w*/
790 case 2: /*CALLX8w*/
791 case 3: /*CALLX12w*/
792 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
553e44f9
MF		 793 {
794 TCGv_i32 tmp = tcg_temp_new_i32();
795
796 tcg_gen_mov_i32(tmp, cpu_R[CALLX_S]);
797 gen_callw(dc, CALLX_N, tmp);
798 tcg_temp_free(tmp);
799 }
5da4a6a8
MF		 800 break;
801 }
802 break;
803 }
dedc5eae
MF		 804 break;
805
806 case 1: /*MOVSPw*/
807 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
772177c1 808 gen_window_check2(dc, RRR_T, RRR_S);
553e44f9
MF		 809 {
810 TCGv_i32 pc = tcg_const_i32(dc->pc);
b994e91b 811 gen_advance_ccount(dc);
553e44f9
MF		 812 gen_helper_movsp(pc);
813 tcg_gen_mov_i32(cpu_R[RRR_T], cpu_R[RRR_S]);
814 tcg_temp_free(pc);
815 }
dedc5eae
MF		 816 break;
817
818 case 2: /*SYNC*/
28067b22
MF		 819 switch (RRR_T) {
820 case 0: /*ISYNC*/
821 break;
822
823 case 1: /*RSYNC*/
824 break;
825
826 case 2: /*ESYNC*/
827 break;
828
829 case 3: /*DSYNC*/
830 break;
831
832 case 8: /*EXCW*/
833 HAS_OPTION(XTENSA_OPTION_EXCEPTION);
834 break;
835
836 case 12: /*MEMW*/
837 break;
838
839 case 13: /*EXTW*/
840 break;
841
842 case 15: /*NOP*/
843 break;
844
845 default: /*reserved*/
846 RESERVED();
847 break;
848 }
91a5bb76
MF		 849 break;
850
851 case 3: /*RFEIx*/
40643d7c
MF		 852 switch (RRR_T) {
853 case 0: /*RFETx*/
854 HAS_OPTION(XTENSA_OPTION_EXCEPTION);
855 switch (RRR_S) {
856 case 0: /*RFEx*/
857 gen_check_privilege(dc);
858 tcg_gen_andi_i32(cpu_SR[PS], cpu_SR[PS], ~PS_EXCM);
b994e91b 859 gen_helper_check_interrupts(cpu_env);
40643d7c
MF		 860 gen_jump(dc, cpu_SR[EPC1]);
861 break;
862
863 case 1: /*RFUEx*/
864 RESERVED();
865 break;
866
867 case 2: /*RFDEx*/
868 gen_check_privilege(dc);
869 gen_jump(dc, cpu_SR[
870 dc->config->ndepc ? DEPC : EPC1]);
871 break;
872
873 case 4: /*RFWOw*/
874 case 5: /*RFWUw*/
875 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
553e44f9
MF		 876 gen_check_privilege(dc);
877 {
878 TCGv_i32 tmp = tcg_const_i32(1);
879
880 tcg_gen_andi_i32(
881 cpu_SR[PS], cpu_SR[PS], ~PS_EXCM);
882 tcg_gen_shl_i32(tmp, tmp, cpu_SR[WINDOW_BASE]);
883
884 if (RRR_S == 4) {
885 tcg_gen_andc_i32(cpu_SR[WINDOW_START],
886 cpu_SR[WINDOW_START], tmp);
887 } else {
888 tcg_gen_or_i32(cpu_SR[WINDOW_START],
889 cpu_SR[WINDOW_START], tmp);
890 }
891
892 gen_helper_restore_owb();
b994e91b 893 gen_helper_check_interrupts(cpu_env);
553e44f9
MF		 894 gen_jump(dc, cpu_SR[EPC1]);
895
896 tcg_temp_free(tmp);
897 }
40643d7c
MF		 898 break;
899
900 default: /*reserved*/
901 RESERVED();
902 break;
903 }
904 break;
905
906 case 1: /*RFIx*/
907 HAS_OPTION(XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT);
b994e91b
MF		 908 if (RRR_S >= 2 && RRR_S <= dc->config->nlevel) {
909 gen_check_privilege(dc);
910 tcg_gen_mov_i32(cpu_SR[PS],
911 cpu_SR[EPS2 + RRR_S - 2]);
912 gen_helper_check_interrupts(cpu_env);
913 gen_jump(dc, cpu_SR[EPC1 + RRR_S - 1]);
914 } else {
915 qemu_log("RFI %d is illegal\n", RRR_S);
916 gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);
917 }
40643d7c
MF		 918 break;
919
920 case 2: /*RFME*/
921 TBD();
922 break;
923
924 default: /*reserved*/
925 RESERVED();
926 break;
927
928 }
91a5bb76
MF		 929 break;
930
931 case 4: /*BREAKx*/
932 HAS_OPTION(XTENSA_OPTION_EXCEPTION);
933 TBD();
934 break;
935
936 case 5: /*SYSCALLx*/
937 HAS_OPTION(XTENSA_OPTION_EXCEPTION);
40643d7c
MF		 938 switch (RRR_S) {
939 case 0: /*SYSCALLx*/
940 gen_exception_cause(dc, SYSCALL_CAUSE);
941 break;
942
943 case 1: /*SIMCALL*/
1ddeaa5d
MF		 944 if (semihosting_enabled) {
945 gen_check_privilege(dc);
946 gen_helper_simcall(cpu_env);
947 } else {
948 qemu_log("SIMCALL but semihosting is disabled\n");
949 gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);
950 }
40643d7c
MF		 951 break;
952
953 default:
954 RESERVED();
955 break;
956 }
91a5bb76
MF		 957 break;
958
959 case 6: /*RSILx*/
960 HAS_OPTION(XTENSA_OPTION_INTERRUPT);
40643d7c 961 gen_check_privilege(dc);
772177c1 962 gen_window_check1(dc, RRR_T);
40643d7c 963 tcg_gen_mov_i32(cpu_R[RRR_T], cpu_SR[PS]);
b994e91b 964 tcg_gen_andi_i32(cpu_SR[PS], cpu_SR[PS], ~PS_INTLEVEL);
40643d7c 965 tcg_gen_ori_i32(cpu_SR[PS], cpu_SR[PS], RRR_S);
b994e91b
MF		 966 gen_helper_check_interrupts(cpu_env);
967 gen_jumpi_check_loop_end(dc, 0);
91a5bb76
MF		 968 break;
969
970 case 7: /*WAITIx*/
971 HAS_OPTION(XTENSA_OPTION_INTERRUPT);
b994e91b
MF		 972 gen_check_privilege(dc);
973 gen_waiti(dc, RRR_S);
91a5bb76
MF		 974 break;
975
976 case 8: /*ANY4p*/
977 HAS_OPTION(XTENSA_OPTION_BOOLEAN);
978 TBD();
979 break;
980
981 case 9: /*ALL4p*/
982 HAS_OPTION(XTENSA_OPTION_BOOLEAN);
983 TBD();
dedc5eae
MF		 984 break;
985
91a5bb76
MF		 986 case 10: /*ANY8p*/
987 HAS_OPTION(XTENSA_OPTION_BOOLEAN);
988 TBD();
989 break;
990
991 case 11: /*ALL8p*/
992 HAS_OPTION(XTENSA_OPTION_BOOLEAN);
993 TBD();
994 break;
995
996 default: /*reserved*/
997 RESERVED();
dedc5eae
MF		 998 break;
999
1000 }
1001 break;
1002
1003 case 1: /*AND*/
772177c1 1004 gen_window_check3(dc, RRR_R, RRR_S, RRR_T);
dedc5eae
MF		 1005 tcg_gen_and_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
1006 break;
1007
1008 case 2: /*OR*/
772177c1 1009 gen_window_check3(dc, RRR_R, RRR_S, RRR_T);
dedc5eae
MF		 1010 tcg_gen_or_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
1011 break;
1012
1013 case 3: /*XOR*/
772177c1 1014 gen_window_check3(dc, RRR_R, RRR_S, RRR_T);
dedc5eae
MF		 1015 tcg_gen_xor_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
1016 break;
1017
1018 case 4: /*ST1*/
3580ecad
MF		 1019 switch (RRR_R) {
1020 case 0: /*SSR*/
772177c1 1021 gen_window_check1(dc, RRR_S);
3580ecad
MF		 1022 gen_right_shift_sar(dc, cpu_R[RRR_S]);
1023 break;
1024
1025 case 1: /*SSL*/
772177c1 1026 gen_window_check1(dc, RRR_S);
3580ecad
MF		 1027 gen_left_shift_sar(dc, cpu_R[RRR_S]);
1028 break;
1029
1030 case 2: /*SSA8L*/
772177c1 1031 gen_window_check1(dc, RRR_S);
3580ecad
MF		 1032 {
1033 TCGv_i32 tmp = tcg_temp_new_i32();
1034 tcg_gen_shli_i32(tmp, cpu_R[RRR_S], 3);
1035 gen_right_shift_sar(dc, tmp);
1036 tcg_temp_free(tmp);
1037 }
1038 break;
1039
1040 case 3: /*SSA8B*/
772177c1 1041 gen_window_check1(dc, RRR_S);
3580ecad
MF		 1042 {
1043 TCGv_i32 tmp = tcg_temp_new_i32();
1044 tcg_gen_shli_i32(tmp, cpu_R[RRR_S], 3);
1045 gen_left_shift_sar(dc, tmp);
1046 tcg_temp_free(tmp);
1047 }
1048 break;
1049
1050 case 4: /*SSAI*/
1051 {
1052 TCGv_i32 tmp = tcg_const_i32(
1053 RRR_S | ((RRR_T & 1) << 4));
1054 gen_right_shift_sar(dc, tmp);
1055 tcg_temp_free(tmp);
1056 }
1057 break;
1058
1059 case 6: /*RER*/
91a5bb76 1060 TBD();
3580ecad
MF		 1061 break;
1062
1063 case 7: /*WER*/
91a5bb76 1064 TBD();
3580ecad
MF		 1065 break;
1066
1067 case 8: /*ROTWw*/
1068 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
553e44f9
MF		 1069 gen_check_privilege(dc);
1070 {
1071 TCGv_i32 tmp = tcg_const_i32(
1072 RRR_T | ((RRR_T & 8) ? 0xfffffff0 : 0));
1073 gen_helper_rotw(tmp);
1074 tcg_temp_free(tmp);
772177c1 1075 reset_used_window(dc);
553e44f9 1076 }
3580ecad
MF		 1077 break;
1078
1079 case 14: /*NSAu*/
1080 HAS_OPTION(XTENSA_OPTION_MISC_OP);
772177c1 1081 gen_window_check2(dc, RRR_S, RRR_T);
3580ecad
MF		 1082 gen_helper_nsa(cpu_R[RRR_T], cpu_R[RRR_S]);
1083 break;
1084
1085 case 15: /*NSAUu*/
1086 HAS_OPTION(XTENSA_OPTION_MISC_OP);
772177c1 1087 gen_window_check2(dc, RRR_S, RRR_T);
3580ecad
MF		 1088 gen_helper_nsau(cpu_R[RRR_T], cpu_R[RRR_S]);
1089 break;
1090
1091 default: /*reserved*/
91a5bb76 1092 RESERVED();
3580ecad
MF		 1093 break;
1094 }
dedc5eae
MF		 1095 break;
1096
1097 case 5: /*TLB*/
b67ea0cd
MF		 1098 HAS_OPTION_BITS(
1099 XTENSA_OPTION_BIT(XTENSA_OPTION_MMU) |
1100 XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_PROTECTION) |
1101 XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_TRANSLATION));
1102 gen_check_privilege(dc);
1103 gen_window_check2(dc, RRR_S, RRR_T);
1104 {
1105 TCGv_i32 dtlb = tcg_const_i32((RRR_R & 8) != 0);
1106
1107 switch (RRR_R & 7) {
1108 case 3: /*RITLB0*/ /*RDTLB0*/
1109 gen_helper_rtlb0(cpu_R[RRR_T], cpu_R[RRR_S], dtlb);
1110 break;
1111
1112 case 4: /*IITLB*/ /*IDTLB*/
1113 gen_helper_itlb(cpu_R[RRR_S], dtlb);
1114 /* This could change memory mapping, so exit tb */
1115 gen_jumpi_check_loop_end(dc, -1);
1116 break;
1117
1118 case 5: /*PITLB*/ /*PDTLB*/
1119 tcg_gen_movi_i32(cpu_pc, dc->pc);
1120 gen_helper_ptlb(cpu_R[RRR_T], cpu_R[RRR_S], dtlb);
1121 break;
1122
1123 case 6: /*WITLB*/ /*WDTLB*/
1124 gen_helper_wtlb(cpu_R[RRR_T], cpu_R[RRR_S], dtlb);
1125 /* This could change memory mapping, so exit tb */
1126 gen_jumpi_check_loop_end(dc, -1);
1127 break;
1128
1129 case 7: /*RITLB1*/ /*RDTLB1*/
1130 gen_helper_rtlb1(cpu_R[RRR_T], cpu_R[RRR_S], dtlb);
1131 break;
1132
1133 default:
1134 tcg_temp_free(dtlb);
1135 RESERVED();
1136 break;
1137 }
1138 tcg_temp_free(dtlb);
1139 }
dedc5eae
MF		 1140 break;
1141
1142 case 6: /*RT0*/
772177c1 1143 gen_window_check2(dc, RRR_R, RRR_T);
f331fe5e
MF		 1144 switch (RRR_S) {
1145 case 0: /*NEG*/
1146 tcg_gen_neg_i32(cpu_R[RRR_R], cpu_R[RRR_T]);
1147 break;
1148
1149 case 1: /*ABS*/
1150 {
1151 int label = gen_new_label();
1152 tcg_gen_mov_i32(cpu_R[RRR_R], cpu_R[RRR_T]);
1153 tcg_gen_brcondi_i32(
1154 TCG_COND_GE, cpu_R[RRR_R], 0, label);
1155 tcg_gen_neg_i32(cpu_R[RRR_R], cpu_R[RRR_T]);
1156 gen_set_label(label);
1157 }
1158 break;
1159
1160 default: /*reserved*/
91a5bb76 1161 RESERVED();
f331fe5e
MF		 1162 break;
1163 }
dedc5eae
MF		 1164 break;
1165
1166 case 7: /*reserved*/
91a5bb76 1167 RESERVED();
dedc5eae
MF		 1168 break;
1169
1170 case 8: /*ADD*/
772177c1 1171 gen_window_check3(dc, RRR_R, RRR_S, RRR_T);
dedc5eae
MF		 1172 tcg_gen_add_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
1173 break;
1174
1175 case 9: /*ADD**/
1176 case 10:
1177 case 11:
772177c1 1178 gen_window_check3(dc, RRR_R, RRR_S, RRR_T);
dedc5eae
MF		 1179 {
1180 TCGv_i32 tmp = tcg_temp_new_i32();
1181 tcg_gen_shli_i32(tmp, cpu_R[RRR_S], OP2 - 8);
1182 tcg_gen_add_i32(cpu_R[RRR_R], tmp, cpu_R[RRR_T]);
1183 tcg_temp_free(tmp);
1184 }
1185 break;
1186
1187 case 12: /*SUB*/
772177c1 1188 gen_window_check3(dc, RRR_R, RRR_S, RRR_T);
dedc5eae
MF		 1189 tcg_gen_sub_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
1190 break;
1191
1192 case 13: /*SUB**/
1193 case 14:
1194 case 15:
772177c1 1195 gen_window_check3(dc, RRR_R, RRR_S, RRR_T);
dedc5eae
MF		 1196 {
1197 TCGv_i32 tmp = tcg_temp_new_i32();
1198 tcg_gen_shli_i32(tmp, cpu_R[RRR_S], OP2 - 12);
1199 tcg_gen_sub_i32(cpu_R[RRR_R], tmp, cpu_R[RRR_T]);
1200 tcg_temp_free(tmp);
1201 }
1202 break;
1203 }
1204 break;
1205
1206 case 1: /*RST1*/
3580ecad
MF		 1207 switch (OP2) {
1208 case 0: /*SLLI*/
1209 case 1:
772177c1 1210 gen_window_check2(dc, RRR_R, RRR_S);
3580ecad
MF		 1211 tcg_gen_shli_i32(cpu_R[RRR_R], cpu_R[RRR_S],
1212 32 - (RRR_T | ((OP2 & 1) << 4)));
1213 break;
1214
1215 case 2: /*SRAI*/
1216 case 3:
772177c1 1217 gen_window_check2(dc, RRR_R, RRR_T);
3580ecad
MF		 1218 tcg_gen_sari_i32(cpu_R[RRR_R], cpu_R[RRR_T],
1219 RRR_S | ((OP2 & 1) << 4));
1220 break;
1221
1222 case 4: /*SRLI*/
772177c1 1223 gen_window_check2(dc, RRR_R, RRR_T);
3580ecad
MF		 1224 tcg_gen_shri_i32(cpu_R[RRR_R], cpu_R[RRR_T], RRR_S);
1225 break;
1226
1227 case 6: /*XSR*/
1228 {
1229 TCGv_i32 tmp = tcg_temp_new_i32();
40643d7c
MF		 1230 if (RSR_SR >= 64) {
1231 gen_check_privilege(dc);
1232 }
772177c1 1233 gen_window_check1(dc, RRR_T);
3580ecad
MF		 1234 tcg_gen_mov_i32(tmp, cpu_R[RRR_T]);
1235 gen_rsr(dc, cpu_R[RRR_T], RSR_SR);
1236 gen_wsr(dc, RSR_SR, tmp);
1237 tcg_temp_free(tmp);
91a5bb76
MF		 1238 if (!sregnames[RSR_SR]) {
1239 TBD();
1240 }
3580ecad
MF		 1241 }
1242 break;
1243
1244 /*
1245 * Note: 64 bit ops are used here solely because SAR values
1246 * have range 0..63
1247 */
1248#define gen_shift_reg(cmd, reg) do { \
1249 TCGv_i64 tmp = tcg_temp_new_i64(); \
1250 tcg_gen_extu_i32_i64(tmp, reg); \
1251 tcg_gen_##cmd##_i64(v, v, tmp); \
1252 tcg_gen_trunc_i64_i32(cpu_R[RRR_R], v); \
1253 tcg_temp_free_i64(v); \
1254 tcg_temp_free_i64(tmp); \
1255 } while (0)
1256
1257#define gen_shift(cmd) gen_shift_reg(cmd, cpu_SR[SAR])
1258
1259 case 8: /*SRC*/
772177c1 1260 gen_window_check3(dc, RRR_R, RRR_S, RRR_T);
3580ecad
MF		 1261 {
1262 TCGv_i64 v = tcg_temp_new_i64();
1263 tcg_gen_concat_i32_i64(v, cpu_R[RRR_T], cpu_R[RRR_S]);
1264 gen_shift(shr);
1265 }
1266 break;
1267
1268 case 9: /*SRL*/
772177c1 1269 gen_window_check2(dc, RRR_R, RRR_T);
3580ecad
MF		 1270 if (dc->sar_5bit) {
1271 tcg_gen_shr_i32(cpu_R[RRR_R], cpu_R[RRR_T], cpu_SR[SAR]);
1272 } else {
1273 TCGv_i64 v = tcg_temp_new_i64();
1274 tcg_gen_extu_i32_i64(v, cpu_R[RRR_T]);
1275 gen_shift(shr);
1276 }
1277 break;
1278
1279 case 10: /*SLL*/
772177c1 1280 gen_window_check2(dc, RRR_R, RRR_S);
3580ecad
MF		 1281 if (dc->sar_m32_5bit) {
1282 tcg_gen_shl_i32(cpu_R[RRR_R], cpu_R[RRR_S], dc->sar_m32);
1283 } else {
1284 TCGv_i64 v = tcg_temp_new_i64();
1285 TCGv_i32 s = tcg_const_i32(32);
1286 tcg_gen_sub_i32(s, s, cpu_SR[SAR]);
1287 tcg_gen_andi_i32(s, s, 0x3f);
1288 tcg_gen_extu_i32_i64(v, cpu_R[RRR_S]);
1289 gen_shift_reg(shl, s);
1290 tcg_temp_free(s);
1291 }
1292 break;
1293
1294 case 11: /*SRA*/
772177c1 1295 gen_window_check2(dc, RRR_R, RRR_T);
3580ecad
MF		 1296 if (dc->sar_5bit) {
1297 tcg_gen_sar_i32(cpu_R[RRR_R], cpu_R[RRR_T], cpu_SR[SAR]);
1298 } else {
1299 TCGv_i64 v = tcg_temp_new_i64();
1300 tcg_gen_ext_i32_i64(v, cpu_R[RRR_T]);
1301 gen_shift(sar);
1302 }
1303 break;
1304#undef gen_shift
1305#undef gen_shift_reg
1306
1307 case 12: /*MUL16U*/
1308 HAS_OPTION(XTENSA_OPTION_16_BIT_IMUL);
772177c1 1309 gen_window_check3(dc, RRR_R, RRR_S, RRR_T);
3580ecad
MF		 1310 {
1311 TCGv_i32 v1 = tcg_temp_new_i32();
1312 TCGv_i32 v2 = tcg_temp_new_i32();
1313 tcg_gen_ext16u_i32(v1, cpu_R[RRR_S]);
1314 tcg_gen_ext16u_i32(v2, cpu_R[RRR_T]);
1315 tcg_gen_mul_i32(cpu_R[RRR_R], v1, v2);
1316 tcg_temp_free(v2);
1317 tcg_temp_free(v1);
1318 }
1319 break;
1320
1321 case 13: /*MUL16S*/
1322 HAS_OPTION(XTENSA_OPTION_16_BIT_IMUL);
772177c1 1323 gen_window_check3(dc, RRR_R, RRR_S, RRR_T);
3580ecad
MF		 1324 {
1325 TCGv_i32 v1 = tcg_temp_new_i32();
1326 TCGv_i32 v2 = tcg_temp_new_i32();
1327 tcg_gen_ext16s_i32(v1, cpu_R[RRR_S]);
1328 tcg_gen_ext16s_i32(v2, cpu_R[RRR_T]);
1329 tcg_gen_mul_i32(cpu_R[RRR_R], v1, v2);
1330 tcg_temp_free(v2);
1331 tcg_temp_free(v1);
1332 }
1333 break;
1334
1335 default: /*reserved*/
91a5bb76 1336 RESERVED();
3580ecad
MF		 1337 break;
1338 }
dedc5eae
MF		 1339 break;
1340
1341 case 2: /*RST2*/
772177c1
MF		 1342 gen_window_check3(dc, RRR_R, RRR_S, RRR_T);
1343
f76ebf55
MF		 1344 if (OP2 >= 12) {
1345 HAS_OPTION(XTENSA_OPTION_32_BIT_IDIV);
1346 int label = gen_new_label();
1347 tcg_gen_brcondi_i32(TCG_COND_NE, cpu_R[RRR_T], 0, label);
1348 gen_exception_cause(dc, INTEGER_DIVIDE_BY_ZERO_CAUSE);
1349 gen_set_label(label);
1350 }
1351
1352 switch (OP2) {
1353 case 8: /*MULLi*/
1354 HAS_OPTION(XTENSA_OPTION_32_BIT_IMUL);
1355 tcg_gen_mul_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
1356 break;
1357
1358 case 10: /*MULUHi*/
1359 case 11: /*MULSHi*/
1360 HAS_OPTION(XTENSA_OPTION_32_BIT_IMUL);
1361 {
1362 TCGv_i64 r = tcg_temp_new_i64();
1363 TCGv_i64 s = tcg_temp_new_i64();
1364 TCGv_i64 t = tcg_temp_new_i64();
1365
1366 if (OP2 == 10) {
1367 tcg_gen_extu_i32_i64(s, cpu_R[RRR_S]);
1368 tcg_gen_extu_i32_i64(t, cpu_R[RRR_T]);
1369 } else {
1370 tcg_gen_ext_i32_i64(s, cpu_R[RRR_S]);
1371 tcg_gen_ext_i32_i64(t, cpu_R[RRR_T]);
1372 }
1373 tcg_gen_mul_i64(r, s, t);
1374 tcg_gen_shri_i64(r, r, 32);
1375 tcg_gen_trunc_i64_i32(cpu_R[RRR_R], r);
1376
1377 tcg_temp_free_i64(r);
1378 tcg_temp_free_i64(s);
1379 tcg_temp_free_i64(t);
1380 }
1381 break;
1382
1383 case 12: /*QUOUi*/
1384 tcg_gen_divu_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
1385 break;
1386
1387 case 13: /*QUOSi*/
1388 case 15: /*REMSi*/
1389 {
1390 int label1 = gen_new_label();
1391 int label2 = gen_new_label();
1392
1393 tcg_gen_brcondi_i32(TCG_COND_NE, cpu_R[RRR_S], 0x80000000,
1394 label1);
1395 tcg_gen_brcondi_i32(TCG_COND_NE, cpu_R[RRR_T], 0xffffffff,
1396 label1);
1397 tcg_gen_movi_i32(cpu_R[RRR_R],
1398 OP2 == 13 ? 0x80000000 : 0);
1399 tcg_gen_br(label2);
1400 gen_set_label(label1);
1401 if (OP2 == 13) {
1402 tcg_gen_div_i32(cpu_R[RRR_R],
1403 cpu_R[RRR_S], cpu_R[RRR_T]);
1404 } else {
1405 tcg_gen_rem_i32(cpu_R[RRR_R],
1406 cpu_R[RRR_S], cpu_R[RRR_T]);
1407 }
1408 gen_set_label(label2);
1409 }
1410 break;
1411
1412 case 14: /*REMUi*/
1413 tcg_gen_remu_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
1414 break;
1415
1416 default: /*reserved*/
1417 RESERVED();
1418 break;
1419 }
dedc5eae
MF		 1420 break;
1421
1422 case 3: /*RST3*/
b8132eff
MF		 1423 switch (OP2) {
1424 case 0: /*RSR*/
40643d7c
MF		 1425 if (RSR_SR >= 64) {
1426 gen_check_privilege(dc);
1427 }
772177c1 1428 gen_window_check1(dc, RRR_T);
b8132eff 1429 gen_rsr(dc, cpu_R[RRR_T], RSR_SR);
91a5bb76
MF		 1430 if (!sregnames[RSR_SR]) {
1431 TBD();
1432 }
b8132eff
MF		 1433 break;
1434
1435 case 1: /*WSR*/
40643d7c
MF		 1436 if (RSR_SR >= 64) {
1437 gen_check_privilege(dc);
1438 }
772177c1 1439 gen_window_check1(dc, RRR_T);
b8132eff 1440 gen_wsr(dc, RSR_SR, cpu_R[RRR_T]);
91a5bb76
MF		 1441 if (!sregnames[RSR_SR]) {
1442 TBD();
1443 }
b8132eff
MF		 1444 break;
1445
1446 case 2: /*SEXTu*/
1447 HAS_OPTION(XTENSA_OPTION_MISC_OP);
772177c1 1448 gen_window_check2(dc, RRR_R, RRR_S);
b8132eff
MF		 1449 {
1450 int shift = 24 - RRR_T;
1451
1452 if (shift == 24) {
1453 tcg_gen_ext8s_i32(cpu_R[RRR_R], cpu_R[RRR_S]);
1454 } else if (shift == 16) {
1455 tcg_gen_ext16s_i32(cpu_R[RRR_R], cpu_R[RRR_S]);
1456 } else {
1457 TCGv_i32 tmp = tcg_temp_new_i32();
1458 tcg_gen_shli_i32(tmp, cpu_R[RRR_S], shift);
1459 tcg_gen_sari_i32(cpu_R[RRR_R], tmp, shift);
1460 tcg_temp_free(tmp);
1461 }
1462 }
1463 break;
1464
1465 case 3: /*CLAMPSu*/
1466 HAS_OPTION(XTENSA_OPTION_MISC_OP);
772177c1 1467 gen_window_check2(dc, RRR_R, RRR_S);
b8132eff
MF		 1468 {
1469 TCGv_i32 tmp1 = tcg_temp_new_i32();
1470 TCGv_i32 tmp2 = tcg_temp_new_i32();
1471 int label = gen_new_label();
1472
1473 tcg_gen_sari_i32(tmp1, cpu_R[RRR_S], 24 - RRR_T);
1474 tcg_gen_xor_i32(tmp2, tmp1, cpu_R[RRR_S]);
1475 tcg_gen_andi_i32(tmp2, tmp2, 0xffffffff << (RRR_T + 7));
1476 tcg_gen_mov_i32(cpu_R[RRR_R], cpu_R[RRR_S]);
1477 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp2, 0, label);
1478
1479 tcg_gen_sari_i32(tmp1, cpu_R[RRR_S], 31);
1480 tcg_gen_xori_i32(cpu_R[RRR_R], tmp1,
1481 0xffffffff >> (25 - RRR_T));
1482
1483 gen_set_label(label);
1484
1485 tcg_temp_free(tmp1);
1486 tcg_temp_free(tmp2);
1487 }
1488 break;
1489
1490 case 4: /*MINu*/
1491 case 5: /*MAXu*/
1492 case 6: /*MINUu*/
1493 case 7: /*MAXUu*/
1494 HAS_OPTION(XTENSA_OPTION_MISC_OP);
772177c1 1495 gen_window_check3(dc, RRR_R, RRR_S, RRR_T);
b8132eff
MF		 1496 {
1497 static const TCGCond cond[] = {
1498 TCG_COND_LE,
1499 TCG_COND_GE,
1500 TCG_COND_LEU,
1501 TCG_COND_GEU
1502 };
1503 int label = gen_new_label();
1504
1505 if (RRR_R != RRR_T) {
1506 tcg_gen_mov_i32(cpu_R[RRR_R], cpu_R[RRR_S]);
1507 tcg_gen_brcond_i32(cond[OP2 - 4],
1508 cpu_R[RRR_S], cpu_R[RRR_T], label);
1509 tcg_gen_mov_i32(cpu_R[RRR_R], cpu_R[RRR_T]);
1510 } else {
1511 tcg_gen_brcond_i32(cond[OP2 - 4],
1512 cpu_R[RRR_T], cpu_R[RRR_S], label);
1513 tcg_gen_mov_i32(cpu_R[RRR_R], cpu_R[RRR_S]);
1514 }
1515 gen_set_label(label);
1516 }
1517 break;
1518
1519 case 8: /*MOVEQZ*/
1520 case 9: /*MOVNEZ*/
1521 case 10: /*MOVLTZ*/
1522 case 11: /*MOVGEZ*/
772177c1 1523 gen_window_check3(dc, RRR_R, RRR_S, RRR_T);
b8132eff
MF		 1524 {
1525 static const TCGCond cond[] = {
1526 TCG_COND_NE,
1527 TCG_COND_EQ,
1528 TCG_COND_GE,
1529 TCG_COND_LT
1530 };
1531 int label = gen_new_label();
1532 tcg_gen_brcondi_i32(cond[OP2 - 8], cpu_R[RRR_T], 0, label);
1533 tcg_gen_mov_i32(cpu_R[RRR_R], cpu_R[RRR_S]);
1534 gen_set_label(label);
1535 }
1536 break;
1537
1538 case 12: /*MOVFp*/
1539 HAS_OPTION(XTENSA_OPTION_BOOLEAN);
91a5bb76 1540 TBD();
b8132eff
MF		 1541 break;
1542
1543 case 13: /*MOVTp*/
1544 HAS_OPTION(XTENSA_OPTION_BOOLEAN);
91a5bb76 1545 TBD();
b8132eff
MF		 1546 break;
1547
1548 case 14: /*RUR*/
772177c1 1549 gen_window_check1(dc, RRR_R);
b8132eff
MF		 1550 {
1551 int st = (RRR_S << 4) + RRR_T;
1552 if (uregnames[st]) {
1553 tcg_gen_mov_i32(cpu_R[RRR_R], cpu_UR[st]);
1554 } else {
1555 qemu_log("RUR %d not implemented, ", st);
91a5bb76 1556 TBD();
b8132eff
MF		 1557 }
1558 }
1559 break;
1560
1561 case 15: /*WUR*/
772177c1 1562 gen_window_check1(dc, RRR_T);
b8132eff
MF		 1563 {
1564 if (uregnames[RSR_SR]) {
1565 tcg_gen_mov_i32(cpu_UR[RSR_SR], cpu_R[RRR_T]);
1566 } else {
1567 qemu_log("WUR %d not implemented, ", RSR_SR);
91a5bb76 1568 TBD();
b8132eff
MF		 1569 }
1570 }
1571 break;
1572
1573 }
dedc5eae
MF		 1574 break;
1575
1576 case 4: /*EXTUI*/
1577 case 5:
772177c1 1578 gen_window_check2(dc, RRR_R, RRR_T);
3580ecad
MF		 1579 {
1580 int shiftimm = RRR_S | (OP1 << 4);
1581 int maskimm = (1 << (OP2 + 1)) - 1;
1582
1583 TCGv_i32 tmp = tcg_temp_new_i32();
1584 tcg_gen_shri_i32(tmp, cpu_R[RRR_T], shiftimm);
1585 tcg_gen_andi_i32(cpu_R[RRR_R], tmp, maskimm);
1586 tcg_temp_free(tmp);
1587 }
dedc5eae
MF		 1588 break;
1589
1590 case 6: /*CUST0*/
91a5bb76 1591 RESERVED();
dedc5eae
MF		 1592 break;
1593
1594 case 7: /*CUST1*/
91a5bb76 1595 RESERVED();
dedc5eae
MF		 1596 break;
1597
1598 case 8: /*LSCXp*/
1599 HAS_OPTION(XTENSA_OPTION_COPROCESSOR);
91a5bb76 1600 TBD();
dedc5eae
MF		 1601 break;
1602
1603 case 9: /*LSC4*/
772177c1 1604 gen_window_check2(dc, RRR_S, RRR_T);
553e44f9
MF		 1605 switch (OP2) {
1606 case 0: /*L32E*/
1607 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
1608 gen_check_privilege(dc);
1609 {
1610 TCGv_i32 addr = tcg_temp_new_i32();
1611 tcg_gen_addi_i32(addr, cpu_R[RRR_S],
1612 (0xffffffc0 | (RRR_R << 2)));
1613 tcg_gen_qemu_ld32u(cpu_R[RRR_T], addr, dc->ring);
1614 tcg_temp_free(addr);
1615 }
1616 break;
1617
1618 case 4: /*S32E*/
1619 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
1620 gen_check_privilege(dc);
1621 {
1622 TCGv_i32 addr = tcg_temp_new_i32();
1623 tcg_gen_addi_i32(addr, cpu_R[RRR_S],
1624 (0xffffffc0 | (RRR_R << 2)));
1625 tcg_gen_qemu_st32(cpu_R[RRR_T], addr, dc->ring);
1626 tcg_temp_free(addr);
1627 }
1628 break;
1629
1630 default:
1631 RESERVED();
1632 break;
1633 }
dedc5eae
MF		 1634 break;
1635
1636 case 10: /*FP0*/
1637 HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR);
91a5bb76 1638 TBD();
dedc5eae
MF		 1639 break;
1640
1641 case 11: /*FP1*/
1642 HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR);
91a5bb76 1643 TBD();
dedc5eae
MF		 1644 break;
1645
1646 default: /*reserved*/
91a5bb76 1647 RESERVED();
dedc5eae
MF		 1648 break;
1649 }
1650 break;
1651
1652 case 1: /*L32R*/
772177c1 1653 gen_window_check1(dc, RRR_T);
dedc5eae
MF		 1654 {
1655 TCGv_i32 tmp = tcg_const_i32(
6ad6dbf7
MF		 1656 ((dc->tb->flags & XTENSA_TBFLAG_LITBASE) ?
1657 0 : ((dc->pc + 3) & ~3)) +
1658 (0xfffc0000 | (RI16_IMM16 << 2)));
dedc5eae 1659
6ad6dbf7
MF		 1660 if (dc->tb->flags & XTENSA_TBFLAG_LITBASE) {
1661 tcg_gen_add_i32(tmp, tmp, dc->litbase);
1662 }
f0a548b9 1663 tcg_gen_qemu_ld32u(cpu_R[RRR_T], tmp, dc->cring);
dedc5eae
MF		 1664 tcg_temp_free(tmp);
1665 }
1666 break;
1667
1668 case 2: /*LSAI*/
809377aa
MF		 1669#define gen_load_store(type, shift) do { \
1670 TCGv_i32 addr = tcg_temp_new_i32(); \
772177c1 1671 gen_window_check2(dc, RRI8_S, RRI8_T); \
809377aa 1672 tcg_gen_addi_i32(addr, cpu_R[RRI8_S], RRI8_IMM8 << shift); \
5b4e481b
MF		 1673 if (shift) { \
1674 gen_load_store_alignment(dc, shift, addr, false); \
1675 } \
f0a548b9 1676 tcg_gen_qemu_##type(cpu_R[RRI8_T], addr, dc->cring); \
809377aa
MF		 1677 tcg_temp_free(addr); \
1678 } while (0)
1679
1680 switch (RRI8_R) {
1681 case 0: /*L8UI*/
1682 gen_load_store(ld8u, 0);
1683 break;
1684
1685 case 1: /*L16UI*/
1686 gen_load_store(ld16u, 1);
1687 break;
1688
1689 case 2: /*L32I*/
1690 gen_load_store(ld32u, 2);
1691 break;
1692
1693 case 4: /*S8I*/
1694 gen_load_store(st8, 0);
1695 break;
1696
1697 case 5: /*S16I*/
1698 gen_load_store(st16, 1);
1699 break;
1700
1701 case 6: /*S32I*/
1702 gen_load_store(st32, 2);
1703 break;
1704
1705 case 7: /*CACHEc*/
8ffc2d0d
MF		 1706 if (RRI8_T < 8) {
1707 HAS_OPTION(XTENSA_OPTION_DCACHE);
1708 }
1709
1710 switch (RRI8_T) {
1711 case 0: /*DPFRc*/
1712 break;
1713
1714 case 1: /*DPFWc*/
1715 break;
1716
1717 case 2: /*DPFROc*/
1718 break;
1719
1720 case 3: /*DPFWOc*/
1721 break;
1722
1723 case 4: /*DHWBc*/
1724 break;
1725
1726 case 5: /*DHWBIc*/
1727 break;
1728
1729 case 6: /*DHIc*/
1730 break;
1731
1732 case 7: /*DIIc*/
1733 break;
1734
1735 case 8: /*DCEc*/
1736 switch (OP1) {
1737 case 0: /*DPFLl*/
1738 HAS_OPTION(XTENSA_OPTION_DCACHE_INDEX_LOCK);
1739 break;
1740
1741 case 2: /*DHUl*/
1742 HAS_OPTION(XTENSA_OPTION_DCACHE_INDEX_LOCK);
1743 break;
1744
1745 case 3: /*DIUl*/
1746 HAS_OPTION(XTENSA_OPTION_DCACHE_INDEX_LOCK);
1747 break;
1748
1749 case 4: /*DIWBc*/
1750 HAS_OPTION(XTENSA_OPTION_DCACHE);
1751 break;
1752
1753 case 5: /*DIWBIc*/
1754 HAS_OPTION(XTENSA_OPTION_DCACHE);
1755 break;
1756
1757 default: /*reserved*/
1758 RESERVED();
1759 break;
1760
1761 }
1762 break;
1763
1764 case 12: /*IPFc*/
1765 HAS_OPTION(XTENSA_OPTION_ICACHE);
1766 break;
1767
1768 case 13: /*ICEc*/
1769 switch (OP1) {
1770 case 0: /*IPFLl*/
1771 HAS_OPTION(XTENSA_OPTION_ICACHE_INDEX_LOCK);
1772 break;
1773
1774 case 2: /*IHUl*/
1775 HAS_OPTION(XTENSA_OPTION_ICACHE_INDEX_LOCK);
1776 break;
1777
1778 case 3: /*IIUl*/
1779 HAS_OPTION(XTENSA_OPTION_ICACHE_INDEX_LOCK);
1780 break;
1781
1782 default: /*reserved*/
1783 RESERVED();
1784 break;
1785 }
1786 break;
1787
1788 case 14: /*IHIc*/
1789 HAS_OPTION(XTENSA_OPTION_ICACHE);
1790 break;
1791
1792 case 15: /*IIIc*/
1793 HAS_OPTION(XTENSA_OPTION_ICACHE);
1794 break;
1795
1796 default: /*reserved*/
1797 RESERVED();
1798 break;
1799 }
809377aa
MF		 1800 break;
1801
1802 case 9: /*L16SI*/
1803 gen_load_store(ld16s, 1);
1804 break;
5b4e481b 1805#undef gen_load_store
809377aa
MF		 1806
1807 case 10: /*MOVI*/
772177c1 1808 gen_window_check1(dc, RRI8_T);
809377aa
MF		 1809 tcg_gen_movi_i32(cpu_R[RRI8_T],
1810 RRI8_IMM8 | (RRI8_S << 8) |
1811 ((RRI8_S & 0x8) ? 0xfffff000 : 0));
1812 break;
1813
5b4e481b
MF		 1814#define gen_load_store_no_hw_align(type) do { \
1815 TCGv_i32 addr = tcg_temp_local_new_i32(); \
772177c1 1816 gen_window_check2(dc, RRI8_S, RRI8_T); \
5b4e481b
MF		 1817 tcg_gen_addi_i32(addr, cpu_R[RRI8_S], RRI8_IMM8 << 2); \
1818 gen_load_store_alignment(dc, 2, addr, true); \
1819 tcg_gen_qemu_##type(cpu_R[RRI8_T], addr, dc->cring); \
1820 tcg_temp_free(addr); \
1821 } while (0)
1822
809377aa
MF		 1823 case 11: /*L32AIy*/
1824 HAS_OPTION(XTENSA_OPTION_MP_SYNCHRO);
5b4e481b 1825 gen_load_store_no_hw_align(ld32u); /*TODO acquire?*/
809377aa
MF		 1826 break;
1827
1828 case 12: /*ADDI*/
772177c1 1829 gen_window_check2(dc, RRI8_S, RRI8_T);
809377aa
MF		 1830 tcg_gen_addi_i32(cpu_R[RRI8_T], cpu_R[RRI8_S], RRI8_IMM8_SE);
1831 break;
1832
1833 case 13: /*ADDMI*/
772177c1 1834 gen_window_check2(dc, RRI8_S, RRI8_T);
809377aa
MF		 1835 tcg_gen_addi_i32(cpu_R[RRI8_T], cpu_R[RRI8_S], RRI8_IMM8_SE << 8);
1836 break;
1837
1838 case 14: /*S32C1Iy*/
1839 HAS_OPTION(XTENSA_OPTION_MP_SYNCHRO);
772177c1 1840 gen_window_check2(dc, RRI8_S, RRI8_T);
809377aa
MF		 1841 {
1842 int label = gen_new_label();
1843 TCGv_i32 tmp = tcg_temp_local_new_i32();
1844 TCGv_i32 addr = tcg_temp_local_new_i32();
1845
1846 tcg_gen_mov_i32(tmp, cpu_R[RRI8_T]);
1847 tcg_gen_addi_i32(addr, cpu_R[RRI8_S], RRI8_IMM8 << 2);
5b4e481b 1848 gen_load_store_alignment(dc, 2, addr, true);
f0a548b9 1849 tcg_gen_qemu_ld32u(cpu_R[RRI8_T], addr, dc->cring);
809377aa
MF		 1850 tcg_gen_brcond_i32(TCG_COND_NE, cpu_R[RRI8_T],
1851 cpu_SR[SCOMPARE1], label);
1852
f0a548b9 1853 tcg_gen_qemu_st32(tmp, addr, dc->cring);
809377aa
MF		 1854
1855 gen_set_label(label);
1856 tcg_temp_free(addr);
1857 tcg_temp_free(tmp);
1858 }
1859 break;
1860
1861 case 15: /*S32RIy*/
1862 HAS_OPTION(XTENSA_OPTION_MP_SYNCHRO);
5b4e481b 1863 gen_load_store_no_hw_align(st32); /*TODO release?*/
809377aa 1864 break;
5b4e481b 1865#undef gen_load_store_no_hw_align
809377aa
MF		 1866
1867 default: /*reserved*/
91a5bb76 1868 RESERVED();
809377aa
MF		 1869 break;
1870 }
dedc5eae
MF		 1871 break;
1872
1873 case 3: /*LSCIp*/
1874 HAS_OPTION(XTENSA_OPTION_COPROCESSOR);
91a5bb76 1875 TBD();
dedc5eae
MF		 1876 break;
1877
1878 case 4: /*MAC16d*/
1879 HAS_OPTION(XTENSA_OPTION_MAC16);
91a5bb76 1880 TBD();
dedc5eae
MF		 1881 break;
1882
1883 case 5: /*CALLN*/
1884 switch (CALL_N) {
1885 case 0: /*CALL0*/
1886 tcg_gen_movi_i32(cpu_R[0], dc->next_pc);
1887 gen_jumpi(dc, (dc->pc & ~3) + (CALL_OFFSET_SE << 2) + 4, 0);
1888 break;
1889
1890 case 1: /*CALL4w*/
1891 case 2: /*CALL8w*/
1892 case 3: /*CALL12w*/
1893 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
772177c1 1894 gen_window_check1(dc, CALL_N << 2);
553e44f9
MF		 1895 gen_callwi(dc, CALL_N,
1896 (dc->pc & ~3) + (CALL_OFFSET_SE << 2) + 4, 0);
dedc5eae
MF		 1897 break;
1898 }
1899 break;
1900
1901 case 6: /*SI*/
1902 switch (CALL_N) {
1903 case 0: /*J*/
1904 gen_jumpi(dc, dc->pc + 4 + CALL_OFFSET_SE, 0);
1905 break;
1906
bd57fb91 1907 case 1: /*BZ*/
772177c1 1908 gen_window_check1(dc, BRI12_S);
bd57fb91
MF		 1909 {
1910 static const TCGCond cond[] = {
1911 TCG_COND_EQ, /*BEQZ*/
1912 TCG_COND_NE, /*BNEZ*/
1913 TCG_COND_LT, /*BLTZ*/
1914 TCG_COND_GE, /*BGEZ*/
1915 };
1916
1917 gen_brcondi(dc, cond[BRI12_M & 3], cpu_R[BRI12_S], 0,
1918 4 + BRI12_IMM12_SE);
1919 }
1920 break;
1921
1922 case 2: /*BI0*/
772177c1 1923 gen_window_check1(dc, BRI8_S);
bd57fb91
MF		 1924 {
1925 static const TCGCond cond[] = {
1926 TCG_COND_EQ, /*BEQI*/
1927 TCG_COND_NE, /*BNEI*/
1928 TCG_COND_LT, /*BLTI*/
1929 TCG_COND_GE, /*BGEI*/
1930 };
1931
1932 gen_brcondi(dc, cond[BRI8_M & 3],
1933 cpu_R[BRI8_S], B4CONST[BRI8_R], 4 + BRI8_IMM8_SE);
1934 }
1935 break;
1936
1937 case 3: /*BI1*/
1938 switch (BRI8_M) {
1939 case 0: /*ENTRYw*/
1940 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
553e44f9
MF		 1941 {
1942 TCGv_i32 pc = tcg_const_i32(dc->pc);
1943 TCGv_i32 s = tcg_const_i32(BRI12_S);
1944 TCGv_i32 imm = tcg_const_i32(BRI12_IMM12);
b994e91b 1945 gen_advance_ccount(dc);
553e44f9
MF		 1946 gen_helper_entry(pc, s, imm);
1947 tcg_temp_free(imm);
1948 tcg_temp_free(s);
1949 tcg_temp_free(pc);
772177c1 1950 reset_used_window(dc);
553e44f9 1951 }
bd57fb91
MF		 1952 break;
1953
1954 case 1: /*B1*/
1955 switch (BRI8_R) {
1956 case 0: /*BFp*/
1957 HAS_OPTION(XTENSA_OPTION_BOOLEAN);
91a5bb76 1958 TBD();
bd57fb91
MF		 1959 break;
1960
1961 case 1: /*BTp*/
1962 HAS_OPTION(XTENSA_OPTION_BOOLEAN);
91a5bb76 1963 TBD();
bd57fb91
MF		 1964 break;
1965
1966 case 8: /*LOOP*/
bd57fb91 1967 case 9: /*LOOPNEZ*/
bd57fb91 1968 case 10: /*LOOPGTZ*/
797d780b 1969 HAS_OPTION(XTENSA_OPTION_LOOP);
772177c1 1970 gen_window_check1(dc, RRI8_S);
797d780b
MF		 1971 {
1972 uint32_t lend = dc->pc + RRI8_IMM8 + 4;
1973 TCGv_i32 tmp = tcg_const_i32(lend);
1974
1975 tcg_gen_subi_i32(cpu_SR[LCOUNT], cpu_R[RRI8_S], 1);
1976 tcg_gen_movi_i32(cpu_SR[LBEG], dc->next_pc);
1977 gen_wsr_lend(dc, LEND, tmp);
1978 tcg_temp_free(tmp);
1979
1980 if (BRI8_R > 8) {
1981 int label = gen_new_label();
1982 tcg_gen_brcondi_i32(
1983 BRI8_R == 9 ? TCG_COND_NE : TCG_COND_GT,
1984 cpu_R[RRI8_S], 0, label);
1985 gen_jumpi(dc, lend, 1);
1986 gen_set_label(label);
1987 }
1988
1989 gen_jumpi(dc, dc->next_pc, 0);
1990 }
bd57fb91
MF		 1991 break;
1992
1993 default: /*reserved*/
91a5bb76 1994 RESERVED();
bd57fb91
MF		 1995 break;
1996
1997 }
1998 break;
1999
2000 case 2: /*BLTUI*/
2001 case 3: /*BGEUI*/
772177c1 2002 gen_window_check1(dc, BRI8_S);
bd57fb91
MF		 2003 gen_brcondi(dc, BRI8_M == 2 ? TCG_COND_LTU : TCG_COND_GEU,
2004 cpu_R[BRI8_S], B4CONSTU[BRI8_R], 4 + BRI8_IMM8_SE);
2005 break;
2006 }
2007 break;
2008
dedc5eae
MF		 2009 }
2010 break;
2011
2012 case 7: /*B*/
bd57fb91
MF		 2013 {
2014 TCGCond eq_ne = (RRI8_R & 8) ? TCG_COND_NE : TCG_COND_EQ;
2015
2016 switch (RRI8_R & 7) {
2017 case 0: /*BNONE*/ /*BANY*/
772177c1 2018 gen_window_check2(dc, RRI8_S, RRI8_T);
bd57fb91
MF		 2019 {
2020 TCGv_i32 tmp = tcg_temp_new_i32();
2021 tcg_gen_and_i32(tmp, cpu_R[RRI8_S], cpu_R[RRI8_T]);
2022 gen_brcondi(dc, eq_ne, tmp, 0, 4 + RRI8_IMM8_SE);
2023 tcg_temp_free(tmp);
2024 }
2025 break;
2026
2027 case 1: /*BEQ*/ /*BNE*/
2028 case 2: /*BLT*/ /*BGE*/
2029 case 3: /*BLTU*/ /*BGEU*/
772177c1 2030 gen_window_check2(dc, RRI8_S, RRI8_T);
bd57fb91
MF		 2031 {
2032 static const TCGCond cond[] = {
2033 [1] = TCG_COND_EQ,
2034 [2] = TCG_COND_LT,
2035 [3] = TCG_COND_LTU,
2036 [9] = TCG_COND_NE,
2037 [10] = TCG_COND_GE,
2038 [11] = TCG_COND_GEU,
2039 };
2040 gen_brcond(dc, cond[RRI8_R], cpu_R[RRI8_S], cpu_R[RRI8_T],
2041 4 + RRI8_IMM8_SE);
2042 }
2043 break;
2044
2045 case 4: /*BALL*/ /*BNALL*/
772177c1 2046 gen_window_check2(dc, RRI8_S, RRI8_T);
bd57fb91
MF		 2047 {
2048 TCGv_i32 tmp = tcg_temp_new_i32();
2049 tcg_gen_and_i32(tmp, cpu_R[RRI8_S], cpu_R[RRI8_T]);
2050 gen_brcond(dc, eq_ne, tmp, cpu_R[RRI8_T],
2051 4 + RRI8_IMM8_SE);
2052 tcg_temp_free(tmp);
2053 }
2054 break;
2055
2056 case 5: /*BBC*/ /*BBS*/
772177c1 2057 gen_window_check2(dc, RRI8_S, RRI8_T);
bd57fb91
MF		 2058 {
2059 TCGv_i32 bit = tcg_const_i32(1);
2060 TCGv_i32 tmp = tcg_temp_new_i32();
2061 tcg_gen_andi_i32(tmp, cpu_R[RRI8_T], 0x1f);
2062 tcg_gen_shl_i32(bit, bit, tmp);
2063 tcg_gen_and_i32(tmp, cpu_R[RRI8_S], bit);
2064 gen_brcondi(dc, eq_ne, tmp, 0, 4 + RRI8_IMM8_SE);
2065 tcg_temp_free(tmp);
2066 tcg_temp_free(bit);
2067 }
2068 break;
2069
2070 case 6: /*BBCI*/ /*BBSI*/
2071 case 7:
772177c1 2072 gen_window_check1(dc, RRI8_S);
bd57fb91
MF		 2073 {
2074 TCGv_i32 tmp = tcg_temp_new_i32();
2075 tcg_gen_andi_i32(tmp, cpu_R[RRI8_S],
2076 1 << (((RRI8_R & 1) << 4) | RRI8_T));
2077 gen_brcondi(dc, eq_ne, tmp, 0, 4 + RRI8_IMM8_SE);
2078 tcg_temp_free(tmp);
2079 }
2080 break;
2081
2082 }
2083 }
dedc5eae
MF		 2084 break;
2085
67882fd1
MF		 2086#define gen_narrow_load_store(type) do { \
2087 TCGv_i32 addr = tcg_temp_new_i32(); \
772177c1 2088 gen_window_check2(dc, RRRN_S, RRRN_T); \
67882fd1 2089 tcg_gen_addi_i32(addr, cpu_R[RRRN_S], RRRN_R << 2); \
5b4e481b 2090 gen_load_store_alignment(dc, 2, addr, false); \
f0a548b9 2091 tcg_gen_qemu_##type(cpu_R[RRRN_T], addr, dc->cring); \
67882fd1
MF		 2092 tcg_temp_free(addr); \
2093 } while (0)
2094
dedc5eae 2095 case 8: /*L32I.Nn*/
67882fd1 2096 gen_narrow_load_store(ld32u);
dedc5eae
MF		 2097 break;
2098
2099 case 9: /*S32I.Nn*/
67882fd1 2100 gen_narrow_load_store(st32);
dedc5eae 2101 break;
67882fd1 2102#undef gen_narrow_load_store
dedc5eae
MF		 2103
2104 case 10: /*ADD.Nn*/
772177c1 2105 gen_window_check3(dc, RRRN_R, RRRN_S, RRRN_T);
67882fd1 2106 tcg_gen_add_i32(cpu_R[RRRN_R], cpu_R[RRRN_S], cpu_R[RRRN_T]);
dedc5eae
MF		 2107 break;
2108
2109 case 11: /*ADDI.Nn*/
772177c1 2110 gen_window_check2(dc, RRRN_R, RRRN_S);
67882fd1 2111 tcg_gen_addi_i32(cpu_R[RRRN_R], cpu_R[RRRN_S], RRRN_T ? RRRN_T : -1);
dedc5eae
MF		 2112 break;
2113
2114 case 12: /*ST2n*/
772177c1 2115 gen_window_check1(dc, RRRN_S);
67882fd1
MF		 2116 if (RRRN_T < 8) { /*MOVI.Nn*/
2117 tcg_gen_movi_i32(cpu_R[RRRN_S],
2118 RRRN_R | (RRRN_T << 4) |
2119 ((RRRN_T & 6) == 6 ? 0xffffff80 : 0));
2120 } else { /*BEQZ.Nn*/ /*BNEZ.Nn*/
bd57fb91
MF		 2121 TCGCond eq_ne = (RRRN_T & 4) ? TCG_COND_NE : TCG_COND_EQ;
2122
2123 gen_brcondi(dc, eq_ne, cpu_R[RRRN_S], 0,
2124 4 + (RRRN_R | ((RRRN_T & 3) << 4)));
67882fd1 2125 }
dedc5eae
MF		 2126 break;
2127
2128 case 13: /*ST3n*/
67882fd1
MF		 2129 switch (RRRN_R) {
2130 case 0: /*MOV.Nn*/
772177c1 2131 gen_window_check2(dc, RRRN_S, RRRN_T);
67882fd1
MF		 2132 tcg_gen_mov_i32(cpu_R[RRRN_T], cpu_R[RRRN_S]);
2133 break;
2134
2135 case 15: /*S3*/
2136 switch (RRRN_T) {
2137 case 0: /*RET.Nn*/
2138 gen_jump(dc, cpu_R[0]);
2139 break;
2140
2141 case 1: /*RETW.Nn*/
91a5bb76 2142 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
553e44f9
MF		 2143 {
2144 TCGv_i32 tmp = tcg_const_i32(dc->pc);
b994e91b 2145 gen_advance_ccount(dc);
553e44f9
MF		 2146 gen_helper_retw(tmp, tmp);
2147 gen_jump(dc, tmp);
2148 tcg_temp_free(tmp);
2149 }
67882fd1
MF		 2150 break;
2151
2152 case 2: /*BREAK.Nn*/
91a5bb76 2153 TBD();
67882fd1
MF		 2154 break;
2155
2156 case 3: /*NOP.Nn*/
2157 break;
2158
2159 case 6: /*ILL.Nn*/
40643d7c 2160 gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);
67882fd1
MF		 2161 break;
2162
2163 default: /*reserved*/
91a5bb76 2164 RESERVED();
67882fd1
MF		 2165 break;
2166 }
2167 break;
2168
2169 default: /*reserved*/
91a5bb76 2170 RESERVED();
67882fd1
MF		 2171 break;
2172 }
dedc5eae
MF		 2173 break;
2174
2175 default: /*reserved*/
91a5bb76 2176 RESERVED();
dedc5eae
MF		 2177 break;
2178 }
2179
797d780b 2180 gen_check_loop_end(dc, 0);
dedc5eae 2181 dc->pc = dc->next_pc;
797d780b 2182
dedc5eae
MF		 2183 return;
2184
2185invalid_opcode:
2186 qemu_log("INVALID(pc = %08x)\n", dc->pc);
2187 dc->pc = dc->next_pc;
2188#undef HAS_OPTION
2189}
2190
2191static void check_breakpoint(CPUState *env, DisasContext *dc)
2192{
2193 CPUBreakpoint *bp;
2194
2195 if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
2196 QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
2197 if (bp->pc == dc->pc) {
2198 tcg_gen_movi_i32(cpu_pc, dc->pc);
b994e91b 2199 gen_exception(dc, EXCP_DEBUG);
dedc5eae
MF		 2200 dc->is_jmp = DISAS_UPDATE;
2201 }
2202 }
2203 }
2204}
2205
2206static void gen_intermediate_code_internal(
2207 CPUState *env, TranslationBlock *tb, int search_pc)
2208{
2209 DisasContext dc;
2210 int insn_count = 0;
2211 int j, lj = -1;
2212 uint16_t *gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
2213 int max_insns = tb->cflags & CF_COUNT_MASK;
2214 uint32_t pc_start = tb->pc;
2215 uint32_t next_page_start =
2216 (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
2217
2218 if (max_insns == 0) {
2219 max_insns = CF_COUNT_MASK;
2220 }
2221
2222 dc.config = env->config;
2223 dc.singlestep_enabled = env->singlestep_enabled;
2224 dc.tb = tb;
2225 dc.pc = pc_start;
f0a548b9
MF		 2226 dc.ring = tb->flags & XTENSA_TBFLAG_RING_MASK;
2227 dc.cring = (tb->flags & XTENSA_TBFLAG_EXCM) ? 0 : dc.ring;
797d780b
MF		 2228 dc.lbeg = env->sregs[LBEG];
2229 dc.lend = env->sregs[LEND];
dedc5eae 2230 dc.is_jmp = DISAS_NEXT;
b994e91b 2231 dc.ccount_delta = 0;
dedc5eae 2232
6ad6dbf7 2233 init_litbase(&dc);
3580ecad 2234 init_sar_tracker(&dc);
772177c1 2235 reset_used_window(&dc);
3580ecad 2236
dedc5eae
MF		 2237 gen_icount_start();
2238
40643d7c
MF		 2239 if (env->singlestep_enabled && env->exception_taken) {
2240 env->exception_taken = 0;
2241 tcg_gen_movi_i32(cpu_pc, dc.pc);
b994e91b 2242 gen_exception(&dc, EXCP_DEBUG);
40643d7c
MF		 2243 }
2244
dedc5eae
MF		 2245 do {
2246 check_breakpoint(env, &dc);
2247
2248 if (search_pc) {
2249 j = gen_opc_ptr - gen_opc_buf;
2250 if (lj < j) {
2251 lj++;
2252 while (lj < j) {
2253 gen_opc_instr_start[lj++] = 0;
2254 }
2255 }
2256 gen_opc_pc[lj] = dc.pc;
2257 gen_opc_instr_start[lj] = 1;
2258 gen_opc_icount[lj] = insn_count;
2259 }
2260
2261 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP))) {
2262 tcg_gen_debug_insn_start(dc.pc);
2263 }
2264
b994e91b
MF		 2265 ++dc.ccount_delta;
2266
2267 if (insn_count + 1 == max_insns && (tb->cflags & CF_LAST_IO)) {
2268 gen_io_start();
2269 }
2270
dedc5eae
MF		 2271 disas_xtensa_insn(&dc);
2272 ++insn_count;
2273 if (env->singlestep_enabled) {
2274 tcg_gen_movi_i32(cpu_pc, dc.pc);
b994e91b 2275 gen_exception(&dc, EXCP_DEBUG);
dedc5eae
MF		 2276 break;
2277 }
2278 } while (dc.is_jmp == DISAS_NEXT &&
2279 insn_count < max_insns &&
2280 dc.pc < next_page_start &&
2281 gen_opc_ptr < gen_opc_end);
2282
6ad6dbf7 2283 reset_litbase(&dc);
3580ecad
MF		 2284 reset_sar_tracker(&dc);
2285
b994e91b
MF		 2286 if (tb->cflags & CF_LAST_IO) {
2287 gen_io_end();
2288 }
2289
dedc5eae
MF		 2290 if (dc.is_jmp == DISAS_NEXT) {
2291 gen_jumpi(&dc, dc.pc, 0);
2292 }
2293 gen_icount_end(tb, insn_count);
2294 *gen_opc_ptr = INDEX_op_end;
2295
2296 if (!search_pc) {
2297 tb->size = dc.pc - pc_start;
2298 tb->icount = insn_count;
2299 }
2328826b
MF		 2300}
2301
2302void gen_intermediate_code(CPUState *env, TranslationBlock *tb)
2303{
dedc5eae 2304 gen_intermediate_code_internal(env, tb, 0);
2328826b
MF		 2305}
2306
2307void gen_intermediate_code_pc(CPUState *env, TranslationBlock *tb)
2308{
dedc5eae 2309 gen_intermediate_code_internal(env, tb, 1);
2328826b
MF		 2310}
2311
2312void cpu_dump_state(CPUState *env, FILE *f, fprintf_function cpu_fprintf,
2313 int flags)
2314{
2af3da91
MF		 2315 int i, j;
2316
2317 cpu_fprintf(f, "PC=%08x\n\n", env->pc);
2318
2319 for (i = j = 0; i < 256; ++i) {
2320 if (sregnames[i]) {
2321 cpu_fprintf(f, "%s=%08x%c", sregnames[i], env->sregs[i],
2322 (j++ % 4) == 3 ? '\n' : ' ');
2323 }
2324 }
2325
2326 cpu_fprintf(f, (j % 4) == 0 ? "\n" : "\n\n");
2327
2328 for (i = j = 0; i < 256; ++i) {
2329 if (uregnames[i]) {
2330 cpu_fprintf(f, "%s=%08x%c", uregnames[i], env->uregs[i],
2331 (j++ % 4) == 3 ? '\n' : ' ');
2332 }
2333 }
2328826b 2334
2af3da91 2335 cpu_fprintf(f, (j % 4) == 0 ? "\n" : "\n\n");
2328826b
MF		 2336
2337 for (i = 0; i < 16; ++i) {
2338 cpu_fprintf(f, "A%02d=%08x%c", i, env->regs[i],
2339 (i % 4) == 3 ? '\n' : ' ');
2340 }
553e44f9
MF		 2341
2342 cpu_fprintf(f, "\n");
2343
2344 for (i = 0; i < env->config->nareg; ++i) {
2345 cpu_fprintf(f, "AR%02d=%08x%c", i, env->phys_regs[i],
2346 (i % 4) == 3 ? '\n' : ' ');
2347 }
2328826b
MF		 2348}
2349
2350void restore_state_to_opc(CPUState *env, TranslationBlock *tb, int pc_pos)
2351{
2352 env->pc = gen_opc_pc[pc_pos];
2353}
Qemu copy for testing