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target-xtensa: implement FP0 conversions
[qemu.git] / target-xtensa / translate.c
CommitLineData
2328826b
MF		 1/*
2 * Xtensa ISA:
3 * http://www.tensilica.com/products/literature-docs/documentation/xtensa-isa-databook.htm
4 *
5 * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions are met:
10 * * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * * Neither the name of the Open Source and Linux Lab nor the
16 * names of its contributors may be used to endorse or promote products
17 * derived from this software without specific prior written permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
23 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
26 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 */
30
31#include <stdio.h>
32
33#include "cpu.h"
34#include "exec-all.h"
35#include "disas.h"
36#include "tcg-op.h"
37#include "qemu-log.h"
1ddeaa5d 38#include "sysemu.h"
2328826b 39
16c1deae 40#include "helper.h"
dedc5eae 41#define GEN_HELPER 1
16c1deae 42#include "helper.h"
dedc5eae
MF		 43
44typedef struct DisasContext {
45 const XtensaConfig *config;
46 TranslationBlock *tb;
47 uint32_t pc;
48 uint32_t next_pc;
f0a548b9
MF		 49 int cring;
50 int ring;
797d780b
MF		 51 uint32_t lbeg;
52 uint32_t lend;
6ad6dbf7 53 TCGv_i32 litbase;
dedc5eae
MF		 54 int is_jmp;
55 int singlestep_enabled;
3580ecad
MF		 56
57 bool sar_5bit;
58 bool sar_m32_5bit;
59 bool sar_m32_allocated;
60 TCGv_i32 sar_m32;
b994e91b
MF		 61
62 uint32_t ccount_delta;
772177c1 63 unsigned used_window;
e61dc8f7
MF		 64
65 bool debug;
35b5c044
MF		 66 bool icount;
67 TCGv_i32 next_icount;
dedc5eae
MF		 68} DisasContext;
69
70static TCGv_ptr cpu_env;
71static TCGv_i32 cpu_pc;
72static TCGv_i32 cpu_R[16];
dd519cbe 73static TCGv_i32 cpu_FR[16];
2af3da91
MF		 74static TCGv_i32 cpu_SR[256];
75static TCGv_i32 cpu_UR[256];
dedc5eae
MF		 76
77#include "gen-icount.h"
2328826b 78
2af3da91 79static const char * const sregnames[256] = {
797d780b
MF		 80 [LBEG] = "LBEG",
81 [LEND] = "LEND",
82 [LCOUNT] = "LCOUNT",
3580ecad 83 [SAR] = "SAR",
4dd85b6b 84 [BR] = "BR",
6ad6dbf7 85 [LITBASE] = "LITBASE",
809377aa 86 [SCOMPARE1] = "SCOMPARE1",
6825b6c3
MF		 87 [ACCLO] = "ACCLO",
88 [ACCHI] = "ACCHI",
89 [MR] = "MR0",
90 [MR + 1] = "MR1",
91 [MR + 2] = "MR2",
92 [MR + 3] = "MR3",
553e44f9
MF		 93 [WINDOW_BASE] = "WINDOW_BASE",
94 [WINDOW_START] = "WINDOW_START",
b67ea0cd
MF		 95 [PTEVADDR] = "PTEVADDR",
96 [RASID] = "RASID",
97 [ITLBCFG] = "ITLBCFG",
98 [DTLBCFG] = "DTLBCFG",
e61dc8f7
MF		 99 [IBREAKENABLE] = "IBREAKENABLE",
100 [IBREAKA] = "IBREAKA0",
101 [IBREAKA + 1] = "IBREAKA1",
f14c4b5f
MF		 102 [DBREAKA] = "DBREAKA0",
103 [DBREAKA + 1] = "DBREAKA1",
104 [DBREAKC] = "DBREAKC0",
105 [DBREAKC + 1] = "DBREAKC1",
40643d7c 106 [EPC1] = "EPC1",
b994e91b
MF		 107 [EPC1 + 1] = "EPC2",
108 [EPC1 + 2] = "EPC3",
109 [EPC1 + 3] = "EPC4",
110 [EPC1 + 4] = "EPC5",
111 [EPC1 + 5] = "EPC6",
112 [EPC1 + 6] = "EPC7",
40643d7c 113 [DEPC] = "DEPC",
b994e91b
MF		 114 [EPS2] = "EPS2",
115 [EPS2 + 1] = "EPS3",
116 [EPS2 + 2] = "EPS4",
117 [EPS2 + 3] = "EPS5",
118 [EPS2 + 4] = "EPS6",
119 [EPS2 + 5] = "EPS7",
40643d7c 120 [EXCSAVE1] = "EXCSAVE1",
b994e91b
MF		 121 [EXCSAVE1 + 1] = "EXCSAVE2",
122 [EXCSAVE1 + 2] = "EXCSAVE3",
123 [EXCSAVE1 + 3] = "EXCSAVE4",
124 [EXCSAVE1 + 4] = "EXCSAVE5",
125 [EXCSAVE1 + 5] = "EXCSAVE6",
126 [EXCSAVE1 + 6] = "EXCSAVE7",
f3df4c04 127 [CPENABLE] = "CPENABLE",
b994e91b
MF		 128 [INTSET] = "INTSET",
129 [INTCLEAR] = "INTCLEAR",
130 [INTENABLE] = "INTENABLE",
f0a548b9 131 [PS] = "PS",
97836cee 132 [VECBASE] = "VECBASE",
40643d7c 133 [EXCCAUSE] = "EXCCAUSE",
ab58c5b4 134 [DEBUGCAUSE] = "DEBUGCAUSE",
b994e91b 135 [CCOUNT] = "CCOUNT",
f3df4c04 136 [PRID] = "PRID",
35b5c044
MF		 137 [ICOUNT] = "ICOUNT",
138 [ICOUNTLEVEL] = "ICOUNTLEVEL",
40643d7c 139 [EXCVADDR] = "EXCVADDR",
b994e91b
MF		 140 [CCOMPARE] = "CCOMPARE0",
141 [CCOMPARE + 1] = "CCOMPARE1",
142 [CCOMPARE + 2] = "CCOMPARE2",
2af3da91
MF		 143};
144
145static const char * const uregnames[256] = {
146 [THREADPTR] = "THREADPTR",
147 [FCR] = "FCR",
148 [FSR] = "FSR",
149};
150
2328826b
MF		 151void xtensa_translate_init(void)
152{
dedc5eae
MF		 153 static const char * const regnames[] = {
154 "ar0", "ar1", "ar2", "ar3",
155 "ar4", "ar5", "ar6", "ar7",
156 "ar8", "ar9", "ar10", "ar11",
157 "ar12", "ar13", "ar14", "ar15",
158 };
dd519cbe
MF		 159 static const char * const fregnames[] = {
160 "f0", "f1", "f2", "f3",
161 "f4", "f5", "f6", "f7",
162 "f8", "f9", "f10", "f11",
163 "f12", "f13", "f14", "f15",
164 };
dedc5eae
MF		 165 int i;
166
167 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
168 cpu_pc = tcg_global_mem_new_i32(TCG_AREG0,
97129ac8 169 offsetof(CPUXtensaState, pc), "pc");
dedc5eae
MF		 170
171 for (i = 0; i < 16; i++) {
172 cpu_R[i] = tcg_global_mem_new_i32(TCG_AREG0,
97129ac8 173 offsetof(CPUXtensaState, regs[i]),
dedc5eae
MF		 174 regnames[i]);
175 }
2af3da91 176
dd519cbe
MF		 177 for (i = 0; i < 16; i++) {
178 cpu_FR[i] = tcg_global_mem_new_i32(TCG_AREG0,
179 offsetof(CPUXtensaState, fregs[i]),
180 fregnames[i]);
181 }
182
2af3da91
MF		 183 for (i = 0; i < 256; ++i) {
184 if (sregnames[i]) {
185 cpu_SR[i] = tcg_global_mem_new_i32(TCG_AREG0,
97129ac8 186 offsetof(CPUXtensaState, sregs[i]),
2af3da91
MF		 187 sregnames[i]);
188 }
189 }
190
191 for (i = 0; i < 256; ++i) {
192 if (uregnames[i]) {
193 cpu_UR[i] = tcg_global_mem_new_i32(TCG_AREG0,
97129ac8 194 offsetof(CPUXtensaState, uregs[i]),
2af3da91
MF		 195 uregnames[i]);
196 }
197 }
dedc5eae 198#define GEN_HELPER 2
16c1deae 199#include "helper.h"
dedc5eae
MF		 200}
201
b67ea0cd
MF		 202static inline bool option_bits_enabled(DisasContext *dc, uint64_t opt)
203{
204 return xtensa_option_bits_enabled(dc->config, opt);
205}
206
dedc5eae
MF		 207static inline bool option_enabled(DisasContext *dc, int opt)
208{
209 return xtensa_option_enabled(dc->config, opt);
210}
211
6ad6dbf7
MF		 212static void init_litbase(DisasContext *dc)
213{
214 if (dc->tb->flags & XTENSA_TBFLAG_LITBASE) {
215 dc->litbase = tcg_temp_local_new_i32();
216 tcg_gen_andi_i32(dc->litbase, cpu_SR[LITBASE], 0xfffff000);
217 }
218}
219
220static void reset_litbase(DisasContext *dc)
221{
222 if (dc->tb->flags & XTENSA_TBFLAG_LITBASE) {
223 tcg_temp_free(dc->litbase);
224 }
225}
226
3580ecad
MF		 227static void init_sar_tracker(DisasContext *dc)
228{
229 dc->sar_5bit = false;
230 dc->sar_m32_5bit = false;
231 dc->sar_m32_allocated = false;
232}
233
234static void reset_sar_tracker(DisasContext *dc)
235{
236 if (dc->sar_m32_allocated) {
237 tcg_temp_free(dc->sar_m32);
238 }
239}
240
241static void gen_right_shift_sar(DisasContext *dc, TCGv_i32 sa)
242{
243 tcg_gen_andi_i32(cpu_SR[SAR], sa, 0x1f);
244 if (dc->sar_m32_5bit) {
245 tcg_gen_discard_i32(dc->sar_m32);
246 }
247 dc->sar_5bit = true;
248 dc->sar_m32_5bit = false;
249}
250
251static void gen_left_shift_sar(DisasContext *dc, TCGv_i32 sa)
252{
253 TCGv_i32 tmp = tcg_const_i32(32);
254 if (!dc->sar_m32_allocated) {
255 dc->sar_m32 = tcg_temp_local_new_i32();
256 dc->sar_m32_allocated = true;
257 }
258 tcg_gen_andi_i32(dc->sar_m32, sa, 0x1f);
259 tcg_gen_sub_i32(cpu_SR[SAR], tmp, dc->sar_m32);
260 dc->sar_5bit = false;
261 dc->sar_m32_5bit = true;
262 tcg_temp_free(tmp);
263}
264
b994e91b
MF		 265static void gen_advance_ccount(DisasContext *dc)
266{
267 if (dc->ccount_delta > 0) {
268 TCGv_i32 tmp = tcg_const_i32(dc->ccount_delta);
269 dc->ccount_delta = 0;
f492b82d 270 gen_helper_advance_ccount(cpu_env, tmp);
b994e91b
MF		 271 tcg_temp_free(tmp);
272 }
273}
274
772177c1
MF		 275static void reset_used_window(DisasContext *dc)
276{
277 dc->used_window = 0;
278}
279
b994e91b 280static void gen_exception(DisasContext *dc, int excp)
dedc5eae
MF		 281{
282 TCGv_i32 tmp = tcg_const_i32(excp);
b994e91b 283 gen_advance_ccount(dc);
f492b82d 284 gen_helper_exception(cpu_env, tmp);
dedc5eae
MF		 285 tcg_temp_free(tmp);
286}
287
40643d7c
MF		 288static void gen_exception_cause(DisasContext *dc, uint32_t cause)
289{
290 TCGv_i32 tpc = tcg_const_i32(dc->pc);
291 TCGv_i32 tcause = tcg_const_i32(cause);
b994e91b 292 gen_advance_ccount(dc);
f492b82d 293 gen_helper_exception_cause(cpu_env, tpc, tcause);
40643d7c
MF		 294 tcg_temp_free(tpc);
295 tcg_temp_free(tcause);
6b814719
MF		 296 if (cause == ILLEGAL_INSTRUCTION_CAUSE ||
297 cause == SYSCALL_CAUSE) {
298 dc->is_jmp = DISAS_UPDATE;
299 }
40643d7c
MF		 300}
301
5b4e481b
MF		 302static void gen_exception_cause_vaddr(DisasContext *dc, uint32_t cause,
303 TCGv_i32 vaddr)
304{
305 TCGv_i32 tpc = tcg_const_i32(dc->pc);
306 TCGv_i32 tcause = tcg_const_i32(cause);
b994e91b 307 gen_advance_ccount(dc);
f492b82d 308 gen_helper_exception_cause_vaddr(cpu_env, tpc, tcause, vaddr);
5b4e481b
MF		 309 tcg_temp_free(tpc);
310 tcg_temp_free(tcause);
311}
312
e61dc8f7
MF		 313static void gen_debug_exception(DisasContext *dc, uint32_t cause)
314{
315 TCGv_i32 tpc = tcg_const_i32(dc->pc);
316 TCGv_i32 tcause = tcg_const_i32(cause);
317 gen_advance_ccount(dc);
f492b82d 318 gen_helper_debug_exception(cpu_env, tpc, tcause);
e61dc8f7
MF		 319 tcg_temp_free(tpc);
320 tcg_temp_free(tcause);
321 if (cause & (DEBUGCAUSE_IB | DEBUGCAUSE_BI | DEBUGCAUSE_BN)) {
322 dc->is_jmp = DISAS_UPDATE;
323 }
324}
325
40643d7c
MF		 326static void gen_check_privilege(DisasContext *dc)
327{
328 if (dc->cring) {
329 gen_exception_cause(dc, PRIVILEGED_CAUSE);
6b814719 330 dc->is_jmp = DISAS_UPDATE;
40643d7c
MF		 331 }
332}
333
dedc5eae
MF		 334static void gen_jump_slot(DisasContext *dc, TCGv dest, int slot)
335{
336 tcg_gen_mov_i32(cpu_pc, dest);
35b5c044
MF		 337 gen_advance_ccount(dc);
338 if (dc->icount) {
339 tcg_gen_mov_i32(cpu_SR[ICOUNT], dc->next_icount);
340 }
dedc5eae 341 if (dc->singlestep_enabled) {
b994e91b 342 gen_exception(dc, EXCP_DEBUG);
dedc5eae
MF		 343 } else {
344 if (slot >= 0) {
345 tcg_gen_goto_tb(slot);
346 tcg_gen_exit_tb((tcg_target_long)dc->tb + slot);
347 } else {
348 tcg_gen_exit_tb(0);
349 }
350 }
351 dc->is_jmp = DISAS_UPDATE;
352}
353
67882fd1
MF		 354static void gen_jump(DisasContext *dc, TCGv dest)
355{
356 gen_jump_slot(dc, dest, -1);
357}
358
dedc5eae
MF		 359static void gen_jumpi(DisasContext *dc, uint32_t dest, int slot)
360{
361 TCGv_i32 tmp = tcg_const_i32(dest);
362 if (((dc->pc ^ dest) & TARGET_PAGE_MASK) != 0) {
363 slot = -1;
364 }
365 gen_jump_slot(dc, tmp, slot);
366 tcg_temp_free(tmp);
367}
368
553e44f9
MF		 369static void gen_callw_slot(DisasContext *dc, int callinc, TCGv_i32 dest,
370 int slot)
371{
372 TCGv_i32 tcallinc = tcg_const_i32(callinc);
373
374 tcg_gen_deposit_i32(cpu_SR[PS], cpu_SR[PS],
375 tcallinc, PS_CALLINC_SHIFT, PS_CALLINC_LEN);
376 tcg_temp_free(tcallinc);
377 tcg_gen_movi_i32(cpu_R[callinc << 2],
378 (callinc << 30) | (dc->next_pc & 0x3fffffff));
379 gen_jump_slot(dc, dest, slot);
380}
381
382static void gen_callw(DisasContext *dc, int callinc, TCGv_i32 dest)
383{
384 gen_callw_slot(dc, callinc, dest, -1);
385}
386
387static void gen_callwi(DisasContext *dc, int callinc, uint32_t dest, int slot)
388{
389 TCGv_i32 tmp = tcg_const_i32(dest);
390 if (((dc->pc ^ dest) & TARGET_PAGE_MASK) != 0) {
391 slot = -1;
392 }
393 gen_callw_slot(dc, callinc, tmp, slot);
394 tcg_temp_free(tmp);
395}
396
797d780b
MF		 397static bool gen_check_loop_end(DisasContext *dc, int slot)
398{
399 if (option_enabled(dc, XTENSA_OPTION_LOOP) &&
400 !(dc->tb->flags & XTENSA_TBFLAG_EXCM) &&
401 dc->next_pc == dc->lend) {
402 int label = gen_new_label();
403
d865f307 404 gen_advance_ccount(dc);
797d780b
MF		 405 tcg_gen_brcondi_i32(TCG_COND_EQ, cpu_SR[LCOUNT], 0, label);
406 tcg_gen_subi_i32(cpu_SR[LCOUNT], cpu_SR[LCOUNT], 1);
407 gen_jumpi(dc, dc->lbeg, slot);
408 gen_set_label(label);
409 gen_jumpi(dc, dc->next_pc, -1);
410 return true;
411 }
412 return false;
413}
414
415static void gen_jumpi_check_loop_end(DisasContext *dc, int slot)
416{
417 if (!gen_check_loop_end(dc, slot)) {
418 gen_jumpi(dc, dc->next_pc, slot);
419 }
420}
421
bd57fb91
MF		 422static void gen_brcond(DisasContext *dc, TCGCond cond,
423 TCGv_i32 t0, TCGv_i32 t1, uint32_t offset)
424{
425 int label = gen_new_label();
426
d865f307 427 gen_advance_ccount(dc);
bd57fb91 428 tcg_gen_brcond_i32(cond, t0, t1, label);
797d780b 429 gen_jumpi_check_loop_end(dc, 0);
bd57fb91
MF		 430 gen_set_label(label);
431 gen_jumpi(dc, dc->pc + offset, 1);
432}
433
434static void gen_brcondi(DisasContext *dc, TCGCond cond,
435 TCGv_i32 t0, uint32_t t1, uint32_t offset)
436{
437 TCGv_i32 tmp = tcg_const_i32(t1);
438 gen_brcond(dc, cond, t0, tmp, offset);
439 tcg_temp_free(tmp);
440}
441
b994e91b
MF		 442static void gen_rsr_ccount(DisasContext *dc, TCGv_i32 d, uint32_t sr)
443{
444 gen_advance_ccount(dc);
445 tcg_gen_mov_i32(d, cpu_SR[sr]);
446}
447
b67ea0cd
MF		 448static void gen_rsr_ptevaddr(DisasContext *dc, TCGv_i32 d, uint32_t sr)
449{
450 tcg_gen_shri_i32(d, cpu_SR[EXCVADDR], 10);
451 tcg_gen_or_i32(d, d, cpu_SR[sr]);
452 tcg_gen_andi_i32(d, d, 0xfffffffc);
453}
454
b8132eff
MF		 455static void gen_rsr(DisasContext *dc, TCGv_i32 d, uint32_t sr)
456{
457 static void (* const rsr_handler[256])(DisasContext *dc,
458 TCGv_i32 d, uint32_t sr) = {
b994e91b 459 [CCOUNT] = gen_rsr_ccount,
b67ea0cd 460 [PTEVADDR] = gen_rsr_ptevaddr,
b8132eff
MF		 461 };
462
463 if (sregnames[sr]) {
464 if (rsr_handler[sr]) {
465 rsr_handler[sr](dc, d, sr);
466 } else {
467 tcg_gen_mov_i32(d, cpu_SR[sr]);
468 }
469 } else {
470 qemu_log("RSR %d not implemented, ", sr);
471 }
472}
473
797d780b
MF		 474static void gen_wsr_lbeg(DisasContext *dc, uint32_t sr, TCGv_i32 s)
475{
f492b82d 476 gen_helper_wsr_lbeg(cpu_env, s);
3d0be8a5 477 gen_jumpi_check_loop_end(dc, 0);
797d780b
MF		 478}
479
480static void gen_wsr_lend(DisasContext *dc, uint32_t sr, TCGv_i32 s)
481{
f492b82d 482 gen_helper_wsr_lend(cpu_env, s);
3d0be8a5 483 gen_jumpi_check_loop_end(dc, 0);
797d780b
MF		 484}
485
3580ecad
MF		 486static void gen_wsr_sar(DisasContext *dc, uint32_t sr, TCGv_i32 s)
487{
488 tcg_gen_andi_i32(cpu_SR[sr], s, 0x3f);
489 if (dc->sar_m32_5bit) {
490 tcg_gen_discard_i32(dc->sar_m32);
491 }
492 dc->sar_5bit = false;
493 dc->sar_m32_5bit = false;
494}
495
4dd85b6b
MF		 496static void gen_wsr_br(DisasContext *dc, uint32_t sr, TCGv_i32 s)
497{
498 tcg_gen_andi_i32(cpu_SR[sr], s, 0xffff);
499}
500
6ad6dbf7
MF		 501static void gen_wsr_litbase(DisasContext *dc, uint32_t sr, TCGv_i32 s)
502{
503 tcg_gen_andi_i32(cpu_SR[sr], s, 0xfffff001);
504 /* This can change tb->flags, so exit tb */
505 gen_jumpi_check_loop_end(dc, -1);
506}
507
6825b6c3
MF		 508static void gen_wsr_acchi(DisasContext *dc, uint32_t sr, TCGv_i32 s)
509{
510 tcg_gen_ext8s_i32(cpu_SR[sr], s);
511}
512
553e44f9
MF		 513static void gen_wsr_windowbase(DisasContext *dc, uint32_t sr, TCGv_i32 v)
514{
f492b82d 515 gen_helper_wsr_windowbase(cpu_env, v);
772177c1
MF		 516 reset_used_window(dc);
517}
518
519static void gen_wsr_windowstart(DisasContext *dc, uint32_t sr, TCGv_i32 v)
520{
53a72dfd 521 tcg_gen_andi_i32(cpu_SR[sr], v, (1 << dc->config->nareg / 4) - 1);
772177c1 522 reset_used_window(dc);
553e44f9
MF		 523}
524
b67ea0cd
MF		 525static void gen_wsr_ptevaddr(DisasContext *dc, uint32_t sr, TCGv_i32 v)
526{
527 tcg_gen_andi_i32(cpu_SR[sr], v, 0xffc00000);
528}
529
530static void gen_wsr_rasid(DisasContext *dc, uint32_t sr, TCGv_i32 v)
531{
f492b82d 532 gen_helper_wsr_rasid(cpu_env, v);
b67ea0cd
MF		 533 /* This can change tb->flags, so exit tb */
534 gen_jumpi_check_loop_end(dc, -1);
535}
536
537static void gen_wsr_tlbcfg(DisasContext *dc, uint32_t sr, TCGv_i32 v)
538{
539 tcg_gen_andi_i32(cpu_SR[sr], v, 0x01130000);
540}
541
e61dc8f7
MF		 542static void gen_wsr_ibreakenable(DisasContext *dc, uint32_t sr, TCGv_i32 v)
543{
f492b82d 544 gen_helper_wsr_ibreakenable(cpu_env, v);
e61dc8f7
MF		 545 gen_jumpi_check_loop_end(dc, 0);
546}
547
548static void gen_wsr_ibreaka(DisasContext *dc, uint32_t sr, TCGv_i32 v)
549{
550 unsigned id = sr - IBREAKA;
551
552 if (id < dc->config->nibreak) {
553 TCGv_i32 tmp = tcg_const_i32(id);
f492b82d 554 gen_helper_wsr_ibreaka(cpu_env, tmp, v);
e61dc8f7
MF		 555 tcg_temp_free(tmp);
556 gen_jumpi_check_loop_end(dc, 0);
557 }
558}
559
f14c4b5f
MF		 560static void gen_wsr_dbreaka(DisasContext *dc, uint32_t sr, TCGv_i32 v)
561{
562 unsigned id = sr - DBREAKA;
563
564 if (id < dc->config->ndbreak) {
565 TCGv_i32 tmp = tcg_const_i32(id);
f492b82d 566 gen_helper_wsr_dbreaka(cpu_env, tmp, v);
f14c4b5f
MF		 567 tcg_temp_free(tmp);
568 }
569}
570
571static void gen_wsr_dbreakc(DisasContext *dc, uint32_t sr, TCGv_i32 v)
572{
573 unsigned id = sr - DBREAKC;
574
575 if (id < dc->config->ndbreak) {
576 TCGv_i32 tmp = tcg_const_i32(id);
f492b82d 577 gen_helper_wsr_dbreakc(cpu_env, tmp, v);
f14c4b5f
MF		 578 tcg_temp_free(tmp);
579 }
580}
581
b994e91b
MF		 582static void gen_wsr_intset(DisasContext *dc, uint32_t sr, TCGv_i32 v)
583{
584 tcg_gen_andi_i32(cpu_SR[sr], v,
585 dc->config->inttype_mask[INTTYPE_SOFTWARE]);
586 gen_helper_check_interrupts(cpu_env);
587 gen_jumpi_check_loop_end(dc, 0);
588}
589
590static void gen_wsr_intclear(DisasContext *dc, uint32_t sr, TCGv_i32 v)
591{
592 TCGv_i32 tmp = tcg_temp_new_i32();
593
594 tcg_gen_andi_i32(tmp, v,
595 dc->config->inttype_mask[INTTYPE_EDGE] |
596 dc->config->inttype_mask[INTTYPE_NMI] |
597 dc->config->inttype_mask[INTTYPE_SOFTWARE]);
598 tcg_gen_andc_i32(cpu_SR[INTSET], cpu_SR[INTSET], tmp);
599 tcg_temp_free(tmp);
600 gen_helper_check_interrupts(cpu_env);
601}
602
603static void gen_wsr_intenable(DisasContext *dc, uint32_t sr, TCGv_i32 v)
604{
605 tcg_gen_mov_i32(cpu_SR[sr], v);
606 gen_helper_check_interrupts(cpu_env);
607 gen_jumpi_check_loop_end(dc, 0);
608}
609
f0a548b9
MF		 610static void gen_wsr_ps(DisasContext *dc, uint32_t sr, TCGv_i32 v)
611{
612 uint32_t mask = PS_WOE | PS_CALLINC | PS_OWB |
613 PS_UM | PS_EXCM | PS_INTLEVEL;
614
615 if (option_enabled(dc, XTENSA_OPTION_MMU)) {
616 mask |= PS_RING;
617 }
618 tcg_gen_andi_i32(cpu_SR[sr], v, mask);
772177c1 619 reset_used_window(dc);
b994e91b
MF		 620 gen_helper_check_interrupts(cpu_env);
621 /* This can change mmu index and tb->flags, so exit tb */
797d780b 622 gen_jumpi_check_loop_end(dc, -1);
f0a548b9
MF		 623}
624
ab58c5b4
MF		 625static void gen_wsr_debugcause(DisasContext *dc, uint32_t sr, TCGv_i32 v)
626{
627}
628
f3df4c04
MF		 629static void gen_wsr_prid(DisasContext *dc, uint32_t sr, TCGv_i32 v)
630{
631}
632
35b5c044
MF		 633static void gen_wsr_icount(DisasContext *dc, uint32_t sr, TCGv_i32 v)
634{
635 if (dc->icount) {
636 tcg_gen_mov_i32(dc->next_icount, v);
637 } else {
638 tcg_gen_mov_i32(cpu_SR[sr], v);
639 }
640}
641
642static void gen_wsr_icountlevel(DisasContext *dc, uint32_t sr, TCGv_i32 v)
643{
644 tcg_gen_andi_i32(cpu_SR[sr], v, 0xf);
645 /* This can change tb->flags, so exit tb */
646 gen_jumpi_check_loop_end(dc, -1);
647}
648
b994e91b
MF		 649static void gen_wsr_ccompare(DisasContext *dc, uint32_t sr, TCGv_i32 v)
650{
651 uint32_t id = sr - CCOMPARE;
652 if (id < dc->config->nccompare) {
653 uint32_t int_bit = 1 << dc->config->timerint[id];
654 gen_advance_ccount(dc);
655 tcg_gen_mov_i32(cpu_SR[sr], v);
656 tcg_gen_andi_i32(cpu_SR[INTSET], cpu_SR[INTSET], ~int_bit);
657 gen_helper_check_interrupts(cpu_env);
658 }
659}
660
b8132eff
MF		 661static void gen_wsr(DisasContext *dc, uint32_t sr, TCGv_i32 s)
662{
663 static void (* const wsr_handler[256])(DisasContext *dc,
664 uint32_t sr, TCGv_i32 v) = {
797d780b
MF		 665 [LBEG] = gen_wsr_lbeg,
666 [LEND] = gen_wsr_lend,
3580ecad 667 [SAR] = gen_wsr_sar,
4dd85b6b 668 [BR] = gen_wsr_br,
6ad6dbf7 669 [LITBASE] = gen_wsr_litbase,
6825b6c3 670 [ACCHI] = gen_wsr_acchi,
553e44f9 671 [WINDOW_BASE] = gen_wsr_windowbase,
772177c1 672 [WINDOW_START] = gen_wsr_windowstart,
b67ea0cd
MF		 673 [PTEVADDR] = gen_wsr_ptevaddr,
674 [RASID] = gen_wsr_rasid,
675 [ITLBCFG] = gen_wsr_tlbcfg,
676 [DTLBCFG] = gen_wsr_tlbcfg,
e61dc8f7
MF		 677 [IBREAKENABLE] = gen_wsr_ibreakenable,
678 [IBREAKA] = gen_wsr_ibreaka,
679 [IBREAKA + 1] = gen_wsr_ibreaka,
f14c4b5f
MF		 680 [DBREAKA] = gen_wsr_dbreaka,
681 [DBREAKA + 1] = gen_wsr_dbreaka,
682 [DBREAKC] = gen_wsr_dbreakc,
683 [DBREAKC + 1] = gen_wsr_dbreakc,
b994e91b
MF		 684 [INTSET] = gen_wsr_intset,
685 [INTCLEAR] = gen_wsr_intclear,
686 [INTENABLE] = gen_wsr_intenable,
f0a548b9 687 [PS] = gen_wsr_ps,
ab58c5b4 688 [DEBUGCAUSE] = gen_wsr_debugcause,
f3df4c04 689 [PRID] = gen_wsr_prid,
35b5c044
MF		 690 [ICOUNT] = gen_wsr_icount,
691 [ICOUNTLEVEL] = gen_wsr_icountlevel,
b994e91b
MF		 692 [CCOMPARE] = gen_wsr_ccompare,
693 [CCOMPARE + 1] = gen_wsr_ccompare,
694 [CCOMPARE + 2] = gen_wsr_ccompare,
b8132eff
MF		 695 };
696
697 if (sregnames[sr]) {
698 if (wsr_handler[sr]) {
699 wsr_handler[sr](dc, sr, s);
700 } else {
701 tcg_gen_mov_i32(cpu_SR[sr], s);
702 }
703 } else {
704 qemu_log("WSR %d not implemented, ", sr);
705 }
706}
707
dd519cbe
MF		 708static void gen_wur(uint32_t ur, TCGv_i32 s)
709{
710 switch (ur) {
711 case FCR:
712 gen_helper_wur_fcr(cpu_env, s);
713 break;
714
715 case FSR:
716 tcg_gen_andi_i32(cpu_UR[ur], s, 0xffffff80);
717 break;
718
719 default:
720 tcg_gen_mov_i32(cpu_UR[ur], s);
721 break;
722 }
723}
724
5b4e481b
MF		 725static void gen_load_store_alignment(DisasContext *dc, int shift,
726 TCGv_i32 addr, bool no_hw_alignment)
727{
728 if (!option_enabled(dc, XTENSA_OPTION_UNALIGNED_EXCEPTION)) {
729 tcg_gen_andi_i32(addr, addr, ~0 << shift);
730 } else if (option_enabled(dc, XTENSA_OPTION_HW_ALIGNMENT) &&
731 no_hw_alignment) {
732 int label = gen_new_label();
733 TCGv_i32 tmp = tcg_temp_new_i32();
734 tcg_gen_andi_i32(tmp, addr, ~(~0 << shift));
735 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, label);
736 gen_exception_cause_vaddr(dc, LOAD_STORE_ALIGNMENT_CAUSE, addr);
737 gen_set_label(label);
738 tcg_temp_free(tmp);
739 }
740}
741
b994e91b
MF		 742static void gen_waiti(DisasContext *dc, uint32_t imm4)
743{
744 TCGv_i32 pc = tcg_const_i32(dc->next_pc);
745 TCGv_i32 intlevel = tcg_const_i32(imm4);
746 gen_advance_ccount(dc);
f492b82d 747 gen_helper_waiti(cpu_env, pc, intlevel);
b994e91b
MF		 748 tcg_temp_free(pc);
749 tcg_temp_free(intlevel);
750}
751
772177c1
MF		 752static void gen_window_check1(DisasContext *dc, unsigned r1)
753{
754 if (dc->tb->flags & XTENSA_TBFLAG_EXCM) {
755 return;
756 }
757 if (option_enabled(dc, XTENSA_OPTION_WINDOWED_REGISTER) &&
758 r1 / 4 > dc->used_window) {
759 TCGv_i32 pc = tcg_const_i32(dc->pc);
760 TCGv_i32 w = tcg_const_i32(r1 / 4);
761
762 dc->used_window = r1 / 4;
763 gen_advance_ccount(dc);
f492b82d 764 gen_helper_window_check(cpu_env, pc, w);
772177c1
MF		 765
766 tcg_temp_free(w);
767 tcg_temp_free(pc);
768 }
769}
770
771static void gen_window_check2(DisasContext *dc, unsigned r1, unsigned r2)
772{
773 gen_window_check1(dc, r1 > r2 ? r1 : r2);
774}
775
776static void gen_window_check3(DisasContext *dc, unsigned r1, unsigned r2,
777 unsigned r3)
778{
779 gen_window_check2(dc, r1, r2 > r3 ? r2 : r3);
780}
781
6825b6c3
MF		 782static TCGv_i32 gen_mac16_m(TCGv_i32 v, bool hi, bool is_unsigned)
783{
784 TCGv_i32 m = tcg_temp_new_i32();
785
786 if (hi) {
787 (is_unsigned ? tcg_gen_shri_i32 : tcg_gen_sari_i32)(m, v, 16);
788 } else {
789 (is_unsigned ? tcg_gen_ext16u_i32 : tcg_gen_ext16s_i32)(m, v);
790 }
791 return m;
792}
793
dedc5eae
MF		 794static void disas_xtensa_insn(DisasContext *dc)
795{
b67ea0cd
MF		 796#define HAS_OPTION_BITS(opt) do { \
797 if (!option_bits_enabled(dc, opt)) { \
798 qemu_log("Option is not enabled %s:%d\n", \
799 __FILE__, __LINE__); \
dedc5eae
MF		 800 goto invalid_opcode; \
801 } \
802 } while (0)
803
b67ea0cd
MF		 804#define HAS_OPTION(opt) HAS_OPTION_BITS(XTENSA_OPTION_BIT(opt))
805
91a5bb76
MF		 806#define TBD() qemu_log("TBD(pc = %08x): %s:%d\n", dc->pc, __FILE__, __LINE__)
807#define RESERVED() do { \
808 qemu_log("RESERVED(pc = %08x, %02x%02x%02x): %s:%d\n", \
809 dc->pc, b0, b1, b2, __FILE__, __LINE__); \
810 goto invalid_opcode; \
811 } while (0)
812
813
dedc5eae
MF		 814#ifdef TARGET_WORDS_BIGENDIAN
815#define OP0 (((b0) & 0xf0) >> 4)
816#define OP1 (((b2) & 0xf0) >> 4)
817#define OP2 ((b2) & 0xf)
818#define RRR_R ((b1) & 0xf)
819#define RRR_S (((b1) & 0xf0) >> 4)
820#define RRR_T ((b0) & 0xf)
821#else
822#define OP0 (((b0) & 0xf))
823#define OP1 (((b2) & 0xf))
824#define OP2 (((b2) & 0xf0) >> 4)
825#define RRR_R (((b1) & 0xf0) >> 4)
826#define RRR_S (((b1) & 0xf))
827#define RRR_T (((b0) & 0xf0) >> 4)
828#endif
6825b6c3
MF		 829#define RRR_X ((RRR_R & 0x4) >> 2)
830#define RRR_Y ((RRR_T & 0x4) >> 2)
831#define RRR_W (RRR_R & 0x3)
dedc5eae
MF		 832
833#define RRRN_R RRR_R
834#define RRRN_S RRR_S
835#define RRRN_T RRR_T
836
837#define RRI8_R RRR_R
838#define RRI8_S RRR_S
839#define RRI8_T RRR_T
840#define RRI8_IMM8 (b2)
841#define RRI8_IMM8_SE ((((b2) & 0x80) ? 0xffffff00 : 0) | RRI8_IMM8)
842
843#ifdef TARGET_WORDS_BIGENDIAN
844#define RI16_IMM16 (((b1) << 8) | (b2))
845#else
846#define RI16_IMM16 (((b2) << 8) | (b1))
847#endif
848
849#ifdef TARGET_WORDS_BIGENDIAN
850#define CALL_N (((b0) & 0xc) >> 2)
851#define CALL_OFFSET ((((b0) & 0x3) << 16) | ((b1) << 8) | (b2))
852#else
853#define CALL_N (((b0) & 0x30) >> 4)
854#define CALL_OFFSET ((((b0) & 0xc0) >> 6) | ((b1) << 2) | ((b2) << 10))
855#endif
856#define CALL_OFFSET_SE \
857 (((CALL_OFFSET & 0x20000) ? 0xfffc0000 : 0) | CALL_OFFSET)
858
859#define CALLX_N CALL_N
860#ifdef TARGET_WORDS_BIGENDIAN
861#define CALLX_M ((b0) & 0x3)
862#else
863#define CALLX_M (((b0) & 0xc0) >> 6)
864#endif
865#define CALLX_S RRR_S
866
867#define BRI12_M CALLX_M
868#define BRI12_S RRR_S
869#ifdef TARGET_WORDS_BIGENDIAN
870#define BRI12_IMM12 ((((b1) & 0xf) << 8) | (b2))
871#else
872#define BRI12_IMM12 ((((b1) & 0xf0) >> 4) | ((b2) << 4))
873#endif
874#define BRI12_IMM12_SE (((BRI12_IMM12 & 0x800) ? 0xfffff000 : 0) | BRI12_IMM12)
875
876#define BRI8_M BRI12_M
877#define BRI8_R RRI8_R
878#define BRI8_S RRI8_S
879#define BRI8_IMM8 RRI8_IMM8
880#define BRI8_IMM8_SE RRI8_IMM8_SE
881
882#define RSR_SR (b1)
883
f492b82d
MF		 884 uint8_t b0 = cpu_ldub_code(cpu_single_env, dc->pc);
885 uint8_t b1 = cpu_ldub_code(cpu_single_env, dc->pc + 1);
a044ec2a 886 uint8_t b2 = 0;
dedc5eae 887
bd57fb91
MF		 888 static const uint32_t B4CONST[] = {
889 0xffffffff, 1, 2, 3, 4, 5, 6, 7, 8, 10, 12, 16, 32, 64, 128, 256
890 };
891
892 static const uint32_t B4CONSTU[] = {
893 32768, 65536, 2, 3, 4, 5, 6, 7, 8, 10, 12, 16, 32, 64, 128, 256
894 };
895
dedc5eae
MF		 896 if (OP0 >= 8) {
897 dc->next_pc = dc->pc + 2;
898 HAS_OPTION(XTENSA_OPTION_CODE_DENSITY);
899 } else {
900 dc->next_pc = dc->pc + 3;
f492b82d 901 b2 = cpu_ldub_code(cpu_single_env, dc->pc + 2);
dedc5eae
MF		 902 }
903
904 switch (OP0) {
905 case 0: /*QRST*/
906 switch (OP1) {
907 case 0: /*RST0*/
908 switch (OP2) {
909 case 0: /*ST0*/
910 if ((RRR_R & 0xc) == 0x8) {
911 HAS_OPTION(XTENSA_OPTION_BOOLEAN);
912 }
913
914 switch (RRR_R) {
915 case 0: /*SNM0*/
5da4a6a8
MF		 916 switch (CALLX_M) {
917 case 0: /*ILL*/
40643d7c 918 gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);
5da4a6a8
MF		 919 break;
920
921 case 1: /*reserved*/
91a5bb76 922 RESERVED();
5da4a6a8
MF		 923 break;
924
925 case 2: /*JR*/
926 switch (CALLX_N) {
927 case 0: /*RET*/
928 case 2: /*JX*/
772177c1 929 gen_window_check1(dc, CALLX_S);
5da4a6a8
MF		 930 gen_jump(dc, cpu_R[CALLX_S]);
931 break;
932
933 case 1: /*RETWw*/
934 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
553e44f9
MF		 935 {
936 TCGv_i32 tmp = tcg_const_i32(dc->pc);
b994e91b 937 gen_advance_ccount(dc);
f492b82d 938 gen_helper_retw(tmp, cpu_env, tmp);
553e44f9
MF		 939 gen_jump(dc, tmp);
940 tcg_temp_free(tmp);
941 }
5da4a6a8
MF		 942 break;
943
944 case 3: /*reserved*/
91a5bb76 945 RESERVED();
5da4a6a8
MF		 946 break;
947 }
948 break;
949
950 case 3: /*CALLX*/
772177c1 951 gen_window_check2(dc, CALLX_S, CALLX_N << 2);
5da4a6a8
MF		 952 switch (CALLX_N) {
953 case 0: /*CALLX0*/
954 {
955 TCGv_i32 tmp = tcg_temp_new_i32();
956 tcg_gen_mov_i32(tmp, cpu_R[CALLX_S]);
957 tcg_gen_movi_i32(cpu_R[0], dc->next_pc);
958 gen_jump(dc, tmp);
959 tcg_temp_free(tmp);
960 }
961 break;
962
963 case 1: /*CALLX4w*/
964 case 2: /*CALLX8w*/
965 case 3: /*CALLX12w*/
966 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
553e44f9
MF		 967 {
968 TCGv_i32 tmp = tcg_temp_new_i32();
969
970 tcg_gen_mov_i32(tmp, cpu_R[CALLX_S]);
971 gen_callw(dc, CALLX_N, tmp);
972 tcg_temp_free(tmp);
973 }
5da4a6a8
MF		 974 break;
975 }
976 break;
977 }
dedc5eae
MF		 978 break;
979
980 case 1: /*MOVSPw*/
981 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
772177c1 982 gen_window_check2(dc, RRR_T, RRR_S);
553e44f9
MF		 983 {
984 TCGv_i32 pc = tcg_const_i32(dc->pc);
b994e91b 985 gen_advance_ccount(dc);
f492b82d 986 gen_helper_movsp(cpu_env, pc);
553e44f9
MF		 987 tcg_gen_mov_i32(cpu_R[RRR_T], cpu_R[RRR_S]);
988 tcg_temp_free(pc);
989 }
dedc5eae
MF		 990 break;
991
992 case 2: /*SYNC*/
28067b22
MF		 993 switch (RRR_T) {
994 case 0: /*ISYNC*/
995 break;
996
997 case 1: /*RSYNC*/
998 break;
999
1000 case 2: /*ESYNC*/
1001 break;
1002
1003 case 3: /*DSYNC*/
1004 break;
1005
1006 case 8: /*EXCW*/
1007 HAS_OPTION(XTENSA_OPTION_EXCEPTION);
1008 break;
1009
1010 case 12: /*MEMW*/
1011 break;
1012
1013 case 13: /*EXTW*/
1014 break;
1015
1016 case 15: /*NOP*/
1017 break;
1018
1019 default: /*reserved*/
1020 RESERVED();
1021 break;
1022 }
91a5bb76
MF		 1023 break;
1024
1025 case 3: /*RFEIx*/
40643d7c
MF		 1026 switch (RRR_T) {
1027 case 0: /*RFETx*/
1028 HAS_OPTION(XTENSA_OPTION_EXCEPTION);
1029 switch (RRR_S) {
1030 case 0: /*RFEx*/
1031 gen_check_privilege(dc);
1032 tcg_gen_andi_i32(cpu_SR[PS], cpu_SR[PS], ~PS_EXCM);
b994e91b 1033 gen_helper_check_interrupts(cpu_env);
40643d7c
MF		 1034 gen_jump(dc, cpu_SR[EPC1]);
1035 break;
1036
1037 case 1: /*RFUEx*/
1038 RESERVED();
1039 break;
1040
1041 case 2: /*RFDEx*/
1042 gen_check_privilege(dc);
1043 gen_jump(dc, cpu_SR[
1044 dc->config->ndepc ? DEPC : EPC1]);
1045 break;
1046
1047 case 4: /*RFWOw*/
1048 case 5: /*RFWUw*/
1049 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
553e44f9
MF		 1050 gen_check_privilege(dc);
1051 {
1052 TCGv_i32 tmp = tcg_const_i32(1);
1053
1054 tcg_gen_andi_i32(
1055 cpu_SR[PS], cpu_SR[PS], ~PS_EXCM);
1056 tcg_gen_shl_i32(tmp, tmp, cpu_SR[WINDOW_BASE]);
1057
1058 if (RRR_S == 4) {
1059 tcg_gen_andc_i32(cpu_SR[WINDOW_START],
1060 cpu_SR[WINDOW_START], tmp);
1061 } else {
1062 tcg_gen_or_i32(cpu_SR[WINDOW_START],
1063 cpu_SR[WINDOW_START], tmp);
1064 }
1065
f492b82d 1066 gen_helper_restore_owb(cpu_env);
b994e91b 1067 gen_helper_check_interrupts(cpu_env);
553e44f9
MF		 1068 gen_jump(dc, cpu_SR[EPC1]);
1069
1070 tcg_temp_free(tmp);
1071 }
40643d7c
MF		 1072 break;
1073
1074 default: /*reserved*/
1075 RESERVED();
1076 break;
1077 }
1078 break;
1079
1080 case 1: /*RFIx*/
1081 HAS_OPTION(XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT);
b994e91b
MF		 1082 if (RRR_S >= 2 && RRR_S <= dc->config->nlevel) {
1083 gen_check_privilege(dc);
1084 tcg_gen_mov_i32(cpu_SR[PS],
1085 cpu_SR[EPS2 + RRR_S - 2]);
1086 gen_helper_check_interrupts(cpu_env);
1087 gen_jump(dc, cpu_SR[EPC1 + RRR_S - 1]);
1088 } else {
1089 qemu_log("RFI %d is illegal\n", RRR_S);
1090 gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);
1091 }
40643d7c
MF		 1092 break;
1093
1094 case 2: /*RFME*/
1095 TBD();
1096 break;
1097
1098 default: /*reserved*/
1099 RESERVED();
1100 break;
1101
1102 }
91a5bb76
MF		 1103 break;
1104
1105 case 4: /*BREAKx*/
e61dc8f7
MF		 1106 HAS_OPTION(XTENSA_OPTION_DEBUG);
1107 if (dc->debug) {
1108 gen_debug_exception(dc, DEBUGCAUSE_BI);
1109 }
91a5bb76
MF		 1110 break;
1111
1112 case 5: /*SYSCALLx*/
1113 HAS_OPTION(XTENSA_OPTION_EXCEPTION);
40643d7c
MF		 1114 switch (RRR_S) {
1115 case 0: /*SYSCALLx*/
1116 gen_exception_cause(dc, SYSCALL_CAUSE);
1117 break;
1118
1119 case 1: /*SIMCALL*/
1ddeaa5d
MF		 1120 if (semihosting_enabled) {
1121 gen_check_privilege(dc);
1122 gen_helper_simcall(cpu_env);
1123 } else {
1124 qemu_log("SIMCALL but semihosting is disabled\n");
1125 gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);
1126 }
40643d7c
MF		 1127 break;
1128
1129 default:
1130 RESERVED();
1131 break;
1132 }
91a5bb76
MF		 1133 break;
1134
1135 case 6: /*RSILx*/
1136 HAS_OPTION(XTENSA_OPTION_INTERRUPT);
40643d7c 1137 gen_check_privilege(dc);
772177c1 1138 gen_window_check1(dc, RRR_T);
40643d7c 1139 tcg_gen_mov_i32(cpu_R[RRR_T], cpu_SR[PS]);
b994e91b 1140 tcg_gen_andi_i32(cpu_SR[PS], cpu_SR[PS], ~PS_INTLEVEL);
40643d7c 1141 tcg_gen_ori_i32(cpu_SR[PS], cpu_SR[PS], RRR_S);
b994e91b
MF		 1142 gen_helper_check_interrupts(cpu_env);
1143 gen_jumpi_check_loop_end(dc, 0);
91a5bb76
MF		 1144 break;
1145
1146 case 7: /*WAITIx*/
1147 HAS_OPTION(XTENSA_OPTION_INTERRUPT);
b994e91b
MF		 1148 gen_check_privilege(dc);
1149 gen_waiti(dc, RRR_S);
91a5bb76
MF		 1150 break;
1151
1152 case 8: /*ANY4p*/
91a5bb76 1153 case 9: /*ALL4p*/
91a5bb76 1154 case 10: /*ANY8p*/
91a5bb76
MF		 1155 case 11: /*ALL8p*/
1156 HAS_OPTION(XTENSA_OPTION_BOOLEAN);
4dd85b6b
MF		 1157 {
1158 const unsigned shift = (RRR_R & 2) ? 8 : 4;
1159 TCGv_i32 mask = tcg_const_i32(
1160 ((1 << shift) - 1) << RRR_S);
1161 TCGv_i32 tmp = tcg_temp_new_i32();
1162
1163 tcg_gen_and_i32(tmp, cpu_SR[BR], mask);
1164 if (RRR_R & 1) { /*ALL*/
1165 tcg_gen_addi_i32(tmp, tmp, 1 << RRR_S);
1166 } else { /*ANY*/
1167 tcg_gen_add_i32(tmp, tmp, mask);
1168 }
1169 tcg_gen_shri_i32(tmp, tmp, RRR_S + shift);
1170 tcg_gen_deposit_i32(cpu_SR[BR], cpu_SR[BR],
1171 tmp, RRR_T, 1);
1172 tcg_temp_free(mask);
1173 tcg_temp_free(tmp);
1174 }
91a5bb76
MF		 1175 break;
1176
1177 default: /*reserved*/
1178 RESERVED();
dedc5eae
MF		 1179 break;
1180
1181 }
1182 break;
1183
1184 case 1: /*AND*/
772177c1 1185 gen_window_check3(dc, RRR_R, RRR_S, RRR_T);
dedc5eae
MF		 1186 tcg_gen_and_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
1187 break;
1188
1189 case 2: /*OR*/
772177c1 1190 gen_window_check3(dc, RRR_R, RRR_S, RRR_T);
dedc5eae
MF		 1191 tcg_gen_or_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
1192 break;
1193
1194 case 3: /*XOR*/
772177c1 1195 gen_window_check3(dc, RRR_R, RRR_S, RRR_T);
dedc5eae
MF		 1196 tcg_gen_xor_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
1197 break;
1198
1199 case 4: /*ST1*/
3580ecad
MF		 1200 switch (RRR_R) {
1201 case 0: /*SSR*/
772177c1 1202 gen_window_check1(dc, RRR_S);
3580ecad
MF		 1203 gen_right_shift_sar(dc, cpu_R[RRR_S]);
1204 break;
1205
1206 case 1: /*SSL*/
772177c1 1207 gen_window_check1(dc, RRR_S);
3580ecad
MF		 1208 gen_left_shift_sar(dc, cpu_R[RRR_S]);
1209 break;
1210
1211 case 2: /*SSA8L*/
772177c1 1212 gen_window_check1(dc, RRR_S);
3580ecad
MF		 1213 {
1214 TCGv_i32 tmp = tcg_temp_new_i32();
1215 tcg_gen_shli_i32(tmp, cpu_R[RRR_S], 3);
1216 gen_right_shift_sar(dc, tmp);
1217 tcg_temp_free(tmp);
1218 }
1219 break;
1220
1221 case 3: /*SSA8B*/
772177c1 1222 gen_window_check1(dc, RRR_S);
3580ecad
MF		 1223 {
1224 TCGv_i32 tmp = tcg_temp_new_i32();
1225 tcg_gen_shli_i32(tmp, cpu_R[RRR_S], 3);
1226 gen_left_shift_sar(dc, tmp);
1227 tcg_temp_free(tmp);
1228 }
1229 break;
1230
1231 case 4: /*SSAI*/
1232 {
1233 TCGv_i32 tmp = tcg_const_i32(
1234 RRR_S | ((RRR_T & 1) << 4));
1235 gen_right_shift_sar(dc, tmp);
1236 tcg_temp_free(tmp);
1237 }
1238 break;
1239
1240 case 6: /*RER*/
91a5bb76 1241 TBD();
3580ecad
MF		 1242 break;
1243
1244 case 7: /*WER*/
91a5bb76 1245 TBD();
3580ecad
MF		 1246 break;
1247
1248 case 8: /*ROTWw*/
1249 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
553e44f9
MF		 1250 gen_check_privilege(dc);
1251 {
1252 TCGv_i32 tmp = tcg_const_i32(
1253 RRR_T | ((RRR_T & 8) ? 0xfffffff0 : 0));
f492b82d 1254 gen_helper_rotw(cpu_env, tmp);
553e44f9 1255 tcg_temp_free(tmp);
772177c1 1256 reset_used_window(dc);
553e44f9 1257 }
3580ecad
MF		 1258 break;
1259
1260 case 14: /*NSAu*/
7f65f4b0 1261 HAS_OPTION(XTENSA_OPTION_MISC_OP_NSA);
772177c1 1262 gen_window_check2(dc, RRR_S, RRR_T);
3580ecad
MF		 1263 gen_helper_nsa(cpu_R[RRR_T], cpu_R[RRR_S]);
1264 break;
1265
1266 case 15: /*NSAUu*/
7f65f4b0 1267 HAS_OPTION(XTENSA_OPTION_MISC_OP_NSA);
772177c1 1268 gen_window_check2(dc, RRR_S, RRR_T);
3580ecad
MF		 1269 gen_helper_nsau(cpu_R[RRR_T], cpu_R[RRR_S]);
1270 break;
1271
1272 default: /*reserved*/
91a5bb76 1273 RESERVED();
3580ecad
MF		 1274 break;
1275 }
dedc5eae
MF		 1276 break;
1277
1278 case 5: /*TLB*/
b67ea0cd
MF		 1279 HAS_OPTION_BITS(
1280 XTENSA_OPTION_BIT(XTENSA_OPTION_MMU) |
1281 XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_PROTECTION) |
1282 XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_TRANSLATION));
1283 gen_check_privilege(dc);
1284 gen_window_check2(dc, RRR_S, RRR_T);
1285 {
1286 TCGv_i32 dtlb = tcg_const_i32((RRR_R & 8) != 0);
1287
1288 switch (RRR_R & 7) {
1289 case 3: /*RITLB0*/ /*RDTLB0*/
f492b82d
MF		 1290 gen_helper_rtlb0(cpu_R[RRR_T],
1291 cpu_env, cpu_R[RRR_S], dtlb);
b67ea0cd
MF		 1292 break;
1293
1294 case 4: /*IITLB*/ /*IDTLB*/
f492b82d 1295 gen_helper_itlb(cpu_env, cpu_R[RRR_S], dtlb);
b67ea0cd
MF		 1296 /* This could change memory mapping, so exit tb */
1297 gen_jumpi_check_loop_end(dc, -1);
1298 break;
1299
1300 case 5: /*PITLB*/ /*PDTLB*/
1301 tcg_gen_movi_i32(cpu_pc, dc->pc);
f492b82d
MF		 1302 gen_helper_ptlb(cpu_R[RRR_T],
1303 cpu_env, cpu_R[RRR_S], dtlb);
b67ea0cd
MF		 1304 break;
1305
1306 case 6: /*WITLB*/ /*WDTLB*/
f492b82d
MF		 1307 gen_helper_wtlb(
1308 cpu_env, cpu_R[RRR_T], cpu_R[RRR_S], dtlb);
b67ea0cd
MF		 1309 /* This could change memory mapping, so exit tb */
1310 gen_jumpi_check_loop_end(dc, -1);
1311 break;
1312
1313 case 7: /*RITLB1*/ /*RDTLB1*/
f492b82d
MF		 1314 gen_helper_rtlb1(cpu_R[RRR_T],
1315 cpu_env, cpu_R[RRR_S], dtlb);
b67ea0cd
MF		 1316 break;
1317
1318 default:
1319 tcg_temp_free(dtlb);
1320 RESERVED();
1321 break;
1322 }
1323 tcg_temp_free(dtlb);
1324 }
dedc5eae
MF		 1325 break;
1326
1327 case 6: /*RT0*/
772177c1 1328 gen_window_check2(dc, RRR_R, RRR_T);
f331fe5e
MF		 1329 switch (RRR_S) {
1330 case 0: /*NEG*/
1331 tcg_gen_neg_i32(cpu_R[RRR_R], cpu_R[RRR_T]);
1332 break;
1333
1334 case 1: /*ABS*/
1335 {
1336 int label = gen_new_label();
1337 tcg_gen_mov_i32(cpu_R[RRR_R], cpu_R[RRR_T]);
1338 tcg_gen_brcondi_i32(
1339 TCG_COND_GE, cpu_R[RRR_R], 0, label);
1340 tcg_gen_neg_i32(cpu_R[RRR_R], cpu_R[RRR_T]);
1341 gen_set_label(label);
1342 }
1343 break;
1344
1345 default: /*reserved*/
91a5bb76 1346 RESERVED();
f331fe5e
MF		 1347 break;
1348 }
dedc5eae
MF		 1349 break;
1350
1351 case 7: /*reserved*/
91a5bb76 1352 RESERVED();
dedc5eae
MF		 1353 break;
1354
1355 case 8: /*ADD*/
772177c1 1356 gen_window_check3(dc, RRR_R, RRR_S, RRR_T);
dedc5eae
MF		 1357 tcg_gen_add_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
1358 break;
1359
1360 case 9: /*ADD**/
1361 case 10:
1362 case 11:
772177c1 1363 gen_window_check3(dc, RRR_R, RRR_S, RRR_T);
dedc5eae
MF		 1364 {
1365 TCGv_i32 tmp = tcg_temp_new_i32();
1366 tcg_gen_shli_i32(tmp, cpu_R[RRR_S], OP2 - 8);
1367 tcg_gen_add_i32(cpu_R[RRR_R], tmp, cpu_R[RRR_T]);
1368 tcg_temp_free(tmp);
1369 }
1370 break;
1371
1372 case 12: /*SUB*/
772177c1 1373 gen_window_check3(dc, RRR_R, RRR_S, RRR_T);
dedc5eae
MF		 1374 tcg_gen_sub_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
1375 break;
1376
1377 case 13: /*SUB**/
1378 case 14:
1379 case 15:
772177c1 1380 gen_window_check3(dc, RRR_R, RRR_S, RRR_T);
dedc5eae
MF		 1381 {
1382 TCGv_i32 tmp = tcg_temp_new_i32();
1383 tcg_gen_shli_i32(tmp, cpu_R[RRR_S], OP2 - 12);
1384 tcg_gen_sub_i32(cpu_R[RRR_R], tmp, cpu_R[RRR_T]);
1385 tcg_temp_free(tmp);
1386 }
1387 break;
1388 }
1389 break;
1390
1391 case 1: /*RST1*/
3580ecad
MF		 1392 switch (OP2) {
1393 case 0: /*SLLI*/
1394 case 1:
772177c1 1395 gen_window_check2(dc, RRR_R, RRR_S);
3580ecad
MF		 1396 tcg_gen_shli_i32(cpu_R[RRR_R], cpu_R[RRR_S],
1397 32 - (RRR_T | ((OP2 & 1) << 4)));
1398 break;
1399
1400 case 2: /*SRAI*/
1401 case 3:
772177c1 1402 gen_window_check2(dc, RRR_R, RRR_T);
3580ecad
MF		 1403 tcg_gen_sari_i32(cpu_R[RRR_R], cpu_R[RRR_T],
1404 RRR_S | ((OP2 & 1) << 4));
1405 break;
1406
1407 case 4: /*SRLI*/
772177c1 1408 gen_window_check2(dc, RRR_R, RRR_T);
3580ecad
MF		 1409 tcg_gen_shri_i32(cpu_R[RRR_R], cpu_R[RRR_T], RRR_S);
1410 break;
1411
1412 case 6: /*XSR*/
1413 {
1414 TCGv_i32 tmp = tcg_temp_new_i32();
40643d7c
MF		 1415 if (RSR_SR >= 64) {
1416 gen_check_privilege(dc);
1417 }
772177c1 1418 gen_window_check1(dc, RRR_T);
3580ecad
MF		 1419 tcg_gen_mov_i32(tmp, cpu_R[RRR_T]);
1420 gen_rsr(dc, cpu_R[RRR_T], RSR_SR);
1421 gen_wsr(dc, RSR_SR, tmp);
1422 tcg_temp_free(tmp);
91a5bb76
MF		 1423 if (!sregnames[RSR_SR]) {
1424 TBD();
1425 }
3580ecad
MF		 1426 }
1427 break;
1428
1429 /*
1430 * Note: 64 bit ops are used here solely because SAR values
1431 * have range 0..63
1432 */
1433#define gen_shift_reg(cmd, reg) do { \
1434 TCGv_i64 tmp = tcg_temp_new_i64(); \
1435 tcg_gen_extu_i32_i64(tmp, reg); \
1436 tcg_gen_##cmd##_i64(v, v, tmp); \
1437 tcg_gen_trunc_i64_i32(cpu_R[RRR_R], v); \
1438 tcg_temp_free_i64(v); \
1439 tcg_temp_free_i64(tmp); \
1440 } while (0)
1441
1442#define gen_shift(cmd) gen_shift_reg(cmd, cpu_SR[SAR])
1443
1444 case 8: /*SRC*/
772177c1 1445 gen_window_check3(dc, RRR_R, RRR_S, RRR_T);
3580ecad
MF		 1446 {
1447 TCGv_i64 v = tcg_temp_new_i64();
1448 tcg_gen_concat_i32_i64(v, cpu_R[RRR_T], cpu_R[RRR_S]);
1449 gen_shift(shr);
1450 }
1451 break;
1452
1453 case 9: /*SRL*/
772177c1 1454 gen_window_check2(dc, RRR_R, RRR_T);
3580ecad
MF		 1455 if (dc->sar_5bit) {
1456 tcg_gen_shr_i32(cpu_R[RRR_R], cpu_R[RRR_T], cpu_SR[SAR]);
1457 } else {
1458 TCGv_i64 v = tcg_temp_new_i64();
1459 tcg_gen_extu_i32_i64(v, cpu_R[RRR_T]);
1460 gen_shift(shr);
1461 }
1462 break;
1463
1464 case 10: /*SLL*/
772177c1 1465 gen_window_check2(dc, RRR_R, RRR_S);
3580ecad
MF		 1466 if (dc->sar_m32_5bit) {
1467 tcg_gen_shl_i32(cpu_R[RRR_R], cpu_R[RRR_S], dc->sar_m32);
1468 } else {
1469 TCGv_i64 v = tcg_temp_new_i64();
1470 TCGv_i32 s = tcg_const_i32(32);
1471 tcg_gen_sub_i32(s, s, cpu_SR[SAR]);
1472 tcg_gen_andi_i32(s, s, 0x3f);
1473 tcg_gen_extu_i32_i64(v, cpu_R[RRR_S]);
1474 gen_shift_reg(shl, s);
1475 tcg_temp_free(s);
1476 }
1477 break;
1478
1479 case 11: /*SRA*/
772177c1 1480 gen_window_check2(dc, RRR_R, RRR_T);
3580ecad
MF		 1481 if (dc->sar_5bit) {
1482 tcg_gen_sar_i32(cpu_R[RRR_R], cpu_R[RRR_T], cpu_SR[SAR]);
1483 } else {
1484 TCGv_i64 v = tcg_temp_new_i64();
1485 tcg_gen_ext_i32_i64(v, cpu_R[RRR_T]);
1486 gen_shift(sar);
1487 }
1488 break;
1489#undef gen_shift
1490#undef gen_shift_reg
1491
1492 case 12: /*MUL16U*/
1493 HAS_OPTION(XTENSA_OPTION_16_BIT_IMUL);
772177c1 1494 gen_window_check3(dc, RRR_R, RRR_S, RRR_T);
3580ecad
MF		 1495 {
1496 TCGv_i32 v1 = tcg_temp_new_i32();
1497 TCGv_i32 v2 = tcg_temp_new_i32();
1498 tcg_gen_ext16u_i32(v1, cpu_R[RRR_S]);
1499 tcg_gen_ext16u_i32(v2, cpu_R[RRR_T]);
1500 tcg_gen_mul_i32(cpu_R[RRR_R], v1, v2);
1501 tcg_temp_free(v2);
1502 tcg_temp_free(v1);
1503 }
1504 break;
1505
1506 case 13: /*MUL16S*/
1507 HAS_OPTION(XTENSA_OPTION_16_BIT_IMUL);
772177c1 1508 gen_window_check3(dc, RRR_R, RRR_S, RRR_T);
3580ecad
MF		 1509 {
1510 TCGv_i32 v1 = tcg_temp_new_i32();
1511 TCGv_i32 v2 = tcg_temp_new_i32();
1512 tcg_gen_ext16s_i32(v1, cpu_R[RRR_S]);
1513 tcg_gen_ext16s_i32(v2, cpu_R[RRR_T]);
1514 tcg_gen_mul_i32(cpu_R[RRR_R], v1, v2);
1515 tcg_temp_free(v2);
1516 tcg_temp_free(v1);
1517 }
1518 break;
1519
1520 default: /*reserved*/
91a5bb76 1521 RESERVED();
3580ecad
MF		 1522 break;
1523 }
dedc5eae
MF		 1524 break;
1525
1526 case 2: /*RST2*/
4dd85b6b
MF		 1527 if (OP2 >= 8) {
1528 gen_window_check3(dc, RRR_R, RRR_S, RRR_T);
1529 }
772177c1 1530
f76ebf55
MF		 1531 if (OP2 >= 12) {
1532 HAS_OPTION(XTENSA_OPTION_32_BIT_IDIV);
1533 int label = gen_new_label();
1534 tcg_gen_brcondi_i32(TCG_COND_NE, cpu_R[RRR_T], 0, label);
1535 gen_exception_cause(dc, INTEGER_DIVIDE_BY_ZERO_CAUSE);
1536 gen_set_label(label);
1537 }
1538
1539 switch (OP2) {
4dd85b6b
MF		 1540#define BOOLEAN_LOGIC(fn, r, s, t) \
1541 do { \
1542 HAS_OPTION(XTENSA_OPTION_BOOLEAN); \
1543 TCGv_i32 tmp1 = tcg_temp_new_i32(); \
1544 TCGv_i32 tmp2 = tcg_temp_new_i32(); \
1545 \
1546 tcg_gen_shri_i32(tmp1, cpu_SR[BR], s); \
1547 tcg_gen_shri_i32(tmp2, cpu_SR[BR], t); \
1548 tcg_gen_##fn##_i32(tmp1, tmp1, tmp2); \
1549 tcg_gen_deposit_i32(cpu_SR[BR], cpu_SR[BR], tmp1, r, 1); \
1550 tcg_temp_free(tmp1); \
1551 tcg_temp_free(tmp2); \
1552 } while (0)
1553
1554 case 0: /*ANDBp*/
1555 BOOLEAN_LOGIC(and, RRR_R, RRR_S, RRR_T);
1556 break;
1557
1558 case 1: /*ANDBCp*/
1559 BOOLEAN_LOGIC(andc, RRR_R, RRR_S, RRR_T);
1560 break;
1561
1562 case 2: /*ORBp*/
1563 BOOLEAN_LOGIC(or, RRR_R, RRR_S, RRR_T);
1564 break;
1565
1566 case 3: /*ORBCp*/
1567 BOOLEAN_LOGIC(orc, RRR_R, RRR_S, RRR_T);
1568 break;
1569
1570 case 4: /*XORBp*/
1571 BOOLEAN_LOGIC(xor, RRR_R, RRR_S, RRR_T);
1572 break;
1573
1574#undef BOOLEAN_LOGIC
1575
f76ebf55
MF		 1576 case 8: /*MULLi*/
1577 HAS_OPTION(XTENSA_OPTION_32_BIT_IMUL);
1578 tcg_gen_mul_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
1579 break;
1580
1581 case 10: /*MULUHi*/
1582 case 11: /*MULSHi*/
7f65f4b0 1583 HAS_OPTION(XTENSA_OPTION_32_BIT_IMUL_HIGH);
f76ebf55
MF		 1584 {
1585 TCGv_i64 r = tcg_temp_new_i64();
1586 TCGv_i64 s = tcg_temp_new_i64();
1587 TCGv_i64 t = tcg_temp_new_i64();
1588
1589 if (OP2 == 10) {
1590 tcg_gen_extu_i32_i64(s, cpu_R[RRR_S]);
1591 tcg_gen_extu_i32_i64(t, cpu_R[RRR_T]);
1592 } else {
1593 tcg_gen_ext_i32_i64(s, cpu_R[RRR_S]);
1594 tcg_gen_ext_i32_i64(t, cpu_R[RRR_T]);
1595 }
1596 tcg_gen_mul_i64(r, s, t);
1597 tcg_gen_shri_i64(r, r, 32);
1598 tcg_gen_trunc_i64_i32(cpu_R[RRR_R], r);
1599
1600 tcg_temp_free_i64(r);
1601 tcg_temp_free_i64(s);
1602 tcg_temp_free_i64(t);
1603 }
1604 break;
1605
1606 case 12: /*QUOUi*/
1607 tcg_gen_divu_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
1608 break;
1609
1610 case 13: /*QUOSi*/
1611 case 15: /*REMSi*/
1612 {
1613 int label1 = gen_new_label();
1614 int label2 = gen_new_label();
1615
1616 tcg_gen_brcondi_i32(TCG_COND_NE, cpu_R[RRR_S], 0x80000000,
1617 label1);
1618 tcg_gen_brcondi_i32(TCG_COND_NE, cpu_R[RRR_T], 0xffffffff,
1619 label1);
1620 tcg_gen_movi_i32(cpu_R[RRR_R],
1621 OP2 == 13 ? 0x80000000 : 0);
1622 tcg_gen_br(label2);
1623 gen_set_label(label1);
1624 if (OP2 == 13) {
1625 tcg_gen_div_i32(cpu_R[RRR_R],
1626 cpu_R[RRR_S], cpu_R[RRR_T]);
1627 } else {
1628 tcg_gen_rem_i32(cpu_R[RRR_R],
1629 cpu_R[RRR_S], cpu_R[RRR_T]);
1630 }
1631 gen_set_label(label2);
1632 }
1633 break;
1634
1635 case 14: /*REMUi*/
1636 tcg_gen_remu_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
1637 break;
1638
1639 default: /*reserved*/
1640 RESERVED();
1641 break;
1642 }
dedc5eae
MF		 1643 break;
1644
1645 case 3: /*RST3*/
b8132eff
MF		 1646 switch (OP2) {
1647 case 0: /*RSR*/
40643d7c
MF		 1648 if (RSR_SR >= 64) {
1649 gen_check_privilege(dc);
1650 }
772177c1 1651 gen_window_check1(dc, RRR_T);
b8132eff 1652 gen_rsr(dc, cpu_R[RRR_T], RSR_SR);
91a5bb76
MF		 1653 if (!sregnames[RSR_SR]) {
1654 TBD();
1655 }
b8132eff
MF		 1656 break;
1657
1658 case 1: /*WSR*/
40643d7c
MF		 1659 if (RSR_SR >= 64) {
1660 gen_check_privilege(dc);
1661 }
772177c1 1662 gen_window_check1(dc, RRR_T);
b8132eff 1663 gen_wsr(dc, RSR_SR, cpu_R[RRR_T]);
91a5bb76
MF		 1664 if (!sregnames[RSR_SR]) {
1665 TBD();
1666 }
b8132eff
MF		 1667 break;
1668
1669 case 2: /*SEXTu*/
7f65f4b0 1670 HAS_OPTION(XTENSA_OPTION_MISC_OP_SEXT);
772177c1 1671 gen_window_check2(dc, RRR_R, RRR_S);
b8132eff
MF		 1672 {
1673 int shift = 24 - RRR_T;
1674
1675 if (shift == 24) {
1676 tcg_gen_ext8s_i32(cpu_R[RRR_R], cpu_R[RRR_S]);
1677 } else if (shift == 16) {
1678 tcg_gen_ext16s_i32(cpu_R[RRR_R], cpu_R[RRR_S]);
1679 } else {
1680 TCGv_i32 tmp = tcg_temp_new_i32();
1681 tcg_gen_shli_i32(tmp, cpu_R[RRR_S], shift);
1682 tcg_gen_sari_i32(cpu_R[RRR_R], tmp, shift);
1683 tcg_temp_free(tmp);
1684 }
1685 }
1686 break;
1687
1688 case 3: /*CLAMPSu*/
7f65f4b0 1689 HAS_OPTION(XTENSA_OPTION_MISC_OP_CLAMPS);
772177c1 1690 gen_window_check2(dc, RRR_R, RRR_S);
b8132eff
MF		 1691 {
1692 TCGv_i32 tmp1 = tcg_temp_new_i32();
1693 TCGv_i32 tmp2 = tcg_temp_new_i32();
1694 int label = gen_new_label();
1695
1696 tcg_gen_sari_i32(tmp1, cpu_R[RRR_S], 24 - RRR_T);
1697 tcg_gen_xor_i32(tmp2, tmp1, cpu_R[RRR_S]);
1698 tcg_gen_andi_i32(tmp2, tmp2, 0xffffffff << (RRR_T + 7));
1699 tcg_gen_mov_i32(cpu_R[RRR_R], cpu_R[RRR_S]);
1700 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp2, 0, label);
1701
1702 tcg_gen_sari_i32(tmp1, cpu_R[RRR_S], 31);
1703 tcg_gen_xori_i32(cpu_R[RRR_R], tmp1,
1704 0xffffffff >> (25 - RRR_T));
1705
1706 gen_set_label(label);
1707
1708 tcg_temp_free(tmp1);
1709 tcg_temp_free(tmp2);
1710 }
1711 break;
1712
1713 case 4: /*MINu*/
1714 case 5: /*MAXu*/
1715 case 6: /*MINUu*/
1716 case 7: /*MAXUu*/
7f65f4b0 1717 HAS_OPTION(XTENSA_OPTION_MISC_OP_MINMAX);
772177c1 1718 gen_window_check3(dc, RRR_R, RRR_S, RRR_T);
b8132eff
MF		 1719 {
1720 static const TCGCond cond[] = {
1721 TCG_COND_LE,
1722 TCG_COND_GE,
1723 TCG_COND_LEU,
1724 TCG_COND_GEU
1725 };
1726 int label = gen_new_label();
1727
1728 if (RRR_R != RRR_T) {
1729 tcg_gen_mov_i32(cpu_R[RRR_R], cpu_R[RRR_S]);
1730 tcg_gen_brcond_i32(cond[OP2 - 4],
1731 cpu_R[RRR_S], cpu_R[RRR_T], label);
1732 tcg_gen_mov_i32(cpu_R[RRR_R], cpu_R[RRR_T]);
1733 } else {
1734 tcg_gen_brcond_i32(cond[OP2 - 4],
1735 cpu_R[RRR_T], cpu_R[RRR_S], label);
1736 tcg_gen_mov_i32(cpu_R[RRR_R], cpu_R[RRR_S]);
1737 }
1738 gen_set_label(label);
1739 }
1740 break;
1741
1742 case 8: /*MOVEQZ*/
1743 case 9: /*MOVNEZ*/
1744 case 10: /*MOVLTZ*/
1745 case 11: /*MOVGEZ*/
772177c1 1746 gen_window_check3(dc, RRR_R, RRR_S, RRR_T);
b8132eff
MF		 1747 {
1748 static const TCGCond cond[] = {
1749 TCG_COND_NE,
1750 TCG_COND_EQ,
1751 TCG_COND_GE,
1752 TCG_COND_LT
1753 };
1754 int label = gen_new_label();
1755 tcg_gen_brcondi_i32(cond[OP2 - 8], cpu_R[RRR_T], 0, label);
1756 tcg_gen_mov_i32(cpu_R[RRR_R], cpu_R[RRR_S]);
1757 gen_set_label(label);
1758 }
1759 break;
1760
1761 case 12: /*MOVFp*/
b8132eff
MF		 1762 case 13: /*MOVTp*/
1763 HAS_OPTION(XTENSA_OPTION_BOOLEAN);
4dd85b6b
MF		 1764 gen_window_check2(dc, RRR_R, RRR_S);
1765 {
1766 int label = gen_new_label();
1767 TCGv_i32 tmp = tcg_temp_new_i32();
1768
1769 tcg_gen_andi_i32(tmp, cpu_SR[BR], 1 << RRR_T);
1770 tcg_gen_brcondi_i32(
1771 OP2 & 1 ? TCG_COND_EQ : TCG_COND_NE,
1772 tmp, 0, label);
1773 tcg_gen_mov_i32(cpu_R[RRR_R], cpu_R[RRR_S]);
1774 gen_set_label(label);
1775 tcg_temp_free(tmp);
1776 }
b8132eff
MF		 1777 break;
1778
1779 case 14: /*RUR*/
772177c1 1780 gen_window_check1(dc, RRR_R);
b8132eff
MF		 1781 {
1782 int st = (RRR_S << 4) + RRR_T;
1783 if (uregnames[st]) {
1784 tcg_gen_mov_i32(cpu_R[RRR_R], cpu_UR[st]);
1785 } else {
1786 qemu_log("RUR %d not implemented, ", st);
91a5bb76 1787 TBD();
b8132eff
MF		 1788 }
1789 }
1790 break;
1791
1792 case 15: /*WUR*/
772177c1 1793 gen_window_check1(dc, RRR_T);
dd519cbe
MF		 1794 if (uregnames[RSR_SR]) {
1795 gen_wur(RSR_SR, cpu_R[RRR_T]);
1796 } else {
1797 qemu_log("WUR %d not implemented, ", RSR_SR);
1798 TBD();
b8132eff
MF		 1799 }
1800 break;
1801
1802 }
dedc5eae
MF		 1803 break;
1804
1805 case 4: /*EXTUI*/
1806 case 5:
772177c1 1807 gen_window_check2(dc, RRR_R, RRR_T);
3580ecad 1808 {
f9cb5045 1809 int shiftimm = RRR_S | ((OP1 & 1) << 4);
3580ecad
MF		 1810 int maskimm = (1 << (OP2 + 1)) - 1;
1811
1812 TCGv_i32 tmp = tcg_temp_new_i32();
f9cb5045
MF		 1813
1814 if (shiftimm) {
1815 tcg_gen_shri_i32(tmp, cpu_R[RRR_T], shiftimm);
1816 } else {
1817 tcg_gen_mov_i32(tmp, cpu_R[RRR_T]);
1818 }
1819
1820 switch (maskimm) {
1821 case 0xff:
1822 tcg_gen_ext8u_i32(cpu_R[RRR_R], tmp);
1823 break;
1824
1825 case 0xffff:
1826 tcg_gen_ext16u_i32(cpu_R[RRR_R], tmp);
1827 break;
1828
1829 default:
1830 tcg_gen_andi_i32(cpu_R[RRR_R], tmp, maskimm);
1831 break;
1832 }
3580ecad
MF		 1833 tcg_temp_free(tmp);
1834 }
dedc5eae
MF		 1835 break;
1836
1837 case 6: /*CUST0*/
91a5bb76 1838 RESERVED();
dedc5eae
MF		 1839 break;
1840
1841 case 7: /*CUST1*/
91a5bb76 1842 RESERVED();
dedc5eae
MF		 1843 break;
1844
1845 case 8: /*LSCXp*/
9ed7ae12
MF		 1846 switch (OP2) {
1847 case 0: /*LSXf*/
1848 case 1: /*LSXUf*/
1849 case 4: /*SSXf*/
1850 case 5: /*SSXUf*/
1851 HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR);
1852 gen_window_check2(dc, RRR_S, RRR_T);
1853 {
1854 TCGv_i32 addr = tcg_temp_new_i32();
1855 tcg_gen_add_i32(addr, cpu_R[RRR_S], cpu_R[RRR_T]);
1856 gen_load_store_alignment(dc, 2, addr, false);
1857 if (OP2 & 0x4) {
1858 tcg_gen_qemu_st32(cpu_FR[RRR_R], addr, dc->cring);
1859 } else {
1860 tcg_gen_qemu_ld32u(cpu_FR[RRR_R], addr, dc->cring);
1861 }
1862 if (OP2 & 0x1) {
1863 tcg_gen_mov_i32(cpu_R[RRR_S], addr);
1864 }
1865 tcg_temp_free(addr);
1866 }
1867 break;
1868
1869 default: /*reserved*/
1870 RESERVED();
1871 break;
1872 }
dedc5eae
MF		 1873 break;
1874
1875 case 9: /*LSC4*/
772177c1 1876 gen_window_check2(dc, RRR_S, RRR_T);
553e44f9
MF		 1877 switch (OP2) {
1878 case 0: /*L32E*/
1879 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
1880 gen_check_privilege(dc);
1881 {
1882 TCGv_i32 addr = tcg_temp_new_i32();
1883 tcg_gen_addi_i32(addr, cpu_R[RRR_S],
1884 (0xffffffc0 | (RRR_R << 2)));
1885 tcg_gen_qemu_ld32u(cpu_R[RRR_T], addr, dc->ring);
1886 tcg_temp_free(addr);
1887 }
1888 break;
1889
1890 case 4: /*S32E*/
1891 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
1892 gen_check_privilege(dc);
1893 {
1894 TCGv_i32 addr = tcg_temp_new_i32();
1895 tcg_gen_addi_i32(addr, cpu_R[RRR_S],
1896 (0xffffffc0 | (RRR_R << 2)));
1897 tcg_gen_qemu_st32(cpu_R[RRR_T], addr, dc->ring);
1898 tcg_temp_free(addr);
1899 }
1900 break;
1901
1902 default:
1903 RESERVED();
1904 break;
1905 }
dedc5eae
MF		 1906 break;
1907
1908 case 10: /*FP0*/
1909 HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR);
0b6df838
MF		 1910 switch (OP2) {
1911 case 0: /*ADD.Sf*/
1912 gen_helper_add_s(cpu_FR[RRR_R], cpu_env,
1913 cpu_FR[RRR_S], cpu_FR[RRR_T]);
1914 break;
1915
1916 case 1: /*SUB.Sf*/
1917 gen_helper_sub_s(cpu_FR[RRR_R], cpu_env,
1918 cpu_FR[RRR_S], cpu_FR[RRR_T]);
1919 break;
1920
1921 case 2: /*MUL.Sf*/
1922 gen_helper_mul_s(cpu_FR[RRR_R], cpu_env,
1923 cpu_FR[RRR_S], cpu_FR[RRR_T]);
1924 break;
1925
1926 case 4: /*MADD.Sf*/
1927 gen_helper_madd_s(cpu_FR[RRR_R], cpu_env,
1928 cpu_FR[RRR_R], cpu_FR[RRR_S], cpu_FR[RRR_T]);
1929 break;
1930
1931 case 5: /*MSUB.Sf*/
1932 gen_helper_msub_s(cpu_FR[RRR_R], cpu_env,
1933 cpu_FR[RRR_R], cpu_FR[RRR_S], cpu_FR[RRR_T]);
1934 break;
1935
b7ee8c6a
MF		 1936 case 8: /*ROUND.Sf*/
1937 case 9: /*TRUNC.Sf*/
1938 case 10: /*FLOOR.Sf*/
1939 case 11: /*CEIL.Sf*/
1940 case 14: /*UTRUNC.Sf*/
1941 gen_window_check1(dc, RRR_R);
1942 {
1943 static const unsigned rounding_mode_const[] = {
1944 float_round_nearest_even,
1945 float_round_to_zero,
1946 float_round_down,
1947 float_round_up,
1948 [6] = float_round_to_zero,
1949 };
1950 TCGv_i32 rounding_mode = tcg_const_i32(
1951 rounding_mode_const[OP2 & 7]);
1952 TCGv_i32 scale = tcg_const_i32(RRR_T);
1953
1954 if (OP2 == 14) {
1955 gen_helper_ftoui(cpu_R[RRR_R], cpu_FR[RRR_S],
1956 rounding_mode, scale);
1957 } else {
1958 gen_helper_ftoi(cpu_R[RRR_R], cpu_FR[RRR_S],
1959 rounding_mode, scale);
1960 }
1961
1962 tcg_temp_free(rounding_mode);
1963 tcg_temp_free(scale);
1964 }
1965 break;
1966
1967 case 12: /*FLOAT.Sf*/
1968 case 13: /*UFLOAT.Sf*/
1969 gen_window_check1(dc, RRR_S);
1970 {
1971 TCGv_i32 scale = tcg_const_i32(-RRR_T);
1972
1973 if (OP2 == 13) {
1974 gen_helper_uitof(cpu_FR[RRR_R], cpu_env,
1975 cpu_R[RRR_S], scale);
1976 } else {
1977 gen_helper_itof(cpu_FR[RRR_R], cpu_env,
1978 cpu_R[RRR_S], scale);
1979 }
1980 tcg_temp_free(scale);
1981 }
1982 break;
1983
0b6df838
MF		 1984 case 15: /*FP1OP*/
1985 switch (RRR_T) {
1986 case 0: /*MOV.Sf*/
1987 tcg_gen_mov_i32(cpu_FR[RRR_R], cpu_FR[RRR_S]);
1988 break;
1989
1990 case 1: /*ABS.Sf*/
1991 gen_helper_abs_s(cpu_FR[RRR_R], cpu_FR[RRR_S]);
1992 break;
1993
1994 case 4: /*RFRf*/
1995 gen_window_check1(dc, RRR_R);
1996 tcg_gen_mov_i32(cpu_R[RRR_R], cpu_FR[RRR_S]);
1997 break;
1998
1999 case 5: /*WFRf*/
2000 gen_window_check1(dc, RRR_S);
2001 tcg_gen_mov_i32(cpu_FR[RRR_R], cpu_R[RRR_S]);
2002 break;
2003
2004 case 6: /*NEG.Sf*/
2005 gen_helper_neg_s(cpu_FR[RRR_R], cpu_FR[RRR_S]);
2006 break;
2007
2008 default: /*reserved*/
2009 RESERVED();
2010 break;
2011 }
2012 break;
2013
2014 default: /*reserved*/
2015 RESERVED();
2016 break;
2017 }
dedc5eae
MF		 2018 break;
2019
2020 case 11: /*FP1*/
2021 HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR);
91a5bb76 2022 TBD();
dedc5eae
MF		 2023 break;
2024
2025 default: /*reserved*/
91a5bb76 2026 RESERVED();
dedc5eae
MF		 2027 break;
2028 }
2029 break;
2030
2031 case 1: /*L32R*/
772177c1 2032 gen_window_check1(dc, RRR_T);
dedc5eae
MF		 2033 {
2034 TCGv_i32 tmp = tcg_const_i32(
6ad6dbf7
MF		 2035 ((dc->tb->flags & XTENSA_TBFLAG_LITBASE) ?
2036 0 : ((dc->pc + 3) & ~3)) +
2037 (0xfffc0000 | (RI16_IMM16 << 2)));
dedc5eae 2038
6ad6dbf7
MF		 2039 if (dc->tb->flags & XTENSA_TBFLAG_LITBASE) {
2040 tcg_gen_add_i32(tmp, tmp, dc->litbase);
2041 }
f0a548b9 2042 tcg_gen_qemu_ld32u(cpu_R[RRR_T], tmp, dc->cring);
dedc5eae
MF		 2043 tcg_temp_free(tmp);
2044 }
2045 break;
2046
2047 case 2: /*LSAI*/
809377aa
MF		 2048#define gen_load_store(type, shift) do { \
2049 TCGv_i32 addr = tcg_temp_new_i32(); \
772177c1 2050 gen_window_check2(dc, RRI8_S, RRI8_T); \
809377aa 2051 tcg_gen_addi_i32(addr, cpu_R[RRI8_S], RRI8_IMM8 << shift); \
5b4e481b
MF		 2052 if (shift) { \
2053 gen_load_store_alignment(dc, shift, addr, false); \
2054 } \
f0a548b9 2055 tcg_gen_qemu_##type(cpu_R[RRI8_T], addr, dc->cring); \
809377aa
MF		 2056 tcg_temp_free(addr); \
2057 } while (0)
2058
2059 switch (RRI8_R) {
2060 case 0: /*L8UI*/
2061 gen_load_store(ld8u, 0);
2062 break;
2063
2064 case 1: /*L16UI*/
2065 gen_load_store(ld16u, 1);
2066 break;
2067
2068 case 2: /*L32I*/
2069 gen_load_store(ld32u, 2);
2070 break;
2071
2072 case 4: /*S8I*/
2073 gen_load_store(st8, 0);
2074 break;
2075
2076 case 5: /*S16I*/
2077 gen_load_store(st16, 1);
2078 break;
2079
2080 case 6: /*S32I*/
2081 gen_load_store(st32, 2);
2082 break;
2083
2084 case 7: /*CACHEc*/
8ffc2d0d
MF		 2085 if (RRI8_T < 8) {
2086 HAS_OPTION(XTENSA_OPTION_DCACHE);
2087 }
2088
2089 switch (RRI8_T) {
2090 case 0: /*DPFRc*/
2091 break;
2092
2093 case 1: /*DPFWc*/
2094 break;
2095
2096 case 2: /*DPFROc*/
2097 break;
2098
2099 case 3: /*DPFWOc*/
2100 break;
2101
2102 case 4: /*DHWBc*/
2103 break;
2104
2105 case 5: /*DHWBIc*/
2106 break;
2107
2108 case 6: /*DHIc*/
2109 break;
2110
2111 case 7: /*DIIc*/
2112 break;
2113
2114 case 8: /*DCEc*/
2115 switch (OP1) {
2116 case 0: /*DPFLl*/
2117 HAS_OPTION(XTENSA_OPTION_DCACHE_INDEX_LOCK);
2118 break;
2119
2120 case 2: /*DHUl*/
2121 HAS_OPTION(XTENSA_OPTION_DCACHE_INDEX_LOCK);
2122 break;
2123
2124 case 3: /*DIUl*/
2125 HAS_OPTION(XTENSA_OPTION_DCACHE_INDEX_LOCK);
2126 break;
2127
2128 case 4: /*DIWBc*/
2129 HAS_OPTION(XTENSA_OPTION_DCACHE);
2130 break;
2131
2132 case 5: /*DIWBIc*/
2133 HAS_OPTION(XTENSA_OPTION_DCACHE);
2134 break;
2135
2136 default: /*reserved*/
2137 RESERVED();
2138 break;
2139
2140 }
2141 break;
2142
2143 case 12: /*IPFc*/
2144 HAS_OPTION(XTENSA_OPTION_ICACHE);
2145 break;
2146
2147 case 13: /*ICEc*/
2148 switch (OP1) {
2149 case 0: /*IPFLl*/
2150 HAS_OPTION(XTENSA_OPTION_ICACHE_INDEX_LOCK);
2151 break;
2152
2153 case 2: /*IHUl*/
2154 HAS_OPTION(XTENSA_OPTION_ICACHE_INDEX_LOCK);
2155 break;
2156
2157 case 3: /*IIUl*/
2158 HAS_OPTION(XTENSA_OPTION_ICACHE_INDEX_LOCK);
2159 break;
2160
2161 default: /*reserved*/
2162 RESERVED();
2163 break;
2164 }
2165 break;
2166
2167 case 14: /*IHIc*/
2168 HAS_OPTION(XTENSA_OPTION_ICACHE);
2169 break;
2170
2171 case 15: /*IIIc*/
2172 HAS_OPTION(XTENSA_OPTION_ICACHE);
2173 break;
2174
2175 default: /*reserved*/
2176 RESERVED();
2177 break;
2178 }
809377aa
MF		 2179 break;
2180
2181 case 9: /*L16SI*/
2182 gen_load_store(ld16s, 1);
2183 break;
5b4e481b 2184#undef gen_load_store
809377aa
MF		 2185
2186 case 10: /*MOVI*/
772177c1 2187 gen_window_check1(dc, RRI8_T);
809377aa
MF		 2188 tcg_gen_movi_i32(cpu_R[RRI8_T],
2189 RRI8_IMM8 | (RRI8_S << 8) |
2190 ((RRI8_S & 0x8) ? 0xfffff000 : 0));
2191 break;
2192
5b4e481b
MF		 2193#define gen_load_store_no_hw_align(type) do { \
2194 TCGv_i32 addr = tcg_temp_local_new_i32(); \
772177c1 2195 gen_window_check2(dc, RRI8_S, RRI8_T); \
5b4e481b
MF		 2196 tcg_gen_addi_i32(addr, cpu_R[RRI8_S], RRI8_IMM8 << 2); \
2197 gen_load_store_alignment(dc, 2, addr, true); \
2198 tcg_gen_qemu_##type(cpu_R[RRI8_T], addr, dc->cring); \
2199 tcg_temp_free(addr); \
2200 } while (0)
2201
809377aa
MF		 2202 case 11: /*L32AIy*/
2203 HAS_OPTION(XTENSA_OPTION_MP_SYNCHRO);
5b4e481b 2204 gen_load_store_no_hw_align(ld32u); /*TODO acquire?*/
809377aa
MF		 2205 break;
2206
2207 case 12: /*ADDI*/
772177c1 2208 gen_window_check2(dc, RRI8_S, RRI8_T);
809377aa
MF		 2209 tcg_gen_addi_i32(cpu_R[RRI8_T], cpu_R[RRI8_S], RRI8_IMM8_SE);
2210 break;
2211
2212 case 13: /*ADDMI*/
772177c1 2213 gen_window_check2(dc, RRI8_S, RRI8_T);
809377aa
MF		 2214 tcg_gen_addi_i32(cpu_R[RRI8_T], cpu_R[RRI8_S], RRI8_IMM8_SE << 8);
2215 break;
2216
2217 case 14: /*S32C1Iy*/
7f65f4b0 2218 HAS_OPTION(XTENSA_OPTION_CONDITIONAL_STORE);
772177c1 2219 gen_window_check2(dc, RRI8_S, RRI8_T);
809377aa
MF		 2220 {
2221 int label = gen_new_label();
2222 TCGv_i32 tmp = tcg_temp_local_new_i32();
2223 TCGv_i32 addr = tcg_temp_local_new_i32();
2224
2225 tcg_gen_mov_i32(tmp, cpu_R[RRI8_T]);
2226 tcg_gen_addi_i32(addr, cpu_R[RRI8_S], RRI8_IMM8 << 2);
5b4e481b 2227 gen_load_store_alignment(dc, 2, addr, true);
f0a548b9 2228 tcg_gen_qemu_ld32u(cpu_R[RRI8_T], addr, dc->cring);
809377aa
MF		 2229 tcg_gen_brcond_i32(TCG_COND_NE, cpu_R[RRI8_T],
2230 cpu_SR[SCOMPARE1], label);
2231
f0a548b9 2232 tcg_gen_qemu_st32(tmp, addr, dc->cring);
809377aa
MF		 2233
2234 gen_set_label(label);
2235 tcg_temp_free(addr);
2236 tcg_temp_free(tmp);
2237 }
2238 break;
2239
2240 case 15: /*S32RIy*/
2241 HAS_OPTION(XTENSA_OPTION_MP_SYNCHRO);
5b4e481b 2242 gen_load_store_no_hw_align(st32); /*TODO release?*/
809377aa 2243 break;
5b4e481b 2244#undef gen_load_store_no_hw_align
809377aa
MF		 2245
2246 default: /*reserved*/
91a5bb76 2247 RESERVED();
809377aa
MF		 2248 break;
2249 }
dedc5eae
MF		 2250 break;
2251
2252 case 3: /*LSCIp*/
9ed7ae12
MF		 2253 switch (RRI8_R) {
2254 case 0: /*LSIf*/
2255 case 4: /*SSIf*/
2256 case 8: /*LSIUf*/
2257 case 12: /*SSIUf*/
2258 HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR);
2259 gen_window_check1(dc, RRI8_S);
2260 {
2261 TCGv_i32 addr = tcg_temp_new_i32();
2262 tcg_gen_addi_i32(addr, cpu_R[RRI8_S], RRI8_IMM8 << 2);
2263 gen_load_store_alignment(dc, 2, addr, false);
2264 if (RRI8_R & 0x4) {
2265 tcg_gen_qemu_st32(cpu_FR[RRI8_T], addr, dc->cring);
2266 } else {
2267 tcg_gen_qemu_ld32u(cpu_FR[RRI8_T], addr, dc->cring);
2268 }
2269 if (RRI8_R & 0x8) {
2270 tcg_gen_mov_i32(cpu_R[RRI8_S], addr);
2271 }
2272 tcg_temp_free(addr);
2273 }
2274 break;
2275
2276 default: /*reserved*/
2277 RESERVED();
2278 break;
2279 }
dedc5eae
MF		 2280 break;
2281
2282 case 4: /*MAC16d*/
2283 HAS_OPTION(XTENSA_OPTION_MAC16);
6825b6c3
MF		 2284 {
2285 enum {
2286 MAC16_UMUL = 0x0,
2287 MAC16_MUL = 0x4,
2288 MAC16_MULA = 0x8,
2289 MAC16_MULS = 0xc,
2290 MAC16_NONE = 0xf,
2291 } op = OP1 & 0xc;
2292 bool is_m1_sr = (OP2 & 0x3) == 2;
2293 bool is_m2_sr = (OP2 & 0xc) == 0;
2294 uint32_t ld_offset = 0;
2295
2296 if (OP2 > 9) {
2297 RESERVED();
2298 }
2299
2300 switch (OP2 & 2) {
2301 case 0: /*MACI?/MACC?*/
2302 is_m1_sr = true;
2303 ld_offset = (OP2 & 1) ? -4 : 4;
2304
2305 if (OP2 >= 8) { /*MACI/MACC*/
2306 if (OP1 == 0) { /*LDINC/LDDEC*/
2307 op = MAC16_NONE;
2308 } else {
2309 RESERVED();
2310 }
2311 } else if (op != MAC16_MULA) { /*MULA.*.*.LDINC/LDDEC*/
2312 RESERVED();
2313 }
2314 break;
2315
2316 case 2: /*MACD?/MACA?*/
2317 if (op == MAC16_UMUL && OP2 != 7) { /*UMUL only in MACAA*/
2318 RESERVED();
2319 }
2320 break;
2321 }
2322
2323 if (op != MAC16_NONE) {
2324 if (!is_m1_sr) {
2325 gen_window_check1(dc, RRR_S);
2326 }
2327 if (!is_m2_sr) {
2328 gen_window_check1(dc, RRR_T);
2329 }
2330 }
2331
2332 {
2333 TCGv_i32 vaddr = tcg_temp_new_i32();
2334 TCGv_i32 mem32 = tcg_temp_new_i32();
2335
2336 if (ld_offset) {
2337 gen_window_check1(dc, RRR_S);
2338 tcg_gen_addi_i32(vaddr, cpu_R[RRR_S], ld_offset);
2339 gen_load_store_alignment(dc, 2, vaddr, false);
2340 tcg_gen_qemu_ld32u(mem32, vaddr, dc->cring);
2341 }
2342 if (op != MAC16_NONE) {
2343 TCGv_i32 m1 = gen_mac16_m(
2344 is_m1_sr ? cpu_SR[MR + RRR_X] : cpu_R[RRR_S],
2345 OP1 & 1, op == MAC16_UMUL);
2346 TCGv_i32 m2 = gen_mac16_m(
2347 is_m2_sr ? cpu_SR[MR + 2 + RRR_Y] : cpu_R[RRR_T],
2348 OP1 & 2, op == MAC16_UMUL);
2349
2350 if (op == MAC16_MUL || op == MAC16_UMUL) {
2351 tcg_gen_mul_i32(cpu_SR[ACCLO], m1, m2);
2352 if (op == MAC16_UMUL) {
2353 tcg_gen_movi_i32(cpu_SR[ACCHI], 0);
2354 } else {
2355 tcg_gen_sari_i32(cpu_SR[ACCHI], cpu_SR[ACCLO], 31);
2356 }
2357 } else {
2358 TCGv_i32 res = tcg_temp_new_i32();
2359 TCGv_i64 res64 = tcg_temp_new_i64();
2360 TCGv_i64 tmp = tcg_temp_new_i64();
2361
2362 tcg_gen_mul_i32(res, m1, m2);
2363 tcg_gen_ext_i32_i64(res64, res);
2364 tcg_gen_concat_i32_i64(tmp,
2365 cpu_SR[ACCLO], cpu_SR[ACCHI]);
2366 if (op == MAC16_MULA) {
2367 tcg_gen_add_i64(tmp, tmp, res64);
2368 } else {
2369 tcg_gen_sub_i64(tmp, tmp, res64);
2370 }
2371 tcg_gen_trunc_i64_i32(cpu_SR[ACCLO], tmp);
2372 tcg_gen_shri_i64(tmp, tmp, 32);
2373 tcg_gen_trunc_i64_i32(cpu_SR[ACCHI], tmp);
2374 tcg_gen_ext8s_i32(cpu_SR[ACCHI], cpu_SR[ACCHI]);
2375
2376 tcg_temp_free(res);
2377 tcg_temp_free_i64(res64);
2378 tcg_temp_free_i64(tmp);
2379 }
2380 tcg_temp_free(m1);
2381 tcg_temp_free(m2);
2382 }
2383 if (ld_offset) {
2384 tcg_gen_mov_i32(cpu_R[RRR_S], vaddr);
2385 tcg_gen_mov_i32(cpu_SR[MR + RRR_W], mem32);
2386 }
2387 tcg_temp_free(vaddr);
2388 tcg_temp_free(mem32);
2389 }
2390 }
dedc5eae
MF		 2391 break;
2392
2393 case 5: /*CALLN*/
2394 switch (CALL_N) {
2395 case 0: /*CALL0*/
2396 tcg_gen_movi_i32(cpu_R[0], dc->next_pc);
2397 gen_jumpi(dc, (dc->pc & ~3) + (CALL_OFFSET_SE << 2) + 4, 0);
2398 break;
2399
2400 case 1: /*CALL4w*/
2401 case 2: /*CALL8w*/
2402 case 3: /*CALL12w*/
2403 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
772177c1 2404 gen_window_check1(dc, CALL_N << 2);
553e44f9
MF		 2405 gen_callwi(dc, CALL_N,
2406 (dc->pc & ~3) + (CALL_OFFSET_SE << 2) + 4, 0);
dedc5eae
MF		 2407 break;
2408 }
2409 break;
2410
2411 case 6: /*SI*/
2412 switch (CALL_N) {
2413 case 0: /*J*/
2414 gen_jumpi(dc, dc->pc + 4 + CALL_OFFSET_SE, 0);
2415 break;
2416
bd57fb91 2417 case 1: /*BZ*/
772177c1 2418 gen_window_check1(dc, BRI12_S);
bd57fb91
MF		 2419 {
2420 static const TCGCond cond[] = {
2421 TCG_COND_EQ, /*BEQZ*/
2422 TCG_COND_NE, /*BNEZ*/
2423 TCG_COND_LT, /*BLTZ*/
2424 TCG_COND_GE, /*BGEZ*/
2425 };
2426
2427 gen_brcondi(dc, cond[BRI12_M & 3], cpu_R[BRI12_S], 0,
2428 4 + BRI12_IMM12_SE);
2429 }
2430 break;
2431
2432 case 2: /*BI0*/
772177c1 2433 gen_window_check1(dc, BRI8_S);
bd57fb91
MF		 2434 {
2435 static const TCGCond cond[] = {
2436 TCG_COND_EQ, /*BEQI*/
2437 TCG_COND_NE, /*BNEI*/
2438 TCG_COND_LT, /*BLTI*/
2439 TCG_COND_GE, /*BGEI*/
2440 };
2441
2442 gen_brcondi(dc, cond[BRI8_M & 3],
2443 cpu_R[BRI8_S], B4CONST[BRI8_R], 4 + BRI8_IMM8_SE);
2444 }
2445 break;
2446
2447 case 3: /*BI1*/
2448 switch (BRI8_M) {
2449 case 0: /*ENTRYw*/
2450 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
553e44f9
MF		 2451 {
2452 TCGv_i32 pc = tcg_const_i32(dc->pc);
2453 TCGv_i32 s = tcg_const_i32(BRI12_S);
2454 TCGv_i32 imm = tcg_const_i32(BRI12_IMM12);
b994e91b 2455 gen_advance_ccount(dc);
f492b82d 2456 gen_helper_entry(cpu_env, pc, s, imm);
553e44f9
MF		 2457 tcg_temp_free(imm);
2458 tcg_temp_free(s);
2459 tcg_temp_free(pc);
772177c1 2460 reset_used_window(dc);
553e44f9 2461 }
bd57fb91
MF		 2462 break;
2463
2464 case 1: /*B1*/
2465 switch (BRI8_R) {
2466 case 0: /*BFp*/
bd57fb91
MF		 2467 case 1: /*BTp*/
2468 HAS_OPTION(XTENSA_OPTION_BOOLEAN);
4dd85b6b
MF		 2469 {
2470 TCGv_i32 tmp = tcg_temp_new_i32();
2471 tcg_gen_andi_i32(tmp, cpu_SR[BR], 1 << RRI8_S);
2472 gen_brcondi(dc,
2473 BRI8_R == 1 ? TCG_COND_NE : TCG_COND_EQ,
2474 tmp, 0, 4 + RRI8_IMM8_SE);
2475 tcg_temp_free(tmp);
2476 }
bd57fb91
MF		 2477 break;
2478
2479 case 8: /*LOOP*/
bd57fb91 2480 case 9: /*LOOPNEZ*/
bd57fb91 2481 case 10: /*LOOPGTZ*/
797d780b 2482 HAS_OPTION(XTENSA_OPTION_LOOP);
772177c1 2483 gen_window_check1(dc, RRI8_S);
797d780b
MF		 2484 {
2485 uint32_t lend = dc->pc + RRI8_IMM8 + 4;
2486 TCGv_i32 tmp = tcg_const_i32(lend);
2487
2488 tcg_gen_subi_i32(cpu_SR[LCOUNT], cpu_R[RRI8_S], 1);
2489 tcg_gen_movi_i32(cpu_SR[LBEG], dc->next_pc);
f492b82d 2490 gen_helper_wsr_lend(cpu_env, tmp);
797d780b
MF		 2491 tcg_temp_free(tmp);
2492
2493 if (BRI8_R > 8) {
2494 int label = gen_new_label();
2495 tcg_gen_brcondi_i32(
2496 BRI8_R == 9 ? TCG_COND_NE : TCG_COND_GT,
2497 cpu_R[RRI8_S], 0, label);
2498 gen_jumpi(dc, lend, 1);
2499 gen_set_label(label);
2500 }
2501
2502 gen_jumpi(dc, dc->next_pc, 0);
2503 }
bd57fb91
MF		 2504 break;
2505
2506 default: /*reserved*/
91a5bb76 2507 RESERVED();
bd57fb91
MF		 2508 break;
2509
2510 }
2511 break;
2512
2513 case 2: /*BLTUI*/
2514 case 3: /*BGEUI*/
772177c1 2515 gen_window_check1(dc, BRI8_S);
bd57fb91
MF		 2516 gen_brcondi(dc, BRI8_M == 2 ? TCG_COND_LTU : TCG_COND_GEU,
2517 cpu_R[BRI8_S], B4CONSTU[BRI8_R], 4 + BRI8_IMM8_SE);
2518 break;
2519 }
2520 break;
2521
dedc5eae
MF		 2522 }
2523 break;
2524
2525 case 7: /*B*/
bd57fb91
MF		 2526 {
2527 TCGCond eq_ne = (RRI8_R & 8) ? TCG_COND_NE : TCG_COND_EQ;
2528
2529 switch (RRI8_R & 7) {
2530 case 0: /*BNONE*/ /*BANY*/
772177c1 2531 gen_window_check2(dc, RRI8_S, RRI8_T);
bd57fb91
MF		 2532 {
2533 TCGv_i32 tmp = tcg_temp_new_i32();
2534 tcg_gen_and_i32(tmp, cpu_R[RRI8_S], cpu_R[RRI8_T]);
2535 gen_brcondi(dc, eq_ne, tmp, 0, 4 + RRI8_IMM8_SE);
2536 tcg_temp_free(tmp);
2537 }
2538 break;
2539
2540 case 1: /*BEQ*/ /*BNE*/
2541 case 2: /*BLT*/ /*BGE*/
2542 case 3: /*BLTU*/ /*BGEU*/
772177c1 2543 gen_window_check2(dc, RRI8_S, RRI8_T);
bd57fb91
MF		 2544 {
2545 static const TCGCond cond[] = {
2546 [1] = TCG_COND_EQ,
2547 [2] = TCG_COND_LT,
2548 [3] = TCG_COND_LTU,
2549 [9] = TCG_COND_NE,
2550 [10] = TCG_COND_GE,
2551 [11] = TCG_COND_GEU,
2552 };
2553 gen_brcond(dc, cond[RRI8_R], cpu_R[RRI8_S], cpu_R[RRI8_T],
2554 4 + RRI8_IMM8_SE);
2555 }
2556 break;
2557
2558 case 4: /*BALL*/ /*BNALL*/
772177c1 2559 gen_window_check2(dc, RRI8_S, RRI8_T);
bd57fb91
MF		 2560 {
2561 TCGv_i32 tmp = tcg_temp_new_i32();
2562 tcg_gen_and_i32(tmp, cpu_R[RRI8_S], cpu_R[RRI8_T]);
2563 gen_brcond(dc, eq_ne, tmp, cpu_R[RRI8_T],
2564 4 + RRI8_IMM8_SE);
2565 tcg_temp_free(tmp);
2566 }
2567 break;
2568
2569 case 5: /*BBC*/ /*BBS*/
772177c1 2570 gen_window_check2(dc, RRI8_S, RRI8_T);
bd57fb91 2571 {
7ff7563f
MF		 2572#ifdef TARGET_WORDS_BIGENDIAN
2573 TCGv_i32 bit = tcg_const_i32(0x80000000);
2574#else
2575 TCGv_i32 bit = tcg_const_i32(0x00000001);
2576#endif
bd57fb91
MF		 2577 TCGv_i32 tmp = tcg_temp_new_i32();
2578 tcg_gen_andi_i32(tmp, cpu_R[RRI8_T], 0x1f);
7ff7563f
MF		 2579#ifdef TARGET_WORDS_BIGENDIAN
2580 tcg_gen_shr_i32(bit, bit, tmp);
2581#else
bd57fb91 2582 tcg_gen_shl_i32(bit, bit, tmp);
7ff7563f 2583#endif
bd57fb91
MF		 2584 tcg_gen_and_i32(tmp, cpu_R[RRI8_S], bit);
2585 gen_brcondi(dc, eq_ne, tmp, 0, 4 + RRI8_IMM8_SE);
2586 tcg_temp_free(tmp);
2587 tcg_temp_free(bit);
2588 }
2589 break;
2590
2591 case 6: /*BBCI*/ /*BBSI*/
2592 case 7:
772177c1 2593 gen_window_check1(dc, RRI8_S);
bd57fb91
MF		 2594 {
2595 TCGv_i32 tmp = tcg_temp_new_i32();
2596 tcg_gen_andi_i32(tmp, cpu_R[RRI8_S],
7ff7563f
MF		 2597#ifdef TARGET_WORDS_BIGENDIAN
2598 0x80000000 >> (((RRI8_R & 1) << 4) | RRI8_T));
2599#else
2600 0x00000001 << (((RRI8_R & 1) << 4) | RRI8_T));
2601#endif
bd57fb91
MF		 2602 gen_brcondi(dc, eq_ne, tmp, 0, 4 + RRI8_IMM8_SE);
2603 tcg_temp_free(tmp);
2604 }
2605 break;
2606
2607 }
2608 }
dedc5eae
MF		 2609 break;
2610
67882fd1
MF		 2611#define gen_narrow_load_store(type) do { \
2612 TCGv_i32 addr = tcg_temp_new_i32(); \
772177c1 2613 gen_window_check2(dc, RRRN_S, RRRN_T); \
67882fd1 2614 tcg_gen_addi_i32(addr, cpu_R[RRRN_S], RRRN_R << 2); \
5b4e481b 2615 gen_load_store_alignment(dc, 2, addr, false); \
f0a548b9 2616 tcg_gen_qemu_##type(cpu_R[RRRN_T], addr, dc->cring); \
67882fd1
MF		 2617 tcg_temp_free(addr); \
2618 } while (0)
2619
dedc5eae 2620 case 8: /*L32I.Nn*/
67882fd1 2621 gen_narrow_load_store(ld32u);
dedc5eae
MF		 2622 break;
2623
2624 case 9: /*S32I.Nn*/
67882fd1 2625 gen_narrow_load_store(st32);
dedc5eae 2626 break;
67882fd1 2627#undef gen_narrow_load_store
dedc5eae
MF		 2628
2629 case 10: /*ADD.Nn*/
772177c1 2630 gen_window_check3(dc, RRRN_R, RRRN_S, RRRN_T);
67882fd1 2631 tcg_gen_add_i32(cpu_R[RRRN_R], cpu_R[RRRN_S], cpu_R[RRRN_T]);
dedc5eae
MF		 2632 break;
2633
2634 case 11: /*ADDI.Nn*/
772177c1 2635 gen_window_check2(dc, RRRN_R, RRRN_S);
67882fd1 2636 tcg_gen_addi_i32(cpu_R[RRRN_R], cpu_R[RRRN_S], RRRN_T ? RRRN_T : -1);
dedc5eae
MF		 2637 break;
2638
2639 case 12: /*ST2n*/
772177c1 2640 gen_window_check1(dc, RRRN_S);
67882fd1
MF		 2641 if (RRRN_T < 8) { /*MOVI.Nn*/
2642 tcg_gen_movi_i32(cpu_R[RRRN_S],
2643 RRRN_R | (RRRN_T << 4) |
2644 ((RRRN_T & 6) == 6 ? 0xffffff80 : 0));
2645 } else { /*BEQZ.Nn*/ /*BNEZ.Nn*/
bd57fb91
MF		 2646 TCGCond eq_ne = (RRRN_T & 4) ? TCG_COND_NE : TCG_COND_EQ;
2647
2648 gen_brcondi(dc, eq_ne, cpu_R[RRRN_S], 0,
2649 4 + (RRRN_R | ((RRRN_T & 3) << 4)));
67882fd1 2650 }
dedc5eae
MF		 2651 break;
2652
2653 case 13: /*ST3n*/
67882fd1
MF		 2654 switch (RRRN_R) {
2655 case 0: /*MOV.Nn*/
772177c1 2656 gen_window_check2(dc, RRRN_S, RRRN_T);
67882fd1
MF		 2657 tcg_gen_mov_i32(cpu_R[RRRN_T], cpu_R[RRRN_S]);
2658 break;
2659
2660 case 15: /*S3*/
2661 switch (RRRN_T) {
2662 case 0: /*RET.Nn*/
2663 gen_jump(dc, cpu_R[0]);
2664 break;
2665
2666 case 1: /*RETW.Nn*/
91a5bb76 2667 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
553e44f9
MF		 2668 {
2669 TCGv_i32 tmp = tcg_const_i32(dc->pc);
b994e91b 2670 gen_advance_ccount(dc);
f492b82d 2671 gen_helper_retw(tmp, cpu_env, tmp);
553e44f9
MF		 2672 gen_jump(dc, tmp);
2673 tcg_temp_free(tmp);
2674 }
67882fd1
MF		 2675 break;
2676
2677 case 2: /*BREAK.Nn*/
e61dc8f7
MF		 2678 HAS_OPTION(XTENSA_OPTION_DEBUG);
2679 if (dc->debug) {
2680 gen_debug_exception(dc, DEBUGCAUSE_BN);
2681 }
67882fd1
MF		 2682 break;
2683
2684 case 3: /*NOP.Nn*/
2685 break;
2686
2687 case 6: /*ILL.Nn*/
40643d7c 2688 gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);
67882fd1
MF		 2689 break;
2690
2691 default: /*reserved*/
91a5bb76 2692 RESERVED();
67882fd1
MF		 2693 break;
2694 }
2695 break;
2696
2697 default: /*reserved*/
91a5bb76 2698 RESERVED();
67882fd1
MF		 2699 break;
2700 }
dedc5eae
MF		 2701 break;
2702
2703 default: /*reserved*/
91a5bb76 2704 RESERVED();
dedc5eae
MF		 2705 break;
2706 }
2707
c26032b2
MF		 2708 if (dc->is_jmp == DISAS_NEXT) {
2709 gen_check_loop_end(dc, 0);
2710 }
dedc5eae 2711 dc->pc = dc->next_pc;
797d780b 2712
dedc5eae
MF		 2713 return;
2714
2715invalid_opcode:
2716 qemu_log("INVALID(pc = %08x)\n", dc->pc);
6b814719 2717 gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);
dedc5eae
MF		 2718#undef HAS_OPTION
2719}
2720
97129ac8 2721static void check_breakpoint(CPUXtensaState *env, DisasContext *dc)
dedc5eae
MF		 2722{
2723 CPUBreakpoint *bp;
2724
2725 if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
2726 QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
2727 if (bp->pc == dc->pc) {
2728 tcg_gen_movi_i32(cpu_pc, dc->pc);
b994e91b 2729 gen_exception(dc, EXCP_DEBUG);
dedc5eae
MF		 2730 dc->is_jmp = DISAS_UPDATE;
2731 }
2732 }
2733 }
2734}
2735
97129ac8 2736static void gen_ibreak_check(CPUXtensaState *env, DisasContext *dc)
e61dc8f7
MF		 2737{
2738 unsigned i;
2739
2740 for (i = 0; i < dc->config->nibreak; ++i) {
2741 if ((env->sregs[IBREAKENABLE] & (1 << i)) &&
2742 env->sregs[IBREAKA + i] == dc->pc) {
2743 gen_debug_exception(dc, DEBUGCAUSE_IB);
2744 break;
2745 }
2746 }
2747}
2748
dedc5eae 2749static void gen_intermediate_code_internal(
97129ac8 2750 CPUXtensaState *env, TranslationBlock *tb, int search_pc)
dedc5eae
MF		 2751{
2752 DisasContext dc;
2753 int insn_count = 0;
2754 int j, lj = -1;
2755 uint16_t *gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
2756 int max_insns = tb->cflags & CF_COUNT_MASK;
2757 uint32_t pc_start = tb->pc;
2758 uint32_t next_page_start =
2759 (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
2760
2761 if (max_insns == 0) {
2762 max_insns = CF_COUNT_MASK;
2763 }
2764
2765 dc.config = env->config;
2766 dc.singlestep_enabled = env->singlestep_enabled;
2767 dc.tb = tb;
2768 dc.pc = pc_start;
f0a548b9
MF		 2769 dc.ring = tb->flags & XTENSA_TBFLAG_RING_MASK;
2770 dc.cring = (tb->flags & XTENSA_TBFLAG_EXCM) ? 0 : dc.ring;
797d780b
MF		 2771 dc.lbeg = env->sregs[LBEG];
2772 dc.lend = env->sregs[LEND];
dedc5eae 2773 dc.is_jmp = DISAS_NEXT;
b994e91b 2774 dc.ccount_delta = 0;
e61dc8f7 2775 dc.debug = tb->flags & XTENSA_TBFLAG_DEBUG;
35b5c044 2776 dc.icount = tb->flags & XTENSA_TBFLAG_ICOUNT;
dedc5eae 2777
6ad6dbf7 2778 init_litbase(&dc);
3580ecad 2779 init_sar_tracker(&dc);
772177c1 2780 reset_used_window(&dc);
35b5c044
MF		 2781 if (dc.icount) {
2782 dc.next_icount = tcg_temp_local_new_i32();
2783 }
3580ecad 2784
dedc5eae
MF		 2785 gen_icount_start();
2786
40643d7c
MF		 2787 if (env->singlestep_enabled && env->exception_taken) {
2788 env->exception_taken = 0;
2789 tcg_gen_movi_i32(cpu_pc, dc.pc);
b994e91b 2790 gen_exception(&dc, EXCP_DEBUG);
40643d7c
MF		 2791 }
2792
dedc5eae
MF		 2793 do {
2794 check_breakpoint(env, &dc);
2795
2796 if (search_pc) {
2797 j = gen_opc_ptr - gen_opc_buf;
2798 if (lj < j) {
2799 lj++;
2800 while (lj < j) {
2801 gen_opc_instr_start[lj++] = 0;
2802 }
2803 }
2804 gen_opc_pc[lj] = dc.pc;
2805 gen_opc_instr_start[lj] = 1;
2806 gen_opc_icount[lj] = insn_count;
2807 }
2808
2809 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP))) {
2810 tcg_gen_debug_insn_start(dc.pc);
2811 }
2812
b994e91b
MF		 2813 ++dc.ccount_delta;
2814
2815 if (insn_count + 1 == max_insns && (tb->cflags & CF_LAST_IO)) {
2816 gen_io_start();
2817 }
2818
35b5c044
MF		 2819 if (dc.icount) {
2820 int label = gen_new_label();
2821
2822 tcg_gen_addi_i32(dc.next_icount, cpu_SR[ICOUNT], 1);
2823 tcg_gen_brcondi_i32(TCG_COND_NE, dc.next_icount, 0, label);
2824 tcg_gen_mov_i32(dc.next_icount, cpu_SR[ICOUNT]);
2825 if (dc.debug) {
2826 gen_debug_exception(&dc, DEBUGCAUSE_IC);
2827 }
2828 gen_set_label(label);
2829 }
2830
e61dc8f7
MF		 2831 if (dc.debug) {
2832 gen_ibreak_check(env, &dc);
2833 }
2834
dedc5eae
MF		 2835 disas_xtensa_insn(&dc);
2836 ++insn_count;
35b5c044
MF		 2837 if (dc.icount) {
2838 tcg_gen_mov_i32(cpu_SR[ICOUNT], dc.next_icount);
2839 }
dedc5eae
MF		 2840 if (env->singlestep_enabled) {
2841 tcg_gen_movi_i32(cpu_pc, dc.pc);
b994e91b 2842 gen_exception(&dc, EXCP_DEBUG);
dedc5eae
MF		 2843 break;
2844 }
2845 } while (dc.is_jmp == DISAS_NEXT &&
2846 insn_count < max_insns &&
2847 dc.pc < next_page_start &&
2848 gen_opc_ptr < gen_opc_end);
2849
6ad6dbf7 2850 reset_litbase(&dc);
3580ecad 2851 reset_sar_tracker(&dc);
35b5c044
MF		 2852 if (dc.icount) {
2853 tcg_temp_free(dc.next_icount);
2854 }
3580ecad 2855
b994e91b
MF		 2856 if (tb->cflags & CF_LAST_IO) {
2857 gen_io_end();
2858 }
2859
dedc5eae
MF		 2860 if (dc.is_jmp == DISAS_NEXT) {
2861 gen_jumpi(&dc, dc.pc, 0);
2862 }
2863 gen_icount_end(tb, insn_count);
2864 *gen_opc_ptr = INDEX_op_end;
2865
2866 if (!search_pc) {
2867 tb->size = dc.pc - pc_start;
2868 tb->icount = insn_count;
2869 }
2328826b
MF		 2870}
2871
97129ac8 2872void gen_intermediate_code(CPUXtensaState *env, TranslationBlock *tb)
2328826b 2873{
dedc5eae 2874 gen_intermediate_code_internal(env, tb, 0);
2328826b
MF		 2875}
2876
97129ac8 2877void gen_intermediate_code_pc(CPUXtensaState *env, TranslationBlock *tb)
2328826b 2878{
dedc5eae 2879 gen_intermediate_code_internal(env, tb, 1);
2328826b
MF		 2880}
2881
97129ac8 2882void cpu_dump_state(CPUXtensaState *env, FILE *f, fprintf_function cpu_fprintf,
2328826b
MF		 2883 int flags)
2884{
2af3da91
MF		 2885 int i, j;
2886
2887 cpu_fprintf(f, "PC=%08x\n\n", env->pc);
2888
2889 for (i = j = 0; i < 256; ++i) {
2890 if (sregnames[i]) {
2891 cpu_fprintf(f, "%s=%08x%c", sregnames[i], env->sregs[i],
2892 (j++ % 4) == 3 ? '\n' : ' ');
2893 }
2894 }
2895
2896 cpu_fprintf(f, (j % 4) == 0 ? "\n" : "\n\n");
2897
2898 for (i = j = 0; i < 256; ++i) {
2899 if (uregnames[i]) {
2900 cpu_fprintf(f, "%s=%08x%c", uregnames[i], env->uregs[i],
2901 (j++ % 4) == 3 ? '\n' : ' ');
2902 }
2903 }
2328826b 2904
2af3da91 2905 cpu_fprintf(f, (j % 4) == 0 ? "\n" : "\n\n");
2328826b
MF		 2906
2907 for (i = 0; i < 16; ++i) {
2908 cpu_fprintf(f, "A%02d=%08x%c", i, env->regs[i],
2909 (i % 4) == 3 ? '\n' : ' ');
2910 }
553e44f9
MF		 2911
2912 cpu_fprintf(f, "\n");
2913
2914 for (i = 0; i < env->config->nareg; ++i) {
2915 cpu_fprintf(f, "AR%02d=%08x%c", i, env->phys_regs[i],
2916 (i % 4) == 3 ? '\n' : ' ');
2917 }
dd519cbe
MF		 2918
2919 if (xtensa_option_enabled(env->config, XTENSA_OPTION_FP_COPROCESSOR)) {
2920 cpu_fprintf(f, "\n");
2921
2922 for (i = 0; i < 16; ++i) {
2923 cpu_fprintf(f, "F%02d=%08x (%+10.8e)%c", i,
2924 float32_val(env->fregs[i]),
2925 *(float *)&env->fregs[i], (i % 2) == 1 ? '\n' : ' ');
2926 }
2927 }
2328826b
MF		 2928}
2929
97129ac8 2930void restore_state_to_opc(CPUXtensaState *env, TranslationBlock *tb, int pc_pos)
2328826b
MF		 2931{
2932 env->pc = gen_opc_pc[pc_pos];
2933}
Qemu copy for testing