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target-xtensa: implement instruction breakpoints
[qemu.git] / target-xtensa / translate.c
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2328826b
MF		 1/*
2 * Xtensa ISA:
3 * http://www.tensilica.com/products/literature-docs/documentation/xtensa-isa-databook.htm
4 *
5 * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions are met:
10 * * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * * Neither the name of the Open Source and Linux Lab nor the
16 * names of its contributors may be used to endorse or promote products
17 * derived from this software without specific prior written permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
23 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
26 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 */
30
31#include <stdio.h>
32
33#include "cpu.h"
34#include "exec-all.h"
35#include "disas.h"
36#include "tcg-op.h"
37#include "qemu-log.h"
1ddeaa5d 38#include "sysemu.h"
2328826b 39
dedc5eae
MF		 40#include "helpers.h"
41#define GEN_HELPER 1
42#include "helpers.h"
43
44typedef struct DisasContext {
45 const XtensaConfig *config;
46 TranslationBlock *tb;
47 uint32_t pc;
48 uint32_t next_pc;
f0a548b9
MF		 49 int cring;
50 int ring;
797d780b
MF		 51 uint32_t lbeg;
52 uint32_t lend;
6ad6dbf7 53 TCGv_i32 litbase;
dedc5eae
MF		 54 int is_jmp;
55 int singlestep_enabled;
3580ecad
MF		 56
57 bool sar_5bit;
58 bool sar_m32_5bit;
59 bool sar_m32_allocated;
60 TCGv_i32 sar_m32;
b994e91b
MF		 61
62 uint32_t ccount_delta;
772177c1 63 unsigned used_window;
e61dc8f7
MF		 64
65 bool debug;
dedc5eae
MF		 66} DisasContext;
67
68static TCGv_ptr cpu_env;
69static TCGv_i32 cpu_pc;
70static TCGv_i32 cpu_R[16];
2af3da91
MF		 71static TCGv_i32 cpu_SR[256];
72static TCGv_i32 cpu_UR[256];
dedc5eae
MF		 73
74#include "gen-icount.h"
2328826b 75
2af3da91 76static const char * const sregnames[256] = {
797d780b
MF		 77 [LBEG] = "LBEG",
78 [LEND] = "LEND",
79 [LCOUNT] = "LCOUNT",
3580ecad 80 [SAR] = "SAR",
4dd85b6b 81 [BR] = "BR",
6ad6dbf7 82 [LITBASE] = "LITBASE",
809377aa 83 [SCOMPARE1] = "SCOMPARE1",
6825b6c3
MF		 84 [ACCLO] = "ACCLO",
85 [ACCHI] = "ACCHI",
86 [MR] = "MR0",
87 [MR + 1] = "MR1",
88 [MR + 2] = "MR2",
89 [MR + 3] = "MR3",
553e44f9
MF		 90 [WINDOW_BASE] = "WINDOW_BASE",
91 [WINDOW_START] = "WINDOW_START",
b67ea0cd
MF		 92 [PTEVADDR] = "PTEVADDR",
93 [RASID] = "RASID",
94 [ITLBCFG] = "ITLBCFG",
95 [DTLBCFG] = "DTLBCFG",
e61dc8f7
MF		 96 [IBREAKENABLE] = "IBREAKENABLE",
97 [IBREAKA] = "IBREAKA0",
98 [IBREAKA + 1] = "IBREAKA1",
40643d7c 99 [EPC1] = "EPC1",
b994e91b
MF		 100 [EPC1 + 1] = "EPC2",
101 [EPC1 + 2] = "EPC3",
102 [EPC1 + 3] = "EPC4",
103 [EPC1 + 4] = "EPC5",
104 [EPC1 + 5] = "EPC6",
105 [EPC1 + 6] = "EPC7",
40643d7c 106 [DEPC] = "DEPC",
b994e91b
MF		 107 [EPS2] = "EPS2",
108 [EPS2 + 1] = "EPS3",
109 [EPS2 + 2] = "EPS4",
110 [EPS2 + 3] = "EPS5",
111 [EPS2 + 4] = "EPS6",
112 [EPS2 + 5] = "EPS7",
40643d7c 113 [EXCSAVE1] = "EXCSAVE1",
b994e91b
MF		 114 [EXCSAVE1 + 1] = "EXCSAVE2",
115 [EXCSAVE1 + 2] = "EXCSAVE3",
116 [EXCSAVE1 + 3] = "EXCSAVE4",
117 [EXCSAVE1 + 4] = "EXCSAVE5",
118 [EXCSAVE1 + 5] = "EXCSAVE6",
119 [EXCSAVE1 + 6] = "EXCSAVE7",
f3df4c04 120 [CPENABLE] = "CPENABLE",
b994e91b
MF		 121 [INTSET] = "INTSET",
122 [INTCLEAR] = "INTCLEAR",
123 [INTENABLE] = "INTENABLE",
f0a548b9 124 [PS] = "PS",
97836cee 125 [VECBASE] = "VECBASE",
40643d7c 126 [EXCCAUSE] = "EXCCAUSE",
ab58c5b4 127 [DEBUGCAUSE] = "DEBUGCAUSE",
b994e91b 128 [CCOUNT] = "CCOUNT",
f3df4c04 129 [PRID] = "PRID",
40643d7c 130 [EXCVADDR] = "EXCVADDR",
b994e91b
MF		 131 [CCOMPARE] = "CCOMPARE0",
132 [CCOMPARE + 1] = "CCOMPARE1",
133 [CCOMPARE + 2] = "CCOMPARE2",
2af3da91
MF		 134};
135
136static const char * const uregnames[256] = {
137 [THREADPTR] = "THREADPTR",
138 [FCR] = "FCR",
139 [FSR] = "FSR",
140};
141
2328826b
MF		 142void xtensa_translate_init(void)
143{
dedc5eae
MF		 144 static const char * const regnames[] = {
145 "ar0", "ar1", "ar2", "ar3",
146 "ar4", "ar5", "ar6", "ar7",
147 "ar8", "ar9", "ar10", "ar11",
148 "ar12", "ar13", "ar14", "ar15",
149 };
150 int i;
151
152 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
153 cpu_pc = tcg_global_mem_new_i32(TCG_AREG0,
154 offsetof(CPUState, pc), "pc");
155
156 for (i = 0; i < 16; i++) {
157 cpu_R[i] = tcg_global_mem_new_i32(TCG_AREG0,
158 offsetof(CPUState, regs[i]),
159 regnames[i]);
160 }
2af3da91
MF		 161
162 for (i = 0; i < 256; ++i) {
163 if (sregnames[i]) {
164 cpu_SR[i] = tcg_global_mem_new_i32(TCG_AREG0,
165 offsetof(CPUState, sregs[i]),
166 sregnames[i]);
167 }
168 }
169
170 for (i = 0; i < 256; ++i) {
171 if (uregnames[i]) {
172 cpu_UR[i] = tcg_global_mem_new_i32(TCG_AREG0,
173 offsetof(CPUState, uregs[i]),
174 uregnames[i]);
175 }
176 }
dedc5eae
MF		 177#define GEN_HELPER 2
178#include "helpers.h"
179}
180
b67ea0cd
MF		 181static inline bool option_bits_enabled(DisasContext *dc, uint64_t opt)
182{
183 return xtensa_option_bits_enabled(dc->config, opt);
184}
185
dedc5eae
MF		 186static inline bool option_enabled(DisasContext *dc, int opt)
187{
188 return xtensa_option_enabled(dc->config, opt);
189}
190
6ad6dbf7
MF		 191static void init_litbase(DisasContext *dc)
192{
193 if (dc->tb->flags & XTENSA_TBFLAG_LITBASE) {
194 dc->litbase = tcg_temp_local_new_i32();
195 tcg_gen_andi_i32(dc->litbase, cpu_SR[LITBASE], 0xfffff000);
196 }
197}
198
199static void reset_litbase(DisasContext *dc)
200{
201 if (dc->tb->flags & XTENSA_TBFLAG_LITBASE) {
202 tcg_temp_free(dc->litbase);
203 }
204}
205
3580ecad
MF		 206static void init_sar_tracker(DisasContext *dc)
207{
208 dc->sar_5bit = false;
209 dc->sar_m32_5bit = false;
210 dc->sar_m32_allocated = false;
211}
212
213static void reset_sar_tracker(DisasContext *dc)
214{
215 if (dc->sar_m32_allocated) {
216 tcg_temp_free(dc->sar_m32);
217 }
218}
219
220static void gen_right_shift_sar(DisasContext *dc, TCGv_i32 sa)
221{
222 tcg_gen_andi_i32(cpu_SR[SAR], sa, 0x1f);
223 if (dc->sar_m32_5bit) {
224 tcg_gen_discard_i32(dc->sar_m32);
225 }
226 dc->sar_5bit = true;
227 dc->sar_m32_5bit = false;
228}
229
230static void gen_left_shift_sar(DisasContext *dc, TCGv_i32 sa)
231{
232 TCGv_i32 tmp = tcg_const_i32(32);
233 if (!dc->sar_m32_allocated) {
234 dc->sar_m32 = tcg_temp_local_new_i32();
235 dc->sar_m32_allocated = true;
236 }
237 tcg_gen_andi_i32(dc->sar_m32, sa, 0x1f);
238 tcg_gen_sub_i32(cpu_SR[SAR], tmp, dc->sar_m32);
239 dc->sar_5bit = false;
240 dc->sar_m32_5bit = true;
241 tcg_temp_free(tmp);
242}
243
b994e91b
MF		 244static void gen_advance_ccount(DisasContext *dc)
245{
246 if (dc->ccount_delta > 0) {
247 TCGv_i32 tmp = tcg_const_i32(dc->ccount_delta);
248 dc->ccount_delta = 0;
249 gen_helper_advance_ccount(tmp);
250 tcg_temp_free(tmp);
251 }
252}
253
772177c1
MF		 254static void reset_used_window(DisasContext *dc)
255{
256 dc->used_window = 0;
257}
258
b994e91b 259static void gen_exception(DisasContext *dc, int excp)
dedc5eae
MF		 260{
261 TCGv_i32 tmp = tcg_const_i32(excp);
b994e91b 262 gen_advance_ccount(dc);
dedc5eae
MF		 263 gen_helper_exception(tmp);
264 tcg_temp_free(tmp);
265}
266
40643d7c
MF		 267static void gen_exception_cause(DisasContext *dc, uint32_t cause)
268{
269 TCGv_i32 tpc = tcg_const_i32(dc->pc);
270 TCGv_i32 tcause = tcg_const_i32(cause);
b994e91b 271 gen_advance_ccount(dc);
40643d7c
MF		 272 gen_helper_exception_cause(tpc, tcause);
273 tcg_temp_free(tpc);
274 tcg_temp_free(tcause);
6b814719
MF		 275 if (cause == ILLEGAL_INSTRUCTION_CAUSE ||
276 cause == SYSCALL_CAUSE) {
277 dc->is_jmp = DISAS_UPDATE;
278 }
40643d7c
MF		 279}
280
5b4e481b
MF		 281static void gen_exception_cause_vaddr(DisasContext *dc, uint32_t cause,
282 TCGv_i32 vaddr)
283{
284 TCGv_i32 tpc = tcg_const_i32(dc->pc);
285 TCGv_i32 tcause = tcg_const_i32(cause);
b994e91b 286 gen_advance_ccount(dc);
5b4e481b
MF		 287 gen_helper_exception_cause_vaddr(tpc, tcause, vaddr);
288 tcg_temp_free(tpc);
289 tcg_temp_free(tcause);
290}
291
e61dc8f7
MF		 292static void gen_debug_exception(DisasContext *dc, uint32_t cause)
293{
294 TCGv_i32 tpc = tcg_const_i32(dc->pc);
295 TCGv_i32 tcause = tcg_const_i32(cause);
296 gen_advance_ccount(dc);
297 gen_helper_debug_exception(tpc, tcause);
298 tcg_temp_free(tpc);
299 tcg_temp_free(tcause);
300 if (cause & (DEBUGCAUSE_IB | DEBUGCAUSE_BI | DEBUGCAUSE_BN)) {
301 dc->is_jmp = DISAS_UPDATE;
302 }
303}
304
40643d7c
MF		 305static void gen_check_privilege(DisasContext *dc)
306{
307 if (dc->cring) {
308 gen_exception_cause(dc, PRIVILEGED_CAUSE);
6b814719 309 dc->is_jmp = DISAS_UPDATE;
40643d7c
MF		 310 }
311}
312
dedc5eae
MF		 313static void gen_jump_slot(DisasContext *dc, TCGv dest, int slot)
314{
315 tcg_gen_mov_i32(cpu_pc, dest);
316 if (dc->singlestep_enabled) {
b994e91b 317 gen_exception(dc, EXCP_DEBUG);
dedc5eae 318 } else {
b994e91b 319 gen_advance_ccount(dc);
dedc5eae
MF		 320 if (slot >= 0) {
321 tcg_gen_goto_tb(slot);
322 tcg_gen_exit_tb((tcg_target_long)dc->tb + slot);
323 } else {
324 tcg_gen_exit_tb(0);
325 }
326 }
327 dc->is_jmp = DISAS_UPDATE;
328}
329
67882fd1
MF		 330static void gen_jump(DisasContext *dc, TCGv dest)
331{
332 gen_jump_slot(dc, dest, -1);
333}
334
dedc5eae
MF		 335static void gen_jumpi(DisasContext *dc, uint32_t dest, int slot)
336{
337 TCGv_i32 tmp = tcg_const_i32(dest);
338 if (((dc->pc ^ dest) & TARGET_PAGE_MASK) != 0) {
339 slot = -1;
340 }
341 gen_jump_slot(dc, tmp, slot);
342 tcg_temp_free(tmp);
343}
344
553e44f9
MF		 345static void gen_callw_slot(DisasContext *dc, int callinc, TCGv_i32 dest,
346 int slot)
347{
348 TCGv_i32 tcallinc = tcg_const_i32(callinc);
349
350 tcg_gen_deposit_i32(cpu_SR[PS], cpu_SR[PS],
351 tcallinc, PS_CALLINC_SHIFT, PS_CALLINC_LEN);
352 tcg_temp_free(tcallinc);
353 tcg_gen_movi_i32(cpu_R[callinc << 2],
354 (callinc << 30) | (dc->next_pc & 0x3fffffff));
355 gen_jump_slot(dc, dest, slot);
356}
357
358static void gen_callw(DisasContext *dc, int callinc, TCGv_i32 dest)
359{
360 gen_callw_slot(dc, callinc, dest, -1);
361}
362
363static void gen_callwi(DisasContext *dc, int callinc, uint32_t dest, int slot)
364{
365 TCGv_i32 tmp = tcg_const_i32(dest);
366 if (((dc->pc ^ dest) & TARGET_PAGE_MASK) != 0) {
367 slot = -1;
368 }
369 gen_callw_slot(dc, callinc, tmp, slot);
370 tcg_temp_free(tmp);
371}
372
797d780b
MF		 373static bool gen_check_loop_end(DisasContext *dc, int slot)
374{
375 if (option_enabled(dc, XTENSA_OPTION_LOOP) &&
376 !(dc->tb->flags & XTENSA_TBFLAG_EXCM) &&
377 dc->next_pc == dc->lend) {
378 int label = gen_new_label();
379
380 tcg_gen_brcondi_i32(TCG_COND_EQ, cpu_SR[LCOUNT], 0, label);
381 tcg_gen_subi_i32(cpu_SR[LCOUNT], cpu_SR[LCOUNT], 1);
382 gen_jumpi(dc, dc->lbeg, slot);
383 gen_set_label(label);
384 gen_jumpi(dc, dc->next_pc, -1);
385 return true;
386 }
387 return false;
388}
389
390static void gen_jumpi_check_loop_end(DisasContext *dc, int slot)
391{
392 if (!gen_check_loop_end(dc, slot)) {
393 gen_jumpi(dc, dc->next_pc, slot);
394 }
395}
396
bd57fb91
MF		 397static void gen_brcond(DisasContext *dc, TCGCond cond,
398 TCGv_i32 t0, TCGv_i32 t1, uint32_t offset)
399{
400 int label = gen_new_label();
401
402 tcg_gen_brcond_i32(cond, t0, t1, label);
797d780b 403 gen_jumpi_check_loop_end(dc, 0);
bd57fb91
MF		 404 gen_set_label(label);
405 gen_jumpi(dc, dc->pc + offset, 1);
406}
407
408static void gen_brcondi(DisasContext *dc, TCGCond cond,
409 TCGv_i32 t0, uint32_t t1, uint32_t offset)
410{
411 TCGv_i32 tmp = tcg_const_i32(t1);
412 gen_brcond(dc, cond, t0, tmp, offset);
413 tcg_temp_free(tmp);
414}
415
b994e91b
MF		 416static void gen_rsr_ccount(DisasContext *dc, TCGv_i32 d, uint32_t sr)
417{
418 gen_advance_ccount(dc);
419 tcg_gen_mov_i32(d, cpu_SR[sr]);
420}
421
b67ea0cd
MF		 422static void gen_rsr_ptevaddr(DisasContext *dc, TCGv_i32 d, uint32_t sr)
423{
424 tcg_gen_shri_i32(d, cpu_SR[EXCVADDR], 10);
425 tcg_gen_or_i32(d, d, cpu_SR[sr]);
426 tcg_gen_andi_i32(d, d, 0xfffffffc);
427}
428
b8132eff
MF		 429static void gen_rsr(DisasContext *dc, TCGv_i32 d, uint32_t sr)
430{
431 static void (* const rsr_handler[256])(DisasContext *dc,
432 TCGv_i32 d, uint32_t sr) = {
b994e91b 433 [CCOUNT] = gen_rsr_ccount,
b67ea0cd 434 [PTEVADDR] = gen_rsr_ptevaddr,
b8132eff
MF		 435 };
436
437 if (sregnames[sr]) {
438 if (rsr_handler[sr]) {
439 rsr_handler[sr](dc, d, sr);
440 } else {
441 tcg_gen_mov_i32(d, cpu_SR[sr]);
442 }
443 } else {
444 qemu_log("RSR %d not implemented, ", sr);
445 }
446}
447
797d780b
MF		 448static void gen_wsr_lbeg(DisasContext *dc, uint32_t sr, TCGv_i32 s)
449{
450 gen_helper_wsr_lbeg(s);
451}
452
453static void gen_wsr_lend(DisasContext *dc, uint32_t sr, TCGv_i32 s)
454{
455 gen_helper_wsr_lend(s);
456}
457
3580ecad
MF		 458static void gen_wsr_sar(DisasContext *dc, uint32_t sr, TCGv_i32 s)
459{
460 tcg_gen_andi_i32(cpu_SR[sr], s, 0x3f);
461 if (dc->sar_m32_5bit) {
462 tcg_gen_discard_i32(dc->sar_m32);
463 }
464 dc->sar_5bit = false;
465 dc->sar_m32_5bit = false;
466}
467
4dd85b6b
MF		 468static void gen_wsr_br(DisasContext *dc, uint32_t sr, TCGv_i32 s)
469{
470 tcg_gen_andi_i32(cpu_SR[sr], s, 0xffff);
471}
472
6ad6dbf7
MF		 473static void gen_wsr_litbase(DisasContext *dc, uint32_t sr, TCGv_i32 s)
474{
475 tcg_gen_andi_i32(cpu_SR[sr], s, 0xfffff001);
476 /* This can change tb->flags, so exit tb */
477 gen_jumpi_check_loop_end(dc, -1);
478}
479
6825b6c3
MF		 480static void gen_wsr_acchi(DisasContext *dc, uint32_t sr, TCGv_i32 s)
481{
482 tcg_gen_ext8s_i32(cpu_SR[sr], s);
483}
484
553e44f9
MF		 485static void gen_wsr_windowbase(DisasContext *dc, uint32_t sr, TCGv_i32 v)
486{
487 gen_helper_wsr_windowbase(v);
772177c1
MF		 488 reset_used_window(dc);
489}
490
491static void gen_wsr_windowstart(DisasContext *dc, uint32_t sr, TCGv_i32 v)
492{
53a72dfd 493 tcg_gen_andi_i32(cpu_SR[sr], v, (1 << dc->config->nareg / 4) - 1);
772177c1 494 reset_used_window(dc);
553e44f9
MF		 495}
496
b67ea0cd
MF		 497static void gen_wsr_ptevaddr(DisasContext *dc, uint32_t sr, TCGv_i32 v)
498{
499 tcg_gen_andi_i32(cpu_SR[sr], v, 0xffc00000);
500}
501
502static void gen_wsr_rasid(DisasContext *dc, uint32_t sr, TCGv_i32 v)
503{
504 gen_helper_wsr_rasid(v);
505 /* This can change tb->flags, so exit tb */
506 gen_jumpi_check_loop_end(dc, -1);
507}
508
509static void gen_wsr_tlbcfg(DisasContext *dc, uint32_t sr, TCGv_i32 v)
510{
511 tcg_gen_andi_i32(cpu_SR[sr], v, 0x01130000);
512}
513
e61dc8f7
MF		 514static void gen_wsr_ibreakenable(DisasContext *dc, uint32_t sr, TCGv_i32 v)
515{
516 gen_helper_wsr_ibreakenable(v);
517 gen_jumpi_check_loop_end(dc, 0);
518}
519
520static void gen_wsr_ibreaka(DisasContext *dc, uint32_t sr, TCGv_i32 v)
521{
522 unsigned id = sr - IBREAKA;
523
524 if (id < dc->config->nibreak) {
525 TCGv_i32 tmp = tcg_const_i32(id);
526 gen_helper_wsr_ibreaka(tmp, v);
527 tcg_temp_free(tmp);
528 gen_jumpi_check_loop_end(dc, 0);
529 }
530}
531
b994e91b
MF		 532static void gen_wsr_intset(DisasContext *dc, uint32_t sr, TCGv_i32 v)
533{
534 tcg_gen_andi_i32(cpu_SR[sr], v,
535 dc->config->inttype_mask[INTTYPE_SOFTWARE]);
536 gen_helper_check_interrupts(cpu_env);
537 gen_jumpi_check_loop_end(dc, 0);
538}
539
540static void gen_wsr_intclear(DisasContext *dc, uint32_t sr, TCGv_i32 v)
541{
542 TCGv_i32 tmp = tcg_temp_new_i32();
543
544 tcg_gen_andi_i32(tmp, v,
545 dc->config->inttype_mask[INTTYPE_EDGE] |
546 dc->config->inttype_mask[INTTYPE_NMI] |
547 dc->config->inttype_mask[INTTYPE_SOFTWARE]);
548 tcg_gen_andc_i32(cpu_SR[INTSET], cpu_SR[INTSET], tmp);
549 tcg_temp_free(tmp);
550 gen_helper_check_interrupts(cpu_env);
551}
552
553static void gen_wsr_intenable(DisasContext *dc, uint32_t sr, TCGv_i32 v)
554{
555 tcg_gen_mov_i32(cpu_SR[sr], v);
556 gen_helper_check_interrupts(cpu_env);
557 gen_jumpi_check_loop_end(dc, 0);
558}
559
f0a548b9
MF		 560static void gen_wsr_ps(DisasContext *dc, uint32_t sr, TCGv_i32 v)
561{
562 uint32_t mask = PS_WOE | PS_CALLINC | PS_OWB |
563 PS_UM | PS_EXCM | PS_INTLEVEL;
564
565 if (option_enabled(dc, XTENSA_OPTION_MMU)) {
566 mask |= PS_RING;
567 }
568 tcg_gen_andi_i32(cpu_SR[sr], v, mask);
772177c1 569 reset_used_window(dc);
b994e91b
MF		 570 gen_helper_check_interrupts(cpu_env);
571 /* This can change mmu index and tb->flags, so exit tb */
797d780b 572 gen_jumpi_check_loop_end(dc, -1);
f0a548b9
MF		 573}
574
ab58c5b4
MF		 575static void gen_wsr_debugcause(DisasContext *dc, uint32_t sr, TCGv_i32 v)
576{
577}
578
f3df4c04
MF		 579static void gen_wsr_prid(DisasContext *dc, uint32_t sr, TCGv_i32 v)
580{
581}
582
b994e91b
MF		 583static void gen_wsr_ccompare(DisasContext *dc, uint32_t sr, TCGv_i32 v)
584{
585 uint32_t id = sr - CCOMPARE;
586 if (id < dc->config->nccompare) {
587 uint32_t int_bit = 1 << dc->config->timerint[id];
588 gen_advance_ccount(dc);
589 tcg_gen_mov_i32(cpu_SR[sr], v);
590 tcg_gen_andi_i32(cpu_SR[INTSET], cpu_SR[INTSET], ~int_bit);
591 gen_helper_check_interrupts(cpu_env);
592 }
593}
594
b8132eff
MF		 595static void gen_wsr(DisasContext *dc, uint32_t sr, TCGv_i32 s)
596{
597 static void (* const wsr_handler[256])(DisasContext *dc,
598 uint32_t sr, TCGv_i32 v) = {
797d780b
MF		 599 [LBEG] = gen_wsr_lbeg,
600 [LEND] = gen_wsr_lend,
3580ecad 601 [SAR] = gen_wsr_sar,
4dd85b6b 602 [BR] = gen_wsr_br,
6ad6dbf7 603 [LITBASE] = gen_wsr_litbase,
6825b6c3 604 [ACCHI] = gen_wsr_acchi,
553e44f9 605 [WINDOW_BASE] = gen_wsr_windowbase,
772177c1 606 [WINDOW_START] = gen_wsr_windowstart,
b67ea0cd
MF		 607 [PTEVADDR] = gen_wsr_ptevaddr,
608 [RASID] = gen_wsr_rasid,
609 [ITLBCFG] = gen_wsr_tlbcfg,
610 [DTLBCFG] = gen_wsr_tlbcfg,
e61dc8f7
MF		 611 [IBREAKENABLE] = gen_wsr_ibreakenable,
612 [IBREAKA] = gen_wsr_ibreaka,
613 [IBREAKA + 1] = gen_wsr_ibreaka,
b994e91b
MF		 614 [INTSET] = gen_wsr_intset,
615 [INTCLEAR] = gen_wsr_intclear,
616 [INTENABLE] = gen_wsr_intenable,
f0a548b9 617 [PS] = gen_wsr_ps,
ab58c5b4 618 [DEBUGCAUSE] = gen_wsr_debugcause,
f3df4c04 619 [PRID] = gen_wsr_prid,
b994e91b
MF		 620 [CCOMPARE] = gen_wsr_ccompare,
621 [CCOMPARE + 1] = gen_wsr_ccompare,
622 [CCOMPARE + 2] = gen_wsr_ccompare,
b8132eff
MF		 623 };
624
625 if (sregnames[sr]) {
626 if (wsr_handler[sr]) {
627 wsr_handler[sr](dc, sr, s);
628 } else {
629 tcg_gen_mov_i32(cpu_SR[sr], s);
630 }
631 } else {
632 qemu_log("WSR %d not implemented, ", sr);
633 }
634}
635
5b4e481b
MF		 636static void gen_load_store_alignment(DisasContext *dc, int shift,
637 TCGv_i32 addr, bool no_hw_alignment)
638{
639 if (!option_enabled(dc, XTENSA_OPTION_UNALIGNED_EXCEPTION)) {
640 tcg_gen_andi_i32(addr, addr, ~0 << shift);
641 } else if (option_enabled(dc, XTENSA_OPTION_HW_ALIGNMENT) &&
642 no_hw_alignment) {
643 int label = gen_new_label();
644 TCGv_i32 tmp = tcg_temp_new_i32();
645 tcg_gen_andi_i32(tmp, addr, ~(~0 << shift));
646 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, label);
647 gen_exception_cause_vaddr(dc, LOAD_STORE_ALIGNMENT_CAUSE, addr);
648 gen_set_label(label);
649 tcg_temp_free(tmp);
650 }
651}
652
b994e91b
MF		 653static void gen_waiti(DisasContext *dc, uint32_t imm4)
654{
655 TCGv_i32 pc = tcg_const_i32(dc->next_pc);
656 TCGv_i32 intlevel = tcg_const_i32(imm4);
657 gen_advance_ccount(dc);
658 gen_helper_waiti(pc, intlevel);
659 tcg_temp_free(pc);
660 tcg_temp_free(intlevel);
661}
662
772177c1
MF		 663static void gen_window_check1(DisasContext *dc, unsigned r1)
664{
665 if (dc->tb->flags & XTENSA_TBFLAG_EXCM) {
666 return;
667 }
668 if (option_enabled(dc, XTENSA_OPTION_WINDOWED_REGISTER) &&
669 r1 / 4 > dc->used_window) {
670 TCGv_i32 pc = tcg_const_i32(dc->pc);
671 TCGv_i32 w = tcg_const_i32(r1 / 4);
672
673 dc->used_window = r1 / 4;
674 gen_advance_ccount(dc);
675 gen_helper_window_check(pc, w);
676
677 tcg_temp_free(w);
678 tcg_temp_free(pc);
679 }
680}
681
682static void gen_window_check2(DisasContext *dc, unsigned r1, unsigned r2)
683{
684 gen_window_check1(dc, r1 > r2 ? r1 : r2);
685}
686
687static void gen_window_check3(DisasContext *dc, unsigned r1, unsigned r2,
688 unsigned r3)
689{
690 gen_window_check2(dc, r1, r2 > r3 ? r2 : r3);
691}
692
6825b6c3
MF		 693static TCGv_i32 gen_mac16_m(TCGv_i32 v, bool hi, bool is_unsigned)
694{
695 TCGv_i32 m = tcg_temp_new_i32();
696
697 if (hi) {
698 (is_unsigned ? tcg_gen_shri_i32 : tcg_gen_sari_i32)(m, v, 16);
699 } else {
700 (is_unsigned ? tcg_gen_ext16u_i32 : tcg_gen_ext16s_i32)(m, v);
701 }
702 return m;
703}
704
dedc5eae
MF		 705static void disas_xtensa_insn(DisasContext *dc)
706{
b67ea0cd
MF		 707#define HAS_OPTION_BITS(opt) do { \
708 if (!option_bits_enabled(dc, opt)) { \
709 qemu_log("Option is not enabled %s:%d\n", \
710 __FILE__, __LINE__); \
dedc5eae
MF		 711 goto invalid_opcode; \
712 } \
713 } while (0)
714
b67ea0cd
MF		 715#define HAS_OPTION(opt) HAS_OPTION_BITS(XTENSA_OPTION_BIT(opt))
716
91a5bb76
MF		 717#define TBD() qemu_log("TBD(pc = %08x): %s:%d\n", dc->pc, __FILE__, __LINE__)
718#define RESERVED() do { \
719 qemu_log("RESERVED(pc = %08x, %02x%02x%02x): %s:%d\n", \
720 dc->pc, b0, b1, b2, __FILE__, __LINE__); \
721 goto invalid_opcode; \
722 } while (0)
723
724
dedc5eae
MF		 725#ifdef TARGET_WORDS_BIGENDIAN
726#define OP0 (((b0) & 0xf0) >> 4)
727#define OP1 (((b2) & 0xf0) >> 4)
728#define OP2 ((b2) & 0xf)
729#define RRR_R ((b1) & 0xf)
730#define RRR_S (((b1) & 0xf0) >> 4)
731#define RRR_T ((b0) & 0xf)
732#else
733#define OP0 (((b0) & 0xf))
734#define OP1 (((b2) & 0xf))
735#define OP2 (((b2) & 0xf0) >> 4)
736#define RRR_R (((b1) & 0xf0) >> 4)
737#define RRR_S (((b1) & 0xf))
738#define RRR_T (((b0) & 0xf0) >> 4)
739#endif
6825b6c3
MF		 740#define RRR_X ((RRR_R & 0x4) >> 2)
741#define RRR_Y ((RRR_T & 0x4) >> 2)
742#define RRR_W (RRR_R & 0x3)
dedc5eae
MF		 743
744#define RRRN_R RRR_R
745#define RRRN_S RRR_S
746#define RRRN_T RRR_T
747
748#define RRI8_R RRR_R
749#define RRI8_S RRR_S
750#define RRI8_T RRR_T
751#define RRI8_IMM8 (b2)
752#define RRI8_IMM8_SE ((((b2) & 0x80) ? 0xffffff00 : 0) | RRI8_IMM8)
753
754#ifdef TARGET_WORDS_BIGENDIAN
755#define RI16_IMM16 (((b1) << 8) | (b2))
756#else
757#define RI16_IMM16 (((b2) << 8) | (b1))
758#endif
759
760#ifdef TARGET_WORDS_BIGENDIAN
761#define CALL_N (((b0) & 0xc) >> 2)
762#define CALL_OFFSET ((((b0) & 0x3) << 16) | ((b1) << 8) | (b2))
763#else
764#define CALL_N (((b0) & 0x30) >> 4)
765#define CALL_OFFSET ((((b0) & 0xc0) >> 6) | ((b1) << 2) | ((b2) << 10))
766#endif
767#define CALL_OFFSET_SE \
768 (((CALL_OFFSET & 0x20000) ? 0xfffc0000 : 0) | CALL_OFFSET)
769
770#define CALLX_N CALL_N
771#ifdef TARGET_WORDS_BIGENDIAN
772#define CALLX_M ((b0) & 0x3)
773#else
774#define CALLX_M (((b0) & 0xc0) >> 6)
775#endif
776#define CALLX_S RRR_S
777
778#define BRI12_M CALLX_M
779#define BRI12_S RRR_S
780#ifdef TARGET_WORDS_BIGENDIAN
781#define BRI12_IMM12 ((((b1) & 0xf) << 8) | (b2))
782#else
783#define BRI12_IMM12 ((((b1) & 0xf0) >> 4) | ((b2) << 4))
784#endif
785#define BRI12_IMM12_SE (((BRI12_IMM12 & 0x800) ? 0xfffff000 : 0) | BRI12_IMM12)
786
787#define BRI8_M BRI12_M
788#define BRI8_R RRI8_R
789#define BRI8_S RRI8_S
790#define BRI8_IMM8 RRI8_IMM8
791#define BRI8_IMM8_SE RRI8_IMM8_SE
792
793#define RSR_SR (b1)
794
795 uint8_t b0 = ldub_code(dc->pc);
796 uint8_t b1 = ldub_code(dc->pc + 1);
a044ec2a 797 uint8_t b2 = 0;
dedc5eae 798
bd57fb91
MF		 799 static const uint32_t B4CONST[] = {
800 0xffffffff, 1, 2, 3, 4, 5, 6, 7, 8, 10, 12, 16, 32, 64, 128, 256
801 };
802
803 static const uint32_t B4CONSTU[] = {
804 32768, 65536, 2, 3, 4, 5, 6, 7, 8, 10, 12, 16, 32, 64, 128, 256
805 };
806
dedc5eae
MF		 807 if (OP0 >= 8) {
808 dc->next_pc = dc->pc + 2;
809 HAS_OPTION(XTENSA_OPTION_CODE_DENSITY);
810 } else {
811 dc->next_pc = dc->pc + 3;
a044ec2a 812 b2 = ldub_code(dc->pc + 2);
dedc5eae
MF		 813 }
814
815 switch (OP0) {
816 case 0: /*QRST*/
817 switch (OP1) {
818 case 0: /*RST0*/
819 switch (OP2) {
820 case 0: /*ST0*/
821 if ((RRR_R & 0xc) == 0x8) {
822 HAS_OPTION(XTENSA_OPTION_BOOLEAN);
823 }
824
825 switch (RRR_R) {
826 case 0: /*SNM0*/
5da4a6a8
MF		 827 switch (CALLX_M) {
828 case 0: /*ILL*/
40643d7c 829 gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);
5da4a6a8
MF		 830 break;
831
832 case 1: /*reserved*/
91a5bb76 833 RESERVED();
5da4a6a8
MF		 834 break;
835
836 case 2: /*JR*/
837 switch (CALLX_N) {
838 case 0: /*RET*/
839 case 2: /*JX*/
772177c1 840 gen_window_check1(dc, CALLX_S);
5da4a6a8
MF		 841 gen_jump(dc, cpu_R[CALLX_S]);
842 break;
843
844 case 1: /*RETWw*/
845 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
553e44f9
MF		 846 {
847 TCGv_i32 tmp = tcg_const_i32(dc->pc);
b994e91b 848 gen_advance_ccount(dc);
553e44f9
MF		 849 gen_helper_retw(tmp, tmp);
850 gen_jump(dc, tmp);
851 tcg_temp_free(tmp);
852 }
5da4a6a8
MF		 853 break;
854
855 case 3: /*reserved*/
91a5bb76 856 RESERVED();
5da4a6a8
MF		 857 break;
858 }
859 break;
860
861 case 3: /*CALLX*/
772177c1 862 gen_window_check2(dc, CALLX_S, CALLX_N << 2);
5da4a6a8
MF		 863 switch (CALLX_N) {
864 case 0: /*CALLX0*/
865 {
866 TCGv_i32 tmp = tcg_temp_new_i32();
867 tcg_gen_mov_i32(tmp, cpu_R[CALLX_S]);
868 tcg_gen_movi_i32(cpu_R[0], dc->next_pc);
869 gen_jump(dc, tmp);
870 tcg_temp_free(tmp);
871 }
872 break;
873
874 case 1: /*CALLX4w*/
875 case 2: /*CALLX8w*/
876 case 3: /*CALLX12w*/
877 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
553e44f9
MF		 878 {
879 TCGv_i32 tmp = tcg_temp_new_i32();
880
881 tcg_gen_mov_i32(tmp, cpu_R[CALLX_S]);
882 gen_callw(dc, CALLX_N, tmp);
883 tcg_temp_free(tmp);
884 }
5da4a6a8
MF		 885 break;
886 }
887 break;
888 }
dedc5eae
MF		 889 break;
890
891 case 1: /*MOVSPw*/
892 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
772177c1 893 gen_window_check2(dc, RRR_T, RRR_S);
553e44f9
MF		 894 {
895 TCGv_i32 pc = tcg_const_i32(dc->pc);
b994e91b 896 gen_advance_ccount(dc);
553e44f9
MF		 897 gen_helper_movsp(pc);
898 tcg_gen_mov_i32(cpu_R[RRR_T], cpu_R[RRR_S]);
899 tcg_temp_free(pc);
900 }
dedc5eae
MF		 901 break;
902
903 case 2: /*SYNC*/
28067b22
MF		 904 switch (RRR_T) {
905 case 0: /*ISYNC*/
906 break;
907
908 case 1: /*RSYNC*/
909 break;
910
911 case 2: /*ESYNC*/
912 break;
913
914 case 3: /*DSYNC*/
915 break;
916
917 case 8: /*EXCW*/
918 HAS_OPTION(XTENSA_OPTION_EXCEPTION);
919 break;
920
921 case 12: /*MEMW*/
922 break;
923
924 case 13: /*EXTW*/
925 break;
926
927 case 15: /*NOP*/
928 break;
929
930 default: /*reserved*/
931 RESERVED();
932 break;
933 }
91a5bb76
MF		 934 break;
935
936 case 3: /*RFEIx*/
40643d7c
MF		 937 switch (RRR_T) {
938 case 0: /*RFETx*/
939 HAS_OPTION(XTENSA_OPTION_EXCEPTION);
940 switch (RRR_S) {
941 case 0: /*RFEx*/
942 gen_check_privilege(dc);
943 tcg_gen_andi_i32(cpu_SR[PS], cpu_SR[PS], ~PS_EXCM);
b994e91b 944 gen_helper_check_interrupts(cpu_env);
40643d7c
MF		 945 gen_jump(dc, cpu_SR[EPC1]);
946 break;
947
948 case 1: /*RFUEx*/
949 RESERVED();
950 break;
951
952 case 2: /*RFDEx*/
953 gen_check_privilege(dc);
954 gen_jump(dc, cpu_SR[
955 dc->config->ndepc ? DEPC : EPC1]);
956 break;
957
958 case 4: /*RFWOw*/
959 case 5: /*RFWUw*/
960 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
553e44f9
MF		 961 gen_check_privilege(dc);
962 {
963 TCGv_i32 tmp = tcg_const_i32(1);
964
965 tcg_gen_andi_i32(
966 cpu_SR[PS], cpu_SR[PS], ~PS_EXCM);
967 tcg_gen_shl_i32(tmp, tmp, cpu_SR[WINDOW_BASE]);
968
969 if (RRR_S == 4) {
970 tcg_gen_andc_i32(cpu_SR[WINDOW_START],
971 cpu_SR[WINDOW_START], tmp);
972 } else {
973 tcg_gen_or_i32(cpu_SR[WINDOW_START],
974 cpu_SR[WINDOW_START], tmp);
975 }
976
977 gen_helper_restore_owb();
b994e91b 978 gen_helper_check_interrupts(cpu_env);
553e44f9
MF		 979 gen_jump(dc, cpu_SR[EPC1]);
980
981 tcg_temp_free(tmp);
982 }
40643d7c
MF		 983 break;
984
985 default: /*reserved*/
986 RESERVED();
987 break;
988 }
989 break;
990
991 case 1: /*RFIx*/
992 HAS_OPTION(XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT);
b994e91b
MF		 993 if (RRR_S >= 2 && RRR_S <= dc->config->nlevel) {
994 gen_check_privilege(dc);
995 tcg_gen_mov_i32(cpu_SR[PS],
996 cpu_SR[EPS2 + RRR_S - 2]);
997 gen_helper_check_interrupts(cpu_env);
998 gen_jump(dc, cpu_SR[EPC1 + RRR_S - 1]);
999 } else {
1000 qemu_log("RFI %d is illegal\n", RRR_S);
1001 gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);
1002 }
40643d7c
MF		 1003 break;
1004
1005 case 2: /*RFME*/
1006 TBD();
1007 break;
1008
1009 default: /*reserved*/
1010 RESERVED();
1011 break;
1012
1013 }
91a5bb76
MF		 1014 break;
1015
1016 case 4: /*BREAKx*/
e61dc8f7
MF		 1017 HAS_OPTION(XTENSA_OPTION_DEBUG);
1018 if (dc->debug) {
1019 gen_debug_exception(dc, DEBUGCAUSE_BI);
1020 }
91a5bb76
MF		 1021 break;
1022
1023 case 5: /*SYSCALLx*/
1024 HAS_OPTION(XTENSA_OPTION_EXCEPTION);
40643d7c
MF		 1025 switch (RRR_S) {
1026 case 0: /*SYSCALLx*/
1027 gen_exception_cause(dc, SYSCALL_CAUSE);
1028 break;
1029
1030 case 1: /*SIMCALL*/
1ddeaa5d
MF		 1031 if (semihosting_enabled) {
1032 gen_check_privilege(dc);
1033 gen_helper_simcall(cpu_env);
1034 } else {
1035 qemu_log("SIMCALL but semihosting is disabled\n");
1036 gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);
1037 }
40643d7c
MF		 1038 break;
1039
1040 default:
1041 RESERVED();
1042 break;
1043 }
91a5bb76
MF		 1044 break;
1045
1046 case 6: /*RSILx*/
1047 HAS_OPTION(XTENSA_OPTION_INTERRUPT);
40643d7c 1048 gen_check_privilege(dc);
772177c1 1049 gen_window_check1(dc, RRR_T);
40643d7c 1050 tcg_gen_mov_i32(cpu_R[RRR_T], cpu_SR[PS]);
b994e91b 1051 tcg_gen_andi_i32(cpu_SR[PS], cpu_SR[PS], ~PS_INTLEVEL);
40643d7c 1052 tcg_gen_ori_i32(cpu_SR[PS], cpu_SR[PS], RRR_S);
b994e91b
MF		 1053 gen_helper_check_interrupts(cpu_env);
1054 gen_jumpi_check_loop_end(dc, 0);
91a5bb76
MF		 1055 break;
1056
1057 case 7: /*WAITIx*/
1058 HAS_OPTION(XTENSA_OPTION_INTERRUPT);
b994e91b
MF		 1059 gen_check_privilege(dc);
1060 gen_waiti(dc, RRR_S);
91a5bb76
MF		 1061 break;
1062
1063 case 8: /*ANY4p*/
91a5bb76 1064 case 9: /*ALL4p*/
91a5bb76 1065 case 10: /*ANY8p*/
91a5bb76
MF		 1066 case 11: /*ALL8p*/
1067 HAS_OPTION(XTENSA_OPTION_BOOLEAN);
4dd85b6b
MF		 1068 {
1069 const unsigned shift = (RRR_R & 2) ? 8 : 4;
1070 TCGv_i32 mask = tcg_const_i32(
1071 ((1 << shift) - 1) << RRR_S);
1072 TCGv_i32 tmp = tcg_temp_new_i32();
1073
1074 tcg_gen_and_i32(tmp, cpu_SR[BR], mask);
1075 if (RRR_R & 1) { /*ALL*/
1076 tcg_gen_addi_i32(tmp, tmp, 1 << RRR_S);
1077 } else { /*ANY*/
1078 tcg_gen_add_i32(tmp, tmp, mask);
1079 }
1080 tcg_gen_shri_i32(tmp, tmp, RRR_S + shift);
1081 tcg_gen_deposit_i32(cpu_SR[BR], cpu_SR[BR],
1082 tmp, RRR_T, 1);
1083 tcg_temp_free(mask);
1084 tcg_temp_free(tmp);
1085 }
91a5bb76
MF		 1086 break;
1087
1088 default: /*reserved*/
1089 RESERVED();
dedc5eae
MF		 1090 break;
1091
1092 }
1093 break;
1094
1095 case 1: /*AND*/
772177c1 1096 gen_window_check3(dc, RRR_R, RRR_S, RRR_T);
dedc5eae
MF		 1097 tcg_gen_and_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
1098 break;
1099
1100 case 2: /*OR*/
772177c1 1101 gen_window_check3(dc, RRR_R, RRR_S, RRR_T);
dedc5eae
MF		 1102 tcg_gen_or_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
1103 break;
1104
1105 case 3: /*XOR*/
772177c1 1106 gen_window_check3(dc, RRR_R, RRR_S, RRR_T);
dedc5eae
MF		 1107 tcg_gen_xor_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
1108 break;
1109
1110 case 4: /*ST1*/
3580ecad
MF		 1111 switch (RRR_R) {
1112 case 0: /*SSR*/
772177c1 1113 gen_window_check1(dc, RRR_S);
3580ecad
MF		 1114 gen_right_shift_sar(dc, cpu_R[RRR_S]);
1115 break;
1116
1117 case 1: /*SSL*/
772177c1 1118 gen_window_check1(dc, RRR_S);
3580ecad
MF		 1119 gen_left_shift_sar(dc, cpu_R[RRR_S]);
1120 break;
1121
1122 case 2: /*SSA8L*/
772177c1 1123 gen_window_check1(dc, RRR_S);
3580ecad
MF		 1124 {
1125 TCGv_i32 tmp = tcg_temp_new_i32();
1126 tcg_gen_shli_i32(tmp, cpu_R[RRR_S], 3);
1127 gen_right_shift_sar(dc, tmp);
1128 tcg_temp_free(tmp);
1129 }
1130 break;
1131
1132 case 3: /*SSA8B*/
772177c1 1133 gen_window_check1(dc, RRR_S);
3580ecad
MF		 1134 {
1135 TCGv_i32 tmp = tcg_temp_new_i32();
1136 tcg_gen_shli_i32(tmp, cpu_R[RRR_S], 3);
1137 gen_left_shift_sar(dc, tmp);
1138 tcg_temp_free(tmp);
1139 }
1140 break;
1141
1142 case 4: /*SSAI*/
1143 {
1144 TCGv_i32 tmp = tcg_const_i32(
1145 RRR_S | ((RRR_T & 1) << 4));
1146 gen_right_shift_sar(dc, tmp);
1147 tcg_temp_free(tmp);
1148 }
1149 break;
1150
1151 case 6: /*RER*/
91a5bb76 1152 TBD();
3580ecad
MF		 1153 break;
1154
1155 case 7: /*WER*/
91a5bb76 1156 TBD();
3580ecad
MF		 1157 break;
1158
1159 case 8: /*ROTWw*/
1160 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
553e44f9
MF		 1161 gen_check_privilege(dc);
1162 {
1163 TCGv_i32 tmp = tcg_const_i32(
1164 RRR_T | ((RRR_T & 8) ? 0xfffffff0 : 0));
1165 gen_helper_rotw(tmp);
1166 tcg_temp_free(tmp);
772177c1 1167 reset_used_window(dc);
553e44f9 1168 }
3580ecad
MF		 1169 break;
1170
1171 case 14: /*NSAu*/
7f65f4b0 1172 HAS_OPTION(XTENSA_OPTION_MISC_OP_NSA);
772177c1 1173 gen_window_check2(dc, RRR_S, RRR_T);
3580ecad
MF		 1174 gen_helper_nsa(cpu_R[RRR_T], cpu_R[RRR_S]);
1175 break;
1176
1177 case 15: /*NSAUu*/
7f65f4b0 1178 HAS_OPTION(XTENSA_OPTION_MISC_OP_NSA);
772177c1 1179 gen_window_check2(dc, RRR_S, RRR_T);
3580ecad
MF		 1180 gen_helper_nsau(cpu_R[RRR_T], cpu_R[RRR_S]);
1181 break;
1182
1183 default: /*reserved*/
91a5bb76 1184 RESERVED();
3580ecad
MF		 1185 break;
1186 }
dedc5eae
MF		 1187 break;
1188
1189 case 5: /*TLB*/
b67ea0cd
MF		 1190 HAS_OPTION_BITS(
1191 XTENSA_OPTION_BIT(XTENSA_OPTION_MMU) |
1192 XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_PROTECTION) |
1193 XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_TRANSLATION));
1194 gen_check_privilege(dc);
1195 gen_window_check2(dc, RRR_S, RRR_T);
1196 {
1197 TCGv_i32 dtlb = tcg_const_i32((RRR_R & 8) != 0);
1198
1199 switch (RRR_R & 7) {
1200 case 3: /*RITLB0*/ /*RDTLB0*/
1201 gen_helper_rtlb0(cpu_R[RRR_T], cpu_R[RRR_S], dtlb);
1202 break;
1203
1204 case 4: /*IITLB*/ /*IDTLB*/
1205 gen_helper_itlb(cpu_R[RRR_S], dtlb);
1206 /* This could change memory mapping, so exit tb */
1207 gen_jumpi_check_loop_end(dc, -1);
1208 break;
1209
1210 case 5: /*PITLB*/ /*PDTLB*/
1211 tcg_gen_movi_i32(cpu_pc, dc->pc);
1212 gen_helper_ptlb(cpu_R[RRR_T], cpu_R[RRR_S], dtlb);
1213 break;
1214
1215 case 6: /*WITLB*/ /*WDTLB*/
1216 gen_helper_wtlb(cpu_R[RRR_T], cpu_R[RRR_S], dtlb);
1217 /* This could change memory mapping, so exit tb */
1218 gen_jumpi_check_loop_end(dc, -1);
1219 break;
1220
1221 case 7: /*RITLB1*/ /*RDTLB1*/
1222 gen_helper_rtlb1(cpu_R[RRR_T], cpu_R[RRR_S], dtlb);
1223 break;
1224
1225 default:
1226 tcg_temp_free(dtlb);
1227 RESERVED();
1228 break;
1229 }
1230 tcg_temp_free(dtlb);
1231 }
dedc5eae
MF		 1232 break;
1233
1234 case 6: /*RT0*/
772177c1 1235 gen_window_check2(dc, RRR_R, RRR_T);
f331fe5e
MF		 1236 switch (RRR_S) {
1237 case 0: /*NEG*/
1238 tcg_gen_neg_i32(cpu_R[RRR_R], cpu_R[RRR_T]);
1239 break;
1240
1241 case 1: /*ABS*/
1242 {
1243 int label = gen_new_label();
1244 tcg_gen_mov_i32(cpu_R[RRR_R], cpu_R[RRR_T]);
1245 tcg_gen_brcondi_i32(
1246 TCG_COND_GE, cpu_R[RRR_R], 0, label);
1247 tcg_gen_neg_i32(cpu_R[RRR_R], cpu_R[RRR_T]);
1248 gen_set_label(label);
1249 }
1250 break;
1251
1252 default: /*reserved*/
91a5bb76 1253 RESERVED();
f331fe5e
MF		 1254 break;
1255 }
dedc5eae
MF		 1256 break;
1257
1258 case 7: /*reserved*/
91a5bb76 1259 RESERVED();
dedc5eae
MF		 1260 break;
1261
1262 case 8: /*ADD*/
772177c1 1263 gen_window_check3(dc, RRR_R, RRR_S, RRR_T);
dedc5eae
MF		 1264 tcg_gen_add_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
1265 break;
1266
1267 case 9: /*ADD**/
1268 case 10:
1269 case 11:
772177c1 1270 gen_window_check3(dc, RRR_R, RRR_S, RRR_T);
dedc5eae
MF		 1271 {
1272 TCGv_i32 tmp = tcg_temp_new_i32();
1273 tcg_gen_shli_i32(tmp, cpu_R[RRR_S], OP2 - 8);
1274 tcg_gen_add_i32(cpu_R[RRR_R], tmp, cpu_R[RRR_T]);
1275 tcg_temp_free(tmp);
1276 }
1277 break;
1278
1279 case 12: /*SUB*/
772177c1 1280 gen_window_check3(dc, RRR_R, RRR_S, RRR_T);
dedc5eae
MF		 1281 tcg_gen_sub_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
1282 break;
1283
1284 case 13: /*SUB**/
1285 case 14:
1286 case 15:
772177c1 1287 gen_window_check3(dc, RRR_R, RRR_S, RRR_T);
dedc5eae
MF		 1288 {
1289 TCGv_i32 tmp = tcg_temp_new_i32();
1290 tcg_gen_shli_i32(tmp, cpu_R[RRR_S], OP2 - 12);
1291 tcg_gen_sub_i32(cpu_R[RRR_R], tmp, cpu_R[RRR_T]);
1292 tcg_temp_free(tmp);
1293 }
1294 break;
1295 }
1296 break;
1297
1298 case 1: /*RST1*/
3580ecad
MF		 1299 switch (OP2) {
1300 case 0: /*SLLI*/
1301 case 1:
772177c1 1302 gen_window_check2(dc, RRR_R, RRR_S);
3580ecad
MF		 1303 tcg_gen_shli_i32(cpu_R[RRR_R], cpu_R[RRR_S],
1304 32 - (RRR_T | ((OP2 & 1) << 4)));
1305 break;
1306
1307 case 2: /*SRAI*/
1308 case 3:
772177c1 1309 gen_window_check2(dc, RRR_R, RRR_T);
3580ecad
MF		 1310 tcg_gen_sari_i32(cpu_R[RRR_R], cpu_R[RRR_T],
1311 RRR_S | ((OP2 & 1) << 4));
1312 break;
1313
1314 case 4: /*SRLI*/
772177c1 1315 gen_window_check2(dc, RRR_R, RRR_T);
3580ecad
MF		 1316 tcg_gen_shri_i32(cpu_R[RRR_R], cpu_R[RRR_T], RRR_S);
1317 break;
1318
1319 case 6: /*XSR*/
1320 {
1321 TCGv_i32 tmp = tcg_temp_new_i32();
40643d7c
MF		 1322 if (RSR_SR >= 64) {
1323 gen_check_privilege(dc);
1324 }
772177c1 1325 gen_window_check1(dc, RRR_T);
3580ecad
MF		 1326 tcg_gen_mov_i32(tmp, cpu_R[RRR_T]);
1327 gen_rsr(dc, cpu_R[RRR_T], RSR_SR);
1328 gen_wsr(dc, RSR_SR, tmp);
1329 tcg_temp_free(tmp);
91a5bb76
MF		 1330 if (!sregnames[RSR_SR]) {
1331 TBD();
1332 }
3580ecad
MF		 1333 }
1334 break;
1335
1336 /*
1337 * Note: 64 bit ops are used here solely because SAR values
1338 * have range 0..63
1339 */
1340#define gen_shift_reg(cmd, reg) do { \
1341 TCGv_i64 tmp = tcg_temp_new_i64(); \
1342 tcg_gen_extu_i32_i64(tmp, reg); \
1343 tcg_gen_##cmd##_i64(v, v, tmp); \
1344 tcg_gen_trunc_i64_i32(cpu_R[RRR_R], v); \
1345 tcg_temp_free_i64(v); \
1346 tcg_temp_free_i64(tmp); \
1347 } while (0)
1348
1349#define gen_shift(cmd) gen_shift_reg(cmd, cpu_SR[SAR])
1350
1351 case 8: /*SRC*/
772177c1 1352 gen_window_check3(dc, RRR_R, RRR_S, RRR_T);
3580ecad
MF		 1353 {
1354 TCGv_i64 v = tcg_temp_new_i64();
1355 tcg_gen_concat_i32_i64(v, cpu_R[RRR_T], cpu_R[RRR_S]);
1356 gen_shift(shr);
1357 }
1358 break;
1359
1360 case 9: /*SRL*/
772177c1 1361 gen_window_check2(dc, RRR_R, RRR_T);
3580ecad
MF		 1362 if (dc->sar_5bit) {
1363 tcg_gen_shr_i32(cpu_R[RRR_R], cpu_R[RRR_T], cpu_SR[SAR]);
1364 } else {
1365 TCGv_i64 v = tcg_temp_new_i64();
1366 tcg_gen_extu_i32_i64(v, cpu_R[RRR_T]);
1367 gen_shift(shr);
1368 }
1369 break;
1370
1371 case 10: /*SLL*/
772177c1 1372 gen_window_check2(dc, RRR_R, RRR_S);
3580ecad
MF		 1373 if (dc->sar_m32_5bit) {
1374 tcg_gen_shl_i32(cpu_R[RRR_R], cpu_R[RRR_S], dc->sar_m32);
1375 } else {
1376 TCGv_i64 v = tcg_temp_new_i64();
1377 TCGv_i32 s = tcg_const_i32(32);
1378 tcg_gen_sub_i32(s, s, cpu_SR[SAR]);
1379 tcg_gen_andi_i32(s, s, 0x3f);
1380 tcg_gen_extu_i32_i64(v, cpu_R[RRR_S]);
1381 gen_shift_reg(shl, s);
1382 tcg_temp_free(s);
1383 }
1384 break;
1385
1386 case 11: /*SRA*/
772177c1 1387 gen_window_check2(dc, RRR_R, RRR_T);
3580ecad
MF		 1388 if (dc->sar_5bit) {
1389 tcg_gen_sar_i32(cpu_R[RRR_R], cpu_R[RRR_T], cpu_SR[SAR]);
1390 } else {
1391 TCGv_i64 v = tcg_temp_new_i64();
1392 tcg_gen_ext_i32_i64(v, cpu_R[RRR_T]);
1393 gen_shift(sar);
1394 }
1395 break;
1396#undef gen_shift
1397#undef gen_shift_reg
1398
1399 case 12: /*MUL16U*/
1400 HAS_OPTION(XTENSA_OPTION_16_BIT_IMUL);
772177c1 1401 gen_window_check3(dc, RRR_R, RRR_S, RRR_T);
3580ecad
MF		 1402 {
1403 TCGv_i32 v1 = tcg_temp_new_i32();
1404 TCGv_i32 v2 = tcg_temp_new_i32();
1405 tcg_gen_ext16u_i32(v1, cpu_R[RRR_S]);
1406 tcg_gen_ext16u_i32(v2, cpu_R[RRR_T]);
1407 tcg_gen_mul_i32(cpu_R[RRR_R], v1, v2);
1408 tcg_temp_free(v2);
1409 tcg_temp_free(v1);
1410 }
1411 break;
1412
1413 case 13: /*MUL16S*/
1414 HAS_OPTION(XTENSA_OPTION_16_BIT_IMUL);
772177c1 1415 gen_window_check3(dc, RRR_R, RRR_S, RRR_T);
3580ecad
MF		 1416 {
1417 TCGv_i32 v1 = tcg_temp_new_i32();
1418 TCGv_i32 v2 = tcg_temp_new_i32();
1419 tcg_gen_ext16s_i32(v1, cpu_R[RRR_S]);
1420 tcg_gen_ext16s_i32(v2, cpu_R[RRR_T]);
1421 tcg_gen_mul_i32(cpu_R[RRR_R], v1, v2);
1422 tcg_temp_free(v2);
1423 tcg_temp_free(v1);
1424 }
1425 break;
1426
1427 default: /*reserved*/
91a5bb76 1428 RESERVED();
3580ecad
MF		 1429 break;
1430 }
dedc5eae
MF		 1431 break;
1432
1433 case 2: /*RST2*/
4dd85b6b
MF		 1434 if (OP2 >= 8) {
1435 gen_window_check3(dc, RRR_R, RRR_S, RRR_T);
1436 }
772177c1 1437
f76ebf55
MF		 1438 if (OP2 >= 12) {
1439 HAS_OPTION(XTENSA_OPTION_32_BIT_IDIV);
1440 int label = gen_new_label();
1441 tcg_gen_brcondi_i32(TCG_COND_NE, cpu_R[RRR_T], 0, label);
1442 gen_exception_cause(dc, INTEGER_DIVIDE_BY_ZERO_CAUSE);
1443 gen_set_label(label);
1444 }
1445
1446 switch (OP2) {
4dd85b6b
MF		 1447#define BOOLEAN_LOGIC(fn, r, s, t) \
1448 do { \
1449 HAS_OPTION(XTENSA_OPTION_BOOLEAN); \
1450 TCGv_i32 tmp1 = tcg_temp_new_i32(); \
1451 TCGv_i32 tmp2 = tcg_temp_new_i32(); \
1452 \
1453 tcg_gen_shri_i32(tmp1, cpu_SR[BR], s); \
1454 tcg_gen_shri_i32(tmp2, cpu_SR[BR], t); \
1455 tcg_gen_##fn##_i32(tmp1, tmp1, tmp2); \
1456 tcg_gen_deposit_i32(cpu_SR[BR], cpu_SR[BR], tmp1, r, 1); \
1457 tcg_temp_free(tmp1); \
1458 tcg_temp_free(tmp2); \
1459 } while (0)
1460
1461 case 0: /*ANDBp*/
1462 BOOLEAN_LOGIC(and, RRR_R, RRR_S, RRR_T);
1463 break;
1464
1465 case 1: /*ANDBCp*/
1466 BOOLEAN_LOGIC(andc, RRR_R, RRR_S, RRR_T);
1467 break;
1468
1469 case 2: /*ORBp*/
1470 BOOLEAN_LOGIC(or, RRR_R, RRR_S, RRR_T);
1471 break;
1472
1473 case 3: /*ORBCp*/
1474 BOOLEAN_LOGIC(orc, RRR_R, RRR_S, RRR_T);
1475 break;
1476
1477 case 4: /*XORBp*/
1478 BOOLEAN_LOGIC(xor, RRR_R, RRR_S, RRR_T);
1479 break;
1480
1481#undef BOOLEAN_LOGIC
1482
f76ebf55
MF		 1483 case 8: /*MULLi*/
1484 HAS_OPTION(XTENSA_OPTION_32_BIT_IMUL);
1485 tcg_gen_mul_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
1486 break;
1487
1488 case 10: /*MULUHi*/
1489 case 11: /*MULSHi*/
7f65f4b0 1490 HAS_OPTION(XTENSA_OPTION_32_BIT_IMUL_HIGH);
f76ebf55
MF		 1491 {
1492 TCGv_i64 r = tcg_temp_new_i64();
1493 TCGv_i64 s = tcg_temp_new_i64();
1494 TCGv_i64 t = tcg_temp_new_i64();
1495
1496 if (OP2 == 10) {
1497 tcg_gen_extu_i32_i64(s, cpu_R[RRR_S]);
1498 tcg_gen_extu_i32_i64(t, cpu_R[RRR_T]);
1499 } else {
1500 tcg_gen_ext_i32_i64(s, cpu_R[RRR_S]);
1501 tcg_gen_ext_i32_i64(t, cpu_R[RRR_T]);
1502 }
1503 tcg_gen_mul_i64(r, s, t);
1504 tcg_gen_shri_i64(r, r, 32);
1505 tcg_gen_trunc_i64_i32(cpu_R[RRR_R], r);
1506
1507 tcg_temp_free_i64(r);
1508 tcg_temp_free_i64(s);
1509 tcg_temp_free_i64(t);
1510 }
1511 break;
1512
1513 case 12: /*QUOUi*/
1514 tcg_gen_divu_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
1515 break;
1516
1517 case 13: /*QUOSi*/
1518 case 15: /*REMSi*/
1519 {
1520 int label1 = gen_new_label();
1521 int label2 = gen_new_label();
1522
1523 tcg_gen_brcondi_i32(TCG_COND_NE, cpu_R[RRR_S], 0x80000000,
1524 label1);
1525 tcg_gen_brcondi_i32(TCG_COND_NE, cpu_R[RRR_T], 0xffffffff,
1526 label1);
1527 tcg_gen_movi_i32(cpu_R[RRR_R],
1528 OP2 == 13 ? 0x80000000 : 0);
1529 tcg_gen_br(label2);
1530 gen_set_label(label1);
1531 if (OP2 == 13) {
1532 tcg_gen_div_i32(cpu_R[RRR_R],
1533 cpu_R[RRR_S], cpu_R[RRR_T]);
1534 } else {
1535 tcg_gen_rem_i32(cpu_R[RRR_R],
1536 cpu_R[RRR_S], cpu_R[RRR_T]);
1537 }
1538 gen_set_label(label2);
1539 }
1540 break;
1541
1542 case 14: /*REMUi*/
1543 tcg_gen_remu_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
1544 break;
1545
1546 default: /*reserved*/
1547 RESERVED();
1548 break;
1549 }
dedc5eae
MF		 1550 break;
1551
1552 case 3: /*RST3*/
b8132eff
MF		 1553 switch (OP2) {
1554 case 0: /*RSR*/
40643d7c
MF		 1555 if (RSR_SR >= 64) {
1556 gen_check_privilege(dc);
1557 }
772177c1 1558 gen_window_check1(dc, RRR_T);
b8132eff 1559 gen_rsr(dc, cpu_R[RRR_T], RSR_SR);
91a5bb76
MF		 1560 if (!sregnames[RSR_SR]) {
1561 TBD();
1562 }
b8132eff
MF		 1563 break;
1564
1565 case 1: /*WSR*/
40643d7c
MF		 1566 if (RSR_SR >= 64) {
1567 gen_check_privilege(dc);
1568 }
772177c1 1569 gen_window_check1(dc, RRR_T);
b8132eff 1570 gen_wsr(dc, RSR_SR, cpu_R[RRR_T]);
91a5bb76
MF		 1571 if (!sregnames[RSR_SR]) {
1572 TBD();
1573 }
b8132eff
MF		 1574 break;
1575
1576 case 2: /*SEXTu*/
7f65f4b0 1577 HAS_OPTION(XTENSA_OPTION_MISC_OP_SEXT);
772177c1 1578 gen_window_check2(dc, RRR_R, RRR_S);
b8132eff
MF		 1579 {
1580 int shift = 24 - RRR_T;
1581
1582 if (shift == 24) {
1583 tcg_gen_ext8s_i32(cpu_R[RRR_R], cpu_R[RRR_S]);
1584 } else if (shift == 16) {
1585 tcg_gen_ext16s_i32(cpu_R[RRR_R], cpu_R[RRR_S]);
1586 } else {
1587 TCGv_i32 tmp = tcg_temp_new_i32();
1588 tcg_gen_shli_i32(tmp, cpu_R[RRR_S], shift);
1589 tcg_gen_sari_i32(cpu_R[RRR_R], tmp, shift);
1590 tcg_temp_free(tmp);
1591 }
1592 }
1593 break;
1594
1595 case 3: /*CLAMPSu*/
7f65f4b0 1596 HAS_OPTION(XTENSA_OPTION_MISC_OP_CLAMPS);
772177c1 1597 gen_window_check2(dc, RRR_R, RRR_S);
b8132eff
MF		 1598 {
1599 TCGv_i32 tmp1 = tcg_temp_new_i32();
1600 TCGv_i32 tmp2 = tcg_temp_new_i32();
1601 int label = gen_new_label();
1602
1603 tcg_gen_sari_i32(tmp1, cpu_R[RRR_S], 24 - RRR_T);
1604 tcg_gen_xor_i32(tmp2, tmp1, cpu_R[RRR_S]);
1605 tcg_gen_andi_i32(tmp2, tmp2, 0xffffffff << (RRR_T + 7));
1606 tcg_gen_mov_i32(cpu_R[RRR_R], cpu_R[RRR_S]);
1607 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp2, 0, label);
1608
1609 tcg_gen_sari_i32(tmp1, cpu_R[RRR_S], 31);
1610 tcg_gen_xori_i32(cpu_R[RRR_R], tmp1,
1611 0xffffffff >> (25 - RRR_T));
1612
1613 gen_set_label(label);
1614
1615 tcg_temp_free(tmp1);
1616 tcg_temp_free(tmp2);
1617 }
1618 break;
1619
1620 case 4: /*MINu*/
1621 case 5: /*MAXu*/
1622 case 6: /*MINUu*/
1623 case 7: /*MAXUu*/
7f65f4b0 1624 HAS_OPTION(XTENSA_OPTION_MISC_OP_MINMAX);
772177c1 1625 gen_window_check3(dc, RRR_R, RRR_S, RRR_T);
b8132eff
MF		 1626 {
1627 static const TCGCond cond[] = {
1628 TCG_COND_LE,
1629 TCG_COND_GE,
1630 TCG_COND_LEU,
1631 TCG_COND_GEU
1632 };
1633 int label = gen_new_label();
1634
1635 if (RRR_R != RRR_T) {
1636 tcg_gen_mov_i32(cpu_R[RRR_R], cpu_R[RRR_S]);
1637 tcg_gen_brcond_i32(cond[OP2 - 4],
1638 cpu_R[RRR_S], cpu_R[RRR_T], label);
1639 tcg_gen_mov_i32(cpu_R[RRR_R], cpu_R[RRR_T]);
1640 } else {
1641 tcg_gen_brcond_i32(cond[OP2 - 4],
1642 cpu_R[RRR_T], cpu_R[RRR_S], label);
1643 tcg_gen_mov_i32(cpu_R[RRR_R], cpu_R[RRR_S]);
1644 }
1645 gen_set_label(label);
1646 }
1647 break;
1648
1649 case 8: /*MOVEQZ*/
1650 case 9: /*MOVNEZ*/
1651 case 10: /*MOVLTZ*/
1652 case 11: /*MOVGEZ*/
772177c1 1653 gen_window_check3(dc, RRR_R, RRR_S, RRR_T);
b8132eff
MF		 1654 {
1655 static const TCGCond cond[] = {
1656 TCG_COND_NE,
1657 TCG_COND_EQ,
1658 TCG_COND_GE,
1659 TCG_COND_LT
1660 };
1661 int label = gen_new_label();
1662 tcg_gen_brcondi_i32(cond[OP2 - 8], cpu_R[RRR_T], 0, label);
1663 tcg_gen_mov_i32(cpu_R[RRR_R], cpu_R[RRR_S]);
1664 gen_set_label(label);
1665 }
1666 break;
1667
1668 case 12: /*MOVFp*/
b8132eff
MF		 1669 case 13: /*MOVTp*/
1670 HAS_OPTION(XTENSA_OPTION_BOOLEAN);
4dd85b6b
MF		 1671 gen_window_check2(dc, RRR_R, RRR_S);
1672 {
1673 int label = gen_new_label();
1674 TCGv_i32 tmp = tcg_temp_new_i32();
1675
1676 tcg_gen_andi_i32(tmp, cpu_SR[BR], 1 << RRR_T);
1677 tcg_gen_brcondi_i32(
1678 OP2 & 1 ? TCG_COND_EQ : TCG_COND_NE,
1679 tmp, 0, label);
1680 tcg_gen_mov_i32(cpu_R[RRR_R], cpu_R[RRR_S]);
1681 gen_set_label(label);
1682 tcg_temp_free(tmp);
1683 }
b8132eff
MF		 1684 break;
1685
1686 case 14: /*RUR*/
772177c1 1687 gen_window_check1(dc, RRR_R);
b8132eff
MF		 1688 {
1689 int st = (RRR_S << 4) + RRR_T;
1690 if (uregnames[st]) {
1691 tcg_gen_mov_i32(cpu_R[RRR_R], cpu_UR[st]);
1692 } else {
1693 qemu_log("RUR %d not implemented, ", st);
91a5bb76 1694 TBD();
b8132eff
MF		 1695 }
1696 }
1697 break;
1698
1699 case 15: /*WUR*/
772177c1 1700 gen_window_check1(dc, RRR_T);
b8132eff
MF		 1701 {
1702 if (uregnames[RSR_SR]) {
1703 tcg_gen_mov_i32(cpu_UR[RSR_SR], cpu_R[RRR_T]);
1704 } else {
1705 qemu_log("WUR %d not implemented, ", RSR_SR);
91a5bb76 1706 TBD();
b8132eff
MF		 1707 }
1708 }
1709 break;
1710
1711 }
dedc5eae
MF		 1712 break;
1713
1714 case 4: /*EXTUI*/
1715 case 5:
772177c1 1716 gen_window_check2(dc, RRR_R, RRR_T);
3580ecad
MF		 1717 {
1718 int shiftimm = RRR_S | (OP1 << 4);
1719 int maskimm = (1 << (OP2 + 1)) - 1;
1720
1721 TCGv_i32 tmp = tcg_temp_new_i32();
1722 tcg_gen_shri_i32(tmp, cpu_R[RRR_T], shiftimm);
1723 tcg_gen_andi_i32(cpu_R[RRR_R], tmp, maskimm);
1724 tcg_temp_free(tmp);
1725 }
dedc5eae
MF		 1726 break;
1727
1728 case 6: /*CUST0*/
91a5bb76 1729 RESERVED();
dedc5eae
MF		 1730 break;
1731
1732 case 7: /*CUST1*/
91a5bb76 1733 RESERVED();
dedc5eae
MF		 1734 break;
1735
1736 case 8: /*LSCXp*/
1737 HAS_OPTION(XTENSA_OPTION_COPROCESSOR);
91a5bb76 1738 TBD();
dedc5eae
MF		 1739 break;
1740
1741 case 9: /*LSC4*/
772177c1 1742 gen_window_check2(dc, RRR_S, RRR_T);
553e44f9
MF		 1743 switch (OP2) {
1744 case 0: /*L32E*/
1745 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
1746 gen_check_privilege(dc);
1747 {
1748 TCGv_i32 addr = tcg_temp_new_i32();
1749 tcg_gen_addi_i32(addr, cpu_R[RRR_S],
1750 (0xffffffc0 | (RRR_R << 2)));
1751 tcg_gen_qemu_ld32u(cpu_R[RRR_T], addr, dc->ring);
1752 tcg_temp_free(addr);
1753 }
1754 break;
1755
1756 case 4: /*S32E*/
1757 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
1758 gen_check_privilege(dc);
1759 {
1760 TCGv_i32 addr = tcg_temp_new_i32();
1761 tcg_gen_addi_i32(addr, cpu_R[RRR_S],
1762 (0xffffffc0 | (RRR_R << 2)));
1763 tcg_gen_qemu_st32(cpu_R[RRR_T], addr, dc->ring);
1764 tcg_temp_free(addr);
1765 }
1766 break;
1767
1768 default:
1769 RESERVED();
1770 break;
1771 }
dedc5eae
MF		 1772 break;
1773
1774 case 10: /*FP0*/
1775 HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR);
91a5bb76 1776 TBD();
dedc5eae
MF		 1777 break;
1778
1779 case 11: /*FP1*/
1780 HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR);
91a5bb76 1781 TBD();
dedc5eae
MF		 1782 break;
1783
1784 default: /*reserved*/
91a5bb76 1785 RESERVED();
dedc5eae
MF		 1786 break;
1787 }
1788 break;
1789
1790 case 1: /*L32R*/
772177c1 1791 gen_window_check1(dc, RRR_T);
dedc5eae
MF		 1792 {
1793 TCGv_i32 tmp = tcg_const_i32(
6ad6dbf7
MF		 1794 ((dc->tb->flags & XTENSA_TBFLAG_LITBASE) ?
1795 0 : ((dc->pc + 3) & ~3)) +
1796 (0xfffc0000 | (RI16_IMM16 << 2)));
dedc5eae 1797
6ad6dbf7
MF		 1798 if (dc->tb->flags & XTENSA_TBFLAG_LITBASE) {
1799 tcg_gen_add_i32(tmp, tmp, dc->litbase);
1800 }
f0a548b9 1801 tcg_gen_qemu_ld32u(cpu_R[RRR_T], tmp, dc->cring);
dedc5eae
MF		 1802 tcg_temp_free(tmp);
1803 }
1804 break;
1805
1806 case 2: /*LSAI*/
809377aa
MF		 1807#define gen_load_store(type, shift) do { \
1808 TCGv_i32 addr = tcg_temp_new_i32(); \
772177c1 1809 gen_window_check2(dc, RRI8_S, RRI8_T); \
809377aa 1810 tcg_gen_addi_i32(addr, cpu_R[RRI8_S], RRI8_IMM8 << shift); \
5b4e481b
MF		 1811 if (shift) { \
1812 gen_load_store_alignment(dc, shift, addr, false); \
1813 } \
f0a548b9 1814 tcg_gen_qemu_##type(cpu_R[RRI8_T], addr, dc->cring); \
809377aa
MF		 1815 tcg_temp_free(addr); \
1816 } while (0)
1817
1818 switch (RRI8_R) {
1819 case 0: /*L8UI*/
1820 gen_load_store(ld8u, 0);
1821 break;
1822
1823 case 1: /*L16UI*/
1824 gen_load_store(ld16u, 1);
1825 break;
1826
1827 case 2: /*L32I*/
1828 gen_load_store(ld32u, 2);
1829 break;
1830
1831 case 4: /*S8I*/
1832 gen_load_store(st8, 0);
1833 break;
1834
1835 case 5: /*S16I*/
1836 gen_load_store(st16, 1);
1837 break;
1838
1839 case 6: /*S32I*/
1840 gen_load_store(st32, 2);
1841 break;
1842
1843 case 7: /*CACHEc*/
8ffc2d0d
MF		 1844 if (RRI8_T < 8) {
1845 HAS_OPTION(XTENSA_OPTION_DCACHE);
1846 }
1847
1848 switch (RRI8_T) {
1849 case 0: /*DPFRc*/
1850 break;
1851
1852 case 1: /*DPFWc*/
1853 break;
1854
1855 case 2: /*DPFROc*/
1856 break;
1857
1858 case 3: /*DPFWOc*/
1859 break;
1860
1861 case 4: /*DHWBc*/
1862 break;
1863
1864 case 5: /*DHWBIc*/
1865 break;
1866
1867 case 6: /*DHIc*/
1868 break;
1869
1870 case 7: /*DIIc*/
1871 break;
1872
1873 case 8: /*DCEc*/
1874 switch (OP1) {
1875 case 0: /*DPFLl*/
1876 HAS_OPTION(XTENSA_OPTION_DCACHE_INDEX_LOCK);
1877 break;
1878
1879 case 2: /*DHUl*/
1880 HAS_OPTION(XTENSA_OPTION_DCACHE_INDEX_LOCK);
1881 break;
1882
1883 case 3: /*DIUl*/
1884 HAS_OPTION(XTENSA_OPTION_DCACHE_INDEX_LOCK);
1885 break;
1886
1887 case 4: /*DIWBc*/
1888 HAS_OPTION(XTENSA_OPTION_DCACHE);
1889 break;
1890
1891 case 5: /*DIWBIc*/
1892 HAS_OPTION(XTENSA_OPTION_DCACHE);
1893 break;
1894
1895 default: /*reserved*/
1896 RESERVED();
1897 break;
1898
1899 }
1900 break;
1901
1902 case 12: /*IPFc*/
1903 HAS_OPTION(XTENSA_OPTION_ICACHE);
1904 break;
1905
1906 case 13: /*ICEc*/
1907 switch (OP1) {
1908 case 0: /*IPFLl*/
1909 HAS_OPTION(XTENSA_OPTION_ICACHE_INDEX_LOCK);
1910 break;
1911
1912 case 2: /*IHUl*/
1913 HAS_OPTION(XTENSA_OPTION_ICACHE_INDEX_LOCK);
1914 break;
1915
1916 case 3: /*IIUl*/
1917 HAS_OPTION(XTENSA_OPTION_ICACHE_INDEX_LOCK);
1918 break;
1919
1920 default: /*reserved*/
1921 RESERVED();
1922 break;
1923 }
1924 break;
1925
1926 case 14: /*IHIc*/
1927 HAS_OPTION(XTENSA_OPTION_ICACHE);
1928 break;
1929
1930 case 15: /*IIIc*/
1931 HAS_OPTION(XTENSA_OPTION_ICACHE);
1932 break;
1933
1934 default: /*reserved*/
1935 RESERVED();
1936 break;
1937 }
809377aa
MF		 1938 break;
1939
1940 case 9: /*L16SI*/
1941 gen_load_store(ld16s, 1);
1942 break;
5b4e481b 1943#undef gen_load_store
809377aa
MF		 1944
1945 case 10: /*MOVI*/
772177c1 1946 gen_window_check1(dc, RRI8_T);
809377aa
MF		 1947 tcg_gen_movi_i32(cpu_R[RRI8_T],
1948 RRI8_IMM8 | (RRI8_S << 8) |
1949 ((RRI8_S & 0x8) ? 0xfffff000 : 0));
1950 break;
1951
5b4e481b
MF		 1952#define gen_load_store_no_hw_align(type) do { \
1953 TCGv_i32 addr = tcg_temp_local_new_i32(); \
772177c1 1954 gen_window_check2(dc, RRI8_S, RRI8_T); \
5b4e481b
MF		 1955 tcg_gen_addi_i32(addr, cpu_R[RRI8_S], RRI8_IMM8 << 2); \
1956 gen_load_store_alignment(dc, 2, addr, true); \
1957 tcg_gen_qemu_##type(cpu_R[RRI8_T], addr, dc->cring); \
1958 tcg_temp_free(addr); \
1959 } while (0)
1960
809377aa
MF		 1961 case 11: /*L32AIy*/
1962 HAS_OPTION(XTENSA_OPTION_MP_SYNCHRO);
5b4e481b 1963 gen_load_store_no_hw_align(ld32u); /*TODO acquire?*/
809377aa
MF		 1964 break;
1965
1966 case 12: /*ADDI*/
772177c1 1967 gen_window_check2(dc, RRI8_S, RRI8_T);
809377aa
MF		 1968 tcg_gen_addi_i32(cpu_R[RRI8_T], cpu_R[RRI8_S], RRI8_IMM8_SE);
1969 break;
1970
1971 case 13: /*ADDMI*/
772177c1 1972 gen_window_check2(dc, RRI8_S, RRI8_T);
809377aa
MF		 1973 tcg_gen_addi_i32(cpu_R[RRI8_T], cpu_R[RRI8_S], RRI8_IMM8_SE << 8);
1974 break;
1975
1976 case 14: /*S32C1Iy*/
7f65f4b0 1977 HAS_OPTION(XTENSA_OPTION_CONDITIONAL_STORE);
772177c1 1978 gen_window_check2(dc, RRI8_S, RRI8_T);
809377aa
MF		 1979 {
1980 int label = gen_new_label();
1981 TCGv_i32 tmp = tcg_temp_local_new_i32();
1982 TCGv_i32 addr = tcg_temp_local_new_i32();
1983
1984 tcg_gen_mov_i32(tmp, cpu_R[RRI8_T]);
1985 tcg_gen_addi_i32(addr, cpu_R[RRI8_S], RRI8_IMM8 << 2);
5b4e481b 1986 gen_load_store_alignment(dc, 2, addr, true);
f0a548b9 1987 tcg_gen_qemu_ld32u(cpu_R[RRI8_T], addr, dc->cring);
809377aa
MF		 1988 tcg_gen_brcond_i32(TCG_COND_NE, cpu_R[RRI8_T],
1989 cpu_SR[SCOMPARE1], label);
1990
f0a548b9 1991 tcg_gen_qemu_st32(tmp, addr, dc->cring);
809377aa
MF		 1992
1993 gen_set_label(label);
1994 tcg_temp_free(addr);
1995 tcg_temp_free(tmp);
1996 }
1997 break;
1998
1999 case 15: /*S32RIy*/
2000 HAS_OPTION(XTENSA_OPTION_MP_SYNCHRO);
5b4e481b 2001 gen_load_store_no_hw_align(st32); /*TODO release?*/
809377aa 2002 break;
5b4e481b 2003#undef gen_load_store_no_hw_align
809377aa
MF		 2004
2005 default: /*reserved*/
91a5bb76 2006 RESERVED();
809377aa
MF		 2007 break;
2008 }
dedc5eae
MF		 2009 break;
2010
2011 case 3: /*LSCIp*/
2012 HAS_OPTION(XTENSA_OPTION_COPROCESSOR);
91a5bb76 2013 TBD();
dedc5eae
MF		 2014 break;
2015
2016 case 4: /*MAC16d*/
2017 HAS_OPTION(XTENSA_OPTION_MAC16);
6825b6c3
MF		 2018 {
2019 enum {
2020 MAC16_UMUL = 0x0,
2021 MAC16_MUL = 0x4,
2022 MAC16_MULA = 0x8,
2023 MAC16_MULS = 0xc,
2024 MAC16_NONE = 0xf,
2025 } op = OP1 & 0xc;
2026 bool is_m1_sr = (OP2 & 0x3) == 2;
2027 bool is_m2_sr = (OP2 & 0xc) == 0;
2028 uint32_t ld_offset = 0;
2029
2030 if (OP2 > 9) {
2031 RESERVED();
2032 }
2033
2034 switch (OP2 & 2) {
2035 case 0: /*MACI?/MACC?*/
2036 is_m1_sr = true;
2037 ld_offset = (OP2 & 1) ? -4 : 4;
2038
2039 if (OP2 >= 8) { /*MACI/MACC*/
2040 if (OP1 == 0) { /*LDINC/LDDEC*/
2041 op = MAC16_NONE;
2042 } else {
2043 RESERVED();
2044 }
2045 } else if (op != MAC16_MULA) { /*MULA.*.*.LDINC/LDDEC*/
2046 RESERVED();
2047 }
2048 break;
2049
2050 case 2: /*MACD?/MACA?*/
2051 if (op == MAC16_UMUL && OP2 != 7) { /*UMUL only in MACAA*/
2052 RESERVED();
2053 }
2054 break;
2055 }
2056
2057 if (op != MAC16_NONE) {
2058 if (!is_m1_sr) {
2059 gen_window_check1(dc, RRR_S);
2060 }
2061 if (!is_m2_sr) {
2062 gen_window_check1(dc, RRR_T);
2063 }
2064 }
2065
2066 {
2067 TCGv_i32 vaddr = tcg_temp_new_i32();
2068 TCGv_i32 mem32 = tcg_temp_new_i32();
2069
2070 if (ld_offset) {
2071 gen_window_check1(dc, RRR_S);
2072 tcg_gen_addi_i32(vaddr, cpu_R[RRR_S], ld_offset);
2073 gen_load_store_alignment(dc, 2, vaddr, false);
2074 tcg_gen_qemu_ld32u(mem32, vaddr, dc->cring);
2075 }
2076 if (op != MAC16_NONE) {
2077 TCGv_i32 m1 = gen_mac16_m(
2078 is_m1_sr ? cpu_SR[MR + RRR_X] : cpu_R[RRR_S],
2079 OP1 & 1, op == MAC16_UMUL);
2080 TCGv_i32 m2 = gen_mac16_m(
2081 is_m2_sr ? cpu_SR[MR + 2 + RRR_Y] : cpu_R[RRR_T],
2082 OP1 & 2, op == MAC16_UMUL);
2083
2084 if (op == MAC16_MUL || op == MAC16_UMUL) {
2085 tcg_gen_mul_i32(cpu_SR[ACCLO], m1, m2);
2086 if (op == MAC16_UMUL) {
2087 tcg_gen_movi_i32(cpu_SR[ACCHI], 0);
2088 } else {
2089 tcg_gen_sari_i32(cpu_SR[ACCHI], cpu_SR[ACCLO], 31);
2090 }
2091 } else {
2092 TCGv_i32 res = tcg_temp_new_i32();
2093 TCGv_i64 res64 = tcg_temp_new_i64();
2094 TCGv_i64 tmp = tcg_temp_new_i64();
2095
2096 tcg_gen_mul_i32(res, m1, m2);
2097 tcg_gen_ext_i32_i64(res64, res);
2098 tcg_gen_concat_i32_i64(tmp,
2099 cpu_SR[ACCLO], cpu_SR[ACCHI]);
2100 if (op == MAC16_MULA) {
2101 tcg_gen_add_i64(tmp, tmp, res64);
2102 } else {
2103 tcg_gen_sub_i64(tmp, tmp, res64);
2104 }
2105 tcg_gen_trunc_i64_i32(cpu_SR[ACCLO], tmp);
2106 tcg_gen_shri_i64(tmp, tmp, 32);
2107 tcg_gen_trunc_i64_i32(cpu_SR[ACCHI], tmp);
2108 tcg_gen_ext8s_i32(cpu_SR[ACCHI], cpu_SR[ACCHI]);
2109
2110 tcg_temp_free(res);
2111 tcg_temp_free_i64(res64);
2112 tcg_temp_free_i64(tmp);
2113 }
2114 tcg_temp_free(m1);
2115 tcg_temp_free(m2);
2116 }
2117 if (ld_offset) {
2118 tcg_gen_mov_i32(cpu_R[RRR_S], vaddr);
2119 tcg_gen_mov_i32(cpu_SR[MR + RRR_W], mem32);
2120 }
2121 tcg_temp_free(vaddr);
2122 tcg_temp_free(mem32);
2123 }
2124 }
dedc5eae
MF		 2125 break;
2126
2127 case 5: /*CALLN*/
2128 switch (CALL_N) {
2129 case 0: /*CALL0*/
2130 tcg_gen_movi_i32(cpu_R[0], dc->next_pc);
2131 gen_jumpi(dc, (dc->pc & ~3) + (CALL_OFFSET_SE << 2) + 4, 0);
2132 break;
2133
2134 case 1: /*CALL4w*/
2135 case 2: /*CALL8w*/
2136 case 3: /*CALL12w*/
2137 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
772177c1 2138 gen_window_check1(dc, CALL_N << 2);
553e44f9
MF		 2139 gen_callwi(dc, CALL_N,
2140 (dc->pc & ~3) + (CALL_OFFSET_SE << 2) + 4, 0);
dedc5eae
MF		 2141 break;
2142 }
2143 break;
2144
2145 case 6: /*SI*/
2146 switch (CALL_N) {
2147 case 0: /*J*/
2148 gen_jumpi(dc, dc->pc + 4 + CALL_OFFSET_SE, 0);
2149 break;
2150
bd57fb91 2151 case 1: /*BZ*/
772177c1 2152 gen_window_check1(dc, BRI12_S);
bd57fb91
MF		 2153 {
2154 static const TCGCond cond[] = {
2155 TCG_COND_EQ, /*BEQZ*/
2156 TCG_COND_NE, /*BNEZ*/
2157 TCG_COND_LT, /*BLTZ*/
2158 TCG_COND_GE, /*BGEZ*/
2159 };
2160
2161 gen_brcondi(dc, cond[BRI12_M & 3], cpu_R[BRI12_S], 0,
2162 4 + BRI12_IMM12_SE);
2163 }
2164 break;
2165
2166 case 2: /*BI0*/
772177c1 2167 gen_window_check1(dc, BRI8_S);
bd57fb91
MF		 2168 {
2169 static const TCGCond cond[] = {
2170 TCG_COND_EQ, /*BEQI*/
2171 TCG_COND_NE, /*BNEI*/
2172 TCG_COND_LT, /*BLTI*/
2173 TCG_COND_GE, /*BGEI*/
2174 };
2175
2176 gen_brcondi(dc, cond[BRI8_M & 3],
2177 cpu_R[BRI8_S], B4CONST[BRI8_R], 4 + BRI8_IMM8_SE);
2178 }
2179 break;
2180
2181 case 3: /*BI1*/
2182 switch (BRI8_M) {
2183 case 0: /*ENTRYw*/
2184 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
553e44f9
MF		 2185 {
2186 TCGv_i32 pc = tcg_const_i32(dc->pc);
2187 TCGv_i32 s = tcg_const_i32(BRI12_S);
2188 TCGv_i32 imm = tcg_const_i32(BRI12_IMM12);
b994e91b 2189 gen_advance_ccount(dc);
553e44f9
MF		 2190 gen_helper_entry(pc, s, imm);
2191 tcg_temp_free(imm);
2192 tcg_temp_free(s);
2193 tcg_temp_free(pc);
772177c1 2194 reset_used_window(dc);
553e44f9 2195 }
bd57fb91
MF		 2196 break;
2197
2198 case 1: /*B1*/
2199 switch (BRI8_R) {
2200 case 0: /*BFp*/
bd57fb91
MF		 2201 case 1: /*BTp*/
2202 HAS_OPTION(XTENSA_OPTION_BOOLEAN);
4dd85b6b
MF		 2203 {
2204 TCGv_i32 tmp = tcg_temp_new_i32();
2205 tcg_gen_andi_i32(tmp, cpu_SR[BR], 1 << RRI8_S);
2206 gen_brcondi(dc,
2207 BRI8_R == 1 ? TCG_COND_NE : TCG_COND_EQ,
2208 tmp, 0, 4 + RRI8_IMM8_SE);
2209 tcg_temp_free(tmp);
2210 }
bd57fb91
MF		 2211 break;
2212
2213 case 8: /*LOOP*/
bd57fb91 2214 case 9: /*LOOPNEZ*/
bd57fb91 2215 case 10: /*LOOPGTZ*/
797d780b 2216 HAS_OPTION(XTENSA_OPTION_LOOP);
772177c1 2217 gen_window_check1(dc, RRI8_S);
797d780b
MF		 2218 {
2219 uint32_t lend = dc->pc + RRI8_IMM8 + 4;
2220 TCGv_i32 tmp = tcg_const_i32(lend);
2221
2222 tcg_gen_subi_i32(cpu_SR[LCOUNT], cpu_R[RRI8_S], 1);
2223 tcg_gen_movi_i32(cpu_SR[LBEG], dc->next_pc);
2224 gen_wsr_lend(dc, LEND, tmp);
2225 tcg_temp_free(tmp);
2226
2227 if (BRI8_R > 8) {
2228 int label = gen_new_label();
2229 tcg_gen_brcondi_i32(
2230 BRI8_R == 9 ? TCG_COND_NE : TCG_COND_GT,
2231 cpu_R[RRI8_S], 0, label);
2232 gen_jumpi(dc, lend, 1);
2233 gen_set_label(label);
2234 }
2235
2236 gen_jumpi(dc, dc->next_pc, 0);
2237 }
bd57fb91
MF		 2238 break;
2239
2240 default: /*reserved*/
91a5bb76 2241 RESERVED();
bd57fb91
MF		 2242 break;
2243
2244 }
2245 break;
2246
2247 case 2: /*BLTUI*/
2248 case 3: /*BGEUI*/
772177c1 2249 gen_window_check1(dc, BRI8_S);
bd57fb91
MF		 2250 gen_brcondi(dc, BRI8_M == 2 ? TCG_COND_LTU : TCG_COND_GEU,
2251 cpu_R[BRI8_S], B4CONSTU[BRI8_R], 4 + BRI8_IMM8_SE);
2252 break;
2253 }
2254 break;
2255
dedc5eae
MF		 2256 }
2257 break;
2258
2259 case 7: /*B*/
bd57fb91
MF		 2260 {
2261 TCGCond eq_ne = (RRI8_R & 8) ? TCG_COND_NE : TCG_COND_EQ;
2262
2263 switch (RRI8_R & 7) {
2264 case 0: /*BNONE*/ /*BANY*/
772177c1 2265 gen_window_check2(dc, RRI8_S, RRI8_T);
bd57fb91
MF		 2266 {
2267 TCGv_i32 tmp = tcg_temp_new_i32();
2268 tcg_gen_and_i32(tmp, cpu_R[RRI8_S], cpu_R[RRI8_T]);
2269 gen_brcondi(dc, eq_ne, tmp, 0, 4 + RRI8_IMM8_SE);
2270 tcg_temp_free(tmp);
2271 }
2272 break;
2273
2274 case 1: /*BEQ*/ /*BNE*/
2275 case 2: /*BLT*/ /*BGE*/
2276 case 3: /*BLTU*/ /*BGEU*/
772177c1 2277 gen_window_check2(dc, RRI8_S, RRI8_T);
bd57fb91
MF		 2278 {
2279 static const TCGCond cond[] = {
2280 [1] = TCG_COND_EQ,
2281 [2] = TCG_COND_LT,
2282 [3] = TCG_COND_LTU,
2283 [9] = TCG_COND_NE,
2284 [10] = TCG_COND_GE,
2285 [11] = TCG_COND_GEU,
2286 };
2287 gen_brcond(dc, cond[RRI8_R], cpu_R[RRI8_S], cpu_R[RRI8_T],
2288 4 + RRI8_IMM8_SE);
2289 }
2290 break;
2291
2292 case 4: /*BALL*/ /*BNALL*/
772177c1 2293 gen_window_check2(dc, RRI8_S, RRI8_T);
bd57fb91
MF		 2294 {
2295 TCGv_i32 tmp = tcg_temp_new_i32();
2296 tcg_gen_and_i32(tmp, cpu_R[RRI8_S], cpu_R[RRI8_T]);
2297 gen_brcond(dc, eq_ne, tmp, cpu_R[RRI8_T],
2298 4 + RRI8_IMM8_SE);
2299 tcg_temp_free(tmp);
2300 }
2301 break;
2302
2303 case 5: /*BBC*/ /*BBS*/
772177c1 2304 gen_window_check2(dc, RRI8_S, RRI8_T);
bd57fb91
MF		 2305 {
2306 TCGv_i32 bit = tcg_const_i32(1);
2307 TCGv_i32 tmp = tcg_temp_new_i32();
2308 tcg_gen_andi_i32(tmp, cpu_R[RRI8_T], 0x1f);
2309 tcg_gen_shl_i32(bit, bit, tmp);
2310 tcg_gen_and_i32(tmp, cpu_R[RRI8_S], bit);
2311 gen_brcondi(dc, eq_ne, tmp, 0, 4 + RRI8_IMM8_SE);
2312 tcg_temp_free(tmp);
2313 tcg_temp_free(bit);
2314 }
2315 break;
2316
2317 case 6: /*BBCI*/ /*BBSI*/
2318 case 7:
772177c1 2319 gen_window_check1(dc, RRI8_S);
bd57fb91
MF		 2320 {
2321 TCGv_i32 tmp = tcg_temp_new_i32();
2322 tcg_gen_andi_i32(tmp, cpu_R[RRI8_S],
2323 1 << (((RRI8_R & 1) << 4) | RRI8_T));
2324 gen_brcondi(dc, eq_ne, tmp, 0, 4 + RRI8_IMM8_SE);
2325 tcg_temp_free(tmp);
2326 }
2327 break;
2328
2329 }
2330 }
dedc5eae
MF		 2331 break;
2332
67882fd1
MF		 2333#define gen_narrow_load_store(type) do { \
2334 TCGv_i32 addr = tcg_temp_new_i32(); \
772177c1 2335 gen_window_check2(dc, RRRN_S, RRRN_T); \
67882fd1 2336 tcg_gen_addi_i32(addr, cpu_R[RRRN_S], RRRN_R << 2); \
5b4e481b 2337 gen_load_store_alignment(dc, 2, addr, false); \
f0a548b9 2338 tcg_gen_qemu_##type(cpu_R[RRRN_T], addr, dc->cring); \
67882fd1
MF		 2339 tcg_temp_free(addr); \
2340 } while (0)
2341
dedc5eae 2342 case 8: /*L32I.Nn*/
67882fd1 2343 gen_narrow_load_store(ld32u);
dedc5eae
MF		 2344 break;
2345
2346 case 9: /*S32I.Nn*/
67882fd1 2347 gen_narrow_load_store(st32);
dedc5eae 2348 break;
67882fd1 2349#undef gen_narrow_load_store
dedc5eae
MF		 2350
2351 case 10: /*ADD.Nn*/
772177c1 2352 gen_window_check3(dc, RRRN_R, RRRN_S, RRRN_T);
67882fd1 2353 tcg_gen_add_i32(cpu_R[RRRN_R], cpu_R[RRRN_S], cpu_R[RRRN_T]);
dedc5eae
MF		 2354 break;
2355
2356 case 11: /*ADDI.Nn*/
772177c1 2357 gen_window_check2(dc, RRRN_R, RRRN_S);
67882fd1 2358 tcg_gen_addi_i32(cpu_R[RRRN_R], cpu_R[RRRN_S], RRRN_T ? RRRN_T : -1);
dedc5eae
MF		 2359 break;
2360
2361 case 12: /*ST2n*/
772177c1 2362 gen_window_check1(dc, RRRN_S);
67882fd1
MF		 2363 if (RRRN_T < 8) { /*MOVI.Nn*/
2364 tcg_gen_movi_i32(cpu_R[RRRN_S],
2365 RRRN_R | (RRRN_T << 4) |
2366 ((RRRN_T & 6) == 6 ? 0xffffff80 : 0));
2367 } else { /*BEQZ.Nn*/ /*BNEZ.Nn*/
bd57fb91
MF		 2368 TCGCond eq_ne = (RRRN_T & 4) ? TCG_COND_NE : TCG_COND_EQ;
2369
2370 gen_brcondi(dc, eq_ne, cpu_R[RRRN_S], 0,
2371 4 + (RRRN_R | ((RRRN_T & 3) << 4)));
67882fd1 2372 }
dedc5eae
MF		 2373 break;
2374
2375 case 13: /*ST3n*/
67882fd1
MF		 2376 switch (RRRN_R) {
2377 case 0: /*MOV.Nn*/
772177c1 2378 gen_window_check2(dc, RRRN_S, RRRN_T);
67882fd1
MF		 2379 tcg_gen_mov_i32(cpu_R[RRRN_T], cpu_R[RRRN_S]);
2380 break;
2381
2382 case 15: /*S3*/
2383 switch (RRRN_T) {
2384 case 0: /*RET.Nn*/
2385 gen_jump(dc, cpu_R[0]);
2386 break;
2387
2388 case 1: /*RETW.Nn*/
91a5bb76 2389 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
553e44f9
MF		 2390 {
2391 TCGv_i32 tmp = tcg_const_i32(dc->pc);
b994e91b 2392 gen_advance_ccount(dc);
553e44f9
MF		 2393 gen_helper_retw(tmp, tmp);
2394 gen_jump(dc, tmp);
2395 tcg_temp_free(tmp);
2396 }
67882fd1
MF		 2397 break;
2398
2399 case 2: /*BREAK.Nn*/
e61dc8f7
MF		 2400 HAS_OPTION(XTENSA_OPTION_DEBUG);
2401 if (dc->debug) {
2402 gen_debug_exception(dc, DEBUGCAUSE_BN);
2403 }
67882fd1
MF		 2404 break;
2405
2406 case 3: /*NOP.Nn*/
2407 break;
2408
2409 case 6: /*ILL.Nn*/
40643d7c 2410 gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);
67882fd1
MF		 2411 break;
2412
2413 default: /*reserved*/
91a5bb76 2414 RESERVED();
67882fd1
MF		 2415 break;
2416 }
2417 break;
2418
2419 default: /*reserved*/
91a5bb76 2420 RESERVED();
67882fd1
MF		 2421 break;
2422 }
dedc5eae
MF		 2423 break;
2424
2425 default: /*reserved*/
91a5bb76 2426 RESERVED();
dedc5eae
MF		 2427 break;
2428 }
2429
797d780b 2430 gen_check_loop_end(dc, 0);
dedc5eae 2431 dc->pc = dc->next_pc;
797d780b 2432
dedc5eae
MF		 2433 return;
2434
2435invalid_opcode:
2436 qemu_log("INVALID(pc = %08x)\n", dc->pc);
6b814719 2437 gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);
dedc5eae
MF		 2438#undef HAS_OPTION
2439}
2440
2441static void check_breakpoint(CPUState *env, DisasContext *dc)
2442{
2443 CPUBreakpoint *bp;
2444
2445 if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
2446 QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
2447 if (bp->pc == dc->pc) {
2448 tcg_gen_movi_i32(cpu_pc, dc->pc);
b994e91b 2449 gen_exception(dc, EXCP_DEBUG);
dedc5eae
MF		 2450 dc->is_jmp = DISAS_UPDATE;
2451 }
2452 }
2453 }
2454}
2455
e61dc8f7
MF		 2456static void gen_ibreak_check(CPUState *env, DisasContext *dc)
2457{
2458 unsigned i;
2459
2460 for (i = 0; i < dc->config->nibreak; ++i) {
2461 if ((env->sregs[IBREAKENABLE] & (1 << i)) &&
2462 env->sregs[IBREAKA + i] == dc->pc) {
2463 gen_debug_exception(dc, DEBUGCAUSE_IB);
2464 break;
2465 }
2466 }
2467}
2468
dedc5eae
MF		 2469static void gen_intermediate_code_internal(
2470 CPUState *env, TranslationBlock *tb, int search_pc)
2471{
2472 DisasContext dc;
2473 int insn_count = 0;
2474 int j, lj = -1;
2475 uint16_t *gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
2476 int max_insns = tb->cflags & CF_COUNT_MASK;
2477 uint32_t pc_start = tb->pc;
2478 uint32_t next_page_start =
2479 (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
2480
2481 if (max_insns == 0) {
2482 max_insns = CF_COUNT_MASK;
2483 }
2484
2485 dc.config = env->config;
2486 dc.singlestep_enabled = env->singlestep_enabled;
2487 dc.tb = tb;
2488 dc.pc = pc_start;
f0a548b9
MF		 2489 dc.ring = tb->flags & XTENSA_TBFLAG_RING_MASK;
2490 dc.cring = (tb->flags & XTENSA_TBFLAG_EXCM) ? 0 : dc.ring;
797d780b
MF		 2491 dc.lbeg = env->sregs[LBEG];
2492 dc.lend = env->sregs[LEND];
dedc5eae 2493 dc.is_jmp = DISAS_NEXT;
b994e91b 2494 dc.ccount_delta = 0;
e61dc8f7 2495 dc.debug = tb->flags & XTENSA_TBFLAG_DEBUG;
dedc5eae 2496
6ad6dbf7 2497 init_litbase(&dc);
3580ecad 2498 init_sar_tracker(&dc);
772177c1 2499 reset_used_window(&dc);
3580ecad 2500
dedc5eae
MF		 2501 gen_icount_start();
2502
40643d7c
MF		 2503 if (env->singlestep_enabled && env->exception_taken) {
2504 env->exception_taken = 0;
2505 tcg_gen_movi_i32(cpu_pc, dc.pc);
b994e91b 2506 gen_exception(&dc, EXCP_DEBUG);
40643d7c
MF		 2507 }
2508
dedc5eae
MF		 2509 do {
2510 check_breakpoint(env, &dc);
2511
2512 if (search_pc) {
2513 j = gen_opc_ptr - gen_opc_buf;
2514 if (lj < j) {
2515 lj++;
2516 while (lj < j) {
2517 gen_opc_instr_start[lj++] = 0;
2518 }
2519 }
2520 gen_opc_pc[lj] = dc.pc;
2521 gen_opc_instr_start[lj] = 1;
2522 gen_opc_icount[lj] = insn_count;
2523 }
2524
2525 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP))) {
2526 tcg_gen_debug_insn_start(dc.pc);
2527 }
2528
b994e91b
MF		 2529 ++dc.ccount_delta;
2530
2531 if (insn_count + 1 == max_insns && (tb->cflags & CF_LAST_IO)) {
2532 gen_io_start();
2533 }
2534
e61dc8f7
MF		 2535 if (dc.debug) {
2536 gen_ibreak_check(env, &dc);
2537 }
2538
dedc5eae
MF		 2539 disas_xtensa_insn(&dc);
2540 ++insn_count;
2541 if (env->singlestep_enabled) {
2542 tcg_gen_movi_i32(cpu_pc, dc.pc);
b994e91b 2543 gen_exception(&dc, EXCP_DEBUG);
dedc5eae
MF		 2544 break;
2545 }
2546 } while (dc.is_jmp == DISAS_NEXT &&
2547 insn_count < max_insns &&
2548 dc.pc < next_page_start &&
2549 gen_opc_ptr < gen_opc_end);
2550
6ad6dbf7 2551 reset_litbase(&dc);
3580ecad
MF		 2552 reset_sar_tracker(&dc);
2553
b994e91b
MF		 2554 if (tb->cflags & CF_LAST_IO) {
2555 gen_io_end();
2556 }
2557
dedc5eae
MF		 2558 if (dc.is_jmp == DISAS_NEXT) {
2559 gen_jumpi(&dc, dc.pc, 0);
2560 }
2561 gen_icount_end(tb, insn_count);
2562 *gen_opc_ptr = INDEX_op_end;
2563
2564 if (!search_pc) {
2565 tb->size = dc.pc - pc_start;
2566 tb->icount = insn_count;
2567 }
2328826b
MF		 2568}
2569
2570void gen_intermediate_code(CPUState *env, TranslationBlock *tb)
2571{
dedc5eae 2572 gen_intermediate_code_internal(env, tb, 0);
2328826b
MF		 2573}
2574
2575void gen_intermediate_code_pc(CPUState *env, TranslationBlock *tb)
2576{
dedc5eae 2577 gen_intermediate_code_internal(env, tb, 1);
2328826b
MF		 2578}
2579
2580void cpu_dump_state(CPUState *env, FILE *f, fprintf_function cpu_fprintf,
2581 int flags)
2582{
2af3da91
MF		 2583 int i, j;
2584
2585 cpu_fprintf(f, "PC=%08x\n\n", env->pc);
2586
2587 for (i = j = 0; i < 256; ++i) {
2588 if (sregnames[i]) {
2589 cpu_fprintf(f, "%s=%08x%c", sregnames[i], env->sregs[i],
2590 (j++ % 4) == 3 ? '\n' : ' ');
2591 }
2592 }
2593
2594 cpu_fprintf(f, (j % 4) == 0 ? "\n" : "\n\n");
2595
2596 for (i = j = 0; i < 256; ++i) {
2597 if (uregnames[i]) {
2598 cpu_fprintf(f, "%s=%08x%c", uregnames[i], env->uregs[i],
2599 (j++ % 4) == 3 ? '\n' : ' ');
2600 }
2601 }
2328826b 2602
2af3da91 2603 cpu_fprintf(f, (j % 4) == 0 ? "\n" : "\n\n");
2328826b
MF		 2604
2605 for (i = 0; i < 16; ++i) {
2606 cpu_fprintf(f, "A%02d=%08x%c", i, env->regs[i],
2607 (i % 4) == 3 ? '\n' : ' ');
2608 }
553e44f9
MF		 2609
2610 cpu_fprintf(f, "\n");
2611
2612 for (i = 0; i < env->config->nareg; ++i) {
2613 cpu_fprintf(f, "AR%02d=%08x%c", i, env->phys_regs[i],
2614 (i % 4) == 3 ? '\n' : ' ');
2615 }
2328826b
MF		 2616}
2617
2618void restore_state_to_opc(CPUState *env, TranslationBlock *tb, int pc_pos)
2619{
2620 env->pc = gen_opc_pc[pc_pos];
2621}
Qemu copy for testing