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1Tiny Code Generator - Fabrice Bellard.
2
31) Introduction
4
5TCG (Tiny Code Generator) began as a generic backend for a C
6compiler. It was simplified to be used in QEMU. It also has its roots
7in the QOP code generator written by Paul Brook.
8
92) Definitions
10
11The TCG "target" is the architecture for which we generate the
12code. It is of course not the same as the "target" of QEMU which is
13the emulated architecture. As TCG started as a generic C backend used
14for cross compiling, it is assumed that the TCG target is different
15from the host, although it is never the case for QEMU.
16
17A TCG "function" corresponds to a QEMU Translated Block (TB).
18
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19A TCG "temporary" is a variable only live in a basic
20block. Temporaries are allocated explicitly in each function.
c896fe29 21
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22A TCG "local temporary" is a variable only live in a function. Local
23temporaries are allocated explicitly in each function.
24
25A TCG "global" is a variable which is live in all the functions
26(equivalent of a C global variable). They are defined before the
27functions defined. A TCG global can be a memory location (e.g. a QEMU
28CPU register), a fixed host register (e.g. the QEMU CPU state pointer)
29or a memory location which is stored in a register outside QEMU TBs
30(not implemented yet).
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31
32A TCG "basic block" corresponds to a list of instructions terminated
33by a branch instruction.
34
353) Intermediate representation
36
373.1) Introduction
38
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39TCG instructions operate on variables which are temporaries, local
40temporaries or globals. TCG instructions and variables are strongly
41typed. Two types are supported: 32 bit integers and 64 bit
42integers. Pointers are defined as an alias to 32 bit or 64 bit
43integers depending on the TCG target word size.
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44
45Each instruction has a fixed number of output variable operands, input
46variable operands and always constant operands.
47
48The notable exception is the call instruction which has a variable
49number of outputs and inputs.
50
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51In the textual form, output operands usually come first, followed by
52input operands, followed by constant operands. The output type is
53included in the instruction name. Constants are prefixed with a '$'.
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54
55add_i32 t0, t1, t2 (t0 <- t1 + t2)
56
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573.2) Assumptions
58
59* Basic blocks
60
61- Basic blocks end after branches (e.g. brcond_i32 instruction),
62 goto_tb and exit_tb instructions.
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63- Basic blocks start after the end of a previous basic block, or at a
64 set_label instruction.
c896fe29 65
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66After the end of a basic block, the content of temporaries is
67destroyed, but local temporaries and globals are preserved.
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68
69* Floating point types are not supported yet
70
71* Pointers: depending on the TCG target, pointer size is 32 bit or 64
72 bit. The type TCG_TYPE_PTR is an alias to TCG_TYPE_I32 or
73 TCG_TYPE_I64.
74
75* Helpers:
76
77Using the tcg_gen_helper_x_y it is possible to call any function
811d4cf4 78taking i32, i64 or pointer types. Before calling an helper, all
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79globals are stored at their canonical location and it is assumed that
80the function can modify them. In the future, function modifiers will
81be allowed to tell that the helper does not read or write some globals.
82
83On some TCG targets (e.g. x86), several calling conventions are
84supported.
85
86* Branches:
87
88Use the instruction 'br' to jump to a label. Use 'jmp' to jump to an
89explicit address. Conditional branches can only jump to labels.
90
913.3) Code Optimizations
92
93When generating instructions, you can count on at least the following
94optimizations:
95
96- Single instructions are simplified, e.g.
97
98 and_i32 t0, t0, $0xffffffff
99
100 is suppressed.
101
102- A liveness analysis is done at the basic block level. The
0a6b7b78 103 information is used to suppress moves from a dead variable to
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104 another one. It is also used to remove instructions which compute
105 dead results. The later is especially useful for condition code
9804c8e2 106 optimization in QEMU.
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107
108 In the following example:
109
110 add_i32 t0, t1, t2
111 add_i32 t0, t0, $1
112 mov_i32 t0, $1
113
114 only the last instruction is kept.
115
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1163.4) Instruction Reference
117
118********* Function call
119
120* call <ret> <params> ptr
121
122call function 'ptr' (pointer type)
123
124<ret> optional 32 bit or 64 bit return value
125<params> optional 32 bit or 64 bit parameters
126
127********* Jumps/Labels
128
129* jmp t0
130
131Absolute jump to address t0 (pointer type).
132
133* set_label $label
134
135Define label 'label' at the current program point.
136
137* br $label
138
139Jump to label.
140
141* brcond_i32/i64 cond, t0, t1, label
142
143Conditional jump if t0 cond t1 is true. cond can be:
144 TCG_COND_EQ
145 TCG_COND_NE
146 TCG_COND_LT /* signed */
147 TCG_COND_GE /* signed */
148 TCG_COND_LE /* signed */
149 TCG_COND_GT /* signed */
150 TCG_COND_LTU /* unsigned */
151 TCG_COND_GEU /* unsigned */
152 TCG_COND_LEU /* unsigned */
153 TCG_COND_GTU /* unsigned */
154
155********* Arithmetic
156
157* add_i32/i64 t0, t1, t2
158
159t0=t1+t2
160
161* sub_i32/i64 t0, t1, t2
162
163t0=t1-t2
164
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165* neg_i32/i64 t0, t1
166
167t0=-t1 (two's complement)
168
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169* mul_i32/i64 t0, t1, t2
170
171t0=t1*t2
172
173* div_i32/i64 t0, t1, t2
174
175t0=t1/t2 (signed). Undefined behavior if division by zero or overflow.
176
177* divu_i32/i64 t0, t1, t2
178
179t0=t1/t2 (unsigned). Undefined behavior if division by zero.
180
181* rem_i32/i64 t0, t1, t2
182
183t0=t1%t2 (signed). Undefined behavior if division by zero or overflow.
184
185* remu_i32/i64 t0, t1, t2
186
187t0=t1%t2 (unsigned). Undefined behavior if division by zero.
188
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189********* Logical
190
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191* and_i32/i64 t0, t1, t2
192
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193t0=t1&t2
194
195* or_i32/i64 t0, t1, t2
196
197t0=t1|t2
198
199* xor_i32/i64 t0, t1, t2
200
201t0=t1^t2
202
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203* not_i32/i64 t0, t1
204
205t0=~t1
206
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207* andc_i32/i64 t0, t1, t2
208
209t0=t1&~t2
210
211* eqv_i32/i64 t0, t1, t2
212
213t0=~(t1^t2)
214
215* nand_i32/i64 t0, t1, t2
216
217t0=~(t1&t2)
218
219* nor_i32/i64 t0, t1, t2
220
221t0=~(t1|t2)
222
223* orc_i32/i64 t0, t1, t2
224
225t0=t1|~t2
226
15824571 227********* Shifts/Rotates
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228
229* shl_i32/i64 t0, t1, t2
230
231t0=t1 << t2. Undefined behavior if t2 < 0 or t2 >= 32 (resp 64)
232
233* shr_i32/i64 t0, t1, t2
234
235t0=t1 >> t2 (unsigned). Undefined behavior if t2 < 0 or t2 >= 32 (resp 64)
236
237* sar_i32/i64 t0, t1, t2
238
239t0=t1 >> t2 (signed). Undefined behavior if t2 < 0 or t2 >= 32 (resp 64)
240
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241* rotl_i32/i64 t0, t1, t2
242
243Rotation of t2 bits to the left. Undefined behavior if t2 < 0 or t2 >= 32 (resp 64)
244
245* rotr_i32/i64 t0, t1, t2
246
247Rotation of t2 bits to the right. Undefined behavior if t2 < 0 or t2 >= 32 (resp 64)
248
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249********* Misc
250
251* mov_i32/i64 t0, t1
252
253t0 = t1
254
255Move t1 to t0 (both operands must have the same type).
256
257* ext8s_i32/i64 t0, t1
86831435 258ext8u_i32/i64 t0, t1
c896fe29 259ext16s_i32/i64 t0, t1
86831435 260ext16u_i32/i64 t0, t1
c896fe29 261ext32s_i64 t0, t1
86831435 262ext32u_i64 t0, t1
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86831435 2648, 16 or 32 bit sign/zero extension (both operands must have the same type)
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4ad4ce16 266* bswap16_i32/i64 t0, t1
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26816 bit byte swap on a 32/64 bit value. The two/six high order bytes must be
269set to zero.
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4ad4ce16 271* bswap32_i32/i64 t0, t1
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604457d7 27332 bit byte swap on a 32/64 bit value. With a 64 bit value, the four high
4ad4ce16 274order bytes must be set to zero.
c896fe29 275
4ad4ce16 276* bswap64_i64 t0, t1
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277
27864 bit byte swap
279
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280* discard_i32/i64 t0
281
282Indicate that the value of t0 won't be used later. It is useful to
283force dead code elimination.
284
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285********* Conditional moves
286
287* setcond_i32/i64 cond, dest, t1, t2
288
289dest = (t1 cond t2)
290
291Set DEST to 1 if (T1 cond T2) is true, otherwise set to 0.
292
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293********* Type conversions
294
295* ext_i32_i64 t0, t1
296Convert t1 (32 bit) to t0 (64 bit) and does sign extension
297
298* extu_i32_i64 t0, t1
299Convert t1 (32 bit) to t0 (64 bit) and does zero extension
300
301* trunc_i64_i32 t0, t1
302Truncate t1 (64 bit) to t0 (32 bit)
303
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304* concat_i32_i64 t0, t1, t2
305Construct t0 (64-bit) taking the low half from t1 (32 bit) and the high half
306from t2 (32 bit).
307
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308* concat32_i64 t0, t1, t2
309Construct t0 (64-bit) taking the low half from t1 (64 bit) and the high half
310from t2 (64 bit).
311
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312********* Load/Store
313
314* ld_i32/i64 t0, t1, offset
315ld8s_i32/i64 t0, t1, offset
316ld8u_i32/i64 t0, t1, offset
317ld16s_i32/i64 t0, t1, offset
318ld16u_i32/i64 t0, t1, offset
319ld32s_i64 t0, t1, offset
320ld32u_i64 t0, t1, offset
321
322t0 = read(t1 + offset)
323Load 8, 16, 32 or 64 bits with or without sign extension from host memory.
324offset must be a constant.
325
326* st_i32/i64 t0, t1, offset
327st8_i32/i64 t0, t1, offset
328st16_i32/i64 t0, t1, offset
329st32_i64 t0, t1, offset
330
331write(t0, t1 + offset)
332Write 8, 16, 32 or 64 bits to host memory.
333
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334********* 64-bit target on 32-bit host support
335
336The following opcodes are internal to TCG. Thus they are to be implemented by
33732-bit host code generators, but are not to be emitted by guest translators.
338They are emitted as needed by inline functions within "tcg-op.h".
339
340* brcond2_i32 cond, t0_low, t0_high, t1_low, t1_high, label
341
342Similar to brcond, except that the 64-bit values T0 and T1
343are formed from two 32-bit arguments.
344
345* add2_i32 t0_low, t0_high, t1_low, t1_high, t2_low, t2_high
346* sub2_i32 t0_low, t0_high, t1_low, t1_high, t2_low, t2_high
347
348Similar to add/sub, except that the 64-bit inputs T1 and T2 are
349formed from two 32-bit arguments, and the 64-bit output T0
350is returned in two 32-bit outputs.
351
352* mulu2_i32 t0_low, t0_high, t1, t2
353
354Similar to mul, except two 32-bit (unsigned) inputs T1 and T2 yielding
355the full 64-bit product T0. The later is returned in two 32-bit outputs.
356
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357* setcond2_i32 cond, dest, t1_low, t1_high, t2_low, t2_high
358
359Similar to setcond, except that the 64-bit values T1 and T2 are
360formed from two 32-bit arguments. The result is a 32-bit value.
361
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362********* QEMU specific operations
363
364* tb_exit t0
365
366Exit the current TB and return the value t0 (word type).
367
368* goto_tb index
369
370Exit the current TB and jump to the TB index 'index' (constant) if the
371current TB was linked to this TB. Otherwise execute the next
372instructions.
373
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374* qemu_ld8u t0, t1, flags
375qemu_ld8s t0, t1, flags
376qemu_ld16u t0, t1, flags
377qemu_ld16s t0, t1, flags
378qemu_ld32u t0, t1, flags
379qemu_ld32s t0, t1, flags
380qemu_ld64 t0, t1, flags
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381
382Load data at the QEMU CPU address t1 into t0. t1 has the QEMU CPU
383address type. 'flags' contains the QEMU memory index (selects user or
384kernel access) for example.
385
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386* qemu_st8 t0, t1, flags
387qemu_st16 t0, t1, flags
388qemu_st32 t0, t1, flags
389qemu_st64 t0, t1, flags
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390
391Store the data t0 at the QEMU CPU Address t1. t1 has the QEMU CPU
392address type. 'flags' contains the QEMU memory index (selects user or
393kernel access) for example.
394
395Note 1: Some shortcuts are defined when the last operand is known to be
396a constant (e.g. addi for add, movi for mov).
397
398Note 2: When using TCG, the opcodes must never be generated directly
399as some of them may not be available as "real" opcodes. Always use the
400function tcg_gen_xxx(args).
401
4024) Backend
403
404tcg-target.h contains the target specific definitions. tcg-target.c
405contains the target specific code.
406
4074.1) Assumptions
408
409The target word size (TCG_TARGET_REG_BITS) is expected to be 32 bit or
41064 bit. It is expected that the pointer has the same size as the word.
411
412On a 32 bit target, all 64 bit operations are converted to 32 bits. A
413few specific operations must be implemented to allow it (see add2_i32,
414sub2_i32, brcond2_i32).
415
416Floating point operations are not supported in this version. A
417previous incarnation of the code generator had full support of them,
418but it is better to concentrate on integer operations first.
419
420On a 64 bit target, no assumption is made in TCG about the storage of
421the 32 bit values in 64 bit registers.
422
4234.2) Constraints
424
425GCC like constraints are used to define the constraints of every
426instruction. Memory constraints are not supported in this
427version. Aliases are specified in the input operands as for GCC.
428
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429The same register may be used for both an input and an output, even when
430they are not explicitly aliased. If an op expands to multiple target
431instructions then care must be taken to avoid clobbering input values.
432GCC style "early clobber" outputs are not currently supported.
433
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434A target can define specific register or constant constraints. If an
435operation uses a constant input constraint which does not allow all
436constants, it must also accept registers in order to have a fallback.
437
438The movi_i32 and movi_i64 operations must accept any constants.
439
440The mov_i32 and mov_i64 operations must accept any registers of the
441same type.
442
443The ld/st instructions must accept signed 32 bit constant offsets. It
444can be implemented by reserving a specific register to compute the
445address if the offset is too big.
446
447The ld/st instructions must accept any destination (ld) or source (st)
448register.
449
4504.3) Function call assumptions
451
452- The only supported types for parameters and return value are: 32 and
453 64 bit integers and pointer.
454- The stack grows downwards.
455- The first N parameters are passed in registers.
456- The next parameters are passed on the stack by storing them as words.
457- Some registers are clobbered during the call.
458- The function can return 0 or 1 value in registers. On a 32 bit
459 target, functions must be able to return 2 values in registers for
460 64 bit return type.
461
86e840ee 4625) Recommended coding rules for best performance
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463
464- Use globals to represent the parts of the QEMU CPU state which are
465 often modified, e.g. the integer registers and the condition
466 codes. TCG will be able to use host registers to store them.
467
468- Avoid globals stored in fixed registers. They must be used only to
469 store the pointer to the CPU state and possibly to store a pointer
86e840ee 470 to a register window.
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471
472- Use temporaries. Use local temporaries only when really needed,
473 e.g. when you need to use a value after a jump. Local temporaries
474 introduce a performance hit in the current TCG implementation: their
475 content is saved to memory at end of each basic block.
476
477- Free temporaries and local temporaries when they are no longer used
478 (tcg_temp_free). Since tcg_const_x() also creates a temporary, you
479 should free it after it is used. Freeing temporaries does not yield
480 a better generated code, but it reduces the memory usage of TCG and
481 the speed of the translation.
482
483- Don't hesitate to use helpers for complicated or seldom used target
484 intructions. There is little performance advantage in using TCG to
485 implement target instructions taking more than about twenty TCG
486 instructions.
487
488- Use the 'discard' instruction if you know that TCG won't be able to
489 prove that a given global is "dead" at a given program point. The
490 x86 target uses it to improve the condition codes optimisation.