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811d4cf4 AZ |
1 | /* |
2 | * Tiny Code Generator for QEMU | |
3 | * | |
4 | * Copyright (c) 2008 Andrzej Zaborowski | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
d4a9eb1f | 24 | |
ac34fb5c AJ |
25 | #if defined(__ARM_ARCH_7__) || \ |
26 | defined(__ARM_ARCH_7A__) || \ | |
27 | defined(__ARM_ARCH_7EM__) || \ | |
28 | defined(__ARM_ARCH_7M__) || \ | |
29 | defined(__ARM_ARCH_7R__) | |
30 | #define USE_ARMV7_INSTRUCTIONS | |
31 | #endif | |
32 | ||
33 | #if defined(USE_ARMV7_INSTRUCTIONS) || \ | |
34 | defined(__ARM_ARCH_6J__) || \ | |
35 | defined(__ARM_ARCH_6K__) || \ | |
36 | defined(__ARM_ARCH_6T2__) || \ | |
37 | defined(__ARM_ARCH_6Z__) || \ | |
38 | defined(__ARM_ARCH_6ZK__) | |
39 | #define USE_ARMV6_INSTRUCTIONS | |
40 | #endif | |
41 | ||
42 | #if defined(USE_ARMV6_INSTRUCTIONS) || \ | |
43 | defined(__ARM_ARCH_5T__) || \ | |
44 | defined(__ARM_ARCH_5TE__) || \ | |
45 | defined(__ARM_ARCH_5TEJ__) | |
46 | #define USE_ARMV5_INSTRUCTIONS | |
47 | #endif | |
48 | ||
49 | #ifdef USE_ARMV5_INSTRUCTIONS | |
50 | static const int use_armv5_instructions = 1; | |
51 | #else | |
52 | static const int use_armv5_instructions = 0; | |
53 | #endif | |
54 | #undef USE_ARMV5_INSTRUCTIONS | |
55 | ||
56 | #ifdef USE_ARMV6_INSTRUCTIONS | |
57 | static const int use_armv6_instructions = 1; | |
58 | #else | |
59 | static const int use_armv6_instructions = 0; | |
60 | #endif | |
61 | #undef USE_ARMV6_INSTRUCTIONS | |
62 | ||
63 | #ifdef USE_ARMV7_INSTRUCTIONS | |
64 | static const int use_armv7_instructions = 1; | |
65 | #else | |
66 | static const int use_armv7_instructions = 0; | |
67 | #endif | |
68 | #undef USE_ARMV7_INSTRUCTIONS | |
69 | ||
d4a9eb1f BS |
70 | #ifndef NDEBUG |
71 | static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = { | |
811d4cf4 AZ |
72 | "%r0", |
73 | "%r1", | |
74 | "%r2", | |
75 | "%r3", | |
76 | "%r4", | |
77 | "%r5", | |
78 | "%r6", | |
79 | "%r7", | |
80 | "%r8", | |
81 | "%r9", | |
82 | "%r10", | |
83 | "%r11", | |
84 | "%r12", | |
85 | "%r13", | |
86 | "%r14", | |
e4a7d5e8 | 87 | "%pc", |
811d4cf4 | 88 | }; |
d4a9eb1f | 89 | #endif |
811d4cf4 | 90 | |
d4a9eb1f | 91 | static const int tcg_target_reg_alloc_order[] = { |
811d4cf4 AZ |
92 | TCG_REG_R4, |
93 | TCG_REG_R5, | |
94 | TCG_REG_R6, | |
95 | TCG_REG_R7, | |
96 | TCG_REG_R8, | |
97 | TCG_REG_R9, | |
98 | TCG_REG_R10, | |
99 | TCG_REG_R11, | |
811d4cf4 | 100 | TCG_REG_R13, |
914ccf51 AJ |
101 | TCG_REG_R0, |
102 | TCG_REG_R1, | |
103 | TCG_REG_R2, | |
104 | TCG_REG_R3, | |
105 | TCG_REG_R12, | |
811d4cf4 AZ |
106 | TCG_REG_R14, |
107 | }; | |
108 | ||
d4a9eb1f | 109 | static const int tcg_target_call_iarg_regs[4] = { |
811d4cf4 AZ |
110 | TCG_REG_R0, TCG_REG_R1, TCG_REG_R2, TCG_REG_R3 |
111 | }; | |
d4a9eb1f | 112 | static const int tcg_target_call_oarg_regs[2] = { |
811d4cf4 AZ |
113 | TCG_REG_R0, TCG_REG_R1 |
114 | }; | |
115 | ||
c69806ab AJ |
116 | static inline void reloc_abs32(void *code_ptr, tcg_target_long target) |
117 | { | |
118 | *(uint32_t *) code_ptr = target; | |
119 | } | |
120 | ||
121 | static inline void reloc_pc24(void *code_ptr, tcg_target_long target) | |
122 | { | |
123 | uint32_t offset = ((target - ((tcg_target_long) code_ptr + 8)) >> 2); | |
124 | ||
125 | *(uint32_t *) code_ptr = ((*(uint32_t *) code_ptr) & ~0xffffff) | |
126 | | (offset & 0xffffff); | |
127 | } | |
128 | ||
650bbb36 | 129 | static void patch_reloc(uint8_t *code_ptr, int type, |
811d4cf4 AZ |
130 | tcg_target_long value, tcg_target_long addend) |
131 | { | |
132 | switch (type) { | |
133 | case R_ARM_ABS32: | |
c69806ab | 134 | reloc_abs32(code_ptr, value); |
811d4cf4 AZ |
135 | break; |
136 | ||
137 | case R_ARM_CALL: | |
138 | case R_ARM_JUMP24: | |
139 | default: | |
140 | tcg_abort(); | |
141 | ||
142 | case R_ARM_PC24: | |
c69806ab | 143 | reloc_pc24(code_ptr, value); |
811d4cf4 AZ |
144 | break; |
145 | } | |
146 | } | |
147 | ||
811d4cf4 | 148 | /* parse target specific constraints */ |
d4a9eb1f | 149 | static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str) |
811d4cf4 AZ |
150 | { |
151 | const char *ct_str; | |
152 | ||
153 | ct_str = *pct_str; | |
154 | switch (ct_str[0]) { | |
cb4e581f LD |
155 | case 'I': |
156 | ct->ct |= TCG_CT_CONST_ARM; | |
157 | break; | |
158 | ||
811d4cf4 | 159 | case 'r': |
811d4cf4 AZ |
160 | ct->ct |= TCG_CT_REG; |
161 | tcg_regset_set32(ct->u.regs, 0, (1 << TCG_TARGET_NB_REGS) - 1); | |
162 | break; | |
163 | ||
67dcab73 AJ |
164 | /* qemu_ld address */ |
165 | case 'l': | |
811d4cf4 AZ |
166 | ct->ct |= TCG_CT_REG; |
167 | tcg_regset_set32(ct->u.regs, 0, (1 << TCG_TARGET_NB_REGS) - 1); | |
67dcab73 AJ |
168 | #ifdef CONFIG_SOFTMMU |
169 | /* r0 and r1 will be overwritten when reading the tlb entry, | |
170 | so don't use these. */ | |
811d4cf4 AZ |
171 | tcg_regset_reset_reg(ct->u.regs, TCG_REG_R0); |
172 | tcg_regset_reset_reg(ct->u.regs, TCG_REG_R1); | |
89c33337 | 173 | #if TARGET_LONG_BITS == 64 |
9716ef3b PM |
174 | /* If we're passing env to the helper as r0 and need a regpair |
175 | * for the address then r2 will be overwritten as we're setting | |
176 | * up the args to the helper. | |
177 | */ | |
178 | tcg_regset_reset_reg(ct->u.regs, TCG_REG_R2); | |
179 | #endif | |
67dcab73 | 180 | #endif |
811d4cf4 | 181 | break; |
67dcab73 | 182 | case 'L': |
d0660ed4 AZ |
183 | ct->ct |= TCG_CT_REG; |
184 | tcg_regset_set32(ct->u.regs, 0, (1 << TCG_TARGET_NB_REGS) - 1); | |
67dcab73 AJ |
185 | #ifdef CONFIG_SOFTMMU |
186 | /* r1 is still needed to load data_reg or data_reg2, | |
187 | so don't use it. */ | |
d0660ed4 | 188 | tcg_regset_reset_reg(ct->u.regs, TCG_REG_R1); |
67dcab73 | 189 | #endif |
d0660ed4 AZ |
190 | break; |
191 | ||
67dcab73 AJ |
192 | /* qemu_st address & data_reg */ |
193 | case 's': | |
811d4cf4 AZ |
194 | ct->ct |= TCG_CT_REG; |
195 | tcg_regset_set32(ct->u.regs, 0, (1 << TCG_TARGET_NB_REGS) - 1); | |
67dcab73 AJ |
196 | /* r0 and r1 will be overwritten when reading the tlb entry |
197 | (softmmu only) and doing the byte swapping, so don't | |
198 | use these. */ | |
811d4cf4 AZ |
199 | tcg_regset_reset_reg(ct->u.regs, TCG_REG_R0); |
200 | tcg_regset_reset_reg(ct->u.regs, TCG_REG_R1); | |
89c33337 | 201 | #if defined(CONFIG_SOFTMMU) && (TARGET_LONG_BITS == 64) |
9716ef3b PM |
202 | /* Avoid clashes with registers being used for helper args */ |
203 | tcg_regset_reset_reg(ct->u.regs, TCG_REG_R2); | |
204 | tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3); | |
205 | #endif | |
811d4cf4 | 206 | break; |
67dcab73 AJ |
207 | /* qemu_st64 data_reg2 */ |
208 | case 'S': | |
811d4cf4 AZ |
209 | ct->ct |= TCG_CT_REG; |
210 | tcg_regset_set32(ct->u.regs, 0, (1 << TCG_TARGET_NB_REGS) - 1); | |
67dcab73 AJ |
211 | /* r0 and r1 will be overwritten when reading the tlb entry |
212 | (softmmu only) and doing the byte swapping, so don't | |
213 | use these. */ | |
811d4cf4 | 214 | tcg_regset_reset_reg(ct->u.regs, TCG_REG_R0); |
811d4cf4 | 215 | tcg_regset_reset_reg(ct->u.regs, TCG_REG_R1); |
67dcab73 AJ |
216 | #ifdef CONFIG_SOFTMMU |
217 | /* r2 is still needed to load data_reg, so don't use it. */ | |
218 | tcg_regset_reset_reg(ct->u.regs, TCG_REG_R2); | |
89c33337 | 219 | #if TARGET_LONG_BITS == 64 |
9716ef3b PM |
220 | /* Avoid clashes with registers being used for helper args */ |
221 | tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3); | |
222 | #endif | |
811d4cf4 | 223 | #endif |
67dcab73 | 224 | break; |
811d4cf4 | 225 | |
811d4cf4 AZ |
226 | default: |
227 | return -1; | |
228 | } | |
229 | ct_str++; | |
230 | *pct_str = ct_str; | |
231 | ||
232 | return 0; | |
233 | } | |
234 | ||
94953e6d LD |
235 | static inline uint32_t rotl(uint32_t val, int n) |
236 | { | |
237 | return (val << n) | (val >> (32 - n)); | |
238 | } | |
239 | ||
240 | /* ARM immediates for ALU instructions are made of an unsigned 8-bit | |
241 | right-rotated by an even amount between 0 and 30. */ | |
242 | static inline int encode_imm(uint32_t imm) | |
243 | { | |
4e6f6d4c LD |
244 | int shift; |
245 | ||
94953e6d LD |
246 | /* simple case, only lower bits */ |
247 | if ((imm & ~0xff) == 0) | |
248 | return 0; | |
249 | /* then try a simple even shift */ | |
250 | shift = ctz32(imm) & ~1; | |
251 | if (((imm >> shift) & ~0xff) == 0) | |
252 | return 32 - shift; | |
253 | /* now try harder with rotations */ | |
254 | if ((rotl(imm, 2) & ~0xff) == 0) | |
255 | return 2; | |
256 | if ((rotl(imm, 4) & ~0xff) == 0) | |
257 | return 4; | |
258 | if ((rotl(imm, 6) & ~0xff) == 0) | |
259 | return 6; | |
260 | /* imm can't be encoded */ | |
261 | return -1; | |
262 | } | |
cb4e581f LD |
263 | |
264 | static inline int check_fit_imm(uint32_t imm) | |
265 | { | |
94953e6d | 266 | return encode_imm(imm) >= 0; |
cb4e581f LD |
267 | } |
268 | ||
811d4cf4 AZ |
269 | /* Test if a constant matches the constraint. |
270 | * TODO: define constraints for: | |
271 | * | |
272 | * ldr/str offset: between -0xfff and 0xfff | |
273 | * ldrh/strh offset: between -0xff and 0xff | |
274 | * mov operand2: values represented with x << (2 * y), x < 0x100 | |
275 | * add, sub, eor...: ditto | |
276 | */ | |
277 | static inline int tcg_target_const_match(tcg_target_long val, | |
278 | const TCGArgConstraint *arg_ct) | |
279 | { | |
280 | int ct; | |
281 | ct = arg_ct->ct; | |
282 | if (ct & TCG_CT_CONST) | |
283 | return 1; | |
cb4e581f LD |
284 | else if ((ct & TCG_CT_CONST_ARM) && check_fit_imm(val)) |
285 | return 1; | |
811d4cf4 AZ |
286 | else |
287 | return 0; | |
288 | } | |
289 | ||
290 | enum arm_data_opc_e { | |
291 | ARITH_AND = 0x0, | |
292 | ARITH_EOR = 0x1, | |
293 | ARITH_SUB = 0x2, | |
294 | ARITH_RSB = 0x3, | |
295 | ARITH_ADD = 0x4, | |
296 | ARITH_ADC = 0x5, | |
297 | ARITH_SBC = 0x6, | |
298 | ARITH_RSC = 0x7, | |
3979144c | 299 | ARITH_TST = 0x8, |
811d4cf4 AZ |
300 | ARITH_CMP = 0xa, |
301 | ARITH_CMN = 0xb, | |
302 | ARITH_ORR = 0xc, | |
303 | ARITH_MOV = 0xd, | |
304 | ARITH_BIC = 0xe, | |
305 | ARITH_MVN = 0xf, | |
306 | }; | |
307 | ||
3979144c PB |
308 | #define TO_CPSR(opc) \ |
309 | ((opc == ARITH_CMP || opc == ARITH_CMN || opc == ARITH_TST) << 20) | |
811d4cf4 AZ |
310 | |
311 | #define SHIFT_IMM_LSL(im) (((im) << 7) | 0x00) | |
312 | #define SHIFT_IMM_LSR(im) (((im) << 7) | 0x20) | |
313 | #define SHIFT_IMM_ASR(im) (((im) << 7) | 0x40) | |
314 | #define SHIFT_IMM_ROR(im) (((im) << 7) | 0x60) | |
315 | #define SHIFT_REG_LSL(rs) (((rs) << 8) | 0x10) | |
316 | #define SHIFT_REG_LSR(rs) (((rs) << 8) | 0x30) | |
317 | #define SHIFT_REG_ASR(rs) (((rs) << 8) | 0x50) | |
318 | #define SHIFT_REG_ROR(rs) (((rs) << 8) | 0x70) | |
319 | ||
320 | enum arm_cond_code_e { | |
321 | COND_EQ = 0x0, | |
322 | COND_NE = 0x1, | |
323 | COND_CS = 0x2, /* Unsigned greater or equal */ | |
324 | COND_CC = 0x3, /* Unsigned less than */ | |
325 | COND_MI = 0x4, /* Negative */ | |
326 | COND_PL = 0x5, /* Zero or greater */ | |
327 | COND_VS = 0x6, /* Overflow */ | |
328 | COND_VC = 0x7, /* No overflow */ | |
329 | COND_HI = 0x8, /* Unsigned greater than */ | |
330 | COND_LS = 0x9, /* Unsigned less or equal */ | |
331 | COND_GE = 0xa, | |
332 | COND_LT = 0xb, | |
333 | COND_GT = 0xc, | |
334 | COND_LE = 0xd, | |
335 | COND_AL = 0xe, | |
336 | }; | |
337 | ||
0aed257f | 338 | static const uint8_t tcg_cond_to_arm_cond[] = { |
811d4cf4 AZ |
339 | [TCG_COND_EQ] = COND_EQ, |
340 | [TCG_COND_NE] = COND_NE, | |
341 | [TCG_COND_LT] = COND_LT, | |
342 | [TCG_COND_GE] = COND_GE, | |
343 | [TCG_COND_LE] = COND_LE, | |
344 | [TCG_COND_GT] = COND_GT, | |
345 | /* unsigned */ | |
346 | [TCG_COND_LTU] = COND_CC, | |
347 | [TCG_COND_GEU] = COND_CS, | |
348 | [TCG_COND_LEU] = COND_LS, | |
349 | [TCG_COND_GTU] = COND_HI, | |
350 | }; | |
351 | ||
352 | static inline void tcg_out_bx(TCGContext *s, int cond, int rn) | |
353 | { | |
354 | tcg_out32(s, (cond << 28) | 0x012fff10 | rn); | |
355 | } | |
356 | ||
357 | static inline void tcg_out_b(TCGContext *s, int cond, int32_t offset) | |
358 | { | |
359 | tcg_out32(s, (cond << 28) | 0x0a000000 | | |
360 | (((offset - 8) >> 2) & 0x00ffffff)); | |
361 | } | |
362 | ||
e936243a AZ |
363 | static inline void tcg_out_b_noaddr(TCGContext *s, int cond) |
364 | { | |
56779034 AJ |
365 | /* We pay attention here to not modify the branch target by skipping |
366 | the corresponding bytes. This ensure that caches and memory are | |
367 | kept coherent during retranslation. */ | |
e2542fe2 | 368 | #ifdef HOST_WORDS_BIGENDIAN |
e936243a AZ |
369 | tcg_out8(s, (cond << 4) | 0x0a); |
370 | s->code_ptr += 3; | |
371 | #else | |
372 | s->code_ptr += 3; | |
373 | tcg_out8(s, (cond << 4) | 0x0a); | |
374 | #endif | |
375 | } | |
376 | ||
811d4cf4 AZ |
377 | static inline void tcg_out_bl(TCGContext *s, int cond, int32_t offset) |
378 | { | |
379 | tcg_out32(s, (cond << 28) | 0x0b000000 | | |
380 | (((offset - 8) >> 2) & 0x00ffffff)); | |
381 | } | |
382 | ||
23401b58 AJ |
383 | static inline void tcg_out_blx(TCGContext *s, int cond, int rn) |
384 | { | |
385 | tcg_out32(s, (cond << 28) | 0x012fff30 | rn); | |
386 | } | |
387 | ||
24e838b7 PM |
388 | static inline void tcg_out_blx_imm(TCGContext *s, int32_t offset) |
389 | { | |
390 | tcg_out32(s, 0xfa000000 | ((offset & 2) << 23) | | |
391 | (((offset - 8) >> 2) & 0x00ffffff)); | |
392 | } | |
393 | ||
811d4cf4 AZ |
394 | static inline void tcg_out_dat_reg(TCGContext *s, |
395 | int cond, int opc, int rd, int rn, int rm, int shift) | |
396 | { | |
397 | tcg_out32(s, (cond << 28) | (0 << 25) | (opc << 21) | TO_CPSR(opc) | | |
398 | (rn << 16) | (rd << 12) | shift | rm); | |
399 | } | |
400 | ||
9716ef3b PM |
401 | static inline void tcg_out_mov_reg(TCGContext *s, int cond, int rd, int rm) |
402 | { | |
403 | /* Simple reg-reg move, optimising out the 'do nothing' case */ | |
404 | if (rd != rm) { | |
405 | tcg_out_dat_reg(s, cond, ARITH_MOV, rd, 0, rm, SHIFT_IMM_LSL(0)); | |
406 | } | |
407 | } | |
408 | ||
811d4cf4 AZ |
409 | static inline void tcg_out_dat_reg2(TCGContext *s, |
410 | int cond, int opc0, int opc1, int rd0, int rd1, | |
411 | int rn0, int rn1, int rm0, int rm1, int shift) | |
412 | { | |
0c9c3a9e AZ |
413 | if (rd0 == rn1 || rd0 == rm1) { |
414 | tcg_out32(s, (cond << 28) | (0 << 25) | (opc0 << 21) | (1 << 20) | | |
415 | (rn0 << 16) | (8 << 12) | shift | rm0); | |
416 | tcg_out32(s, (cond << 28) | (0 << 25) | (opc1 << 21) | | |
417 | (rn1 << 16) | (rd1 << 12) | shift | rm1); | |
418 | tcg_out_dat_reg(s, cond, ARITH_MOV, | |
419 | rd0, 0, TCG_REG_R8, SHIFT_IMM_LSL(0)); | |
420 | } else { | |
421 | tcg_out32(s, (cond << 28) | (0 << 25) | (opc0 << 21) | (1 << 20) | | |
422 | (rn0 << 16) | (rd0 << 12) | shift | rm0); | |
423 | tcg_out32(s, (cond << 28) | (0 << 25) | (opc1 << 21) | | |
424 | (rn1 << 16) | (rd1 << 12) | shift | rm1); | |
425 | } | |
811d4cf4 AZ |
426 | } |
427 | ||
428 | static inline void tcg_out_dat_imm(TCGContext *s, | |
429 | int cond, int opc, int rd, int rn, int im) | |
430 | { | |
3979144c | 431 | tcg_out32(s, (cond << 28) | (1 << 25) | (opc << 21) | TO_CPSR(opc) | |
811d4cf4 AZ |
432 | (rn << 16) | (rd << 12) | im); |
433 | } | |
434 | ||
435 | static inline void tcg_out_movi32(TCGContext *s, | |
0f11f25a | 436 | int cond, int rd, uint32_t arg) |
811d4cf4 | 437 | { |
811d4cf4 AZ |
438 | /* TODO: This is very suboptimal, we can easily have a constant |
439 | * pool somewhere after all the instructions. */ | |
0f11f25a AJ |
440 | if ((int)arg < 0 && (int)arg >= -0x100) { |
441 | tcg_out_dat_imm(s, cond, ARITH_MVN, rd, 0, (~arg) & 0xff); | |
442 | } else if (use_armv7_instructions) { | |
ac34fb5c AJ |
443 | /* use movw/movt */ |
444 | /* movw */ | |
445 | tcg_out32(s, (cond << 28) | 0x03000000 | (rd << 12) | |
446 | | ((arg << 4) & 0x000f0000) | (arg & 0xfff)); | |
0f11f25a | 447 | if (arg & 0xffff0000) { |
ac34fb5c AJ |
448 | /* movt */ |
449 | tcg_out32(s, (cond << 28) | 0x03400000 | (rd << 12) | |
450 | | ((arg >> 12) & 0x000f0000) | ((arg >> 16) & 0xfff)); | |
ac34fb5c | 451 | } |
0f11f25a AJ |
452 | } else { |
453 | int opc = ARITH_MOV; | |
454 | int rn = 0; | |
455 | ||
456 | do { | |
457 | int i, rot; | |
458 | ||
459 | i = ctz32(arg) & ~1; | |
460 | rot = ((32 - i) << 7) & 0xf00; | |
461 | tcg_out_dat_imm(s, cond, opc, rd, rn, ((arg >> i) & 0xff) | rot); | |
462 | arg &= ~(0xff << i); | |
463 | ||
464 | opc = ARITH_ORR; | |
465 | rn = rd; | |
466 | } while (arg); | |
467 | } | |
811d4cf4 AZ |
468 | } |
469 | ||
7fc645bf PM |
470 | static inline void tcg_out_dat_rI(TCGContext *s, int cond, int opc, TCGArg dst, |
471 | TCGArg lhs, TCGArg rhs, int rhs_is_const) | |
472 | { | |
473 | /* Emit either the reg,imm or reg,reg form of a data-processing insn. | |
474 | * rhs must satisfy the "rI" constraint. | |
475 | */ | |
476 | if (rhs_is_const) { | |
477 | int rot = encode_imm(rhs); | |
478 | assert(rot >= 0); | |
479 | tcg_out_dat_imm(s, cond, opc, dst, lhs, rotl(rhs, rot) | (rot << 7)); | |
480 | } else { | |
481 | tcg_out_dat_reg(s, cond, opc, dst, lhs, rhs, SHIFT_IMM_LSL(0)); | |
482 | } | |
483 | } | |
484 | ||
811d4cf4 AZ |
485 | static inline void tcg_out_mul32(TCGContext *s, |
486 | int cond, int rd, int rs, int rm) | |
487 | { | |
488 | if (rd != rm) | |
489 | tcg_out32(s, (cond << 28) | (rd << 16) | (0 << 12) | | |
490 | (rs << 8) | 0x90 | rm); | |
491 | else if (rd != rs) | |
492 | tcg_out32(s, (cond << 28) | (rd << 16) | (0 << 12) | | |
493 | (rm << 8) | 0x90 | rs); | |
494 | else { | |
495 | tcg_out32(s, (cond << 28) | ( 8 << 16) | (0 << 12) | | |
496 | (rs << 8) | 0x90 | rm); | |
497 | tcg_out_dat_reg(s, cond, ARITH_MOV, | |
c8d80cef | 498 | rd, 0, TCG_REG_R8, SHIFT_IMM_LSL(0)); |
811d4cf4 AZ |
499 | } |
500 | } | |
501 | ||
502 | static inline void tcg_out_umull32(TCGContext *s, | |
503 | int cond, int rd0, int rd1, int rs, int rm) | |
504 | { | |
505 | if (rd0 != rm && rd1 != rm) | |
506 | tcg_out32(s, (cond << 28) | 0x800090 | | |
507 | (rd1 << 16) | (rd0 << 12) | (rs << 8) | rm); | |
508 | else if (rd0 != rs && rd1 != rs) | |
509 | tcg_out32(s, (cond << 28) | 0x800090 | | |
510 | (rd1 << 16) | (rd0 << 12) | (rm << 8) | rs); | |
511 | else { | |
512 | tcg_out_dat_reg(s, cond, ARITH_MOV, | |
513 | TCG_REG_R8, 0, rm, SHIFT_IMM_LSL(0)); | |
514 | tcg_out32(s, (cond << 28) | 0x800098 | | |
515 | (rd1 << 16) | (rd0 << 12) | (rs << 8)); | |
516 | } | |
517 | } | |
518 | ||
519 | static inline void tcg_out_smull32(TCGContext *s, | |
520 | int cond, int rd0, int rd1, int rs, int rm) | |
521 | { | |
522 | if (rd0 != rm && rd1 != rm) | |
523 | tcg_out32(s, (cond << 28) | 0xc00090 | | |
524 | (rd1 << 16) | (rd0 << 12) | (rs << 8) | rm); | |
525 | else if (rd0 != rs && rd1 != rs) | |
526 | tcg_out32(s, (cond << 28) | 0xc00090 | | |
527 | (rd1 << 16) | (rd0 << 12) | (rm << 8) | rs); | |
528 | else { | |
529 | tcg_out_dat_reg(s, cond, ARITH_MOV, | |
530 | TCG_REG_R8, 0, rm, SHIFT_IMM_LSL(0)); | |
531 | tcg_out32(s, (cond << 28) | 0xc00098 | | |
532 | (rd1 << 16) | (rd0 << 12) | (rs << 8)); | |
533 | } | |
534 | } | |
535 | ||
9517094f AJ |
536 | static inline void tcg_out_ext8s(TCGContext *s, int cond, |
537 | int rd, int rn) | |
538 | { | |
539 | if (use_armv6_instructions) { | |
540 | /* sxtb */ | |
541 | tcg_out32(s, 0x06af0070 | (cond << 28) | (rd << 12) | rn); | |
542 | } else { | |
e23886a9 | 543 | tcg_out_dat_reg(s, cond, ARITH_MOV, |
9517094f | 544 | rd, 0, rn, SHIFT_IMM_LSL(24)); |
e23886a9 | 545 | tcg_out_dat_reg(s, cond, ARITH_MOV, |
9517094f AJ |
546 | rd, 0, rd, SHIFT_IMM_ASR(24)); |
547 | } | |
548 | } | |
549 | ||
e854b6d3 AJ |
550 | static inline void tcg_out_ext8u(TCGContext *s, int cond, |
551 | int rd, int rn) | |
552 | { | |
553 | tcg_out_dat_imm(s, cond, ARITH_AND, rd, rn, 0xff); | |
554 | } | |
555 | ||
9517094f AJ |
556 | static inline void tcg_out_ext16s(TCGContext *s, int cond, |
557 | int rd, int rn) | |
558 | { | |
559 | if (use_armv6_instructions) { | |
560 | /* sxth */ | |
561 | tcg_out32(s, 0x06bf0070 | (cond << 28) | (rd << 12) | rn); | |
562 | } else { | |
e23886a9 | 563 | tcg_out_dat_reg(s, cond, ARITH_MOV, |
9517094f | 564 | rd, 0, rn, SHIFT_IMM_LSL(16)); |
e23886a9 | 565 | tcg_out_dat_reg(s, cond, ARITH_MOV, |
9517094f AJ |
566 | rd, 0, rd, SHIFT_IMM_ASR(16)); |
567 | } | |
568 | } | |
569 | ||
570 | static inline void tcg_out_ext16u(TCGContext *s, int cond, | |
571 | int rd, int rn) | |
572 | { | |
573 | if (use_armv6_instructions) { | |
574 | /* uxth */ | |
575 | tcg_out32(s, 0x06ff0070 | (cond << 28) | (rd << 12) | rn); | |
576 | } else { | |
e23886a9 | 577 | tcg_out_dat_reg(s, cond, ARITH_MOV, |
9517094f | 578 | rd, 0, rn, SHIFT_IMM_LSL(16)); |
e23886a9 | 579 | tcg_out_dat_reg(s, cond, ARITH_MOV, |
9517094f AJ |
580 | rd, 0, rd, SHIFT_IMM_LSR(16)); |
581 | } | |
582 | } | |
583 | ||
67dcab73 AJ |
584 | static inline void tcg_out_bswap16s(TCGContext *s, int cond, int rd, int rn) |
585 | { | |
586 | if (use_armv6_instructions) { | |
587 | /* revsh */ | |
588 | tcg_out32(s, 0x06ff0fb0 | (cond << 28) | (rd << 12) | rn); | |
589 | } else { | |
590 | tcg_out_dat_reg(s, cond, ARITH_MOV, | |
591 | TCG_REG_R8, 0, rn, SHIFT_IMM_LSL(24)); | |
592 | tcg_out_dat_reg(s, cond, ARITH_MOV, | |
593 | TCG_REG_R8, 0, TCG_REG_R8, SHIFT_IMM_ASR(16)); | |
594 | tcg_out_dat_reg(s, cond, ARITH_ORR, | |
595 | rd, TCG_REG_R8, rn, SHIFT_IMM_LSR(8)); | |
596 | } | |
597 | } | |
598 | ||
244b1e81 AJ |
599 | static inline void tcg_out_bswap16(TCGContext *s, int cond, int rd, int rn) |
600 | { | |
601 | if (use_armv6_instructions) { | |
602 | /* rev16 */ | |
603 | tcg_out32(s, 0x06bf0fb0 | (cond << 28) | (rd << 12) | rn); | |
604 | } else { | |
605 | tcg_out_dat_reg(s, cond, ARITH_MOV, | |
606 | TCG_REG_R8, 0, rn, SHIFT_IMM_LSL(24)); | |
607 | tcg_out_dat_reg(s, cond, ARITH_MOV, | |
608 | TCG_REG_R8, 0, TCG_REG_R8, SHIFT_IMM_LSR(16)); | |
609 | tcg_out_dat_reg(s, cond, ARITH_ORR, | |
610 | rd, TCG_REG_R8, rn, SHIFT_IMM_LSR(8)); | |
611 | } | |
612 | } | |
613 | ||
614 | static inline void tcg_out_bswap32(TCGContext *s, int cond, int rd, int rn) | |
615 | { | |
616 | if (use_armv6_instructions) { | |
617 | /* rev */ | |
618 | tcg_out32(s, 0x06bf0f30 | (cond << 28) | (rd << 12) | rn); | |
619 | } else { | |
620 | tcg_out_dat_reg(s, cond, ARITH_EOR, | |
621 | TCG_REG_R8, rn, rn, SHIFT_IMM_ROR(16)); | |
622 | tcg_out_dat_imm(s, cond, ARITH_BIC, | |
623 | TCG_REG_R8, TCG_REG_R8, 0xff | 0x800); | |
624 | tcg_out_dat_reg(s, cond, ARITH_MOV, | |
625 | rd, 0, rn, SHIFT_IMM_ROR(8)); | |
626 | tcg_out_dat_reg(s, cond, ARITH_EOR, | |
627 | rd, rd, TCG_REG_R8, SHIFT_IMM_LSR(8)); | |
628 | } | |
629 | } | |
630 | ||
811d4cf4 AZ |
631 | static inline void tcg_out_ld32_12(TCGContext *s, int cond, |
632 | int rd, int rn, tcg_target_long im) | |
633 | { | |
634 | if (im >= 0) | |
635 | tcg_out32(s, (cond << 28) | 0x05900000 | | |
636 | (rn << 16) | (rd << 12) | (im & 0xfff)); | |
637 | else | |
638 | tcg_out32(s, (cond << 28) | 0x05100000 | | |
639 | (rn << 16) | (rd << 12) | ((-im) & 0xfff)); | |
640 | } | |
641 | ||
642 | static inline void tcg_out_st32_12(TCGContext *s, int cond, | |
643 | int rd, int rn, tcg_target_long im) | |
644 | { | |
645 | if (im >= 0) | |
646 | tcg_out32(s, (cond << 28) | 0x05800000 | | |
647 | (rn << 16) | (rd << 12) | (im & 0xfff)); | |
648 | else | |
649 | tcg_out32(s, (cond << 28) | 0x05000000 | | |
650 | (rn << 16) | (rd << 12) | ((-im) & 0xfff)); | |
651 | } | |
652 | ||
653 | static inline void tcg_out_ld32_r(TCGContext *s, int cond, | |
654 | int rd, int rn, int rm) | |
655 | { | |
656 | tcg_out32(s, (cond << 28) | 0x07900000 | | |
657 | (rn << 16) | (rd << 12) | rm); | |
658 | } | |
659 | ||
660 | static inline void tcg_out_st32_r(TCGContext *s, int cond, | |
661 | int rd, int rn, int rm) | |
662 | { | |
663 | tcg_out32(s, (cond << 28) | 0x07800000 | | |
664 | (rn << 16) | (rd << 12) | rm); | |
665 | } | |
666 | ||
3979144c PB |
667 | /* Register pre-increment with base writeback. */ |
668 | static inline void tcg_out_ld32_rwb(TCGContext *s, int cond, | |
669 | int rd, int rn, int rm) | |
670 | { | |
671 | tcg_out32(s, (cond << 28) | 0x07b00000 | | |
672 | (rn << 16) | (rd << 12) | rm); | |
673 | } | |
674 | ||
675 | static inline void tcg_out_st32_rwb(TCGContext *s, int cond, | |
676 | int rd, int rn, int rm) | |
677 | { | |
678 | tcg_out32(s, (cond << 28) | 0x07a00000 | | |
679 | (rn << 16) | (rd << 12) | rm); | |
680 | } | |
681 | ||
811d4cf4 AZ |
682 | static inline void tcg_out_ld16u_8(TCGContext *s, int cond, |
683 | int rd, int rn, tcg_target_long im) | |
684 | { | |
685 | if (im >= 0) | |
686 | tcg_out32(s, (cond << 28) | 0x01d000b0 | | |
687 | (rn << 16) | (rd << 12) | | |
688 | ((im & 0xf0) << 4) | (im & 0xf)); | |
689 | else | |
690 | tcg_out32(s, (cond << 28) | 0x015000b0 | | |
691 | (rn << 16) | (rd << 12) | | |
692 | (((-im) & 0xf0) << 4) | ((-im) & 0xf)); | |
693 | } | |
694 | ||
f694a27e | 695 | static inline void tcg_out_st16_8(TCGContext *s, int cond, |
811d4cf4 AZ |
696 | int rd, int rn, tcg_target_long im) |
697 | { | |
698 | if (im >= 0) | |
699 | tcg_out32(s, (cond << 28) | 0x01c000b0 | | |
700 | (rn << 16) | (rd << 12) | | |
701 | ((im & 0xf0) << 4) | (im & 0xf)); | |
702 | else | |
703 | tcg_out32(s, (cond << 28) | 0x014000b0 | | |
704 | (rn << 16) | (rd << 12) | | |
705 | (((-im) & 0xf0) << 4) | ((-im) & 0xf)); | |
706 | } | |
707 | ||
708 | static inline void tcg_out_ld16u_r(TCGContext *s, int cond, | |
709 | int rd, int rn, int rm) | |
710 | { | |
711 | tcg_out32(s, (cond << 28) | 0x019000b0 | | |
712 | (rn << 16) | (rd << 12) | rm); | |
713 | } | |
714 | ||
f694a27e | 715 | static inline void tcg_out_st16_r(TCGContext *s, int cond, |
811d4cf4 AZ |
716 | int rd, int rn, int rm) |
717 | { | |
718 | tcg_out32(s, (cond << 28) | 0x018000b0 | | |
719 | (rn << 16) | (rd << 12) | rm); | |
720 | } | |
721 | ||
722 | static inline void tcg_out_ld16s_8(TCGContext *s, int cond, | |
723 | int rd, int rn, tcg_target_long im) | |
724 | { | |
725 | if (im >= 0) | |
726 | tcg_out32(s, (cond << 28) | 0x01d000f0 | | |
727 | (rn << 16) | (rd << 12) | | |
728 | ((im & 0xf0) << 4) | (im & 0xf)); | |
729 | else | |
730 | tcg_out32(s, (cond << 28) | 0x015000f0 | | |
731 | (rn << 16) | (rd << 12) | | |
732 | (((-im) & 0xf0) << 4) | ((-im) & 0xf)); | |
733 | } | |
734 | ||
811d4cf4 AZ |
735 | static inline void tcg_out_ld16s_r(TCGContext *s, int cond, |
736 | int rd, int rn, int rm) | |
737 | { | |
738 | tcg_out32(s, (cond << 28) | 0x019000f0 | | |
739 | (rn << 16) | (rd << 12) | rm); | |
740 | } | |
741 | ||
811d4cf4 AZ |
742 | static inline void tcg_out_ld8_12(TCGContext *s, int cond, |
743 | int rd, int rn, tcg_target_long im) | |
744 | { | |
745 | if (im >= 0) | |
746 | tcg_out32(s, (cond << 28) | 0x05d00000 | | |
747 | (rn << 16) | (rd << 12) | (im & 0xfff)); | |
748 | else | |
749 | tcg_out32(s, (cond << 28) | 0x05500000 | | |
750 | (rn << 16) | (rd << 12) | ((-im) & 0xfff)); | |
751 | } | |
752 | ||
753 | static inline void tcg_out_st8_12(TCGContext *s, int cond, | |
754 | int rd, int rn, tcg_target_long im) | |
755 | { | |
756 | if (im >= 0) | |
757 | tcg_out32(s, (cond << 28) | 0x05c00000 | | |
758 | (rn << 16) | (rd << 12) | (im & 0xfff)); | |
759 | else | |
760 | tcg_out32(s, (cond << 28) | 0x05400000 | | |
761 | (rn << 16) | (rd << 12) | ((-im) & 0xfff)); | |
762 | } | |
763 | ||
764 | static inline void tcg_out_ld8_r(TCGContext *s, int cond, | |
765 | int rd, int rn, int rm) | |
766 | { | |
767 | tcg_out32(s, (cond << 28) | 0x07d00000 | | |
768 | (rn << 16) | (rd << 12) | rm); | |
769 | } | |
770 | ||
771 | static inline void tcg_out_st8_r(TCGContext *s, int cond, | |
772 | int rd, int rn, int rm) | |
773 | { | |
774 | tcg_out32(s, (cond << 28) | 0x07c00000 | | |
775 | (rn << 16) | (rd << 12) | rm); | |
776 | } | |
777 | ||
778 | static inline void tcg_out_ld8s_8(TCGContext *s, int cond, | |
779 | int rd, int rn, tcg_target_long im) | |
780 | { | |
781 | if (im >= 0) | |
782 | tcg_out32(s, (cond << 28) | 0x01d000d0 | | |
783 | (rn << 16) | (rd << 12) | | |
784 | ((im & 0xf0) << 4) | (im & 0xf)); | |
785 | else | |
786 | tcg_out32(s, (cond << 28) | 0x015000d0 | | |
787 | (rn << 16) | (rd << 12) | | |
788 | (((-im) & 0xf0) << 4) | ((-im) & 0xf)); | |
789 | } | |
790 | ||
811d4cf4 AZ |
791 | static inline void tcg_out_ld8s_r(TCGContext *s, int cond, |
792 | int rd, int rn, int rm) | |
793 | { | |
204c1674 | 794 | tcg_out32(s, (cond << 28) | 0x019000d0 | |
811d4cf4 AZ |
795 | (rn << 16) | (rd << 12) | rm); |
796 | } | |
797 | ||
811d4cf4 AZ |
798 | static inline void tcg_out_ld32u(TCGContext *s, int cond, |
799 | int rd, int rn, int32_t offset) | |
800 | { | |
801 | if (offset > 0xfff || offset < -0xfff) { | |
802 | tcg_out_movi32(s, cond, TCG_REG_R8, offset); | |
803 | tcg_out_ld32_r(s, cond, rd, rn, TCG_REG_R8); | |
804 | } else | |
805 | tcg_out_ld32_12(s, cond, rd, rn, offset); | |
806 | } | |
807 | ||
808 | static inline void tcg_out_st32(TCGContext *s, int cond, | |
809 | int rd, int rn, int32_t offset) | |
810 | { | |
811 | if (offset > 0xfff || offset < -0xfff) { | |
812 | tcg_out_movi32(s, cond, TCG_REG_R8, offset); | |
813 | tcg_out_st32_r(s, cond, rd, rn, TCG_REG_R8); | |
814 | } else | |
815 | tcg_out_st32_12(s, cond, rd, rn, offset); | |
816 | } | |
817 | ||
818 | static inline void tcg_out_ld16u(TCGContext *s, int cond, | |
819 | int rd, int rn, int32_t offset) | |
820 | { | |
821 | if (offset > 0xff || offset < -0xff) { | |
822 | tcg_out_movi32(s, cond, TCG_REG_R8, offset); | |
823 | tcg_out_ld16u_r(s, cond, rd, rn, TCG_REG_R8); | |
824 | } else | |
825 | tcg_out_ld16u_8(s, cond, rd, rn, offset); | |
826 | } | |
827 | ||
828 | static inline void tcg_out_ld16s(TCGContext *s, int cond, | |
829 | int rd, int rn, int32_t offset) | |
830 | { | |
831 | if (offset > 0xff || offset < -0xff) { | |
832 | tcg_out_movi32(s, cond, TCG_REG_R8, offset); | |
833 | tcg_out_ld16s_r(s, cond, rd, rn, TCG_REG_R8); | |
834 | } else | |
835 | tcg_out_ld16s_8(s, cond, rd, rn, offset); | |
836 | } | |
837 | ||
f694a27e | 838 | static inline void tcg_out_st16(TCGContext *s, int cond, |
811d4cf4 AZ |
839 | int rd, int rn, int32_t offset) |
840 | { | |
841 | if (offset > 0xff || offset < -0xff) { | |
842 | tcg_out_movi32(s, cond, TCG_REG_R8, offset); | |
f694a27e | 843 | tcg_out_st16_r(s, cond, rd, rn, TCG_REG_R8); |
811d4cf4 | 844 | } else |
f694a27e | 845 | tcg_out_st16_8(s, cond, rd, rn, offset); |
811d4cf4 AZ |
846 | } |
847 | ||
848 | static inline void tcg_out_ld8u(TCGContext *s, int cond, | |
849 | int rd, int rn, int32_t offset) | |
850 | { | |
851 | if (offset > 0xfff || offset < -0xfff) { | |
852 | tcg_out_movi32(s, cond, TCG_REG_R8, offset); | |
853 | tcg_out_ld8_r(s, cond, rd, rn, TCG_REG_R8); | |
854 | } else | |
855 | tcg_out_ld8_12(s, cond, rd, rn, offset); | |
856 | } | |
857 | ||
858 | static inline void tcg_out_ld8s(TCGContext *s, int cond, | |
859 | int rd, int rn, int32_t offset) | |
860 | { | |
861 | if (offset > 0xff || offset < -0xff) { | |
862 | tcg_out_movi32(s, cond, TCG_REG_R8, offset); | |
863 | tcg_out_ld8s_r(s, cond, rd, rn, TCG_REG_R8); | |
864 | } else | |
865 | tcg_out_ld8s_8(s, cond, rd, rn, offset); | |
866 | } | |
867 | ||
f694a27e | 868 | static inline void tcg_out_st8(TCGContext *s, int cond, |
811d4cf4 AZ |
869 | int rd, int rn, int32_t offset) |
870 | { | |
871 | if (offset > 0xfff || offset < -0xfff) { | |
872 | tcg_out_movi32(s, cond, TCG_REG_R8, offset); | |
873 | tcg_out_st8_r(s, cond, rd, rn, TCG_REG_R8); | |
874 | } else | |
875 | tcg_out_st8_12(s, cond, rd, rn, offset); | |
876 | } | |
877 | ||
222f23f5 | 878 | /* The _goto case is normally between TBs within the same code buffer, |
5c84bd90 | 879 | * and with the code buffer limited to 16MB we shouldn't need the long |
222f23f5 DDAG |
880 | * case. |
881 | * | |
882 | * .... except to the prologue that is in its own buffer. | |
883 | */ | |
811d4cf4 AZ |
884 | static inline void tcg_out_goto(TCGContext *s, int cond, uint32_t addr) |
885 | { | |
886 | int32_t val; | |
887 | ||
24e838b7 PM |
888 | if (addr & 1) { |
889 | /* goto to a Thumb destination isn't supported */ | |
890 | tcg_abort(); | |
891 | } | |
892 | ||
811d4cf4 AZ |
893 | val = addr - (tcg_target_long) s->code_ptr; |
894 | if (val - 8 < 0x01fffffd && val - 8 > -0x01fffffd) | |
895 | tcg_out_b(s, cond, val); | |
896 | else { | |
811d4cf4 | 897 | if (cond == COND_AL) { |
c8d80cef | 898 | tcg_out_ld32_12(s, COND_AL, TCG_REG_PC, TCG_REG_PC, -4); |
222f23f5 | 899 | tcg_out32(s, addr); |
811d4cf4 AZ |
900 | } else { |
901 | tcg_out_movi32(s, cond, TCG_REG_R8, val - 8); | |
902 | tcg_out_dat_reg(s, cond, ARITH_ADD, | |
c8d80cef AJ |
903 | TCG_REG_PC, TCG_REG_PC, |
904 | TCG_REG_R8, SHIFT_IMM_LSL(0)); | |
811d4cf4 | 905 | } |
811d4cf4 AZ |
906 | } |
907 | } | |
908 | ||
222f23f5 DDAG |
909 | /* The call case is mostly used for helpers - so it's not unreasonable |
910 | * for them to be beyond branch range */ | |
24e838b7 | 911 | static inline void tcg_out_call(TCGContext *s, uint32_t addr) |
811d4cf4 AZ |
912 | { |
913 | int32_t val; | |
914 | ||
811d4cf4 | 915 | val = addr - (tcg_target_long) s->code_ptr; |
24e838b7 PM |
916 | if (val - 8 < 0x02000000 && val - 8 >= -0x02000000) { |
917 | if (addr & 1) { | |
918 | /* Use BLX if the target is in Thumb mode */ | |
919 | if (!use_armv5_instructions) { | |
920 | tcg_abort(); | |
921 | } | |
922 | tcg_out_blx_imm(s, val); | |
923 | } else { | |
924 | tcg_out_bl(s, COND_AL, val); | |
925 | } | |
926 | } else { | |
222f23f5 DDAG |
927 | tcg_out_dat_imm(s, COND_AL, ARITH_ADD, TCG_REG_R14, TCG_REG_PC, 4); |
928 | tcg_out_ld32_12(s, COND_AL, TCG_REG_PC, TCG_REG_PC, -4); | |
929 | tcg_out32(s, addr); | |
811d4cf4 | 930 | } |
811d4cf4 AZ |
931 | } |
932 | ||
933 | static inline void tcg_out_callr(TCGContext *s, int cond, int arg) | |
934 | { | |
23401b58 AJ |
935 | if (use_armv5_instructions) { |
936 | tcg_out_blx(s, cond, arg); | |
937 | } else { | |
938 | tcg_out_dat_reg(s, cond, ARITH_MOV, TCG_REG_R14, 0, | |
939 | TCG_REG_PC, SHIFT_IMM_LSL(0)); | |
940 | tcg_out_bx(s, cond, arg); | |
941 | } | |
811d4cf4 AZ |
942 | } |
943 | ||
944 | static inline void tcg_out_goto_label(TCGContext *s, int cond, int label_index) | |
945 | { | |
946 | TCGLabel *l = &s->labels[label_index]; | |
947 | ||
948 | if (l->has_value) | |
949 | tcg_out_goto(s, cond, l->u.value); | |
950 | else if (cond == COND_AL) { | |
c8d80cef | 951 | tcg_out_ld32_12(s, COND_AL, TCG_REG_PC, TCG_REG_PC, -4); |
811d4cf4 AZ |
952 | tcg_out_reloc(s, s->code_ptr, R_ARM_ABS32, label_index, 31337); |
953 | s->code_ptr += 4; | |
954 | } else { | |
955 | /* Probably this should be preferred even for COND_AL... */ | |
956 | tcg_out_reloc(s, s->code_ptr, R_ARM_PC24, label_index, 31337); | |
e936243a | 957 | tcg_out_b_noaddr(s, cond); |
811d4cf4 AZ |
958 | } |
959 | } | |
960 | ||
811d4cf4 | 961 | #ifdef CONFIG_SOFTMMU |
79383c9c BS |
962 | |
963 | #include "../../softmmu_defs.h" | |
811d4cf4 | 964 | |
e141ab52 BS |
965 | /* helper signature: helper_ld_mmu(CPUState *env, target_ulong addr, |
966 | int mmu_idx) */ | |
967 | static const void * const qemu_ld_helpers[4] = { | |
968 | helper_ldb_mmu, | |
969 | helper_ldw_mmu, | |
970 | helper_ldl_mmu, | |
971 | helper_ldq_mmu, | |
972 | }; | |
973 | ||
974 | /* helper signature: helper_st_mmu(CPUState *env, target_ulong addr, | |
975 | uintxx_t val, int mmu_idx) */ | |
976 | static const void * const qemu_st_helpers[4] = { | |
977 | helper_stb_mmu, | |
978 | helper_stw_mmu, | |
979 | helper_stl_mmu, | |
980 | helper_stq_mmu, | |
981 | }; | |
9716ef3b PM |
982 | |
983 | /* Helper routines for marshalling helper function arguments into | |
984 | * the correct registers and stack. | |
985 | * argreg is where we want to put this argument, arg is the argument itself. | |
986 | * Return value is the updated argreg ready for the next call. | |
987 | * Note that argreg 0..3 is real registers, 4+ on stack. | |
988 | * When we reach the first stacked argument, we allocate space for it | |
989 | * and the following stacked arguments using "str r8, [sp, #-0x10]!". | |
990 | * Following arguments are filled in with "str r8, [sp, #0xNN]". | |
991 | * For more than 4 stacked arguments we'd need to know how much | |
992 | * space to allocate when we pushed the first stacked argument. | |
993 | * We don't need this, so don't implement it (and will assert if you try it.) | |
994 | * | |
995 | * We provide routines for arguments which are: immediate, 32 bit | |
996 | * value in register, 16 and 8 bit values in register (which must be zero | |
997 | * extended before use) and 64 bit value in a lo:hi register pair. | |
998 | */ | |
999 | #define DEFINE_TCG_OUT_ARG(NAME, ARGPARAM) \ | |
1000 | static TCGReg NAME(TCGContext *s, TCGReg argreg, ARGPARAM) \ | |
1001 | { \ | |
1002 | if (argreg < 4) { \ | |
1003 | TCG_OUT_ARG_GET_ARG(argreg); \ | |
1004 | } else if (argreg == 4) { \ | |
1005 | TCG_OUT_ARG_GET_ARG(TCG_REG_R8); \ | |
1006 | tcg_out32(s, (COND_AL << 28) | 0x052d8010); \ | |
1007 | } else { \ | |
1008 | assert(argreg < 8); \ | |
1009 | TCG_OUT_ARG_GET_ARG(TCG_REG_R8); \ | |
1010 | tcg_out32(s, (COND_AL << 28) | 0x058d8000 | (argreg - 4) * 4); \ | |
1011 | } \ | |
1012 | return argreg + 1; \ | |
1013 | } | |
1014 | ||
1015 | #define TCG_OUT_ARG_GET_ARG(A) tcg_out_dat_imm(s, COND_AL, ARITH_MOV, A, 0, arg) | |
1016 | DEFINE_TCG_OUT_ARG(tcg_out_arg_imm32, uint32_t arg) | |
1017 | #undef TCG_OUT_ARG_GET_ARG | |
1018 | #define TCG_OUT_ARG_GET_ARG(A) tcg_out_ext8u(s, COND_AL, A, arg) | |
1019 | DEFINE_TCG_OUT_ARG(tcg_out_arg_reg8, TCGReg arg) | |
1020 | #undef TCG_OUT_ARG_GET_ARG | |
1021 | #define TCG_OUT_ARG_GET_ARG(A) tcg_out_ext16u(s, COND_AL, A, arg) | |
1022 | DEFINE_TCG_OUT_ARG(tcg_out_arg_reg16, TCGReg arg) | |
1023 | #undef TCG_OUT_ARG_GET_ARG | |
1024 | ||
1025 | /* We don't use the macro for this one to avoid an unnecessary reg-reg | |
1026 | * move when storing to the stack. | |
1027 | */ | |
1028 | static TCGReg tcg_out_arg_reg32(TCGContext *s, TCGReg argreg, TCGReg arg) | |
1029 | { | |
1030 | if (argreg < 4) { | |
1031 | tcg_out_mov_reg(s, COND_AL, argreg, arg); | |
1032 | } else if (argreg == 4) { | |
1033 | /* str arg, [sp, #-0x10]! */ | |
1034 | tcg_out32(s, (COND_AL << 28) | 0x052d0010 | (arg << 12)); | |
1035 | } else { | |
1036 | assert(argreg < 8); | |
1037 | /* str arg, [sp, #0xNN] */ | |
1038 | tcg_out32(s, (COND_AL << 28) | 0x058d0000 | | |
1039 | (arg << 12) | (argreg - 4) * 4); | |
1040 | } | |
1041 | return argreg + 1; | |
1042 | } | |
1043 | ||
1044 | static inline TCGReg tcg_out_arg_reg64(TCGContext *s, TCGReg argreg, | |
1045 | TCGReg arglo, TCGReg arghi) | |
1046 | { | |
1047 | /* 64 bit arguments must go in even/odd register pairs | |
1048 | * and in 8-aligned stack slots. | |
1049 | */ | |
1050 | if (argreg & 1) { | |
1051 | argreg++; | |
1052 | } | |
1053 | argreg = tcg_out_arg_reg32(s, argreg, arglo); | |
1054 | argreg = tcg_out_arg_reg32(s, argreg, arghi); | |
1055 | return argreg; | |
1056 | } | |
1057 | ||
1058 | static inline void tcg_out_arg_stacktidy(TCGContext *s, TCGReg argreg) | |
1059 | { | |
1060 | /* Output any necessary post-call cleanup of the stack */ | |
1061 | if (argreg > 4) { | |
1062 | tcg_out_dat_imm(s, COND_AL, ARITH_ADD, TCG_REG_R13, TCG_REG_R13, 0x10); | |
1063 | } | |
1064 | } | |
1065 | ||
e141ab52 | 1066 | #endif |
811d4cf4 | 1067 | |
3979144c PB |
1068 | #define TLB_SHIFT (CPU_TLB_ENTRY_BITS + CPU_TLB_BITS) |
1069 | ||
7e0d9562 | 1070 | static inline void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int opc) |
811d4cf4 | 1071 | { |
67dcab73 | 1072 | int addr_reg, data_reg, data_reg2, bswap; |
811d4cf4 AZ |
1073 | #ifdef CONFIG_SOFTMMU |
1074 | int mem_index, s_bits; | |
9716ef3b | 1075 | TCGReg argreg; |
811d4cf4 AZ |
1076 | # if TARGET_LONG_BITS == 64 |
1077 | int addr_reg2; | |
1078 | # endif | |
811d4cf4 | 1079 | uint32_t *label_ptr; |
811d4cf4 AZ |
1080 | #endif |
1081 | ||
67dcab73 AJ |
1082 | #ifdef TARGET_WORDS_BIGENDIAN |
1083 | bswap = 1; | |
1084 | #else | |
1085 | bswap = 0; | |
1086 | #endif | |
811d4cf4 AZ |
1087 | data_reg = *args++; |
1088 | if (opc == 3) | |
1089 | data_reg2 = *args++; | |
1090 | else | |
d89c682f | 1091 | data_reg2 = 0; /* suppress warning */ |
811d4cf4 | 1092 | addr_reg = *args++; |
811d4cf4 | 1093 | #ifdef CONFIG_SOFTMMU |
aef3a282 AZ |
1094 | # if TARGET_LONG_BITS == 64 |
1095 | addr_reg2 = *args++; | |
1096 | # endif | |
811d4cf4 AZ |
1097 | mem_index = *args; |
1098 | s_bits = opc & 3; | |
1099 | ||
91a3c1b0 | 1100 | /* Should generate something like the following: |
3979144c | 1101 | * shr r8, addr_reg, #TARGET_PAGE_BITS |
91a3c1b0 | 1102 | * and r0, r8, #(CPU_TLB_SIZE - 1) @ Assumption: CPU_TLB_BITS <= 8 |
3979144c | 1103 | * add r0, env, r0 lsl #CPU_TLB_ENTRY_BITS |
91a3c1b0 AZ |
1104 | */ |
1105 | # if CPU_TLB_BITS > 8 | |
1106 | # error | |
1107 | # endif | |
c8d80cef AJ |
1108 | tcg_out_dat_reg(s, COND_AL, ARITH_MOV, TCG_REG_R8, |
1109 | 0, addr_reg, SHIFT_IMM_LSR(TARGET_PAGE_BITS)); | |
811d4cf4 | 1110 | tcg_out_dat_imm(s, COND_AL, ARITH_AND, |
c8d80cef AJ |
1111 | TCG_REG_R0, TCG_REG_R8, CPU_TLB_SIZE - 1); |
1112 | tcg_out_dat_reg(s, COND_AL, ARITH_ADD, TCG_REG_R0, TCG_AREG0, | |
1113 | TCG_REG_R0, SHIFT_IMM_LSL(CPU_TLB_ENTRY_BITS)); | |
91a3c1b0 | 1114 | /* In the |
9349b4f9 | 1115 | * ldr r1 [r0, #(offsetof(CPUArchState, tlb_table[mem_index][0].addr_read))] |
91a3c1b0 AZ |
1116 | * below, the offset is likely to exceed 12 bits if mem_index != 0 and |
1117 | * not exceed otherwise, so use an | |
9349b4f9 | 1118 | * add r0, r0, #(mem_index * sizeof *CPUArchState.tlb_table) |
91a3c1b0 AZ |
1119 | * before. |
1120 | */ | |
225b4376 | 1121 | if (mem_index) |
c8d80cef | 1122 | tcg_out_dat_imm(s, COND_AL, ARITH_ADD, TCG_REG_R0, TCG_REG_R0, |
225b4376 AZ |
1123 | (mem_index << (TLB_SHIFT & 1)) | |
1124 | ((16 - (TLB_SHIFT >> 1)) << 8)); | |
c8d80cef | 1125 | tcg_out_ld32_12(s, COND_AL, TCG_REG_R1, TCG_REG_R0, |
9349b4f9 | 1126 | offsetof(CPUArchState, tlb_table[0][0].addr_read)); |
c8d80cef AJ |
1127 | tcg_out_dat_reg(s, COND_AL, ARITH_CMP, 0, TCG_REG_R1, |
1128 | TCG_REG_R8, SHIFT_IMM_LSL(TARGET_PAGE_BITS)); | |
3979144c PB |
1129 | /* Check alignment. */ |
1130 | if (s_bits) | |
1131 | tcg_out_dat_imm(s, COND_EQ, ARITH_TST, | |
1132 | 0, addr_reg, (1 << s_bits) - 1); | |
811d4cf4 AZ |
1133 | # if TARGET_LONG_BITS == 64 |
1134 | /* XXX: possibly we could use a block data load or writeback in | |
1135 | * the first access. */ | |
c8d80cef | 1136 | tcg_out_ld32_12(s, COND_EQ, TCG_REG_R1, TCG_REG_R0, |
9349b4f9 | 1137 | offsetof(CPUArchState, tlb_table[0][0].addr_read) + 4); |
c8d80cef AJ |
1138 | tcg_out_dat_reg(s, COND_EQ, ARITH_CMP, 0, |
1139 | TCG_REG_R1, addr_reg2, SHIFT_IMM_LSL(0)); | |
811d4cf4 | 1140 | # endif |
c8d80cef | 1141 | tcg_out_ld32_12(s, COND_EQ, TCG_REG_R1, TCG_REG_R0, |
9349b4f9 | 1142 | offsetof(CPUArchState, tlb_table[0][0].addend)); |
811d4cf4 AZ |
1143 | |
1144 | switch (opc) { | |
1145 | case 0: | |
c8d80cef | 1146 | tcg_out_ld8_r(s, COND_EQ, data_reg, addr_reg, TCG_REG_R1); |
811d4cf4 AZ |
1147 | break; |
1148 | case 0 | 4: | |
c8d80cef | 1149 | tcg_out_ld8s_r(s, COND_EQ, data_reg, addr_reg, TCG_REG_R1); |
811d4cf4 AZ |
1150 | break; |
1151 | case 1: | |
c8d80cef | 1152 | tcg_out_ld16u_r(s, COND_EQ, data_reg, addr_reg, TCG_REG_R1); |
67dcab73 AJ |
1153 | if (bswap) { |
1154 | tcg_out_bswap16(s, COND_EQ, data_reg, data_reg); | |
1155 | } | |
811d4cf4 AZ |
1156 | break; |
1157 | case 1 | 4: | |
67dcab73 AJ |
1158 | if (bswap) { |
1159 | tcg_out_ld16u_r(s, COND_EQ, data_reg, addr_reg, TCG_REG_R1); | |
1160 | tcg_out_bswap16s(s, COND_EQ, data_reg, data_reg); | |
1161 | } else { | |
1162 | tcg_out_ld16s_r(s, COND_EQ, data_reg, addr_reg, TCG_REG_R1); | |
1163 | } | |
811d4cf4 AZ |
1164 | break; |
1165 | case 2: | |
1166 | default: | |
c8d80cef | 1167 | tcg_out_ld32_r(s, COND_EQ, data_reg, addr_reg, TCG_REG_R1); |
67dcab73 AJ |
1168 | if (bswap) { |
1169 | tcg_out_bswap32(s, COND_EQ, data_reg, data_reg); | |
1170 | } | |
811d4cf4 AZ |
1171 | break; |
1172 | case 3: | |
67dcab73 AJ |
1173 | if (bswap) { |
1174 | tcg_out_ld32_rwb(s, COND_EQ, data_reg2, TCG_REG_R1, addr_reg); | |
1175 | tcg_out_ld32_12(s, COND_EQ, data_reg, TCG_REG_R1, 4); | |
1176 | tcg_out_bswap32(s, COND_EQ, data_reg2, data_reg2); | |
1177 | tcg_out_bswap32(s, COND_EQ, data_reg, data_reg); | |
1178 | } else { | |
1179 | tcg_out_ld32_rwb(s, COND_EQ, data_reg, TCG_REG_R1, addr_reg); | |
1180 | tcg_out_ld32_12(s, COND_EQ, data_reg2, TCG_REG_R1, 4); | |
1181 | } | |
811d4cf4 AZ |
1182 | break; |
1183 | } | |
1184 | ||
1185 | label_ptr = (void *) s->code_ptr; | |
c69806ab | 1186 | tcg_out_b_noaddr(s, COND_EQ); |
811d4cf4 | 1187 | |
811d4cf4 | 1188 | /* TODO: move this code to where the constants pool will be */ |
9716ef3b PM |
1189 | /* Note that this code relies on the constraints we set in arm_op_defs[] |
1190 | * to ensure that later arguments are not passed to us in registers we | |
1191 | * trash by moving the earlier arguments into them. | |
1192 | */ | |
1193 | argreg = TCG_REG_R0; | |
9716ef3b | 1194 | argreg = tcg_out_arg_reg32(s, argreg, TCG_AREG0); |
9716ef3b PM |
1195 | #if TARGET_LONG_BITS == 64 |
1196 | argreg = tcg_out_arg_reg64(s, argreg, addr_reg, addr_reg2); | |
1197 | #else | |
1198 | argreg = tcg_out_arg_reg32(s, argreg, addr_reg); | |
e141ab52 | 1199 | #endif |
9716ef3b | 1200 | argreg = tcg_out_arg_imm32(s, argreg, mem_index); |
24e838b7 | 1201 | tcg_out_call(s, (tcg_target_long) qemu_ld_helpers[s_bits]); |
9716ef3b | 1202 | tcg_out_arg_stacktidy(s, argreg); |
811d4cf4 AZ |
1203 | |
1204 | switch (opc) { | |
1205 | case 0 | 4: | |
e854b6d3 | 1206 | tcg_out_ext8s(s, COND_AL, data_reg, TCG_REG_R0); |
811d4cf4 AZ |
1207 | break; |
1208 | case 1 | 4: | |
e854b6d3 | 1209 | tcg_out_ext16s(s, COND_AL, data_reg, TCG_REG_R0); |
811d4cf4 AZ |
1210 | break; |
1211 | case 0: | |
1212 | case 1: | |
1213 | case 2: | |
1214 | default: | |
f97713ff | 1215 | tcg_out_mov_reg(s, COND_AL, data_reg, TCG_REG_R0); |
811d4cf4 AZ |
1216 | break; |
1217 | case 3: | |
f97713ff PM |
1218 | tcg_out_mov_reg(s, COND_AL, data_reg, TCG_REG_R0); |
1219 | tcg_out_mov_reg(s, COND_AL, data_reg2, TCG_REG_R1); | |
811d4cf4 AZ |
1220 | break; |
1221 | } | |
1222 | ||
c69806ab | 1223 | reloc_pc24(label_ptr, (tcg_target_long)s->code_ptr); |
379f6698 PB |
1224 | #else /* !CONFIG_SOFTMMU */ |
1225 | if (GUEST_BASE) { | |
1226 | uint32_t offset = GUEST_BASE; | |
1227 | int i; | |
1228 | int rot; | |
1229 | ||
1230 | while (offset) { | |
1231 | i = ctz32(offset) & ~1; | |
1232 | rot = ((32 - i) << 7) & 0xf00; | |
1233 | ||
c8d80cef | 1234 | tcg_out_dat_imm(s, COND_AL, ARITH_ADD, TCG_REG_R8, addr_reg, |
379f6698 | 1235 | ((offset >> i) & 0xff) | rot); |
c8d80cef | 1236 | addr_reg = TCG_REG_R8; |
379f6698 PB |
1237 | offset &= ~(0xff << i); |
1238 | } | |
1239 | } | |
811d4cf4 AZ |
1240 | switch (opc) { |
1241 | case 0: | |
1242 | tcg_out_ld8_12(s, COND_AL, data_reg, addr_reg, 0); | |
1243 | break; | |
1244 | case 0 | 4: | |
1245 | tcg_out_ld8s_8(s, COND_AL, data_reg, addr_reg, 0); | |
1246 | break; | |
1247 | case 1: | |
1248 | tcg_out_ld16u_8(s, COND_AL, data_reg, addr_reg, 0); | |
67dcab73 AJ |
1249 | if (bswap) { |
1250 | tcg_out_bswap16(s, COND_AL, data_reg, data_reg); | |
1251 | } | |
811d4cf4 AZ |
1252 | break; |
1253 | case 1 | 4: | |
67dcab73 AJ |
1254 | if (bswap) { |
1255 | tcg_out_ld16u_8(s, COND_AL, data_reg, addr_reg, 0); | |
1256 | tcg_out_bswap16s(s, COND_AL, data_reg, data_reg); | |
1257 | } else { | |
1258 | tcg_out_ld16s_8(s, COND_AL, data_reg, addr_reg, 0); | |
1259 | } | |
811d4cf4 AZ |
1260 | break; |
1261 | case 2: | |
1262 | default: | |
1263 | tcg_out_ld32_12(s, COND_AL, data_reg, addr_reg, 0); | |
67dcab73 AJ |
1264 | if (bswap) { |
1265 | tcg_out_bswap32(s, COND_AL, data_reg, data_reg); | |
1266 | } | |
811d4cf4 AZ |
1267 | break; |
1268 | case 3: | |
eae6ce52 AZ |
1269 | /* TODO: use block load - |
1270 | * check that data_reg2 > data_reg or the other way */ | |
419bafa5 | 1271 | if (data_reg == addr_reg) { |
67dcab73 AJ |
1272 | tcg_out_ld32_12(s, COND_AL, data_reg2, addr_reg, bswap ? 0 : 4); |
1273 | tcg_out_ld32_12(s, COND_AL, data_reg, addr_reg, bswap ? 4 : 0); | |
419bafa5 | 1274 | } else { |
67dcab73 AJ |
1275 | tcg_out_ld32_12(s, COND_AL, data_reg, addr_reg, bswap ? 4 : 0); |
1276 | tcg_out_ld32_12(s, COND_AL, data_reg2, addr_reg, bswap ? 0 : 4); | |
1277 | } | |
1278 | if (bswap) { | |
1279 | tcg_out_bswap32(s, COND_AL, data_reg, data_reg); | |
1280 | tcg_out_bswap32(s, COND_AL, data_reg2, data_reg2); | |
419bafa5 | 1281 | } |
811d4cf4 AZ |
1282 | break; |
1283 | } | |
1284 | #endif | |
1285 | } | |
1286 | ||
7e0d9562 | 1287 | static inline void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int opc) |
811d4cf4 | 1288 | { |
67dcab73 | 1289 | int addr_reg, data_reg, data_reg2, bswap; |
811d4cf4 AZ |
1290 | #ifdef CONFIG_SOFTMMU |
1291 | int mem_index, s_bits; | |
9716ef3b | 1292 | TCGReg argreg; |
811d4cf4 AZ |
1293 | # if TARGET_LONG_BITS == 64 |
1294 | int addr_reg2; | |
1295 | # endif | |
811d4cf4 | 1296 | uint32_t *label_ptr; |
811d4cf4 AZ |
1297 | #endif |
1298 | ||
67dcab73 AJ |
1299 | #ifdef TARGET_WORDS_BIGENDIAN |
1300 | bswap = 1; | |
1301 | #else | |
1302 | bswap = 0; | |
1303 | #endif | |
811d4cf4 AZ |
1304 | data_reg = *args++; |
1305 | if (opc == 3) | |
1306 | data_reg2 = *args++; | |
1307 | else | |
d89c682f | 1308 | data_reg2 = 0; /* suppress warning */ |
811d4cf4 | 1309 | addr_reg = *args++; |
811d4cf4 | 1310 | #ifdef CONFIG_SOFTMMU |
aef3a282 AZ |
1311 | # if TARGET_LONG_BITS == 64 |
1312 | addr_reg2 = *args++; | |
1313 | # endif | |
811d4cf4 AZ |
1314 | mem_index = *args; |
1315 | s_bits = opc & 3; | |
1316 | ||
91a3c1b0 | 1317 | /* Should generate something like the following: |
3979144c | 1318 | * shr r8, addr_reg, #TARGET_PAGE_BITS |
91a3c1b0 | 1319 | * and r0, r8, #(CPU_TLB_SIZE - 1) @ Assumption: CPU_TLB_BITS <= 8 |
3979144c | 1320 | * add r0, env, r0 lsl #CPU_TLB_ENTRY_BITS |
91a3c1b0 | 1321 | */ |
811d4cf4 | 1322 | tcg_out_dat_reg(s, COND_AL, ARITH_MOV, |
c8d80cef | 1323 | TCG_REG_R8, 0, addr_reg, SHIFT_IMM_LSR(TARGET_PAGE_BITS)); |
811d4cf4 | 1324 | tcg_out_dat_imm(s, COND_AL, ARITH_AND, |
c8d80cef AJ |
1325 | TCG_REG_R0, TCG_REG_R8, CPU_TLB_SIZE - 1); |
1326 | tcg_out_dat_reg(s, COND_AL, ARITH_ADD, TCG_REG_R0, | |
1327 | TCG_AREG0, TCG_REG_R0, SHIFT_IMM_LSL(CPU_TLB_ENTRY_BITS)); | |
91a3c1b0 | 1328 | /* In the |
9349b4f9 | 1329 | * ldr r1 [r0, #(offsetof(CPUArchState, tlb_table[mem_index][0].addr_write))] |
91a3c1b0 AZ |
1330 | * below, the offset is likely to exceed 12 bits if mem_index != 0 and |
1331 | * not exceed otherwise, so use an | |
9349b4f9 | 1332 | * add r0, r0, #(mem_index * sizeof *CPUArchState.tlb_table) |
91a3c1b0 AZ |
1333 | * before. |
1334 | */ | |
225b4376 | 1335 | if (mem_index) |
c8d80cef | 1336 | tcg_out_dat_imm(s, COND_AL, ARITH_ADD, TCG_REG_R0, TCG_REG_R0, |
225b4376 AZ |
1337 | (mem_index << (TLB_SHIFT & 1)) | |
1338 | ((16 - (TLB_SHIFT >> 1)) << 8)); | |
c8d80cef | 1339 | tcg_out_ld32_12(s, COND_AL, TCG_REG_R1, TCG_REG_R0, |
9349b4f9 | 1340 | offsetof(CPUArchState, tlb_table[0][0].addr_write)); |
c8d80cef AJ |
1341 | tcg_out_dat_reg(s, COND_AL, ARITH_CMP, 0, TCG_REG_R1, |
1342 | TCG_REG_R8, SHIFT_IMM_LSL(TARGET_PAGE_BITS)); | |
3979144c PB |
1343 | /* Check alignment. */ |
1344 | if (s_bits) | |
1345 | tcg_out_dat_imm(s, COND_EQ, ARITH_TST, | |
1346 | 0, addr_reg, (1 << s_bits) - 1); | |
811d4cf4 AZ |
1347 | # if TARGET_LONG_BITS == 64 |
1348 | /* XXX: possibly we could use a block data load or writeback in | |
1349 | * the first access. */ | |
c8d80cef | 1350 | tcg_out_ld32_12(s, COND_EQ, TCG_REG_R1, TCG_REG_R0, |
9349b4f9 | 1351 | offsetof(CPUArchState, tlb_table[0][0].addr_write) + 4); |
c8d80cef AJ |
1352 | tcg_out_dat_reg(s, COND_EQ, ARITH_CMP, 0, |
1353 | TCG_REG_R1, addr_reg2, SHIFT_IMM_LSL(0)); | |
811d4cf4 | 1354 | # endif |
c8d80cef | 1355 | tcg_out_ld32_12(s, COND_EQ, TCG_REG_R1, TCG_REG_R0, |
9349b4f9 | 1356 | offsetof(CPUArchState, tlb_table[0][0].addend)); |
811d4cf4 AZ |
1357 | |
1358 | switch (opc) { | |
1359 | case 0: | |
c8d80cef | 1360 | tcg_out_st8_r(s, COND_EQ, data_reg, addr_reg, TCG_REG_R1); |
811d4cf4 | 1361 | break; |
811d4cf4 | 1362 | case 1: |
67dcab73 AJ |
1363 | if (bswap) { |
1364 | tcg_out_bswap16(s, COND_EQ, TCG_REG_R0, data_reg); | |
1365 | tcg_out_st16_r(s, COND_EQ, TCG_REG_R0, addr_reg, TCG_REG_R1); | |
1366 | } else { | |
1367 | tcg_out_st16_r(s, COND_EQ, data_reg, addr_reg, TCG_REG_R1); | |
1368 | } | |
811d4cf4 AZ |
1369 | break; |
1370 | case 2: | |
1371 | default: | |
67dcab73 AJ |
1372 | if (bswap) { |
1373 | tcg_out_bswap32(s, COND_EQ, TCG_REG_R0, data_reg); | |
1374 | tcg_out_st32_r(s, COND_EQ, TCG_REG_R0, addr_reg, TCG_REG_R1); | |
1375 | } else { | |
1376 | tcg_out_st32_r(s, COND_EQ, data_reg, addr_reg, TCG_REG_R1); | |
1377 | } | |
811d4cf4 AZ |
1378 | break; |
1379 | case 3: | |
67dcab73 AJ |
1380 | if (bswap) { |
1381 | tcg_out_bswap32(s, COND_EQ, TCG_REG_R0, data_reg2); | |
1382 | tcg_out_st32_rwb(s, COND_EQ, TCG_REG_R0, TCG_REG_R1, addr_reg); | |
1383 | tcg_out_bswap32(s, COND_EQ, TCG_REG_R0, data_reg); | |
9a3abc21 | 1384 | tcg_out_st32_12(s, COND_EQ, TCG_REG_R0, TCG_REG_R1, 4); |
67dcab73 AJ |
1385 | } else { |
1386 | tcg_out_st32_rwb(s, COND_EQ, data_reg, TCG_REG_R1, addr_reg); | |
1387 | tcg_out_st32_12(s, COND_EQ, data_reg2, TCG_REG_R1, 4); | |
1388 | } | |
811d4cf4 AZ |
1389 | break; |
1390 | } | |
1391 | ||
1392 | label_ptr = (void *) s->code_ptr; | |
c69806ab | 1393 | tcg_out_b_noaddr(s, COND_EQ); |
811d4cf4 | 1394 | |
811d4cf4 | 1395 | /* TODO: move this code to where the constants pool will be */ |
9716ef3b PM |
1396 | /* Note that this code relies on the constraints we set in arm_op_defs[] |
1397 | * to ensure that later arguments are not passed to us in registers we | |
1398 | * trash by moving the earlier arguments into them. | |
1399 | */ | |
1400 | argreg = TCG_REG_R0; | |
9716ef3b | 1401 | argreg = tcg_out_arg_reg32(s, argreg, TCG_AREG0); |
9716ef3b PM |
1402 | #if TARGET_LONG_BITS == 64 |
1403 | argreg = tcg_out_arg_reg64(s, argreg, addr_reg, addr_reg2); | |
1404 | #else | |
1405 | argreg = tcg_out_arg_reg32(s, argreg, addr_reg); | |
1406 | #endif | |
1407 | ||
811d4cf4 AZ |
1408 | switch (opc) { |
1409 | case 0: | |
9716ef3b | 1410 | argreg = tcg_out_arg_reg8(s, argreg, data_reg); |
811d4cf4 AZ |
1411 | break; |
1412 | case 1: | |
9716ef3b | 1413 | argreg = tcg_out_arg_reg16(s, argreg, data_reg); |
811d4cf4 AZ |
1414 | break; |
1415 | case 2: | |
9716ef3b | 1416 | argreg = tcg_out_arg_reg32(s, argreg, data_reg); |
811d4cf4 AZ |
1417 | break; |
1418 | case 3: | |
9716ef3b | 1419 | argreg = tcg_out_arg_reg64(s, argreg, data_reg, data_reg2); |
811d4cf4 AZ |
1420 | break; |
1421 | } | |
811d4cf4 | 1422 | |
9716ef3b | 1423 | argreg = tcg_out_arg_imm32(s, argreg, mem_index); |
24e838b7 | 1424 | tcg_out_call(s, (tcg_target_long) qemu_st_helpers[s_bits]); |
9716ef3b | 1425 | tcg_out_arg_stacktidy(s, argreg); |
811d4cf4 | 1426 | |
c69806ab | 1427 | reloc_pc24(label_ptr, (tcg_target_long)s->code_ptr); |
379f6698 PB |
1428 | #else /* !CONFIG_SOFTMMU */ |
1429 | if (GUEST_BASE) { | |
1430 | uint32_t offset = GUEST_BASE; | |
1431 | int i; | |
1432 | int rot; | |
1433 | ||
1434 | while (offset) { | |
1435 | i = ctz32(offset) & ~1; | |
1436 | rot = ((32 - i) << 7) & 0xf00; | |
1437 | ||
67dcab73 | 1438 | tcg_out_dat_imm(s, COND_AL, ARITH_ADD, TCG_REG_R1, addr_reg, |
379f6698 | 1439 | ((offset >> i) & 0xff) | rot); |
67dcab73 | 1440 | addr_reg = TCG_REG_R1; |
379f6698 PB |
1441 | offset &= ~(0xff << i); |
1442 | } | |
1443 | } | |
811d4cf4 AZ |
1444 | switch (opc) { |
1445 | case 0: | |
1446 | tcg_out_st8_12(s, COND_AL, data_reg, addr_reg, 0); | |
1447 | break; | |
811d4cf4 | 1448 | case 1: |
67dcab73 AJ |
1449 | if (bswap) { |
1450 | tcg_out_bswap16(s, COND_AL, TCG_REG_R0, data_reg); | |
1451 | tcg_out_st16_8(s, COND_AL, TCG_REG_R0, addr_reg, 0); | |
1452 | } else { | |
1453 | tcg_out_st16_8(s, COND_AL, data_reg, addr_reg, 0); | |
1454 | } | |
811d4cf4 AZ |
1455 | break; |
1456 | case 2: | |
1457 | default: | |
67dcab73 AJ |
1458 | if (bswap) { |
1459 | tcg_out_bswap32(s, COND_AL, TCG_REG_R0, data_reg); | |
1460 | tcg_out_st32_12(s, COND_AL, TCG_REG_R0, addr_reg, 0); | |
1461 | } else { | |
1462 | tcg_out_st32_12(s, COND_AL, data_reg, addr_reg, 0); | |
1463 | } | |
811d4cf4 AZ |
1464 | break; |
1465 | case 3: | |
eae6ce52 AZ |
1466 | /* TODO: use block store - |
1467 | * check that data_reg2 > data_reg or the other way */ | |
67dcab73 AJ |
1468 | if (bswap) { |
1469 | tcg_out_bswap32(s, COND_AL, TCG_REG_R0, data_reg2); | |
1470 | tcg_out_st32_12(s, COND_AL, TCG_REG_R0, addr_reg, 0); | |
1471 | tcg_out_bswap32(s, COND_AL, TCG_REG_R0, data_reg); | |
1472 | tcg_out_st32_12(s, COND_AL, TCG_REG_R0, addr_reg, 4); | |
1473 | } else { | |
1474 | tcg_out_st32_12(s, COND_AL, data_reg, addr_reg, 0); | |
1475 | tcg_out_st32_12(s, COND_AL, data_reg2, addr_reg, 4); | |
1476 | } | |
811d4cf4 AZ |
1477 | break; |
1478 | } | |
1479 | #endif | |
1480 | } | |
1481 | ||
811d4cf4 AZ |
1482 | static uint8_t *tb_ret_addr; |
1483 | ||
a9751609 | 1484 | static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, |
811d4cf4 AZ |
1485 | const TCGArg *args, const int *const_args) |
1486 | { | |
1487 | int c; | |
1488 | ||
1489 | switch (opc) { | |
1490 | case INDEX_op_exit_tb: | |
fe33867b AZ |
1491 | { |
1492 | uint8_t *ld_ptr = s->code_ptr; | |
1493 | if (args[0] >> 8) | |
c8d80cef | 1494 | tcg_out_ld32_12(s, COND_AL, TCG_REG_R0, TCG_REG_PC, 0); |
fe33867b | 1495 | else |
c8d80cef | 1496 | tcg_out_dat_imm(s, COND_AL, ARITH_MOV, TCG_REG_R0, 0, args[0]); |
fe33867b AZ |
1497 | tcg_out_goto(s, COND_AL, (tcg_target_ulong) tb_ret_addr); |
1498 | if (args[0] >> 8) { | |
1499 | *ld_ptr = (uint8_t) (s->code_ptr - ld_ptr) - 8; | |
1500 | tcg_out32(s, args[0]); | |
1501 | } | |
1502 | } | |
811d4cf4 AZ |
1503 | break; |
1504 | case INDEX_op_goto_tb: | |
1505 | if (s->tb_jmp_offset) { | |
1506 | /* Direct jump method */ | |
fe33867b | 1507 | #if defined(USE_DIRECT_JUMP) |
811d4cf4 | 1508 | s->tb_jmp_offset[args[0]] = s->code_ptr - s->code_buf; |
c69806ab | 1509 | tcg_out_b_noaddr(s, COND_AL); |
811d4cf4 | 1510 | #else |
c8d80cef | 1511 | tcg_out_ld32_12(s, COND_AL, TCG_REG_PC, TCG_REG_PC, -4); |
811d4cf4 AZ |
1512 | s->tb_jmp_offset[args[0]] = s->code_ptr - s->code_buf; |
1513 | tcg_out32(s, 0); | |
1514 | #endif | |
1515 | } else { | |
1516 | /* Indirect jump method */ | |
1517 | #if 1 | |
1518 | c = (int) (s->tb_next + args[0]) - ((int) s->code_ptr + 8); | |
1519 | if (c > 0xfff || c < -0xfff) { | |
1520 | tcg_out_movi32(s, COND_AL, TCG_REG_R0, | |
1521 | (tcg_target_long) (s->tb_next + args[0])); | |
c8d80cef | 1522 | tcg_out_ld32_12(s, COND_AL, TCG_REG_PC, TCG_REG_R0, 0); |
811d4cf4 | 1523 | } else |
c8d80cef | 1524 | tcg_out_ld32_12(s, COND_AL, TCG_REG_PC, TCG_REG_PC, c); |
811d4cf4 | 1525 | #else |
c8d80cef AJ |
1526 | tcg_out_ld32_12(s, COND_AL, TCG_REG_R0, TCG_REG_PC, 0); |
1527 | tcg_out_ld32_12(s, COND_AL, TCG_REG_PC, TCG_REG_R0, 0); | |
811d4cf4 AZ |
1528 | tcg_out32(s, (tcg_target_long) (s->tb_next + args[0])); |
1529 | #endif | |
1530 | } | |
1531 | s->tb_next_offset[args[0]] = s->code_ptr - s->code_buf; | |
1532 | break; | |
1533 | case INDEX_op_call: | |
1534 | if (const_args[0]) | |
24e838b7 | 1535 | tcg_out_call(s, args[0]); |
811d4cf4 AZ |
1536 | else |
1537 | tcg_out_callr(s, COND_AL, args[0]); | |
1538 | break; | |
811d4cf4 AZ |
1539 | case INDEX_op_br: |
1540 | tcg_out_goto_label(s, COND_AL, args[0]); | |
1541 | break; | |
1542 | ||
1543 | case INDEX_op_ld8u_i32: | |
1544 | tcg_out_ld8u(s, COND_AL, args[0], args[1], args[2]); | |
1545 | break; | |
1546 | case INDEX_op_ld8s_i32: | |
1547 | tcg_out_ld8s(s, COND_AL, args[0], args[1], args[2]); | |
1548 | break; | |
1549 | case INDEX_op_ld16u_i32: | |
1550 | tcg_out_ld16u(s, COND_AL, args[0], args[1], args[2]); | |
1551 | break; | |
1552 | case INDEX_op_ld16s_i32: | |
1553 | tcg_out_ld16s(s, COND_AL, args[0], args[1], args[2]); | |
1554 | break; | |
1555 | case INDEX_op_ld_i32: | |
1556 | tcg_out_ld32u(s, COND_AL, args[0], args[1], args[2]); | |
1557 | break; | |
1558 | case INDEX_op_st8_i32: | |
f694a27e | 1559 | tcg_out_st8(s, COND_AL, args[0], args[1], args[2]); |
811d4cf4 AZ |
1560 | break; |
1561 | case INDEX_op_st16_i32: | |
f694a27e | 1562 | tcg_out_st16(s, COND_AL, args[0], args[1], args[2]); |
811d4cf4 AZ |
1563 | break; |
1564 | case INDEX_op_st_i32: | |
1565 | tcg_out_st32(s, COND_AL, args[0], args[1], args[2]); | |
1566 | break; | |
1567 | ||
1568 | case INDEX_op_mov_i32: | |
1569 | tcg_out_dat_reg(s, COND_AL, ARITH_MOV, | |
1570 | args[0], 0, args[1], SHIFT_IMM_LSL(0)); | |
1571 | break; | |
1572 | case INDEX_op_movi_i32: | |
1573 | tcg_out_movi32(s, COND_AL, args[0], args[1]); | |
1574 | break; | |
4a1d241e PM |
1575 | case INDEX_op_movcond_i32: |
1576 | /* Constraints mean that v2 is always in the same register as dest, | |
1577 | * so we only need to do "if condition passed, move v1 to dest". | |
1578 | */ | |
1579 | tcg_out_dat_rI(s, COND_AL, ARITH_CMP, 0, | |
1580 | args[1], args[2], const_args[2]); | |
1581 | tcg_out_dat_rI(s, tcg_cond_to_arm_cond[args[5]], | |
1582 | ARITH_MOV, args[0], 0, args[3], const_args[3]); | |
1583 | break; | |
811d4cf4 AZ |
1584 | case INDEX_op_add_i32: |
1585 | c = ARITH_ADD; | |
1586 | goto gen_arith; | |
1587 | case INDEX_op_sub_i32: | |
1588 | c = ARITH_SUB; | |
1589 | goto gen_arith; | |
1590 | case INDEX_op_and_i32: | |
1591 | c = ARITH_AND; | |
1592 | goto gen_arith; | |
932234f6 AJ |
1593 | case INDEX_op_andc_i32: |
1594 | c = ARITH_BIC; | |
1595 | goto gen_arith; | |
811d4cf4 AZ |
1596 | case INDEX_op_or_i32: |
1597 | c = ARITH_ORR; | |
1598 | goto gen_arith; | |
1599 | case INDEX_op_xor_i32: | |
1600 | c = ARITH_EOR; | |
1601 | /* Fall through. */ | |
1602 | gen_arith: | |
7fc645bf | 1603 | tcg_out_dat_rI(s, COND_AL, c, args[0], args[1], args[2], const_args[2]); |
811d4cf4 AZ |
1604 | break; |
1605 | case INDEX_op_add2_i32: | |
1606 | tcg_out_dat_reg2(s, COND_AL, ARITH_ADD, ARITH_ADC, | |
1607 | args[0], args[1], args[2], args[3], | |
1608 | args[4], args[5], SHIFT_IMM_LSL(0)); | |
1609 | break; | |
1610 | case INDEX_op_sub2_i32: | |
1611 | tcg_out_dat_reg2(s, COND_AL, ARITH_SUB, ARITH_SBC, | |
1612 | args[0], args[1], args[2], args[3], | |
1613 | args[4], args[5], SHIFT_IMM_LSL(0)); | |
1614 | break; | |
650bbb36 AZ |
1615 | case INDEX_op_neg_i32: |
1616 | tcg_out_dat_imm(s, COND_AL, ARITH_RSB, args[0], args[1], 0); | |
1617 | break; | |
f878d2d2 LD |
1618 | case INDEX_op_not_i32: |
1619 | tcg_out_dat_reg(s, COND_AL, | |
1620 | ARITH_MVN, args[0], 0, args[1], SHIFT_IMM_LSL(0)); | |
1621 | break; | |
811d4cf4 AZ |
1622 | case INDEX_op_mul_i32: |
1623 | tcg_out_mul32(s, COND_AL, args[0], args[1], args[2]); | |
1624 | break; | |
1625 | case INDEX_op_mulu2_i32: | |
1626 | tcg_out_umull32(s, COND_AL, args[0], args[1], args[2], args[3]); | |
1627 | break; | |
811d4cf4 AZ |
1628 | /* XXX: Perhaps args[2] & 0x1f is wrong */ |
1629 | case INDEX_op_shl_i32: | |
1630 | c = const_args[2] ? | |
1631 | SHIFT_IMM_LSL(args[2] & 0x1f) : SHIFT_REG_LSL(args[2]); | |
1632 | goto gen_shift32; | |
1633 | case INDEX_op_shr_i32: | |
1634 | c = const_args[2] ? (args[2] & 0x1f) ? SHIFT_IMM_LSR(args[2] & 0x1f) : | |
1635 | SHIFT_IMM_LSL(0) : SHIFT_REG_LSR(args[2]); | |
1636 | goto gen_shift32; | |
1637 | case INDEX_op_sar_i32: | |
1638 | c = const_args[2] ? (args[2] & 0x1f) ? SHIFT_IMM_ASR(args[2] & 0x1f) : | |
1639 | SHIFT_IMM_LSL(0) : SHIFT_REG_ASR(args[2]); | |
293579e5 AJ |
1640 | goto gen_shift32; |
1641 | case INDEX_op_rotr_i32: | |
1642 | c = const_args[2] ? (args[2] & 0x1f) ? SHIFT_IMM_ROR(args[2] & 0x1f) : | |
1643 | SHIFT_IMM_LSL(0) : SHIFT_REG_ROR(args[2]); | |
811d4cf4 AZ |
1644 | /* Fall through. */ |
1645 | gen_shift32: | |
1646 | tcg_out_dat_reg(s, COND_AL, ARITH_MOV, args[0], 0, args[1], c); | |
1647 | break; | |
1648 | ||
293579e5 AJ |
1649 | case INDEX_op_rotl_i32: |
1650 | if (const_args[2]) { | |
1651 | tcg_out_dat_reg(s, COND_AL, ARITH_MOV, args[0], 0, args[1], | |
1652 | ((0x20 - args[2]) & 0x1f) ? | |
1653 | SHIFT_IMM_ROR((0x20 - args[2]) & 0x1f) : | |
1654 | SHIFT_IMM_LSL(0)); | |
1655 | } else { | |
1656 | tcg_out_dat_imm(s, COND_AL, ARITH_RSB, TCG_REG_R8, args[1], 0x20); | |
1657 | tcg_out_dat_reg(s, COND_AL, ARITH_MOV, args[0], 0, args[1], | |
1658 | SHIFT_REG_ROR(TCG_REG_R8)); | |
1659 | } | |
1660 | break; | |
1661 | ||
811d4cf4 | 1662 | case INDEX_op_brcond_i32: |
7fc645bf PM |
1663 | tcg_out_dat_rI(s, COND_AL, ARITH_CMP, 0, |
1664 | args[0], args[1], const_args[1]); | |
811d4cf4 AZ |
1665 | tcg_out_goto_label(s, tcg_cond_to_arm_cond[args[2]], args[3]); |
1666 | break; | |
1667 | case INDEX_op_brcond2_i32: | |
1668 | /* The resulting conditions are: | |
1669 | * TCG_COND_EQ --> a0 == a2 && a1 == a3, | |
1670 | * TCG_COND_NE --> (a0 != a2 && a1 == a3) || a1 != a3, | |
1671 | * TCG_COND_LT(U) --> (a0 < a2 && a1 == a3) || a1 < a3, | |
1672 | * TCG_COND_GE(U) --> (a0 >= a2 && a1 == a3) || (a1 >= a3 && a1 != a3), | |
1673 | * TCG_COND_LE(U) --> (a0 <= a2 && a1 == a3) || (a1 <= a3 && a1 != a3), | |
1674 | * TCG_COND_GT(U) --> (a0 > a2 && a1 == a3) || a1 > a3, | |
1675 | */ | |
1676 | tcg_out_dat_reg(s, COND_AL, ARITH_CMP, 0, | |
1677 | args[1], args[3], SHIFT_IMM_LSL(0)); | |
1678 | tcg_out_dat_reg(s, COND_EQ, ARITH_CMP, 0, | |
1679 | args[0], args[2], SHIFT_IMM_LSL(0)); | |
1680 | tcg_out_goto_label(s, tcg_cond_to_arm_cond[args[4]], args[5]); | |
1681 | break; | |
f72a6cd7 | 1682 | case INDEX_op_setcond_i32: |
7fc645bf PM |
1683 | tcg_out_dat_rI(s, COND_AL, ARITH_CMP, 0, |
1684 | args[1], args[2], const_args[2]); | |
f72a6cd7 AJ |
1685 | tcg_out_dat_imm(s, tcg_cond_to_arm_cond[args[3]], |
1686 | ARITH_MOV, args[0], 0, 1); | |
1687 | tcg_out_dat_imm(s, tcg_cond_to_arm_cond[tcg_invert_cond(args[3])], | |
1688 | ARITH_MOV, args[0], 0, 0); | |
1689 | break; | |
e0404769 AJ |
1690 | case INDEX_op_setcond2_i32: |
1691 | /* See brcond2_i32 comment */ | |
1692 | tcg_out_dat_reg(s, COND_AL, ARITH_CMP, 0, | |
1693 | args[2], args[4], SHIFT_IMM_LSL(0)); | |
1694 | tcg_out_dat_reg(s, COND_EQ, ARITH_CMP, 0, | |
1695 | args[1], args[3], SHIFT_IMM_LSL(0)); | |
1696 | tcg_out_dat_imm(s, tcg_cond_to_arm_cond[args[5]], | |
1697 | ARITH_MOV, args[0], 0, 1); | |
1698 | tcg_out_dat_imm(s, tcg_cond_to_arm_cond[tcg_invert_cond(args[5])], | |
1699 | ARITH_MOV, args[0], 0, 0); | |
b525f0a9 | 1700 | break; |
811d4cf4 AZ |
1701 | |
1702 | case INDEX_op_qemu_ld8u: | |
7e0d9562 | 1703 | tcg_out_qemu_ld(s, args, 0); |
811d4cf4 AZ |
1704 | break; |
1705 | case INDEX_op_qemu_ld8s: | |
7e0d9562 | 1706 | tcg_out_qemu_ld(s, args, 0 | 4); |
811d4cf4 AZ |
1707 | break; |
1708 | case INDEX_op_qemu_ld16u: | |
7e0d9562 | 1709 | tcg_out_qemu_ld(s, args, 1); |
811d4cf4 AZ |
1710 | break; |
1711 | case INDEX_op_qemu_ld16s: | |
7e0d9562 | 1712 | tcg_out_qemu_ld(s, args, 1 | 4); |
811d4cf4 | 1713 | break; |
86feb1c8 | 1714 | case INDEX_op_qemu_ld32: |
7e0d9562 | 1715 | tcg_out_qemu_ld(s, args, 2); |
811d4cf4 AZ |
1716 | break; |
1717 | case INDEX_op_qemu_ld64: | |
7e0d9562 | 1718 | tcg_out_qemu_ld(s, args, 3); |
811d4cf4 | 1719 | break; |
650bbb36 | 1720 | |
811d4cf4 | 1721 | case INDEX_op_qemu_st8: |
7e0d9562 | 1722 | tcg_out_qemu_st(s, args, 0); |
811d4cf4 AZ |
1723 | break; |
1724 | case INDEX_op_qemu_st16: | |
7e0d9562 | 1725 | tcg_out_qemu_st(s, args, 1); |
811d4cf4 AZ |
1726 | break; |
1727 | case INDEX_op_qemu_st32: | |
7e0d9562 | 1728 | tcg_out_qemu_st(s, args, 2); |
811d4cf4 AZ |
1729 | break; |
1730 | case INDEX_op_qemu_st64: | |
7e0d9562 | 1731 | tcg_out_qemu_st(s, args, 3); |
811d4cf4 AZ |
1732 | break; |
1733 | ||
244b1e81 AJ |
1734 | case INDEX_op_bswap16_i32: |
1735 | tcg_out_bswap16(s, COND_AL, args[0], args[1]); | |
1736 | break; | |
1737 | case INDEX_op_bswap32_i32: | |
1738 | tcg_out_bswap32(s, COND_AL, args[0], args[1]); | |
1739 | break; | |
1740 | ||
811d4cf4 | 1741 | case INDEX_op_ext8s_i32: |
9517094f | 1742 | tcg_out_ext8s(s, COND_AL, args[0], args[1]); |
811d4cf4 AZ |
1743 | break; |
1744 | case INDEX_op_ext16s_i32: | |
9517094f AJ |
1745 | tcg_out_ext16s(s, COND_AL, args[0], args[1]); |
1746 | break; | |
1747 | case INDEX_op_ext16u_i32: | |
1748 | tcg_out_ext16u(s, COND_AL, args[0], args[1]); | |
811d4cf4 AZ |
1749 | break; |
1750 | ||
1751 | default: | |
1752 | tcg_abort(); | |
1753 | } | |
1754 | } | |
1755 | ||
1756 | static const TCGTargetOpDef arm_op_defs[] = { | |
1757 | { INDEX_op_exit_tb, { } }, | |
1758 | { INDEX_op_goto_tb, { } }, | |
1759 | { INDEX_op_call, { "ri" } }, | |
811d4cf4 AZ |
1760 | { INDEX_op_br, { } }, |
1761 | ||
1762 | { INDEX_op_mov_i32, { "r", "r" } }, | |
1763 | { INDEX_op_movi_i32, { "r" } }, | |
1764 | ||
1765 | { INDEX_op_ld8u_i32, { "r", "r" } }, | |
1766 | { INDEX_op_ld8s_i32, { "r", "r" } }, | |
1767 | { INDEX_op_ld16u_i32, { "r", "r" } }, | |
1768 | { INDEX_op_ld16s_i32, { "r", "r" } }, | |
1769 | { INDEX_op_ld_i32, { "r", "r" } }, | |
1770 | { INDEX_op_st8_i32, { "r", "r" } }, | |
1771 | { INDEX_op_st16_i32, { "r", "r" } }, | |
1772 | { INDEX_op_st_i32, { "r", "r" } }, | |
1773 | ||
1774 | /* TODO: "r", "r", "ri" */ | |
cb4e581f LD |
1775 | { INDEX_op_add_i32, { "r", "r", "rI" } }, |
1776 | { INDEX_op_sub_i32, { "r", "r", "rI" } }, | |
811d4cf4 AZ |
1777 | { INDEX_op_mul_i32, { "r", "r", "r" } }, |
1778 | { INDEX_op_mulu2_i32, { "r", "r", "r", "r" } }, | |
cb4e581f | 1779 | { INDEX_op_and_i32, { "r", "r", "rI" } }, |
932234f6 | 1780 | { INDEX_op_andc_i32, { "r", "r", "rI" } }, |
cb4e581f LD |
1781 | { INDEX_op_or_i32, { "r", "r", "rI" } }, |
1782 | { INDEX_op_xor_i32, { "r", "r", "rI" } }, | |
650bbb36 | 1783 | { INDEX_op_neg_i32, { "r", "r" } }, |
f878d2d2 | 1784 | { INDEX_op_not_i32, { "r", "r" } }, |
811d4cf4 AZ |
1785 | |
1786 | { INDEX_op_shl_i32, { "r", "r", "ri" } }, | |
1787 | { INDEX_op_shr_i32, { "r", "r", "ri" } }, | |
1788 | { INDEX_op_sar_i32, { "r", "r", "ri" } }, | |
293579e5 AJ |
1789 | { INDEX_op_rotl_i32, { "r", "r", "ri" } }, |
1790 | { INDEX_op_rotr_i32, { "r", "r", "ri" } }, | |
811d4cf4 | 1791 | |
023e77f8 AJ |
1792 | { INDEX_op_brcond_i32, { "r", "rI" } }, |
1793 | { INDEX_op_setcond_i32, { "r", "r", "rI" } }, | |
4a1d241e | 1794 | { INDEX_op_movcond_i32, { "r", "r", "rI", "rI", "0" } }, |
811d4cf4 AZ |
1795 | |
1796 | /* TODO: "r", "r", "r", "r", "ri", "ri" */ | |
1797 | { INDEX_op_add2_i32, { "r", "r", "r", "r", "r", "r" } }, | |
1798 | { INDEX_op_sub2_i32, { "r", "r", "r", "r", "r", "r" } }, | |
1799 | { INDEX_op_brcond2_i32, { "r", "r", "r", "r" } }, | |
e0404769 | 1800 | { INDEX_op_setcond2_i32, { "r", "r", "r", "r", "r" } }, |
811d4cf4 | 1801 | |
26c5d372 | 1802 | #if TARGET_LONG_BITS == 32 |
67dcab73 AJ |
1803 | { INDEX_op_qemu_ld8u, { "r", "l" } }, |
1804 | { INDEX_op_qemu_ld8s, { "r", "l" } }, | |
1805 | { INDEX_op_qemu_ld16u, { "r", "l" } }, | |
1806 | { INDEX_op_qemu_ld16s, { "r", "l" } }, | |
1807 | { INDEX_op_qemu_ld32, { "r", "l" } }, | |
1808 | { INDEX_op_qemu_ld64, { "L", "L", "l" } }, | |
1809 | ||
1810 | { INDEX_op_qemu_st8, { "s", "s" } }, | |
1811 | { INDEX_op_qemu_st16, { "s", "s" } }, | |
1812 | { INDEX_op_qemu_st32, { "s", "s" } }, | |
bf5675ef | 1813 | { INDEX_op_qemu_st64, { "S", "S", "s" } }, |
26c5d372 | 1814 | #else |
67dcab73 AJ |
1815 | { INDEX_op_qemu_ld8u, { "r", "l", "l" } }, |
1816 | { INDEX_op_qemu_ld8s, { "r", "l", "l" } }, | |
1817 | { INDEX_op_qemu_ld16u, { "r", "l", "l" } }, | |
1818 | { INDEX_op_qemu_ld16s, { "r", "l", "l" } }, | |
1819 | { INDEX_op_qemu_ld32, { "r", "l", "l" } }, | |
1820 | { INDEX_op_qemu_ld64, { "L", "L", "l", "l" } }, | |
1821 | ||
1822 | { INDEX_op_qemu_st8, { "s", "s", "s" } }, | |
1823 | { INDEX_op_qemu_st16, { "s", "s", "s" } }, | |
1824 | { INDEX_op_qemu_st32, { "s", "s", "s" } }, | |
bf5675ef | 1825 | { INDEX_op_qemu_st64, { "S", "S", "s", "s" } }, |
26c5d372 | 1826 | #endif |
811d4cf4 | 1827 | |
244b1e81 AJ |
1828 | { INDEX_op_bswap16_i32, { "r", "r" } }, |
1829 | { INDEX_op_bswap32_i32, { "r", "r" } }, | |
1830 | ||
811d4cf4 AZ |
1831 | { INDEX_op_ext8s_i32, { "r", "r" } }, |
1832 | { INDEX_op_ext16s_i32, { "r", "r" } }, | |
9517094f | 1833 | { INDEX_op_ext16u_i32, { "r", "r" } }, |
811d4cf4 AZ |
1834 | |
1835 | { -1 }, | |
1836 | }; | |
1837 | ||
e4d58b41 | 1838 | static void tcg_target_init(TCGContext *s) |
811d4cf4 | 1839 | { |
20cb400d | 1840 | #if !defined(CONFIG_USER_ONLY) |
811d4cf4 AZ |
1841 | /* fail safe */ |
1842 | if ((1 << CPU_TLB_ENTRY_BITS) != sizeof(CPUTLBEntry)) | |
1843 | tcg_abort(); | |
20cb400d | 1844 | #endif |
811d4cf4 | 1845 | |
e4a7d5e8 | 1846 | tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0, 0xffff); |
811d4cf4 | 1847 | tcg_regset_set32(tcg_target_call_clobber_regs, 0, |
e4a7d5e8 AJ |
1848 | (1 << TCG_REG_R0) | |
1849 | (1 << TCG_REG_R1) | | |
1850 | (1 << TCG_REG_R2) | | |
1851 | (1 << TCG_REG_R3) | | |
1852 | (1 << TCG_REG_R12) | | |
1853 | (1 << TCG_REG_R14)); | |
811d4cf4 AZ |
1854 | |
1855 | tcg_regset_clear(s->reserved_regs); | |
811d4cf4 AZ |
1856 | tcg_regset_set_reg(s->reserved_regs, TCG_REG_CALL_STACK); |
1857 | tcg_regset_set_reg(s->reserved_regs, TCG_REG_R8); | |
e4a7d5e8 | 1858 | tcg_regset_set_reg(s->reserved_regs, TCG_REG_PC); |
811d4cf4 AZ |
1859 | |
1860 | tcg_add_target_add_op_defs(arm_op_defs); | |
9349b4f9 | 1861 | tcg_set_frame(s, TCG_AREG0, offsetof(CPUArchState, temp_buf), |
614f104d | 1862 | CPU_TEMP_BUF_NLONGS * sizeof(long)); |
811d4cf4 AZ |
1863 | } |
1864 | ||
2a534aff RH |
1865 | static inline void tcg_out_ld(TCGContext *s, TCGType type, TCGReg arg, |
1866 | TCGReg arg1, tcg_target_long arg2) | |
811d4cf4 AZ |
1867 | { |
1868 | tcg_out_ld32u(s, COND_AL, arg, arg1, arg2); | |
1869 | } | |
1870 | ||
2a534aff RH |
1871 | static inline void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, |
1872 | TCGReg arg1, tcg_target_long arg2) | |
811d4cf4 AZ |
1873 | { |
1874 | tcg_out_st32(s, COND_AL, arg, arg1, arg2); | |
1875 | } | |
1876 | ||
2a534aff RH |
1877 | static inline void tcg_out_mov(TCGContext *s, TCGType type, |
1878 | TCGReg ret, TCGReg arg) | |
811d4cf4 AZ |
1879 | { |
1880 | tcg_out_dat_reg(s, COND_AL, ARITH_MOV, ret, 0, arg, SHIFT_IMM_LSL(0)); | |
1881 | } | |
1882 | ||
1883 | static inline void tcg_out_movi(TCGContext *s, TCGType type, | |
2a534aff | 1884 | TCGReg ret, tcg_target_long arg) |
811d4cf4 AZ |
1885 | { |
1886 | tcg_out_movi32(s, COND_AL, ret, arg); | |
1887 | } | |
1888 | ||
e4d58b41 | 1889 | static void tcg_target_qemu_prologue(TCGContext *s) |
811d4cf4 | 1890 | { |
cea5f9a2 BS |
1891 | /* Calling convention requires us to save r4-r11 and lr; |
1892 | * save also r12 to maintain stack 8-alignment. | |
1893 | */ | |
1894 | ||
1895 | /* stmdb sp!, { r4 - r12, lr } */ | |
1896 | tcg_out32(s, (COND_AL << 28) | 0x092d5ff0); | |
4e17eae9 | 1897 | |
cea5f9a2 | 1898 | tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]); |
811d4cf4 | 1899 | |
cea5f9a2 | 1900 | tcg_out_bx(s, COND_AL, tcg_target_call_iarg_regs[1]); |
811d4cf4 AZ |
1901 | tb_ret_addr = s->code_ptr; |
1902 | ||
cea5f9a2 BS |
1903 | /* ldmia sp!, { r4 - r12, pc } */ |
1904 | tcg_out32(s, (COND_AL << 28) | 0x08bd9ff0); | |
811d4cf4 | 1905 | } |