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tcg/arm: remove conditional argument for qemu_ld/st
[qemu.git] / tcg / arm / tcg-target.c
CommitLineData
811d4cf4
AZ		 1/*
2 * Tiny Code Generator for QEMU
3 *
4 * Copyright (c) 2008 Andrzej Zaborowski
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
d4a9eb1f 24
ac34fb5c
AJ		 25#if defined(__ARM_ARCH_7__) || \
26 defined(__ARM_ARCH_7A__) || \
27 defined(__ARM_ARCH_7EM__) || \
28 defined(__ARM_ARCH_7M__) || \
29 defined(__ARM_ARCH_7R__)
30#define USE_ARMV7_INSTRUCTIONS
31#endif
32
33#if defined(USE_ARMV7_INSTRUCTIONS) || \
34 defined(__ARM_ARCH_6J__) || \
35 defined(__ARM_ARCH_6K__) || \
36 defined(__ARM_ARCH_6T2__) || \
37 defined(__ARM_ARCH_6Z__) || \
38 defined(__ARM_ARCH_6ZK__)
39#define USE_ARMV6_INSTRUCTIONS
40#endif
41
42#if defined(USE_ARMV6_INSTRUCTIONS) || \
43 defined(__ARM_ARCH_5T__) || \
44 defined(__ARM_ARCH_5TE__) || \
45 defined(__ARM_ARCH_5TEJ__)
46#define USE_ARMV5_INSTRUCTIONS
47#endif
48
49#ifdef USE_ARMV5_INSTRUCTIONS
50static const int use_armv5_instructions = 1;
51#else
52static const int use_armv5_instructions = 0;
53#endif
54#undef USE_ARMV5_INSTRUCTIONS
55
56#ifdef USE_ARMV6_INSTRUCTIONS
57static const int use_armv6_instructions = 1;
58#else
59static const int use_armv6_instructions = 0;
60#endif
61#undef USE_ARMV6_INSTRUCTIONS
62
63#ifdef USE_ARMV7_INSTRUCTIONS
64static const int use_armv7_instructions = 1;
65#else
66static const int use_armv7_instructions = 0;
67#endif
68#undef USE_ARMV7_INSTRUCTIONS
69
d4a9eb1f
BS		 70#ifndef NDEBUG
71static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
811d4cf4
AZ		 72 "%r0",
73 "%r1",
74 "%r2",
75 "%r3",
76 "%r4",
77 "%r5",
78 "%r6",
79 "%r7",
80 "%r8",
81 "%r9",
82 "%r10",
83 "%r11",
84 "%r12",
85 "%r13",
86 "%r14",
e4a7d5e8 87 "%pc",
811d4cf4 88};
d4a9eb1f 89#endif
811d4cf4 90
d4a9eb1f 91static const int tcg_target_reg_alloc_order[] = {
811d4cf4
AZ		 92 TCG_REG_R0,
93 TCG_REG_R1,
94 TCG_REG_R2,
95 TCG_REG_R3,
96 TCG_REG_R4,
97 TCG_REG_R5,
98 TCG_REG_R6,
99 TCG_REG_R7,
100 TCG_REG_R8,
101 TCG_REG_R9,
102 TCG_REG_R10,
103 TCG_REG_R11,
104 TCG_REG_R12,
105 TCG_REG_R13,
106 TCG_REG_R14,
107};
108
d4a9eb1f 109static const int tcg_target_call_iarg_regs[4] = {
811d4cf4
AZ		 110 TCG_REG_R0, TCG_REG_R1, TCG_REG_R2, TCG_REG_R3
111};
d4a9eb1f 112static const int tcg_target_call_oarg_regs[2] = {
811d4cf4
AZ		 113 TCG_REG_R0, TCG_REG_R1
114};
115
650bbb36 116static void patch_reloc(uint8_t *code_ptr, int type,
811d4cf4
AZ		 117 tcg_target_long value, tcg_target_long addend)
118{
119 switch (type) {
120 case R_ARM_ABS32:
121 *(uint32_t *) code_ptr = value;
122 break;
123
124 case R_ARM_CALL:
125 case R_ARM_JUMP24:
126 default:
127 tcg_abort();
128
129 case R_ARM_PC24:
eae6ce52 130 *(uint32_t *) code_ptr = ((*(uint32_t *) code_ptr) & 0xff000000) |
e936243a 131 (((value - ((tcg_target_long) code_ptr + 8)) >> 2) & 0xffffff);
811d4cf4
AZ		 132 break;
133 }
134}
135
136/* maximum number of register used for input function arguments */
137static inline int tcg_target_get_call_iarg_regs_count(int flags)
138{
139 return 4;
140}
141
811d4cf4 142/* parse target specific constraints */
d4a9eb1f 143static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
811d4cf4
AZ		 144{
145 const char *ct_str;
146
147 ct_str = *pct_str;
148 switch (ct_str[0]) {
cb4e581f
LD		 149 case 'I':
150 ct->ct |= TCG_CT_CONST_ARM;
151 break;
152
811d4cf4
AZ		 153 case 'r':
154#ifndef CONFIG_SOFTMMU
155 case 'd':
156 case 'D':
157 case 'x':
158 case 'X':
159#endif
160 ct->ct |= TCG_CT_REG;
161 tcg_regset_set32(ct->u.regs, 0, (1 << TCG_TARGET_NB_REGS) - 1);
162 break;
163
164#ifdef CONFIG_SOFTMMU
d0660ed4 165 /* qemu_ld/st inputs (unless 'X', 'd' or 'D') */
811d4cf4
AZ		 166 case 'x':
167 ct->ct |= TCG_CT_REG;
168 tcg_regset_set32(ct->u.regs, 0, (1 << TCG_TARGET_NB_REGS) - 1);
811d4cf4
AZ		 169 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R0);
170 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R1);
811d4cf4
AZ		 171 break;
172
d0660ed4
AZ		 173 /* qemu_ld64 data_reg */
174 case 'd':
175 ct->ct |= TCG_CT_REG;
176 tcg_regset_set32(ct->u.regs, 0, (1 << TCG_TARGET_NB_REGS) - 1);
177 /* r1 is still needed to load data_reg2, so don't use it. */
178 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R1);
179 break;
180
811d4cf4
AZ		 181 /* qemu_ld/st64 data_reg2 */
182 case 'D':
183 ct->ct |= TCG_CT_REG;
184 tcg_regset_set32(ct->u.regs, 0, (1 << TCG_TARGET_NB_REGS) - 1);
185 /* r0, r1 and optionally r2 will be overwritten by the address
186 * and the low word of data, so don't use these. */
187 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R0);
188 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R1);
189# if TARGET_LONG_BITS == 64
190 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R2);
191# endif
192 break;
193
194# if TARGET_LONG_BITS == 64
195 /* qemu_ld/st addr_reg2 */
196 case 'X':
197 ct->ct |= TCG_CT_REG;
198 tcg_regset_set32(ct->u.regs, 0, (1 << TCG_TARGET_NB_REGS) - 1);
199 /* r0 will be overwritten by the low word of base, so don't use it. */
200 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R0);
811d4cf4 201 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R1);
811d4cf4
AZ		 202 break;
203# endif
204#endif
205
811d4cf4
AZ		 206 default:
207 return -1;
208 }
209 ct_str++;
210 *pct_str = ct_str;
211
212 return 0;
213}
214
94953e6d
LD		 215static inline uint32_t rotl(uint32_t val, int n)
216{
217 return (val << n) | (val >> (32 - n));
218}
219
220/* ARM immediates for ALU instructions are made of an unsigned 8-bit
221 right-rotated by an even amount between 0 and 30. */
222static inline int encode_imm(uint32_t imm)
223{
4e6f6d4c
LD		 224 int shift;
225
94953e6d
LD		 226 /* simple case, only lower bits */
227 if ((imm & ~0xff) == 0)
228 return 0;
229 /* then try a simple even shift */
230 shift = ctz32(imm) & ~1;
231 if (((imm >> shift) & ~0xff) == 0)
232 return 32 - shift;
233 /* now try harder with rotations */
234 if ((rotl(imm, 2) & ~0xff) == 0)
235 return 2;
236 if ((rotl(imm, 4) & ~0xff) == 0)
237 return 4;
238 if ((rotl(imm, 6) & ~0xff) == 0)
239 return 6;
240 /* imm can't be encoded */
241 return -1;
242}
cb4e581f
LD		 243
244static inline int check_fit_imm(uint32_t imm)
245{
94953e6d 246 return encode_imm(imm) >= 0;
cb4e581f
LD		 247}
248
811d4cf4
AZ		 249/* Test if a constant matches the constraint.
250 * TODO: define constraints for:
251 *
252 * ldr/str offset: between -0xfff and 0xfff
253 * ldrh/strh offset: between -0xff and 0xff
254 * mov operand2: values represented with x << (2 * y), x < 0x100
255 * add, sub, eor...: ditto
256 */
257static inline int tcg_target_const_match(tcg_target_long val,
258 const TCGArgConstraint *arg_ct)
259{
260 int ct;
261 ct = arg_ct->ct;
262 if (ct & TCG_CT_CONST)
263 return 1;
cb4e581f
LD		 264 else if ((ct & TCG_CT_CONST_ARM) && check_fit_imm(val))
265 return 1;
811d4cf4
AZ		 266 else
267 return 0;
268}
269
270enum arm_data_opc_e {
271 ARITH_AND = 0x0,
272 ARITH_EOR = 0x1,
273 ARITH_SUB = 0x2,
274 ARITH_RSB = 0x3,
275 ARITH_ADD = 0x4,
276 ARITH_ADC = 0x5,
277 ARITH_SBC = 0x6,
278 ARITH_RSC = 0x7,
3979144c 279 ARITH_TST = 0x8,
811d4cf4
AZ		 280 ARITH_CMP = 0xa,
281 ARITH_CMN = 0xb,
282 ARITH_ORR = 0xc,
283 ARITH_MOV = 0xd,
284 ARITH_BIC = 0xe,
285 ARITH_MVN = 0xf,
286};
287
3979144c
PB		 288#define TO_CPSR(opc) \
289 ((opc == ARITH_CMP || opc == ARITH_CMN || opc == ARITH_TST) << 20)
811d4cf4
AZ		 290
291#define SHIFT_IMM_LSL(im) (((im) << 7) | 0x00)
292#define SHIFT_IMM_LSR(im) (((im) << 7) | 0x20)
293#define SHIFT_IMM_ASR(im) (((im) << 7) | 0x40)
294#define SHIFT_IMM_ROR(im) (((im) << 7) | 0x60)
295#define SHIFT_REG_LSL(rs) (((rs) << 8) | 0x10)
296#define SHIFT_REG_LSR(rs) (((rs) << 8) | 0x30)
297#define SHIFT_REG_ASR(rs) (((rs) << 8) | 0x50)
298#define SHIFT_REG_ROR(rs) (((rs) << 8) | 0x70)
299
300enum arm_cond_code_e {
301 COND_EQ = 0x0,
302 COND_NE = 0x1,
303 COND_CS = 0x2, /* Unsigned greater or equal */
304 COND_CC = 0x3, /* Unsigned less than */
305 COND_MI = 0x4, /* Negative */
306 COND_PL = 0x5, /* Zero or greater */
307 COND_VS = 0x6, /* Overflow */
308 COND_VC = 0x7, /* No overflow */
309 COND_HI = 0x8, /* Unsigned greater than */
310 COND_LS = 0x9, /* Unsigned less or equal */
311 COND_GE = 0xa,
312 COND_LT = 0xb,
313 COND_GT = 0xc,
314 COND_LE = 0xd,
315 COND_AL = 0xe,
316};
317
318static const uint8_t tcg_cond_to_arm_cond[10] = {
319 [TCG_COND_EQ] = COND_EQ,
320 [TCG_COND_NE] = COND_NE,
321 [TCG_COND_LT] = COND_LT,
322 [TCG_COND_GE] = COND_GE,
323 [TCG_COND_LE] = COND_LE,
324 [TCG_COND_GT] = COND_GT,
325 /* unsigned */
326 [TCG_COND_LTU] = COND_CC,
327 [TCG_COND_GEU] = COND_CS,
328 [TCG_COND_LEU] = COND_LS,
329 [TCG_COND_GTU] = COND_HI,
330};
331
332static inline void tcg_out_bx(TCGContext *s, int cond, int rn)
333{
334 tcg_out32(s, (cond << 28) | 0x012fff10 | rn);
335}
336
337static inline void tcg_out_b(TCGContext *s, int cond, int32_t offset)
338{
339 tcg_out32(s, (cond << 28) | 0x0a000000 |
340 (((offset - 8) >> 2) & 0x00ffffff));
341}
342
e936243a
AZ		 343static inline void tcg_out_b_noaddr(TCGContext *s, int cond)
344{
e2542fe2 345#ifdef HOST_WORDS_BIGENDIAN
e936243a
AZ		 346 tcg_out8(s, (cond << 4) | 0x0a);
347 s->code_ptr += 3;
348#else
349 s->code_ptr += 3;
350 tcg_out8(s, (cond << 4) | 0x0a);
351#endif
352}
353
811d4cf4
AZ		 354static inline void tcg_out_bl(TCGContext *s, int cond, int32_t offset)
355{
356 tcg_out32(s, (cond << 28) | 0x0b000000 |
357 (((offset - 8) >> 2) & 0x00ffffff));
358}
359
23401b58
AJ		 360static inline void tcg_out_blx(TCGContext *s, int cond, int rn)
361{
362 tcg_out32(s, (cond << 28) | 0x012fff30 | rn);
363}
364
811d4cf4
AZ		 365static inline void tcg_out_dat_reg(TCGContext *s,
366 int cond, int opc, int rd, int rn, int rm, int shift)
367{
368 tcg_out32(s, (cond << 28) | (0 << 25) | (opc << 21) | TO_CPSR(opc) |
369 (rn << 16) | (rd << 12) | shift | rm);
370}
371
372static inline void tcg_out_dat_reg2(TCGContext *s,
373 int cond, int opc0, int opc1, int rd0, int rd1,
374 int rn0, int rn1, int rm0, int rm1, int shift)
375{
0c9c3a9e
AZ		 376 if (rd0 == rn1 || rd0 == rm1) {
377 tcg_out32(s, (cond << 28) | (0 << 25) | (opc0 << 21) | (1 << 20) |
378 (rn0 << 16) | (8 << 12) | shift | rm0);
379 tcg_out32(s, (cond << 28) | (0 << 25) | (opc1 << 21) |
380 (rn1 << 16) | (rd1 << 12) | shift | rm1);
381 tcg_out_dat_reg(s, cond, ARITH_MOV,
382 rd0, 0, TCG_REG_R8, SHIFT_IMM_LSL(0));
383 } else {
384 tcg_out32(s, (cond << 28) | (0 << 25) | (opc0 << 21) | (1 << 20) |
385 (rn0 << 16) | (rd0 << 12) | shift | rm0);
386 tcg_out32(s, (cond << 28) | (0 << 25) | (opc1 << 21) |
387 (rn1 << 16) | (rd1 << 12) | shift | rm1);
388 }
811d4cf4
AZ		 389}
390
391static inline void tcg_out_dat_imm(TCGContext *s,
392 int cond, int opc, int rd, int rn, int im)
393{
3979144c 394 tcg_out32(s, (cond << 28) | (1 << 25) | (opc << 21) | TO_CPSR(opc) |
811d4cf4
AZ		 395 (rn << 16) | (rd << 12) | im);
396}
397
398static inline void tcg_out_movi32(TCGContext *s,
399 int cond, int rd, int32_t arg)
400{
401 int offset = (uint32_t) arg - ((uint32_t) s->code_ptr + 8);
402
403 /* TODO: This is very suboptimal, we can easily have a constant
404 * pool somewhere after all the instructions. */
405
406 if (arg < 0 && arg > -0x100)
407 return tcg_out_dat_imm(s, cond, ARITH_MVN, rd, 0, (~arg) & 0xff);
408
409 if (offset < 0x100 && offset > -0x100)
410 return offset >= 0 ?
411 tcg_out_dat_imm(s, cond, ARITH_ADD, rd, 15, offset) :
412 tcg_out_dat_imm(s, cond, ARITH_SUB, rd, 15, -offset);
413
ac34fb5c
AJ		 414 if (use_armv7_instructions) {
415 /* use movw/movt */
416 /* movw */
417 tcg_out32(s, (cond << 28) | 0x03000000 | (rd << 12)
418 | ((arg << 4) & 0x000f0000) | (arg & 0xfff));
419 if (arg & 0xffff0000)
420 /* movt */
421 tcg_out32(s, (cond << 28) | 0x03400000 | (rd << 12)
422 | ((arg >> 12) & 0x000f0000) | ((arg >> 16) & 0xfff));
423 } else {
424 tcg_out_dat_imm(s, cond, ARITH_MOV, rd, 0, arg & 0xff);
425 if (arg & 0x0000ff00)
426 tcg_out_dat_imm(s, cond, ARITH_ORR, rd, rd,
427 ((arg >> 8) & 0xff) | 0xc00);
428 if (arg & 0x00ff0000)
429 tcg_out_dat_imm(s, cond, ARITH_ORR, rd, rd,
430 ((arg >> 16) & 0xff) | 0x800);
431 if (arg & 0xff000000)
432 tcg_out_dat_imm(s, cond, ARITH_ORR, rd, rd,
433 ((arg >> 24) & 0xff) | 0x400);
434 }
811d4cf4
AZ		 435}
436
437static inline void tcg_out_mul32(TCGContext *s,
438 int cond, int rd, int rs, int rm)
439{
440 if (rd != rm)
441 tcg_out32(s, (cond << 28) | (rd << 16) | (0 << 12) |
442 (rs << 8) | 0x90 | rm);
443 else if (rd != rs)
444 tcg_out32(s, (cond << 28) | (rd << 16) | (0 << 12) |
445 (rm << 8) | 0x90 | rs);
446 else {
447 tcg_out32(s, (cond << 28) | ( 8 << 16) | (0 << 12) |
448 (rs << 8) | 0x90 | rm);
449 tcg_out_dat_reg(s, cond, ARITH_MOV,
c8d80cef 450 rd, 0, TCG_REG_R8, SHIFT_IMM_LSL(0));
811d4cf4
AZ		 451 }
452}
453
454static inline void tcg_out_umull32(TCGContext *s,
455 int cond, int rd0, int rd1, int rs, int rm)
456{
457 if (rd0 != rm && rd1 != rm)
458 tcg_out32(s, (cond << 28) | 0x800090 |
459 (rd1 << 16) | (rd0 << 12) | (rs << 8) | rm);
460 else if (rd0 != rs && rd1 != rs)
461 tcg_out32(s, (cond << 28) | 0x800090 |
462 (rd1 << 16) | (rd0 << 12) | (rm << 8) | rs);
463 else {
464 tcg_out_dat_reg(s, cond, ARITH_MOV,
465 TCG_REG_R8, 0, rm, SHIFT_IMM_LSL(0));
466 tcg_out32(s, (cond << 28) | 0x800098 |
467 (rd1 << 16) | (rd0 << 12) | (rs << 8));
468 }
469}
470
471static inline void tcg_out_smull32(TCGContext *s,
472 int cond, int rd0, int rd1, int rs, int rm)
473{
474 if (rd0 != rm && rd1 != rm)
475 tcg_out32(s, (cond << 28) | 0xc00090 |
476 (rd1 << 16) | (rd0 << 12) | (rs << 8) | rm);
477 else if (rd0 != rs && rd1 != rs)
478 tcg_out32(s, (cond << 28) | 0xc00090 |
479 (rd1 << 16) | (rd0 << 12) | (rm << 8) | rs);
480 else {
481 tcg_out_dat_reg(s, cond, ARITH_MOV,
482 TCG_REG_R8, 0, rm, SHIFT_IMM_LSL(0));
483 tcg_out32(s, (cond << 28) | 0xc00098 |
484 (rd1 << 16) | (rd0 << 12) | (rs << 8));
485 }
486}
487
9517094f
AJ		 488static inline void tcg_out_ext8s(TCGContext *s, int cond,
489 int rd, int rn)
490{
491 if (use_armv6_instructions) {
492 /* sxtb */
493 tcg_out32(s, 0x06af0070 | (cond << 28) | (rd << 12) | rn);
494 } else {
495 tcg_out_dat_reg(s, COND_AL, ARITH_MOV,
496 rd, 0, rn, SHIFT_IMM_LSL(24));
497 tcg_out_dat_reg(s, COND_AL, ARITH_MOV,
498 rd, 0, rd, SHIFT_IMM_ASR(24));
499 }
500}
501
502static inline void tcg_out_ext16s(TCGContext *s, int cond,
503 int rd, int rn)
504{
505 if (use_armv6_instructions) {
506 /* sxth */
507 tcg_out32(s, 0x06bf0070 | (cond << 28) | (rd << 12) | rn);
508 } else {
509 tcg_out_dat_reg(s, COND_AL, ARITH_MOV,
510 rd, 0, rn, SHIFT_IMM_LSL(16));
511 tcg_out_dat_reg(s, COND_AL, ARITH_MOV,
512 rd, 0, rd, SHIFT_IMM_ASR(16));
513 }
514}
515
516static inline void tcg_out_ext16u(TCGContext *s, int cond,
517 int rd, int rn)
518{
519 if (use_armv6_instructions) {
520 /* uxth */
521 tcg_out32(s, 0x06ff0070 | (cond << 28) | (rd << 12) | rn);
522 } else {
523 tcg_out_dat_reg(s, COND_AL, ARITH_MOV,
524 rd, 0, rn, SHIFT_IMM_LSL(16));
525 tcg_out_dat_reg(s, COND_AL, ARITH_MOV,
526 rd, 0, rd, SHIFT_IMM_LSR(16));
527 }
528}
529
244b1e81
AJ		 530static inline void tcg_out_bswap16(TCGContext *s, int cond, int rd, int rn)
531{
532 if (use_armv6_instructions) {
533 /* rev16 */
534 tcg_out32(s, 0x06bf0fb0 | (cond << 28) | (rd << 12) | rn);
535 } else {
536 tcg_out_dat_reg(s, cond, ARITH_MOV,
537 TCG_REG_R8, 0, rn, SHIFT_IMM_LSL(24));
538 tcg_out_dat_reg(s, cond, ARITH_MOV,
539 TCG_REG_R8, 0, TCG_REG_R8, SHIFT_IMM_LSR(16));
540 tcg_out_dat_reg(s, cond, ARITH_ORR,
541 rd, TCG_REG_R8, rn, SHIFT_IMM_LSR(8));
542 }
543}
544
545static inline void tcg_out_bswap32(TCGContext *s, int cond, int rd, int rn)
546{
547 if (use_armv6_instructions) {
548 /* rev */
549 tcg_out32(s, 0x06bf0f30 | (cond << 28) | (rd << 12) | rn);
550 } else {
551 tcg_out_dat_reg(s, cond, ARITH_EOR,
552 TCG_REG_R8, rn, rn, SHIFT_IMM_ROR(16));
553 tcg_out_dat_imm(s, cond, ARITH_BIC,
554 TCG_REG_R8, TCG_REG_R8, 0xff | 0x800);
555 tcg_out_dat_reg(s, cond, ARITH_MOV,
556 rd, 0, rn, SHIFT_IMM_ROR(8));
557 tcg_out_dat_reg(s, cond, ARITH_EOR,
558 rd, rd, TCG_REG_R8, SHIFT_IMM_LSR(8));
559 }
560}
561
811d4cf4
AZ		 562static inline void tcg_out_ld32_12(TCGContext *s, int cond,
563 int rd, int rn, tcg_target_long im)
564{
565 if (im >= 0)
566 tcg_out32(s, (cond << 28) | 0x05900000 |
567 (rn << 16) | (rd << 12) | (im & 0xfff));
568 else
569 tcg_out32(s, (cond << 28) | 0x05100000 |
570 (rn << 16) | (rd << 12) | ((-im) & 0xfff));
571}
572
573static inline void tcg_out_st32_12(TCGContext *s, int cond,
574 int rd, int rn, tcg_target_long im)
575{
576 if (im >= 0)
577 tcg_out32(s, (cond << 28) | 0x05800000 |
578 (rn << 16) | (rd << 12) | (im & 0xfff));
579 else
580 tcg_out32(s, (cond << 28) | 0x05000000 |
581 (rn << 16) | (rd << 12) | ((-im) & 0xfff));
582}
583
584static inline void tcg_out_ld32_r(TCGContext *s, int cond,
585 int rd, int rn, int rm)
586{
587 tcg_out32(s, (cond << 28) | 0x07900000 |
588 (rn << 16) | (rd << 12) | rm);
589}
590
591static inline void tcg_out_st32_r(TCGContext *s, int cond,
592 int rd, int rn, int rm)
593{
594 tcg_out32(s, (cond << 28) | 0x07800000 |
595 (rn << 16) | (rd << 12) | rm);
596}
597
3979144c
PB		 598/* Register pre-increment with base writeback. */
599static inline void tcg_out_ld32_rwb(TCGContext *s, int cond,
600 int rd, int rn, int rm)
601{
602 tcg_out32(s, (cond << 28) | 0x07b00000 |
603 (rn << 16) | (rd << 12) | rm);
604}
605
606static inline void tcg_out_st32_rwb(TCGContext *s, int cond,
607 int rd, int rn, int rm)
608{
609 tcg_out32(s, (cond << 28) | 0x07a00000 |
610 (rn << 16) | (rd << 12) | rm);
611}
612
811d4cf4
AZ		 613static inline void tcg_out_ld16u_8(TCGContext *s, int cond,
614 int rd, int rn, tcg_target_long im)
615{
616 if (im >= 0)
617 tcg_out32(s, (cond << 28) | 0x01d000b0 |
618 (rn << 16) | (rd << 12) |
619 ((im & 0xf0) << 4) | (im & 0xf));
620 else
621 tcg_out32(s, (cond << 28) | 0x015000b0 |
622 (rn << 16) | (rd << 12) |
623 (((-im) & 0xf0) << 4) | ((-im) & 0xf));
624}
625
f694a27e 626static inline void tcg_out_st16_8(TCGContext *s, int cond,
811d4cf4
AZ		 627 int rd, int rn, tcg_target_long im)
628{
629 if (im >= 0)
630 tcg_out32(s, (cond << 28) | 0x01c000b0 |
631 (rn << 16) | (rd << 12) |
632 ((im & 0xf0) << 4) | (im & 0xf));
633 else
634 tcg_out32(s, (cond << 28) | 0x014000b0 |
635 (rn << 16) | (rd << 12) |
636 (((-im) & 0xf0) << 4) | ((-im) & 0xf));
637}
638
639static inline void tcg_out_ld16u_r(TCGContext *s, int cond,
640 int rd, int rn, int rm)
641{
642 tcg_out32(s, (cond << 28) | 0x019000b0 |
643 (rn << 16) | (rd << 12) | rm);
644}
645
f694a27e 646static inline void tcg_out_st16_r(TCGContext *s, int cond,
811d4cf4
AZ		 647 int rd, int rn, int rm)
648{
649 tcg_out32(s, (cond << 28) | 0x018000b0 |
650 (rn << 16) | (rd << 12) | rm);
651}
652
653static inline void tcg_out_ld16s_8(TCGContext *s, int cond,
654 int rd, int rn, tcg_target_long im)
655{
656 if (im >= 0)
657 tcg_out32(s, (cond << 28) | 0x01d000f0 |
658 (rn << 16) | (rd << 12) |
659 ((im & 0xf0) << 4) | (im & 0xf));
660 else
661 tcg_out32(s, (cond << 28) | 0x015000f0 |
662 (rn << 16) | (rd << 12) |
663 (((-im) & 0xf0) << 4) | ((-im) & 0xf));
664}
665
811d4cf4
AZ		 666static inline void tcg_out_ld16s_r(TCGContext *s, int cond,
667 int rd, int rn, int rm)
668{
669 tcg_out32(s, (cond << 28) | 0x019000f0 |
670 (rn << 16) | (rd << 12) | rm);
671}
672
811d4cf4
AZ		 673static inline void tcg_out_ld8_12(TCGContext *s, int cond,
674 int rd, int rn, tcg_target_long im)
675{
676 if (im >= 0)
677 tcg_out32(s, (cond << 28) | 0x05d00000 |
678 (rn << 16) | (rd << 12) | (im & 0xfff));
679 else
680 tcg_out32(s, (cond << 28) | 0x05500000 |
681 (rn << 16) | (rd << 12) | ((-im) & 0xfff));
682}
683
684static inline void tcg_out_st8_12(TCGContext *s, int cond,
685 int rd, int rn, tcg_target_long im)
686{
687 if (im >= 0)
688 tcg_out32(s, (cond << 28) | 0x05c00000 |
689 (rn << 16) | (rd << 12) | (im & 0xfff));
690 else
691 tcg_out32(s, (cond << 28) | 0x05400000 |
692 (rn << 16) | (rd << 12) | ((-im) & 0xfff));
693}
694
695static inline void tcg_out_ld8_r(TCGContext *s, int cond,
696 int rd, int rn, int rm)
697{
698 tcg_out32(s, (cond << 28) | 0x07d00000 |
699 (rn << 16) | (rd << 12) | rm);
700}
701
702static inline void tcg_out_st8_r(TCGContext *s, int cond,
703 int rd, int rn, int rm)
704{
705 tcg_out32(s, (cond << 28) | 0x07c00000 |
706 (rn << 16) | (rd << 12) | rm);
707}
708
709static inline void tcg_out_ld8s_8(TCGContext *s, int cond,
710 int rd, int rn, tcg_target_long im)
711{
712 if (im >= 0)
713 tcg_out32(s, (cond << 28) | 0x01d000d0 |
714 (rn << 16) | (rd << 12) |
715 ((im & 0xf0) << 4) | (im & 0xf));
716 else
717 tcg_out32(s, (cond << 28) | 0x015000d0 |
718 (rn << 16) | (rd << 12) |
719 (((-im) & 0xf0) << 4) | ((-im) & 0xf));
720}
721
811d4cf4
AZ		 722static inline void tcg_out_ld8s_r(TCGContext *s, int cond,
723 int rd, int rn, int rm)
724{
204c1674 725 tcg_out32(s, (cond << 28) | 0x019000d0 |
811d4cf4
AZ		 726 (rn << 16) | (rd << 12) | rm);
727}
728
811d4cf4
AZ		 729static inline void tcg_out_ld32u(TCGContext *s, int cond,
730 int rd, int rn, int32_t offset)
731{
732 if (offset > 0xfff || offset < -0xfff) {
733 tcg_out_movi32(s, cond, TCG_REG_R8, offset);
734 tcg_out_ld32_r(s, cond, rd, rn, TCG_REG_R8);
735 } else
736 tcg_out_ld32_12(s, cond, rd, rn, offset);
737}
738
739static inline void tcg_out_st32(TCGContext *s, int cond,
740 int rd, int rn, int32_t offset)
741{
742 if (offset > 0xfff || offset < -0xfff) {
743 tcg_out_movi32(s, cond, TCG_REG_R8, offset);
744 tcg_out_st32_r(s, cond, rd, rn, TCG_REG_R8);
745 } else
746 tcg_out_st32_12(s, cond, rd, rn, offset);
747}
748
749static inline void tcg_out_ld16u(TCGContext *s, int cond,
750 int rd, int rn, int32_t offset)
751{
752 if (offset > 0xff || offset < -0xff) {
753 tcg_out_movi32(s, cond, TCG_REG_R8, offset);
754 tcg_out_ld16u_r(s, cond, rd, rn, TCG_REG_R8);
755 } else
756 tcg_out_ld16u_8(s, cond, rd, rn, offset);
757}
758
759static inline void tcg_out_ld16s(TCGContext *s, int cond,
760 int rd, int rn, int32_t offset)
761{
762 if (offset > 0xff || offset < -0xff) {
763 tcg_out_movi32(s, cond, TCG_REG_R8, offset);
764 tcg_out_ld16s_r(s, cond, rd, rn, TCG_REG_R8);
765 } else
766 tcg_out_ld16s_8(s, cond, rd, rn, offset);
767}
768
f694a27e 769static inline void tcg_out_st16(TCGContext *s, int cond,
811d4cf4
AZ		 770 int rd, int rn, int32_t offset)
771{
772 if (offset > 0xff || offset < -0xff) {
773 tcg_out_movi32(s, cond, TCG_REG_R8, offset);
f694a27e 774 tcg_out_st16_r(s, cond, rd, rn, TCG_REG_R8);
811d4cf4 775 } else
f694a27e 776 tcg_out_st16_8(s, cond, rd, rn, offset);
811d4cf4
AZ		 777}
778
779static inline void tcg_out_ld8u(TCGContext *s, int cond,
780 int rd, int rn, int32_t offset)
781{
782 if (offset > 0xfff || offset < -0xfff) {
783 tcg_out_movi32(s, cond, TCG_REG_R8, offset);
784 tcg_out_ld8_r(s, cond, rd, rn, TCG_REG_R8);
785 } else
786 tcg_out_ld8_12(s, cond, rd, rn, offset);
787}
788
789static inline void tcg_out_ld8s(TCGContext *s, int cond,
790 int rd, int rn, int32_t offset)
791{
792 if (offset > 0xff || offset < -0xff) {
793 tcg_out_movi32(s, cond, TCG_REG_R8, offset);
794 tcg_out_ld8s_r(s, cond, rd, rn, TCG_REG_R8);
795 } else
796 tcg_out_ld8s_8(s, cond, rd, rn, offset);
797}
798
f694a27e 799static inline void tcg_out_st8(TCGContext *s, int cond,
811d4cf4
AZ		 800 int rd, int rn, int32_t offset)
801{
802 if (offset > 0xfff || offset < -0xfff) {
803 tcg_out_movi32(s, cond, TCG_REG_R8, offset);
804 tcg_out_st8_r(s, cond, rd, rn, TCG_REG_R8);
805 } else
806 tcg_out_st8_12(s, cond, rd, rn, offset);
807}
808
809static inline void tcg_out_goto(TCGContext *s, int cond, uint32_t addr)
810{
811 int32_t val;
812
813 val = addr - (tcg_target_long) s->code_ptr;
814 if (val - 8 < 0x01fffffd && val - 8 > -0x01fffffd)
815 tcg_out_b(s, cond, val);
816 else {
817#if 1
818 tcg_abort();
819#else
820 if (cond == COND_AL) {
c8d80cef 821 tcg_out_ld32_12(s, COND_AL, TCG_REG_PC, TCG_REG_PC, -4);
811d4cf4
AZ		 822 tcg_out32(s, addr); /* XXX: This is l->u.value, can we use it? */
823 } else {
824 tcg_out_movi32(s, cond, TCG_REG_R8, val - 8);
825 tcg_out_dat_reg(s, cond, ARITH_ADD,
c8d80cef
AJ		 826 TCG_REG_PC, TCG_REG_PC,
827 TCG_REG_R8, SHIFT_IMM_LSL(0));
811d4cf4
AZ		 828 }
829#endif
830 }
831}
832
833static inline void tcg_out_call(TCGContext *s, int cond, uint32_t addr)
834{
835 int32_t val;
836
811d4cf4
AZ		 837 val = addr - (tcg_target_long) s->code_ptr;
838 if (val < 0x01fffffd && val > -0x01fffffd)
839 tcg_out_bl(s, cond, val);
840 else {
841#if 1
842 tcg_abort();
843#else
844 if (cond == COND_AL) {
c8d80cef
AJ		 845 tcg_out_dat_imm(s, cond, ARITH_ADD, TCG_REG_R14, TCG_REG_PC, 4);
846 tcg_out_ld32_12(s, COND_AL, TCG_REG_PC, TCG_REG_PC, -4);
811d4cf4
AZ		 847 tcg_out32(s, addr); /* XXX: This is l->u.value, can we use it? */
848 } else {
849 tcg_out_movi32(s, cond, TCG_REG_R9, addr);
c8d80cef
AJ		 850 tcg_out_dat_reg(s, cond, ARITH_MOV, TCG_REG_R14, 0,
851 TCG_REG_PC, SHIFT_IMM_LSL(0));
811d4cf4
AZ		 852 tcg_out_bx(s, cond, TCG_REG_R9);
853 }
854#endif
855 }
811d4cf4
AZ		 856}
857
858static inline void tcg_out_callr(TCGContext *s, int cond, int arg)
859{
23401b58
AJ		 860 if (use_armv5_instructions) {
861 tcg_out_blx(s, cond, arg);
862 } else {
863 tcg_out_dat_reg(s, cond, ARITH_MOV, TCG_REG_R14, 0,
864 TCG_REG_PC, SHIFT_IMM_LSL(0));
865 tcg_out_bx(s, cond, arg);
866 }
811d4cf4
AZ		 867}
868
869static inline void tcg_out_goto_label(TCGContext *s, int cond, int label_index)
870{
871 TCGLabel *l = &s->labels[label_index];
872
873 if (l->has_value)
874 tcg_out_goto(s, cond, l->u.value);
875 else if (cond == COND_AL) {
c8d80cef 876 tcg_out_ld32_12(s, COND_AL, TCG_REG_PC, TCG_REG_PC, -4);
811d4cf4
AZ		 877 tcg_out_reloc(s, s->code_ptr, R_ARM_ABS32, label_index, 31337);
878 s->code_ptr += 4;
879 } else {
880 /* Probably this should be preferred even for COND_AL... */
881 tcg_out_reloc(s, s->code_ptr, R_ARM_PC24, label_index, 31337);
e936243a 882 tcg_out_b_noaddr(s, cond);
811d4cf4
AZ		 883 }
884}
885
811d4cf4 886#ifdef CONFIG_SOFTMMU
79383c9c
BS		 887
888#include "../../softmmu_defs.h"
811d4cf4
AZ		 889
890static void *qemu_ld_helpers[4] = {
891 __ldb_mmu,
892 __ldw_mmu,
893 __ldl_mmu,
894 __ldq_mmu,
895};
896
897static void *qemu_st_helpers[4] = {
898 __stb_mmu,
899 __stw_mmu,
900 __stl_mmu,
901 __stq_mmu,
902};
903#endif
904
3979144c
PB		 905#define TLB_SHIFT (CPU_TLB_ENTRY_BITS + CPU_TLB_BITS)
906
7e0d9562 907static inline void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int opc)
811d4cf4
AZ		 908{
909 int addr_reg, data_reg, data_reg2;
910#ifdef CONFIG_SOFTMMU
911 int mem_index, s_bits;
912# if TARGET_LONG_BITS == 64
913 int addr_reg2;
914# endif
811d4cf4 915 uint32_t *label_ptr;
811d4cf4
AZ		 916#endif
917
918 data_reg = *args++;
919 if (opc == 3)
920 data_reg2 = *args++;
921 else
d89c682f 922 data_reg2 = 0; /* suppress warning */
811d4cf4 923 addr_reg = *args++;
811d4cf4 924#ifdef CONFIG_SOFTMMU
aef3a282
AZ		 925# if TARGET_LONG_BITS == 64
926 addr_reg2 = *args++;
927# endif
811d4cf4
AZ		 928 mem_index = *args;
929 s_bits = opc & 3;
930
91a3c1b0 931 /* Should generate something like the following:
3979144c 932 * shr r8, addr_reg, #TARGET_PAGE_BITS
91a3c1b0 933 * and r0, r8, #(CPU_TLB_SIZE - 1) @ Assumption: CPU_TLB_BITS <= 8
3979144c 934 * add r0, env, r0 lsl #CPU_TLB_ENTRY_BITS
91a3c1b0
AZ		 935 */
936# if CPU_TLB_BITS > 8
937# error
938# endif
c8d80cef
AJ		 939 tcg_out_dat_reg(s, COND_AL, ARITH_MOV, TCG_REG_R8,
940 0, addr_reg, SHIFT_IMM_LSR(TARGET_PAGE_BITS));
811d4cf4 941 tcg_out_dat_imm(s, COND_AL, ARITH_AND,
c8d80cef
AJ		 942 TCG_REG_R0, TCG_REG_R8, CPU_TLB_SIZE - 1);
943 tcg_out_dat_reg(s, COND_AL, ARITH_ADD, TCG_REG_R0, TCG_AREG0,
944 TCG_REG_R0, SHIFT_IMM_LSL(CPU_TLB_ENTRY_BITS));
91a3c1b0
AZ		 945 /* In the
946 * ldr r1 [r0, #(offsetof(CPUState, tlb_table[mem_index][0].addr_read))]
947 * below, the offset is likely to exceed 12 bits if mem_index != 0 and
948 * not exceed otherwise, so use an
949 * add r0, r0, #(mem_index * sizeof *CPUState.tlb_table)
950 * before.
951 */
225b4376 952 if (mem_index)
c8d80cef 953 tcg_out_dat_imm(s, COND_AL, ARITH_ADD, TCG_REG_R0, TCG_REG_R0,
225b4376
AZ		 954 (mem_index << (TLB_SHIFT & 1)) |
955 ((16 - (TLB_SHIFT >> 1)) << 8));
c8d80cef 956 tcg_out_ld32_12(s, COND_AL, TCG_REG_R1, TCG_REG_R0,
225b4376 957 offsetof(CPUState, tlb_table[0][0].addr_read));
c8d80cef
AJ		 958 tcg_out_dat_reg(s, COND_AL, ARITH_CMP, 0, TCG_REG_R1,
959 TCG_REG_R8, SHIFT_IMM_LSL(TARGET_PAGE_BITS));
3979144c
PB		 960 /* Check alignment. */
961 if (s_bits)
962 tcg_out_dat_imm(s, COND_EQ, ARITH_TST,
963 0, addr_reg, (1 << s_bits) - 1);
811d4cf4
AZ		 964# if TARGET_LONG_BITS == 64
965 /* XXX: possibly we could use a block data load or writeback in
966 * the first access. */
c8d80cef 967 tcg_out_ld32_12(s, COND_EQ, TCG_REG_R1, TCG_REG_R0,
225b4376 968 offsetof(CPUState, tlb_table[0][0].addr_read) + 4);
c8d80cef
AJ		 969 tcg_out_dat_reg(s, COND_EQ, ARITH_CMP, 0,
970 TCG_REG_R1, addr_reg2, SHIFT_IMM_LSL(0));
811d4cf4 971# endif
c8d80cef 972 tcg_out_ld32_12(s, COND_EQ, TCG_REG_R1, TCG_REG_R0,
225b4376 973 offsetof(CPUState, tlb_table[0][0].addend));
811d4cf4
AZ		 974
975 switch (opc) {
976 case 0:
c8d80cef 977 tcg_out_ld8_r(s, COND_EQ, data_reg, addr_reg, TCG_REG_R1);
811d4cf4
AZ		 978 break;
979 case 0 | 4:
c8d80cef 980 tcg_out_ld8s_r(s, COND_EQ, data_reg, addr_reg, TCG_REG_R1);
811d4cf4
AZ		 981 break;
982 case 1:
c8d80cef 983 tcg_out_ld16u_r(s, COND_EQ, data_reg, addr_reg, TCG_REG_R1);
811d4cf4
AZ		 984 break;
985 case 1 | 4:
c8d80cef 986 tcg_out_ld16s_r(s, COND_EQ, data_reg, addr_reg, TCG_REG_R1);
811d4cf4
AZ		 987 break;
988 case 2:
989 default:
c8d80cef 990 tcg_out_ld32_r(s, COND_EQ, data_reg, addr_reg, TCG_REG_R1);
811d4cf4
AZ		 991 break;
992 case 3:
c8d80cef
AJ		 993 tcg_out_ld32_rwb(s, COND_EQ, data_reg, TCG_REG_R1, addr_reg);
994 tcg_out_ld32_12(s, COND_EQ, data_reg2, TCG_REG_R1, 4);
811d4cf4
AZ		 995 break;
996 }
997
998 label_ptr = (void *) s->code_ptr;
999 tcg_out_b(s, COND_EQ, 8);
811d4cf4 1000
811d4cf4 1001 /* TODO: move this code to where the constants pool will be */
c8d80cef 1002 if (addr_reg != TCG_REG_R0) {
7e0d9562 1003 tcg_out_dat_reg(s, COND_AL, ARITH_MOV,
c8d80cef
AJ		 1004 TCG_REG_R0, 0, addr_reg, SHIFT_IMM_LSL(0));
1005 }
811d4cf4 1006# if TARGET_LONG_BITS == 32
7e0d9562 1007 tcg_out_dat_imm(s, COND_AL, ARITH_MOV, TCG_REG_R1, 0, mem_index);
811d4cf4 1008# else
c8d80cef 1009 if (addr_reg2 != TCG_REG_R1) {
7e0d9562 1010 tcg_out_dat_reg(s, COND_AL, ARITH_MOV,
c8d80cef
AJ		 1011 TCG_REG_R1, 0, addr_reg2, SHIFT_IMM_LSL(0));
1012 }
7e0d9562 1013 tcg_out_dat_imm(s, COND_AL, ARITH_MOV, TCG_REG_R2, 0, mem_index);
811d4cf4 1014# endif
7e0d9562 1015 tcg_out_bl(s, COND_AL, (tcg_target_long) qemu_ld_helpers[s_bits] -
811d4cf4
AZ		 1016 (tcg_target_long) s->code_ptr);
1017
1018 switch (opc) {
1019 case 0 | 4:
7e0d9562 1020 tcg_out_dat_reg(s, COND_AL, ARITH_MOV,
c8d80cef 1021 TCG_REG_R0, 0, TCG_REG_R0, SHIFT_IMM_LSL(24));
7e0d9562 1022 tcg_out_dat_reg(s, COND_AL, ARITH_MOV,
c8d80cef 1023 data_reg, 0, TCG_REG_R0, SHIFT_IMM_ASR(24));
811d4cf4
AZ		 1024 break;
1025 case 1 | 4:
7e0d9562 1026 tcg_out_dat_reg(s, COND_AL, ARITH_MOV,
c8d80cef 1027 TCG_REG_R0, 0, TCG_REG_R0, SHIFT_IMM_LSL(16));
7e0d9562 1028 tcg_out_dat_reg(s, COND_AL, ARITH_MOV,
c8d80cef 1029 data_reg, 0, TCG_REG_R0, SHIFT_IMM_ASR(16));
811d4cf4
AZ		 1030 break;
1031 case 0:
1032 case 1:
1033 case 2:
1034 default:
c8d80cef 1035 if (data_reg != TCG_REG_R0) {
7e0d9562 1036 tcg_out_dat_reg(s, COND_AL, ARITH_MOV,
c8d80cef
AJ		 1037 data_reg, 0, TCG_REG_R0, SHIFT_IMM_LSL(0));
1038 }
811d4cf4
AZ		 1039 break;
1040 case 3:
c8d80cef 1041 if (data_reg != TCG_REG_R0) {
7e0d9562 1042 tcg_out_dat_reg(s, COND_AL, ARITH_MOV,
c8d80cef
AJ		 1043 data_reg, 0, TCG_REG_R0, SHIFT_IMM_LSL(0));
1044 }
1045 if (data_reg2 != TCG_REG_R1) {
7e0d9562 1046 tcg_out_dat_reg(s, COND_AL, ARITH_MOV,
c8d80cef
AJ		 1047 data_reg2, 0, TCG_REG_R1, SHIFT_IMM_LSL(0));
1048 }
811d4cf4
AZ		 1049 break;
1050 }
1051
811d4cf4 1052 *label_ptr += ((void *) s->code_ptr - (void *) label_ptr - 8) >> 2;
379f6698
PB		 1053#else /* !CONFIG_SOFTMMU */
1054 if (GUEST_BASE) {
1055 uint32_t offset = GUEST_BASE;
1056 int i;
1057 int rot;
1058
1059 while (offset) {
1060 i = ctz32(offset) & ~1;
1061 rot = ((32 - i) << 7) & 0xf00;
1062
c8d80cef 1063 tcg_out_dat_imm(s, COND_AL, ARITH_ADD, TCG_REG_R8, addr_reg,
379f6698 1064 ((offset >> i) & 0xff) | rot);
c8d80cef 1065 addr_reg = TCG_REG_R8;
379f6698
PB		 1066 offset &= ~(0xff << i);
1067 }
1068 }
811d4cf4
AZ		 1069 switch (opc) {
1070 case 0:
1071 tcg_out_ld8_12(s, COND_AL, data_reg, addr_reg, 0);
1072 break;
1073 case 0 | 4:
1074 tcg_out_ld8s_8(s, COND_AL, data_reg, addr_reg, 0);
1075 break;
1076 case 1:
1077 tcg_out_ld16u_8(s, COND_AL, data_reg, addr_reg, 0);
1078 break;
1079 case 1 | 4:
1080 tcg_out_ld16s_8(s, COND_AL, data_reg, addr_reg, 0);
1081 break;
1082 case 2:
1083 default:
1084 tcg_out_ld32_12(s, COND_AL, data_reg, addr_reg, 0);
1085 break;
1086 case 3:
eae6ce52
AZ		 1087 /* TODO: use block load -
1088 * check that data_reg2 > data_reg or the other way */
419bafa5
AJ		 1089 if (data_reg == addr_reg) {
1090 tcg_out_ld32_12(s, COND_AL, data_reg2, addr_reg, 4);
1091 tcg_out_ld32_12(s, COND_AL, data_reg, addr_reg, 0);
1092 } else {
1093 tcg_out_ld32_12(s, COND_AL, data_reg, addr_reg, 0);
1094 tcg_out_ld32_12(s, COND_AL, data_reg2, addr_reg, 4);
1095 }
811d4cf4
AZ		 1096 break;
1097 }
1098#endif
1099}
1100
7e0d9562 1101static inline void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int opc)
811d4cf4
AZ		 1102{
1103 int addr_reg, data_reg, data_reg2;
1104#ifdef CONFIG_SOFTMMU
1105 int mem_index, s_bits;
1106# if TARGET_LONG_BITS == 64
1107 int addr_reg2;
1108# endif
811d4cf4 1109 uint32_t *label_ptr;
811d4cf4
AZ		 1110#endif
1111
1112 data_reg = *args++;
1113 if (opc == 3)
1114 data_reg2 = *args++;
1115 else
d89c682f 1116 data_reg2 = 0; /* suppress warning */
811d4cf4 1117 addr_reg = *args++;
811d4cf4 1118#ifdef CONFIG_SOFTMMU
aef3a282
AZ		 1119# if TARGET_LONG_BITS == 64
1120 addr_reg2 = *args++;
1121# endif
811d4cf4
AZ		 1122 mem_index = *args;
1123 s_bits = opc & 3;
1124
91a3c1b0 1125 /* Should generate something like the following:
3979144c 1126 * shr r8, addr_reg, #TARGET_PAGE_BITS
91a3c1b0 1127 * and r0, r8, #(CPU_TLB_SIZE - 1) @ Assumption: CPU_TLB_BITS <= 8
3979144c 1128 * add r0, env, r0 lsl #CPU_TLB_ENTRY_BITS
91a3c1b0 1129 */
811d4cf4 1130 tcg_out_dat_reg(s, COND_AL, ARITH_MOV,
c8d80cef 1131 TCG_REG_R8, 0, addr_reg, SHIFT_IMM_LSR(TARGET_PAGE_BITS));
811d4cf4 1132 tcg_out_dat_imm(s, COND_AL, ARITH_AND,
c8d80cef
AJ		 1133 TCG_REG_R0, TCG_REG_R8, CPU_TLB_SIZE - 1);
1134 tcg_out_dat_reg(s, COND_AL, ARITH_ADD, TCG_REG_R0,
1135 TCG_AREG0, TCG_REG_R0, SHIFT_IMM_LSL(CPU_TLB_ENTRY_BITS));
91a3c1b0
AZ		 1136 /* In the
1137 * ldr r1 [r0, #(offsetof(CPUState, tlb_table[mem_index][0].addr_write))]
1138 * below, the offset is likely to exceed 12 bits if mem_index != 0 and
1139 * not exceed otherwise, so use an
1140 * add r0, r0, #(mem_index * sizeof *CPUState.tlb_table)
1141 * before.
1142 */
225b4376 1143 if (mem_index)
c8d80cef 1144 tcg_out_dat_imm(s, COND_AL, ARITH_ADD, TCG_REG_R0, TCG_REG_R0,
225b4376
AZ		 1145 (mem_index << (TLB_SHIFT & 1)) |
1146 ((16 - (TLB_SHIFT >> 1)) << 8));
c8d80cef 1147 tcg_out_ld32_12(s, COND_AL, TCG_REG_R1, TCG_REG_R0,
225b4376 1148 offsetof(CPUState, tlb_table[0][0].addr_write));
c8d80cef
AJ		 1149 tcg_out_dat_reg(s, COND_AL, ARITH_CMP, 0, TCG_REG_R1,
1150 TCG_REG_R8, SHIFT_IMM_LSL(TARGET_PAGE_BITS));
3979144c
PB		 1151 /* Check alignment. */
1152 if (s_bits)
1153 tcg_out_dat_imm(s, COND_EQ, ARITH_TST,
1154 0, addr_reg, (1 << s_bits) - 1);
811d4cf4
AZ		 1155# if TARGET_LONG_BITS == 64
1156 /* XXX: possibly we could use a block data load or writeback in
1157 * the first access. */
c8d80cef
AJ		 1158 tcg_out_ld32_12(s, COND_EQ, TCG_REG_R1, TCG_REG_R0,
1159 offsetof(CPUState, tlb_table[0][0].addr_write) + 4);
1160 tcg_out_dat_reg(s, COND_EQ, ARITH_CMP, 0,
1161 TCG_REG_R1, addr_reg2, SHIFT_IMM_LSL(0));
811d4cf4 1162# endif
c8d80cef 1163 tcg_out_ld32_12(s, COND_EQ, TCG_REG_R1, TCG_REG_R0,
225b4376 1164 offsetof(CPUState, tlb_table[0][0].addend));
811d4cf4
AZ		 1165
1166 switch (opc) {
1167 case 0:
c8d80cef 1168 tcg_out_st8_r(s, COND_EQ, data_reg, addr_reg, TCG_REG_R1);
811d4cf4 1169 break;
811d4cf4 1170 case 1:
c8d80cef 1171 tcg_out_st16_r(s, COND_EQ, data_reg, addr_reg, TCG_REG_R1);
811d4cf4
AZ		 1172 break;
1173 case 2:
1174 default:
c8d80cef 1175 tcg_out_st32_r(s, COND_EQ, data_reg, addr_reg, TCG_REG_R1);
811d4cf4
AZ		 1176 break;
1177 case 3:
c8d80cef
AJ		 1178 tcg_out_st32_rwb(s, COND_EQ, data_reg, TCG_REG_R1, addr_reg);
1179 tcg_out_st32_12(s, COND_EQ, data_reg2, TCG_REG_R1, 4);
811d4cf4
AZ		 1180 break;
1181 }
1182
1183 label_ptr = (void *) s->code_ptr;
1184 tcg_out_b(s, COND_EQ, 8);
811d4cf4 1185
811d4cf4 1186 /* TODO: move this code to where the constants pool will be */
c8d80cef 1187 if (addr_reg != TCG_REG_R0) {
7e0d9562 1188 tcg_out_dat_reg(s, COND_AL, ARITH_MOV,
c8d80cef
AJ		 1189 TCG_REG_R0, 0, addr_reg, SHIFT_IMM_LSL(0));
1190 }
811d4cf4
AZ		 1191# if TARGET_LONG_BITS == 32
1192 switch (opc) {
1193 case 0:
7e0d9562
AJ		 1194 tcg_out_dat_imm(s, COND_AL, ARITH_AND, TCG_REG_R1, data_reg, 0xff);
1195 tcg_out_dat_imm(s, COND_AL, ARITH_MOV, TCG_REG_R2, 0, mem_index);
811d4cf4
AZ		 1196 break;
1197 case 1:
7e0d9562 1198 tcg_out_dat_reg(s, COND_AL, ARITH_MOV,
c8d80cef 1199 TCG_REG_R1, 0, data_reg, SHIFT_IMM_LSL(16));
7e0d9562 1200 tcg_out_dat_reg(s, COND_AL, ARITH_MOV,
c8d80cef 1201 TCG_REG_R1, 0, TCG_REG_R1, SHIFT_IMM_LSR(16));
7e0d9562 1202 tcg_out_dat_imm(s, COND_AL, ARITH_MOV, TCG_REG_R2, 0, mem_index);
811d4cf4
AZ		 1203 break;
1204 case 2:
c8d80cef 1205 if (data_reg != TCG_REG_R1) {
7e0d9562 1206 tcg_out_dat_reg(s, COND_AL, ARITH_MOV,
c8d80cef
AJ		 1207 TCG_REG_R1, 0, data_reg, SHIFT_IMM_LSL(0));
1208 }
7e0d9562 1209 tcg_out_dat_imm(s, COND_AL, ARITH_MOV, TCG_REG_R2, 0, mem_index);
811d4cf4
AZ		 1210 break;
1211 case 3:
c8d80cef 1212 if (data_reg != TCG_REG_R1) {
7e0d9562 1213 tcg_out_dat_reg(s, COND_AL, ARITH_MOV,
c8d80cef
AJ		 1214 TCG_REG_R1, 0, data_reg, SHIFT_IMM_LSL(0));
1215 }
1216 if (data_reg2 != TCG_REG_R2) {
7e0d9562 1217 tcg_out_dat_reg(s, COND_AL, ARITH_MOV,
c8d80cef
AJ		 1218 TCG_REG_R2, 0, data_reg2, SHIFT_IMM_LSL(0));
1219 }
7e0d9562 1220 tcg_out_dat_imm(s, COND_AL, ARITH_MOV, TCG_REG_R3, 0, mem_index);
811d4cf4
AZ		 1221 break;
1222 }
1223# else
c8d80cef 1224 if (addr_reg2 != TCG_REG_R1) {
7e0d9562 1225 tcg_out_dat_reg(s, COND_AL, ARITH_MOV,
c8d80cef
AJ		 1226 TCG_REG_R1, 0, addr_reg2, SHIFT_IMM_LSL(0));
1227 }
811d4cf4
AZ		 1228 switch (opc) {
1229 case 0:
7e0d9562
AJ		 1230 tcg_out_dat_imm(s, COND_AL, ARITH_AND, TCG_REG_R2, data_reg, 0xff);
1231 tcg_out_dat_imm(s, COND_AL, ARITH_MOV, TCG_REG_R3, 0, mem_index);
811d4cf4
AZ		 1232 break;
1233 case 1:
7e0d9562 1234 tcg_out_dat_reg(s, COND_AL, ARITH_MOV,
c8d80cef 1235 TCG_REG_R2, 0, data_reg, SHIFT_IMM_LSL(16));
7e0d9562 1236 tcg_out_dat_reg(s, COND_AL, ARITH_MOV,
c8d80cef 1237 TCG_REG_R2, 0, TCG_REG_R2, SHIFT_IMM_LSR(16));
7e0d9562 1238 tcg_out_dat_imm(s, COND_AL, ARITH_MOV, TCG_REG_R3, 0, mem_index);
811d4cf4
AZ		 1239 break;
1240 case 2:
c8d80cef 1241 if (data_reg != TCG_REG_R2) {
7e0d9562 1242 tcg_out_dat_reg(s, COND_AL, ARITH_MOV,
c8d80cef
AJ		 1243 TCG_REG_R2, 0, data_reg, SHIFT_IMM_LSL(0));
1244 }
7e0d9562 1245 tcg_out_dat_imm(s, COND_AL, ARITH_MOV, TCG_REG_R3, 0, mem_index);
811d4cf4
AZ		 1246 break;
1247 case 3:
7e0d9562
AJ		 1248 tcg_out_dat_imm(s, COND_AL, ARITH_MOV, TCG_REG_R8, 0, mem_index);
1249 tcg_out32(s, (COND_AL << 28) | 0x052d8010); /* str r8, [sp, #-0x10]! */
c8d80cef 1250 if (data_reg != TCG_REG_R2) {
7e0d9562 1251 tcg_out_dat_reg(s, COND_AL, ARITH_MOV,
c8d80cef
AJ		 1252 TCG_REG_R2, 0, data_reg, SHIFT_IMM_LSL(0));
1253 }
1254 if (data_reg2 != TCG_REG_R3) {
7e0d9562 1255 tcg_out_dat_reg(s, COND_AL, ARITH_MOV,
c8d80cef
AJ		 1256 TCG_REG_R3, 0, data_reg2, SHIFT_IMM_LSL(0));
1257 }
811d4cf4
AZ		 1258 break;
1259 }
1260# endif
1261
7e0d9562 1262 tcg_out_bl(s, COND_AL, (tcg_target_long) qemu_st_helpers[s_bits] -
811d4cf4 1263 (tcg_target_long) s->code_ptr);
811d4cf4
AZ		 1264# if TARGET_LONG_BITS == 64
1265 if (opc == 3)
7e0d9562 1266 tcg_out_dat_imm(s, COND_AL, ARITH_ADD, TCG_REG_R13, TCG_REG_R13, 0x10);
811d4cf4
AZ		 1267# endif
1268
811d4cf4 1269 *label_ptr += ((void *) s->code_ptr - (void *) label_ptr - 8) >> 2;
379f6698
PB		 1270#else /* !CONFIG_SOFTMMU */
1271 if (GUEST_BASE) {
1272 uint32_t offset = GUEST_BASE;
1273 int i;
1274 int rot;
1275
1276 while (offset) {
1277 i = ctz32(offset) & ~1;
1278 rot = ((32 - i) << 7) & 0xf00;
1279
c8d80cef 1280 tcg_out_dat_imm(s, COND_AL, ARITH_ADD, TCG_REG_R8, addr_reg,
379f6698 1281 ((offset >> i) & 0xff) | rot);
c8d80cef 1282 addr_reg = TCG_REG_R8;
379f6698
PB		 1283 offset &= ~(0xff << i);
1284 }
1285 }
811d4cf4
AZ		 1286 switch (opc) {
1287 case 0:
1288 tcg_out_st8_12(s, COND_AL, data_reg, addr_reg, 0);
1289 break;
811d4cf4 1290 case 1:
f694a27e 1291 tcg_out_st16_8(s, COND_AL, data_reg, addr_reg, 0);
811d4cf4
AZ		 1292 break;
1293 case 2:
1294 default:
1295 tcg_out_st32_12(s, COND_AL, data_reg, addr_reg, 0);
1296 break;
1297 case 3:
eae6ce52
AZ		 1298 /* TODO: use block store -
1299 * check that data_reg2 > data_reg or the other way */
811d4cf4
AZ		 1300 tcg_out_st32_12(s, COND_AL, data_reg, addr_reg, 0);
1301 tcg_out_st32_12(s, COND_AL, data_reg2, addr_reg, 4);
1302 break;
1303 }
1304#endif
1305}
1306
811d4cf4
AZ		 1307static uint8_t *tb_ret_addr;
1308
a9751609 1309static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
811d4cf4
AZ		 1310 const TCGArg *args, const int *const_args)
1311{
1312 int c;
1313
1314 switch (opc) {
1315 case INDEX_op_exit_tb:
fe33867b
AZ		 1316 {
1317 uint8_t *ld_ptr = s->code_ptr;
1318 if (args[0] >> 8)
c8d80cef 1319 tcg_out_ld32_12(s, COND_AL, TCG_REG_R0, TCG_REG_PC, 0);
fe33867b 1320 else
c8d80cef 1321 tcg_out_dat_imm(s, COND_AL, ARITH_MOV, TCG_REG_R0, 0, args[0]);
fe33867b
AZ		 1322 tcg_out_goto(s, COND_AL, (tcg_target_ulong) tb_ret_addr);
1323 if (args[0] >> 8) {
1324 *ld_ptr = (uint8_t) (s->code_ptr - ld_ptr) - 8;
1325 tcg_out32(s, args[0]);
1326 }
1327 }
811d4cf4
AZ		 1328 break;
1329 case INDEX_op_goto_tb:
1330 if (s->tb_jmp_offset) {
1331 /* Direct jump method */
fe33867b 1332#if defined(USE_DIRECT_JUMP)
811d4cf4
AZ		 1333 s->tb_jmp_offset[args[0]] = s->code_ptr - s->code_buf;
1334 tcg_out_b(s, COND_AL, 8);
1335#else
c8d80cef 1336 tcg_out_ld32_12(s, COND_AL, TCG_REG_PC, TCG_REG_PC, -4);
811d4cf4
AZ		 1337 s->tb_jmp_offset[args[0]] = s->code_ptr - s->code_buf;
1338 tcg_out32(s, 0);
1339#endif
1340 } else {
1341 /* Indirect jump method */
1342#if 1
1343 c = (int) (s->tb_next + args[0]) - ((int) s->code_ptr + 8);
1344 if (c > 0xfff || c < -0xfff) {
1345 tcg_out_movi32(s, COND_AL, TCG_REG_R0,
1346 (tcg_target_long) (s->tb_next + args[0]));
c8d80cef 1347 tcg_out_ld32_12(s, COND_AL, TCG_REG_PC, TCG_REG_R0, 0);
811d4cf4 1348 } else
c8d80cef 1349 tcg_out_ld32_12(s, COND_AL, TCG_REG_PC, TCG_REG_PC, c);
811d4cf4 1350#else
c8d80cef
AJ		 1351 tcg_out_ld32_12(s, COND_AL, TCG_REG_R0, TCG_REG_PC, 0);
1352 tcg_out_ld32_12(s, COND_AL, TCG_REG_PC, TCG_REG_R0, 0);
811d4cf4
AZ		 1353 tcg_out32(s, (tcg_target_long) (s->tb_next + args[0]));
1354#endif
1355 }
1356 s->tb_next_offset[args[0]] = s->code_ptr - s->code_buf;
1357 break;
1358 case INDEX_op_call:
1359 if (const_args[0])
1360 tcg_out_call(s, COND_AL, args[0]);
1361 else
1362 tcg_out_callr(s, COND_AL, args[0]);
1363 break;
1364 case INDEX_op_jmp:
1365 if (const_args[0])
1366 tcg_out_goto(s, COND_AL, args[0]);
1367 else
1368 tcg_out_bx(s, COND_AL, args[0]);
1369 break;
1370 case INDEX_op_br:
1371 tcg_out_goto_label(s, COND_AL, args[0]);
1372 break;
1373
1374 case INDEX_op_ld8u_i32:
1375 tcg_out_ld8u(s, COND_AL, args[0], args[1], args[2]);
1376 break;
1377 case INDEX_op_ld8s_i32:
1378 tcg_out_ld8s(s, COND_AL, args[0], args[1], args[2]);
1379 break;
1380 case INDEX_op_ld16u_i32:
1381 tcg_out_ld16u(s, COND_AL, args[0], args[1], args[2]);
1382 break;
1383 case INDEX_op_ld16s_i32:
1384 tcg_out_ld16s(s, COND_AL, args[0], args[1], args[2]);
1385 break;
1386 case INDEX_op_ld_i32:
1387 tcg_out_ld32u(s, COND_AL, args[0], args[1], args[2]);
1388 break;
1389 case INDEX_op_st8_i32:
f694a27e 1390 tcg_out_st8(s, COND_AL, args[0], args[1], args[2]);
811d4cf4
AZ		 1391 break;
1392 case INDEX_op_st16_i32:
f694a27e 1393 tcg_out_st16(s, COND_AL, args[0], args[1], args[2]);
811d4cf4
AZ		 1394 break;
1395 case INDEX_op_st_i32:
1396 tcg_out_st32(s, COND_AL, args[0], args[1], args[2]);
1397 break;
1398
1399 case INDEX_op_mov_i32:
1400 tcg_out_dat_reg(s, COND_AL, ARITH_MOV,
1401 args[0], 0, args[1], SHIFT_IMM_LSL(0));
1402 break;
1403 case INDEX_op_movi_i32:
1404 tcg_out_movi32(s, COND_AL, args[0], args[1]);
1405 break;
1406 case INDEX_op_add_i32:
1407 c = ARITH_ADD;
1408 goto gen_arith;
1409 case INDEX_op_sub_i32:
1410 c = ARITH_SUB;
1411 goto gen_arith;
1412 case INDEX_op_and_i32:
1413 c = ARITH_AND;
1414 goto gen_arith;
932234f6
AJ		 1415 case INDEX_op_andc_i32:
1416 c = ARITH_BIC;
1417 goto gen_arith;
811d4cf4
AZ		 1418 case INDEX_op_or_i32:
1419 c = ARITH_ORR;
1420 goto gen_arith;
1421 case INDEX_op_xor_i32:
1422 c = ARITH_EOR;
1423 /* Fall through. */
1424 gen_arith:
94953e6d
LD		 1425 if (const_args[2]) {
1426 int rot;
1427 rot = encode_imm(args[2]);
cb4e581f 1428 tcg_out_dat_imm(s, COND_AL, c,
94953e6d
LD		 1429 args[0], args[1], rotl(args[2], rot) | (rot << 7));
1430 } else
cb4e581f
LD		 1431 tcg_out_dat_reg(s, COND_AL, c,
1432 args[0], args[1], args[2], SHIFT_IMM_LSL(0));
811d4cf4
AZ		 1433 break;
1434 case INDEX_op_add2_i32:
1435 tcg_out_dat_reg2(s, COND_AL, ARITH_ADD, ARITH_ADC,
1436 args[0], args[1], args[2], args[3],
1437 args[4], args[5], SHIFT_IMM_LSL(0));
1438 break;
1439 case INDEX_op_sub2_i32:
1440 tcg_out_dat_reg2(s, COND_AL, ARITH_SUB, ARITH_SBC,
1441 args[0], args[1], args[2], args[3],
1442 args[4], args[5], SHIFT_IMM_LSL(0));
1443 break;
650bbb36
AZ		 1444 case INDEX_op_neg_i32:
1445 tcg_out_dat_imm(s, COND_AL, ARITH_RSB, args[0], args[1], 0);
1446 break;
f878d2d2
LD		 1447 case INDEX_op_not_i32:
1448 tcg_out_dat_reg(s, COND_AL,
1449 ARITH_MVN, args[0], 0, args[1], SHIFT_IMM_LSL(0));
1450 break;
811d4cf4
AZ		 1451 case INDEX_op_mul_i32:
1452 tcg_out_mul32(s, COND_AL, args[0], args[1], args[2]);
1453 break;
1454 case INDEX_op_mulu2_i32:
1455 tcg_out_umull32(s, COND_AL, args[0], args[1], args[2], args[3]);
1456 break;
811d4cf4
AZ		 1457 /* XXX: Perhaps args[2] & 0x1f is wrong */
1458 case INDEX_op_shl_i32:
1459 c = const_args[2] ?
1460 SHIFT_IMM_LSL(args[2] & 0x1f) : SHIFT_REG_LSL(args[2]);
1461 goto gen_shift32;
1462 case INDEX_op_shr_i32:
1463 c = const_args[2] ? (args[2] & 0x1f) ? SHIFT_IMM_LSR(args[2] & 0x1f) :
1464 SHIFT_IMM_LSL(0) : SHIFT_REG_LSR(args[2]);
1465 goto gen_shift32;
1466 case INDEX_op_sar_i32:
1467 c = const_args[2] ? (args[2] & 0x1f) ? SHIFT_IMM_ASR(args[2] & 0x1f) :
1468 SHIFT_IMM_LSL(0) : SHIFT_REG_ASR(args[2]);
293579e5
AJ		 1469 goto gen_shift32;
1470 case INDEX_op_rotr_i32:
1471 c = const_args[2] ? (args[2] & 0x1f) ? SHIFT_IMM_ROR(args[2] & 0x1f) :
1472 SHIFT_IMM_LSL(0) : SHIFT_REG_ROR(args[2]);
811d4cf4
AZ		 1473 /* Fall through. */
1474 gen_shift32:
1475 tcg_out_dat_reg(s, COND_AL, ARITH_MOV, args[0], 0, args[1], c);
1476 break;
1477
293579e5
AJ		 1478 case INDEX_op_rotl_i32:
1479 if (const_args[2]) {
1480 tcg_out_dat_reg(s, COND_AL, ARITH_MOV, args[0], 0, args[1],
1481 ((0x20 - args[2]) & 0x1f) ?
1482 SHIFT_IMM_ROR((0x20 - args[2]) & 0x1f) :
1483 SHIFT_IMM_LSL(0));
1484 } else {
1485 tcg_out_dat_imm(s, COND_AL, ARITH_RSB, TCG_REG_R8, args[1], 0x20);
1486 tcg_out_dat_reg(s, COND_AL, ARITH_MOV, args[0], 0, args[1],
1487 SHIFT_REG_ROR(TCG_REG_R8));
1488 }
1489 break;
1490
811d4cf4 1491 case INDEX_op_brcond_i32:
023e77f8
AJ		 1492 if (const_args[1]) {
1493 int rot;
1494 rot = encode_imm(args[1]);
c8d80cef
AJ		 1495 tcg_out_dat_imm(s, COND_AL, ARITH_CMP, 0,
1496 args[0], rotl(args[1], rot) | (rot << 7));
023e77f8
AJ		 1497 } else {
1498 tcg_out_dat_reg(s, COND_AL, ARITH_CMP, 0,
1499 args[0], args[1], SHIFT_IMM_LSL(0));
1500 }
811d4cf4
AZ		 1501 tcg_out_goto_label(s, tcg_cond_to_arm_cond[args[2]], args[3]);
1502 break;
1503 case INDEX_op_brcond2_i32:
1504 /* The resulting conditions are:
1505 * TCG_COND_EQ --> a0 == a2 && a1 == a3,
1506 * TCG_COND_NE --> (a0 != a2 && a1 == a3) || a1 != a3,
1507 * TCG_COND_LT(U) --> (a0 < a2 && a1 == a3) || a1 < a3,
1508 * TCG_COND_GE(U) --> (a0 >= a2 && a1 == a3) || (a1 >= a3 && a1 != a3),
1509 * TCG_COND_LE(U) --> (a0 <= a2 && a1 == a3) || (a1 <= a3 && a1 != a3),
1510 * TCG_COND_GT(U) --> (a0 > a2 && a1 == a3) || a1 > a3,
1511 */
1512 tcg_out_dat_reg(s, COND_AL, ARITH_CMP, 0,
1513 args[1], args[3], SHIFT_IMM_LSL(0));
1514 tcg_out_dat_reg(s, COND_EQ, ARITH_CMP, 0,
1515 args[0], args[2], SHIFT_IMM_LSL(0));
1516 tcg_out_goto_label(s, tcg_cond_to_arm_cond[args[4]], args[5]);
1517 break;
f72a6cd7 1518 case INDEX_op_setcond_i32:
023e77f8
AJ		 1519 if (const_args[2]) {
1520 int rot;
1521 rot = encode_imm(args[2]);
c8d80cef
AJ		 1522 tcg_out_dat_imm(s, COND_AL, ARITH_CMP, 0,
1523 args[1], rotl(args[2], rot) | (rot << 7));
023e77f8
AJ		 1524 } else {
1525 tcg_out_dat_reg(s, COND_AL, ARITH_CMP, 0,
1526 args[1], args[2], SHIFT_IMM_LSL(0));
1527 }
f72a6cd7
AJ		 1528 tcg_out_dat_imm(s, tcg_cond_to_arm_cond[args[3]],
1529 ARITH_MOV, args[0], 0, 1);
1530 tcg_out_dat_imm(s, tcg_cond_to_arm_cond[tcg_invert_cond(args[3])],
1531 ARITH_MOV, args[0], 0, 0);
1532 break;
e0404769
AJ		 1533 case INDEX_op_setcond2_i32:
1534 /* See brcond2_i32 comment */
1535 tcg_out_dat_reg(s, COND_AL, ARITH_CMP, 0,
1536 args[2], args[4], SHIFT_IMM_LSL(0));
1537 tcg_out_dat_reg(s, COND_EQ, ARITH_CMP, 0,
1538 args[1], args[3], SHIFT_IMM_LSL(0));
1539 tcg_out_dat_imm(s, tcg_cond_to_arm_cond[args[5]],
1540 ARITH_MOV, args[0], 0, 1);
1541 tcg_out_dat_imm(s, tcg_cond_to_arm_cond[tcg_invert_cond(args[5])],
1542 ARITH_MOV, args[0], 0, 0);
b525f0a9 1543 break;
811d4cf4
AZ		 1544
1545 case INDEX_op_qemu_ld8u:
7e0d9562 1546 tcg_out_qemu_ld(s, args, 0);
811d4cf4
AZ		 1547 break;
1548 case INDEX_op_qemu_ld8s:
7e0d9562 1549 tcg_out_qemu_ld(s, args, 0 | 4);
811d4cf4
AZ		 1550 break;
1551 case INDEX_op_qemu_ld16u:
7e0d9562 1552 tcg_out_qemu_ld(s, args, 1);
811d4cf4
AZ		 1553 break;
1554 case INDEX_op_qemu_ld16s:
7e0d9562 1555 tcg_out_qemu_ld(s, args, 1 | 4);
811d4cf4 1556 break;
86feb1c8 1557 case INDEX_op_qemu_ld32:
7e0d9562 1558 tcg_out_qemu_ld(s, args, 2);
811d4cf4
AZ		 1559 break;
1560 case INDEX_op_qemu_ld64:
7e0d9562 1561 tcg_out_qemu_ld(s, args, 3);
811d4cf4 1562 break;
650bbb36 1563
811d4cf4 1564 case INDEX_op_qemu_st8:
7e0d9562 1565 tcg_out_qemu_st(s, args, 0);
811d4cf4
AZ		 1566 break;
1567 case INDEX_op_qemu_st16:
7e0d9562 1568 tcg_out_qemu_st(s, args, 1);
811d4cf4
AZ		 1569 break;
1570 case INDEX_op_qemu_st32:
7e0d9562 1571 tcg_out_qemu_st(s, args, 2);
811d4cf4
AZ		 1572 break;
1573 case INDEX_op_qemu_st64:
7e0d9562 1574 tcg_out_qemu_st(s, args, 3);
811d4cf4
AZ		 1575 break;
1576
244b1e81
AJ		 1577 case INDEX_op_bswap16_i32:
1578 tcg_out_bswap16(s, COND_AL, args[0], args[1]);
1579 break;
1580 case INDEX_op_bswap32_i32:
1581 tcg_out_bswap32(s, COND_AL, args[0], args[1]);
1582 break;
1583
811d4cf4 1584 case INDEX_op_ext8s_i32:
9517094f 1585 tcg_out_ext8s(s, COND_AL, args[0], args[1]);
811d4cf4
AZ		 1586 break;
1587 case INDEX_op_ext16s_i32:
9517094f
AJ		 1588 tcg_out_ext16s(s, COND_AL, args[0], args[1]);
1589 break;
1590 case INDEX_op_ext16u_i32:
1591 tcg_out_ext16u(s, COND_AL, args[0], args[1]);
811d4cf4
AZ		 1592 break;
1593
1594 default:
1595 tcg_abort();
1596 }
1597}
1598
1599static const TCGTargetOpDef arm_op_defs[] = {
1600 { INDEX_op_exit_tb, { } },
1601 { INDEX_op_goto_tb, { } },
1602 { INDEX_op_call, { "ri" } },
1603 { INDEX_op_jmp, { "ri" } },
1604 { INDEX_op_br, { } },
1605
1606 { INDEX_op_mov_i32, { "r", "r" } },
1607 { INDEX_op_movi_i32, { "r" } },
1608
1609 { INDEX_op_ld8u_i32, { "r", "r" } },
1610 { INDEX_op_ld8s_i32, { "r", "r" } },
1611 { INDEX_op_ld16u_i32, { "r", "r" } },
1612 { INDEX_op_ld16s_i32, { "r", "r" } },
1613 { INDEX_op_ld_i32, { "r", "r" } },
1614 { INDEX_op_st8_i32, { "r", "r" } },
1615 { INDEX_op_st16_i32, { "r", "r" } },
1616 { INDEX_op_st_i32, { "r", "r" } },
1617
1618 /* TODO: "r", "r", "ri" */
cb4e581f
LD		 1619 { INDEX_op_add_i32, { "r", "r", "rI" } },
1620 { INDEX_op_sub_i32, { "r", "r", "rI" } },
811d4cf4
AZ		 1621 { INDEX_op_mul_i32, { "r", "r", "r" } },
1622 { INDEX_op_mulu2_i32, { "r", "r", "r", "r" } },
cb4e581f 1623 { INDEX_op_and_i32, { "r", "r", "rI" } },
932234f6 1624 { INDEX_op_andc_i32, { "r", "r", "rI" } },
cb4e581f
LD		 1625 { INDEX_op_or_i32, { "r", "r", "rI" } },
1626 { INDEX_op_xor_i32, { "r", "r", "rI" } },
650bbb36 1627 { INDEX_op_neg_i32, { "r", "r" } },
f878d2d2 1628 { INDEX_op_not_i32, { "r", "r" } },
811d4cf4
AZ		 1629
1630 { INDEX_op_shl_i32, { "r", "r", "ri" } },
1631 { INDEX_op_shr_i32, { "r", "r", "ri" } },
1632 { INDEX_op_sar_i32, { "r", "r", "ri" } },
293579e5
AJ		 1633 { INDEX_op_rotl_i32, { "r", "r", "ri" } },
1634 { INDEX_op_rotr_i32, { "r", "r", "ri" } },
811d4cf4 1635
023e77f8
AJ		 1636 { INDEX_op_brcond_i32, { "r", "rI" } },
1637 { INDEX_op_setcond_i32, { "r", "r", "rI" } },
811d4cf4
AZ		 1638
1639 /* TODO: "r", "r", "r", "r", "ri", "ri" */
1640 { INDEX_op_add2_i32, { "r", "r", "r", "r", "r", "r" } },
1641 { INDEX_op_sub2_i32, { "r", "r", "r", "r", "r", "r" } },
1642 { INDEX_op_brcond2_i32, { "r", "r", "r", "r" } },
e0404769 1643 { INDEX_op_setcond2_i32, { "r", "r", "r", "r", "r" } },
811d4cf4 1644
26c5d372
AJ		 1645#if TARGET_LONG_BITS == 32
1646 { INDEX_op_qemu_ld8u, { "r", "x" } },
1647 { INDEX_op_qemu_ld8s, { "r", "x" } },
1648 { INDEX_op_qemu_ld16u, { "r", "x" } },
1649 { INDEX_op_qemu_ld16s, { "r", "x" } },
1584c845 1650 { INDEX_op_qemu_ld32, { "r", "x" } },
26c5d372
AJ		 1651 { INDEX_op_qemu_ld64, { "d", "r", "x" } },
1652
1653 { INDEX_op_qemu_st8, { "x", "x" } },
1654 { INDEX_op_qemu_st16, { "x", "x" } },
1655 { INDEX_op_qemu_st32, { "x", "x" } },
1656 { INDEX_op_qemu_st64, { "x", "D", "x" } },
1657#else
811d4cf4
AZ		 1658 { INDEX_op_qemu_ld8u, { "r", "x", "X" } },
1659 { INDEX_op_qemu_ld8s, { "r", "x", "X" } },
1660 { INDEX_op_qemu_ld16u, { "r", "x", "X" } },
1661 { INDEX_op_qemu_ld16s, { "r", "x", "X" } },
86feb1c8 1662 { INDEX_op_qemu_ld32, { "r", "x", "X" } },
d0660ed4 1663 { INDEX_op_qemu_ld64, { "d", "r", "x", "X" } },
811d4cf4 1664
3979144c
PB		 1665 { INDEX_op_qemu_st8, { "x", "x", "X" } },
1666 { INDEX_op_qemu_st16, { "x", "x", "X" } },
1667 { INDEX_op_qemu_st32, { "x", "x", "X" } },
1668 { INDEX_op_qemu_st64, { "x", "D", "x", "X" } },
26c5d372 1669#endif
811d4cf4 1670
244b1e81
AJ		 1671 { INDEX_op_bswap16_i32, { "r", "r" } },
1672 { INDEX_op_bswap32_i32, { "r", "r" } },
1673
811d4cf4
AZ		 1674 { INDEX_op_ext8s_i32, { "r", "r" } },
1675 { INDEX_op_ext16s_i32, { "r", "r" } },
9517094f 1676 { INDEX_op_ext16u_i32, { "r", "r" } },
811d4cf4
AZ		 1677
1678 { -1 },
1679};
1680
1681void tcg_target_init(TCGContext *s)
1682{
20cb400d 1683#if !defined(CONFIG_USER_ONLY)
811d4cf4
AZ		 1684 /* fail safe */
1685 if ((1 << CPU_TLB_ENTRY_BITS) != sizeof(CPUTLBEntry))
1686 tcg_abort();
20cb400d 1687#endif
811d4cf4 1688
e4a7d5e8 1689 tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0, 0xffff);
811d4cf4 1690 tcg_regset_set32(tcg_target_call_clobber_regs, 0,
e4a7d5e8
AJ		 1691 (1 << TCG_REG_R0) |
1692 (1 << TCG_REG_R1) |
1693 (1 << TCG_REG_R2) |
1694 (1 << TCG_REG_R3) |
1695 (1 << TCG_REG_R12) |
1696 (1 << TCG_REG_R14));
811d4cf4
AZ		 1697
1698 tcg_regset_clear(s->reserved_regs);
811d4cf4
AZ		 1699 tcg_regset_set_reg(s->reserved_regs, TCG_REG_CALL_STACK);
1700 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R8);
e4a7d5e8 1701 tcg_regset_set_reg(s->reserved_regs, TCG_REG_PC);
811d4cf4
AZ		 1702
1703 tcg_add_target_add_op_defs(arm_op_defs);
1704}
1705
1706static inline void tcg_out_ld(TCGContext *s, TCGType type, int arg,
1707 int arg1, tcg_target_long arg2)
1708{
1709 tcg_out_ld32u(s, COND_AL, arg, arg1, arg2);
1710}
1711
1712static inline void tcg_out_st(TCGContext *s, TCGType type, int arg,
1713 int arg1, tcg_target_long arg2)
1714{
1715 tcg_out_st32(s, COND_AL, arg, arg1, arg2);
1716}
1717
2d69f359 1718static void tcg_out_addi(TCGContext *s, int reg, tcg_target_long val)
811d4cf4
AZ		 1719{
1720 if (val > 0)
1721 if (val < 0x100)
1722 tcg_out_dat_imm(s, COND_AL, ARITH_ADD, reg, reg, val);
1723 else
1724 tcg_abort();
1725 else if (val < 0) {
1726 if (val > -0x100)
1727 tcg_out_dat_imm(s, COND_AL, ARITH_SUB, reg, reg, -val);
1728 else
1729 tcg_abort();
1730 }
1731}
1732
1733static inline void tcg_out_mov(TCGContext *s, int ret, int arg)
1734{
1735 tcg_out_dat_reg(s, COND_AL, ARITH_MOV, ret, 0, arg, SHIFT_IMM_LSL(0));
1736}
1737
1738static inline void tcg_out_movi(TCGContext *s, TCGType type,
1739 int ret, tcg_target_long arg)
1740{
1741 tcg_out_movi32(s, COND_AL, ret, arg);
1742}
1743
1744void tcg_target_qemu_prologue(TCGContext *s)
1745{
9e97d8e9
AJ		 1746 /* There is no need to save r7, it is used to store the address
1747 of the env structure and is not modified by GCC. */
4e17eae9 1748
9e97d8e9
AJ		 1749 /* stmdb sp!, { r4 - r6, r8 - r11, lr } */
1750 tcg_out32(s, (COND_AL << 28) | 0x092d4f70);
811d4cf4
AZ		 1751
1752 tcg_out_bx(s, COND_AL, TCG_REG_R0);
1753 tb_ret_addr = s->code_ptr;
1754
9e97d8e9
AJ		 1755 /* ldmia sp!, { r4 - r6, r8 - r11, pc } */
1756 tcg_out32(s, (COND_AL << 28) | 0x08bd8f70);
811d4cf4 1757}
Qemu copy for testing