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[qemu.git] / tcg / arm / tcg-target.c
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811d4cf4
AZ		 1/*
2 * Tiny Code Generator for QEMU
3 *
4 * Copyright (c) 2008 Andrzej Zaborowski
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
d4a9eb1f 24
ac34fb5c
AJ		 25#if defined(__ARM_ARCH_7__) || \
26 defined(__ARM_ARCH_7A__) || \
27 defined(__ARM_ARCH_7EM__) || \
28 defined(__ARM_ARCH_7M__) || \
29 defined(__ARM_ARCH_7R__)
30#define USE_ARMV7_INSTRUCTIONS
31#endif
32
33#if defined(USE_ARMV7_INSTRUCTIONS) || \
34 defined(__ARM_ARCH_6J__) || \
35 defined(__ARM_ARCH_6K__) || \
36 defined(__ARM_ARCH_6T2__) || \
37 defined(__ARM_ARCH_6Z__) || \
38 defined(__ARM_ARCH_6ZK__)
39#define USE_ARMV6_INSTRUCTIONS
40#endif
41
42#if defined(USE_ARMV6_INSTRUCTIONS) || \
43 defined(__ARM_ARCH_5T__) || \
44 defined(__ARM_ARCH_5TE__) || \
45 defined(__ARM_ARCH_5TEJ__)
46#define USE_ARMV5_INSTRUCTIONS
47#endif
48
49#ifdef USE_ARMV5_INSTRUCTIONS
50static const int use_armv5_instructions = 1;
51#else
52static const int use_armv5_instructions = 0;
53#endif
54#undef USE_ARMV5_INSTRUCTIONS
55
56#ifdef USE_ARMV6_INSTRUCTIONS
57static const int use_armv6_instructions = 1;
58#else
59static const int use_armv6_instructions = 0;
60#endif
61#undef USE_ARMV6_INSTRUCTIONS
62
63#ifdef USE_ARMV7_INSTRUCTIONS
64static const int use_armv7_instructions = 1;
65#else
66static const int use_armv7_instructions = 0;
67#endif
68#undef USE_ARMV7_INSTRUCTIONS
69
d4a9eb1f
BS		 70#ifndef NDEBUG
71static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
811d4cf4
AZ		 72 "%r0",
73 "%r1",
74 "%r2",
75 "%r3",
76 "%r4",
77 "%r5",
78 "%r6",
79 "%r7",
80 "%r8",
81 "%r9",
82 "%r10",
83 "%r11",
84 "%r12",
85 "%r13",
86 "%r14",
e4a7d5e8 87 "%pc",
811d4cf4 88};
d4a9eb1f 89#endif
811d4cf4 90
d4a9eb1f 91static const int tcg_target_reg_alloc_order[] = {
811d4cf4
AZ		 92 TCG_REG_R4,
93 TCG_REG_R5,
94 TCG_REG_R6,
95 TCG_REG_R7,
96 TCG_REG_R8,
97 TCG_REG_R9,
98 TCG_REG_R10,
99 TCG_REG_R11,
811d4cf4 100 TCG_REG_R13,
914ccf51
AJ		 101 TCG_REG_R0,
102 TCG_REG_R1,
103 TCG_REG_R2,
104 TCG_REG_R3,
105 TCG_REG_R12,
811d4cf4
AZ		 106 TCG_REG_R14,
107};
108
d4a9eb1f 109static const int tcg_target_call_iarg_regs[4] = {
811d4cf4
AZ		 110 TCG_REG_R0, TCG_REG_R1, TCG_REG_R2, TCG_REG_R3
111};
d4a9eb1f 112static const int tcg_target_call_oarg_regs[2] = {
811d4cf4
AZ		 113 TCG_REG_R0, TCG_REG_R1
114};
115
c69806ab
AJ		 116static inline void reloc_abs32(void *code_ptr, tcg_target_long target)
117{
118 *(uint32_t *) code_ptr = target;
119}
120
121static inline void reloc_pc24(void *code_ptr, tcg_target_long target)
122{
123 uint32_t offset = ((target - ((tcg_target_long) code_ptr + 8)) >> 2);
124
125 *(uint32_t *) code_ptr = ((*(uint32_t *) code_ptr) & ~0xffffff)
126 | (offset & 0xffffff);
127}
128
650bbb36 129static void patch_reloc(uint8_t *code_ptr, int type,
811d4cf4
AZ		 130 tcg_target_long value, tcg_target_long addend)
131{
132 switch (type) {
133 case R_ARM_ABS32:
c69806ab 134 reloc_abs32(code_ptr, value);
811d4cf4
AZ		 135 break;
136
137 case R_ARM_CALL:
138 case R_ARM_JUMP24:
139 default:
140 tcg_abort();
141
142 case R_ARM_PC24:
c69806ab 143 reloc_pc24(code_ptr, value);
811d4cf4
AZ		 144 break;
145 }
146}
147
148/* maximum number of register used for input function arguments */
149static inline int tcg_target_get_call_iarg_regs_count(int flags)
150{
151 return 4;
152}
153
811d4cf4 154/* parse target specific constraints */
d4a9eb1f 155static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
811d4cf4
AZ		 156{
157 const char *ct_str;
158
159 ct_str = *pct_str;
160 switch (ct_str[0]) {
cb4e581f
LD		 161 case 'I':
162 ct->ct |= TCG_CT_CONST_ARM;
163 break;
164
811d4cf4 165 case 'r':
811d4cf4
AZ		 166 ct->ct |= TCG_CT_REG;
167 tcg_regset_set32(ct->u.regs, 0, (1 << TCG_TARGET_NB_REGS) - 1);
168 break;
169
67dcab73
AJ		 170 /* qemu_ld address */
171 case 'l':
811d4cf4
AZ		 172 ct->ct |= TCG_CT_REG;
173 tcg_regset_set32(ct->u.regs, 0, (1 << TCG_TARGET_NB_REGS) - 1);
67dcab73
AJ		 174#ifdef CONFIG_SOFTMMU
175 /* r0 and r1 will be overwritten when reading the tlb entry,
176 so don't use these. */
811d4cf4
AZ		 177 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R0);
178 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R1);
67dcab73 179#endif
811d4cf4 180 break;
67dcab73 181 case 'L':
d0660ed4
AZ		 182 ct->ct |= TCG_CT_REG;
183 tcg_regset_set32(ct->u.regs, 0, (1 << TCG_TARGET_NB_REGS) - 1);
67dcab73
AJ		 184#ifdef CONFIG_SOFTMMU
185 /* r1 is still needed to load data_reg or data_reg2,
186 so don't use it. */
d0660ed4 187 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R1);
67dcab73 188#endif
d0660ed4
AZ		 189 break;
190
67dcab73
AJ		 191 /* qemu_st address & data_reg */
192 case 's':
811d4cf4
AZ		 193 ct->ct |= TCG_CT_REG;
194 tcg_regset_set32(ct->u.regs, 0, (1 << TCG_TARGET_NB_REGS) - 1);
67dcab73
AJ		 195 /* r0 and r1 will be overwritten when reading the tlb entry
196 (softmmu only) and doing the byte swapping, so don't
197 use these. */
811d4cf4
AZ		 198 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R0);
199 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R1);
811d4cf4 200 break;
67dcab73
AJ		 201 /* qemu_st64 data_reg2 */
202 case 'S':
811d4cf4
AZ		 203 ct->ct |= TCG_CT_REG;
204 tcg_regset_set32(ct->u.regs, 0, (1 << TCG_TARGET_NB_REGS) - 1);
67dcab73
AJ		 205 /* r0 and r1 will be overwritten when reading the tlb entry
206 (softmmu only) and doing the byte swapping, so don't
207 use these. */
811d4cf4 208 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R0);
811d4cf4 209 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R1);
67dcab73
AJ		 210#ifdef CONFIG_SOFTMMU
211 /* r2 is still needed to load data_reg, so don't use it. */
212 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R2);
811d4cf4 213#endif
67dcab73 214 break;
811d4cf4 215
811d4cf4
AZ		 216 default:
217 return -1;
218 }
219 ct_str++;
220 *pct_str = ct_str;
221
222 return 0;
223}
224
94953e6d
LD		 225static inline uint32_t rotl(uint32_t val, int n)
226{
227 return (val << n) | (val >> (32 - n));
228}
229
230/* ARM immediates for ALU instructions are made of an unsigned 8-bit
231 right-rotated by an even amount between 0 and 30. */
232static inline int encode_imm(uint32_t imm)
233{
4e6f6d4c
LD		 234 int shift;
235
94953e6d
LD		 236 /* simple case, only lower bits */
237 if ((imm & ~0xff) == 0)
238 return 0;
239 /* then try a simple even shift */
240 shift = ctz32(imm) & ~1;
241 if (((imm >> shift) & ~0xff) == 0)
242 return 32 - shift;
243 /* now try harder with rotations */
244 if ((rotl(imm, 2) & ~0xff) == 0)
245 return 2;
246 if ((rotl(imm, 4) & ~0xff) == 0)
247 return 4;
248 if ((rotl(imm, 6) & ~0xff) == 0)
249 return 6;
250 /* imm can't be encoded */
251 return -1;
252}
cb4e581f
LD		 253
254static inline int check_fit_imm(uint32_t imm)
255{
94953e6d 256 return encode_imm(imm) >= 0;
cb4e581f
LD		 257}
258
811d4cf4
AZ		 259/* Test if a constant matches the constraint.
260 * TODO: define constraints for:
261 *
262 * ldr/str offset: between -0xfff and 0xfff
263 * ldrh/strh offset: between -0xff and 0xff
264 * mov operand2: values represented with x << (2 * y), x < 0x100
265 * add, sub, eor...: ditto
266 */
267static inline int tcg_target_const_match(tcg_target_long val,
268 const TCGArgConstraint *arg_ct)
269{
270 int ct;
271 ct = arg_ct->ct;
272 if (ct & TCG_CT_CONST)
273 return 1;
cb4e581f
LD		 274 else if ((ct & TCG_CT_CONST_ARM) && check_fit_imm(val))
275 return 1;
811d4cf4
AZ		 276 else
277 return 0;
278}
279
280enum arm_data_opc_e {
281 ARITH_AND = 0x0,
282 ARITH_EOR = 0x1,
283 ARITH_SUB = 0x2,
284 ARITH_RSB = 0x3,
285 ARITH_ADD = 0x4,
286 ARITH_ADC = 0x5,
287 ARITH_SBC = 0x6,
288 ARITH_RSC = 0x7,
3979144c 289 ARITH_TST = 0x8,
811d4cf4
AZ		 290 ARITH_CMP = 0xa,
291 ARITH_CMN = 0xb,
292 ARITH_ORR = 0xc,
293 ARITH_MOV = 0xd,
294 ARITH_BIC = 0xe,
295 ARITH_MVN = 0xf,
296};
297
3979144c
PB		 298#define TO_CPSR(opc) \
299 ((opc == ARITH_CMP || opc == ARITH_CMN || opc == ARITH_TST) << 20)
811d4cf4
AZ		 300
301#define SHIFT_IMM_LSL(im) (((im) << 7) | 0x00)
302#define SHIFT_IMM_LSR(im) (((im) << 7) | 0x20)
303#define SHIFT_IMM_ASR(im) (((im) << 7) | 0x40)
304#define SHIFT_IMM_ROR(im) (((im) << 7) | 0x60)
305#define SHIFT_REG_LSL(rs) (((rs) << 8) | 0x10)
306#define SHIFT_REG_LSR(rs) (((rs) << 8) | 0x30)
307#define SHIFT_REG_ASR(rs) (((rs) << 8) | 0x50)
308#define SHIFT_REG_ROR(rs) (((rs) << 8) | 0x70)
309
310enum arm_cond_code_e {
311 COND_EQ = 0x0,
312 COND_NE = 0x1,
313 COND_CS = 0x2, /* Unsigned greater or equal */
314 COND_CC = 0x3, /* Unsigned less than */
315 COND_MI = 0x4, /* Negative */
316 COND_PL = 0x5, /* Zero or greater */
317 COND_VS = 0x6, /* Overflow */
318 COND_VC = 0x7, /* No overflow */
319 COND_HI = 0x8, /* Unsigned greater than */
320 COND_LS = 0x9, /* Unsigned less or equal */
321 COND_GE = 0xa,
322 COND_LT = 0xb,
323 COND_GT = 0xc,
324 COND_LE = 0xd,
325 COND_AL = 0xe,
326};
327
328static const uint8_t tcg_cond_to_arm_cond[10] = {
329 [TCG_COND_EQ] = COND_EQ,
330 [TCG_COND_NE] = COND_NE,
331 [TCG_COND_LT] = COND_LT,
332 [TCG_COND_GE] = COND_GE,
333 [TCG_COND_LE] = COND_LE,
334 [TCG_COND_GT] = COND_GT,
335 /* unsigned */
336 [TCG_COND_LTU] = COND_CC,
337 [TCG_COND_GEU] = COND_CS,
338 [TCG_COND_LEU] = COND_LS,
339 [TCG_COND_GTU] = COND_HI,
340};
341
342static inline void tcg_out_bx(TCGContext *s, int cond, int rn)
343{
344 tcg_out32(s, (cond << 28) | 0x012fff10 | rn);
345}
346
347static inline void tcg_out_b(TCGContext *s, int cond, int32_t offset)
348{
349 tcg_out32(s, (cond << 28) | 0x0a000000 |
350 (((offset - 8) >> 2) & 0x00ffffff));
351}
352
e936243a
AZ		 353static inline void tcg_out_b_noaddr(TCGContext *s, int cond)
354{
e2542fe2 355#ifdef HOST_WORDS_BIGENDIAN
e936243a
AZ		 356 tcg_out8(s, (cond << 4) | 0x0a);
357 s->code_ptr += 3;
358#else
359 s->code_ptr += 3;
360 tcg_out8(s, (cond << 4) | 0x0a);
361#endif
362}
363
811d4cf4
AZ		 364static inline void tcg_out_bl(TCGContext *s, int cond, int32_t offset)
365{
366 tcg_out32(s, (cond << 28) | 0x0b000000 |
367 (((offset - 8) >> 2) & 0x00ffffff));
368}
369
23401b58
AJ		 370static inline void tcg_out_blx(TCGContext *s, int cond, int rn)
371{
372 tcg_out32(s, (cond << 28) | 0x012fff30 | rn);
373}
374
811d4cf4
AZ		 375static inline void tcg_out_dat_reg(TCGContext *s,
376 int cond, int opc, int rd, int rn, int rm, int shift)
377{
378 tcg_out32(s, (cond << 28) | (0 << 25) | (opc << 21) | TO_CPSR(opc) |
379 (rn << 16) | (rd << 12) | shift | rm);
380}
381
382static inline void tcg_out_dat_reg2(TCGContext *s,
383 int cond, int opc0, int opc1, int rd0, int rd1,
384 int rn0, int rn1, int rm0, int rm1, int shift)
385{
0c9c3a9e
AZ		 386 if (rd0 == rn1 || rd0 == rm1) {
387 tcg_out32(s, (cond << 28) | (0 << 25) | (opc0 << 21) | (1 << 20) |
388 (rn0 << 16) | (8 << 12) | shift | rm0);
389 tcg_out32(s, (cond << 28) | (0 << 25) | (opc1 << 21) |
390 (rn1 << 16) | (rd1 << 12) | shift | rm1);
391 tcg_out_dat_reg(s, cond, ARITH_MOV,
392 rd0, 0, TCG_REG_R8, SHIFT_IMM_LSL(0));
393 } else {
394 tcg_out32(s, (cond << 28) | (0 << 25) | (opc0 << 21) | (1 << 20) |
395 (rn0 << 16) | (rd0 << 12) | shift | rm0);
396 tcg_out32(s, (cond << 28) | (0 << 25) | (opc1 << 21) |
397 (rn1 << 16) | (rd1 << 12) | shift | rm1);
398 }
811d4cf4
AZ		 399}
400
401static inline void tcg_out_dat_imm(TCGContext *s,
402 int cond, int opc, int rd, int rn, int im)
403{
3979144c 404 tcg_out32(s, (cond << 28) | (1 << 25) | (opc << 21) | TO_CPSR(opc) |
811d4cf4
AZ		 405 (rn << 16) | (rd << 12) | im);
406}
407
408static inline void tcg_out_movi32(TCGContext *s,
0f11f25a 409 int cond, int rd, uint32_t arg)
811d4cf4 410{
811d4cf4
AZ		 411 /* TODO: This is very suboptimal, we can easily have a constant
412 * pool somewhere after all the instructions. */
0f11f25a
AJ		 413 if ((int)arg < 0 && (int)arg >= -0x100) {
414 tcg_out_dat_imm(s, cond, ARITH_MVN, rd, 0, (~arg) & 0xff);
415 } else if (use_armv7_instructions) {
ac34fb5c
AJ		 416 /* use movw/movt */
417 /* movw */
418 tcg_out32(s, (cond << 28) | 0x03000000 | (rd << 12)
419 | ((arg << 4) & 0x000f0000) | (arg & 0xfff));
0f11f25a 420 if (arg & 0xffff0000) {
ac34fb5c
AJ		 421 /* movt */
422 tcg_out32(s, (cond << 28) | 0x03400000 | (rd << 12)
423 | ((arg >> 12) & 0x000f0000) | ((arg >> 16) & 0xfff));
ac34fb5c 424 }
0f11f25a
AJ		 425 } else {
426 int opc = ARITH_MOV;
427 int rn = 0;
428
429 do {
430 int i, rot;
431
432 i = ctz32(arg) & ~1;
433 rot = ((32 - i) << 7) & 0xf00;
434 tcg_out_dat_imm(s, cond, opc, rd, rn, ((arg >> i) & 0xff) | rot);
435 arg &= ~(0xff << i);
436
437 opc = ARITH_ORR;
438 rn = rd;
439 } while (arg);
440 }
811d4cf4
AZ		 441}
442
443static inline void tcg_out_mul32(TCGContext *s,
444 int cond, int rd, int rs, int rm)
445{
446 if (rd != rm)
447 tcg_out32(s, (cond << 28) | (rd << 16) | (0 << 12) |
448 (rs << 8) | 0x90 | rm);
449 else if (rd != rs)
450 tcg_out32(s, (cond << 28) | (rd << 16) | (0 << 12) |
451 (rm << 8) | 0x90 | rs);
452 else {
453 tcg_out32(s, (cond << 28) | ( 8 << 16) | (0 << 12) |
454 (rs << 8) | 0x90 | rm);
455 tcg_out_dat_reg(s, cond, ARITH_MOV,
c8d80cef 456 rd, 0, TCG_REG_R8, SHIFT_IMM_LSL(0));
811d4cf4
AZ		 457 }
458}
459
460static inline void tcg_out_umull32(TCGContext *s,
461 int cond, int rd0, int rd1, int rs, int rm)
462{
463 if (rd0 != rm && rd1 != rm)
464 tcg_out32(s, (cond << 28) | 0x800090 |
465 (rd1 << 16) | (rd0 << 12) | (rs << 8) | rm);
466 else if (rd0 != rs && rd1 != rs)
467 tcg_out32(s, (cond << 28) | 0x800090 |
468 (rd1 << 16) | (rd0 << 12) | (rm << 8) | rs);
469 else {
470 tcg_out_dat_reg(s, cond, ARITH_MOV,
471 TCG_REG_R8, 0, rm, SHIFT_IMM_LSL(0));
472 tcg_out32(s, (cond << 28) | 0x800098 |
473 (rd1 << 16) | (rd0 << 12) | (rs << 8));
474 }
475}
476
477static inline void tcg_out_smull32(TCGContext *s,
478 int cond, int rd0, int rd1, int rs, int rm)
479{
480 if (rd0 != rm && rd1 != rm)
481 tcg_out32(s, (cond << 28) | 0xc00090 |
482 (rd1 << 16) | (rd0 << 12) | (rs << 8) | rm);
483 else if (rd0 != rs && rd1 != rs)
484 tcg_out32(s, (cond << 28) | 0xc00090 |
485 (rd1 << 16) | (rd0 << 12) | (rm << 8) | rs);
486 else {
487 tcg_out_dat_reg(s, cond, ARITH_MOV,
488 TCG_REG_R8, 0, rm, SHIFT_IMM_LSL(0));
489 tcg_out32(s, (cond << 28) | 0xc00098 |
490 (rd1 << 16) | (rd0 << 12) | (rs << 8));
491 }
492}
493
9517094f
AJ		 494static inline void tcg_out_ext8s(TCGContext *s, int cond,
495 int rd, int rn)
496{
497 if (use_armv6_instructions) {
498 /* sxtb */
499 tcg_out32(s, 0x06af0070 | (cond << 28) | (rd << 12) | rn);
500 } else {
e23886a9 501 tcg_out_dat_reg(s, cond, ARITH_MOV,
9517094f 502 rd, 0, rn, SHIFT_IMM_LSL(24));
e23886a9 503 tcg_out_dat_reg(s, cond, ARITH_MOV,
9517094f
AJ		 504 rd, 0, rd, SHIFT_IMM_ASR(24));
505 }
506}
507
e854b6d3
AJ		 508static inline void tcg_out_ext8u(TCGContext *s, int cond,
509 int rd, int rn)
510{
511 tcg_out_dat_imm(s, cond, ARITH_AND, rd, rn, 0xff);
512}
513
9517094f
AJ		 514static inline void tcg_out_ext16s(TCGContext *s, int cond,
515 int rd, int rn)
516{
517 if (use_armv6_instructions) {
518 /* sxth */
519 tcg_out32(s, 0x06bf0070 | (cond << 28) | (rd << 12) | rn);
520 } else {
e23886a9 521 tcg_out_dat_reg(s, cond, ARITH_MOV,
9517094f 522 rd, 0, rn, SHIFT_IMM_LSL(16));
e23886a9 523 tcg_out_dat_reg(s, cond, ARITH_MOV,
9517094f
AJ		 524 rd, 0, rd, SHIFT_IMM_ASR(16));
525 }
526}
527
528static inline void tcg_out_ext16u(TCGContext *s, int cond,
529 int rd, int rn)
530{
531 if (use_armv6_instructions) {
532 /* uxth */
533 tcg_out32(s, 0x06ff0070 | (cond << 28) | (rd << 12) | rn);
534 } else {
e23886a9 535 tcg_out_dat_reg(s, cond, ARITH_MOV,
9517094f 536 rd, 0, rn, SHIFT_IMM_LSL(16));
e23886a9 537 tcg_out_dat_reg(s, cond, ARITH_MOV,
9517094f
AJ		 538 rd, 0, rd, SHIFT_IMM_LSR(16));
539 }
540}
541
67dcab73
AJ		 542static inline void tcg_out_bswap16s(TCGContext *s, int cond, int rd, int rn)
543{
544 if (use_armv6_instructions) {
545 /* revsh */
546 tcg_out32(s, 0x06ff0fb0 | (cond << 28) | (rd << 12) | rn);
547 } else {
548 tcg_out_dat_reg(s, cond, ARITH_MOV,
549 TCG_REG_R8, 0, rn, SHIFT_IMM_LSL(24));
550 tcg_out_dat_reg(s, cond, ARITH_MOV,
551 TCG_REG_R8, 0, TCG_REG_R8, SHIFT_IMM_ASR(16));
552 tcg_out_dat_reg(s, cond, ARITH_ORR,
553 rd, TCG_REG_R8, rn, SHIFT_IMM_LSR(8));
554 }
555}
556
244b1e81
AJ		 557static inline void tcg_out_bswap16(TCGContext *s, int cond, int rd, int rn)
558{
559 if (use_armv6_instructions) {
560 /* rev16 */
561 tcg_out32(s, 0x06bf0fb0 | (cond << 28) | (rd << 12) | rn);
562 } else {
563 tcg_out_dat_reg(s, cond, ARITH_MOV,
564 TCG_REG_R8, 0, rn, SHIFT_IMM_LSL(24));
565 tcg_out_dat_reg(s, cond, ARITH_MOV,
566 TCG_REG_R8, 0, TCG_REG_R8, SHIFT_IMM_LSR(16));
567 tcg_out_dat_reg(s, cond, ARITH_ORR,
568 rd, TCG_REG_R8, rn, SHIFT_IMM_LSR(8));
569 }
570}
571
572static inline void tcg_out_bswap32(TCGContext *s, int cond, int rd, int rn)
573{
574 if (use_armv6_instructions) {
575 /* rev */
576 tcg_out32(s, 0x06bf0f30 | (cond << 28) | (rd << 12) | rn);
577 } else {
578 tcg_out_dat_reg(s, cond, ARITH_EOR,
579 TCG_REG_R8, rn, rn, SHIFT_IMM_ROR(16));
580 tcg_out_dat_imm(s, cond, ARITH_BIC,
581 TCG_REG_R8, TCG_REG_R8, 0xff | 0x800);
582 tcg_out_dat_reg(s, cond, ARITH_MOV,
583 rd, 0, rn, SHIFT_IMM_ROR(8));
584 tcg_out_dat_reg(s, cond, ARITH_EOR,
585 rd, rd, TCG_REG_R8, SHIFT_IMM_LSR(8));
586 }
587}
588
811d4cf4
AZ		 589static inline void tcg_out_ld32_12(TCGContext *s, int cond,
590 int rd, int rn, tcg_target_long im)
591{
592 if (im >= 0)
593 tcg_out32(s, (cond << 28) | 0x05900000 |
594 (rn << 16) | (rd << 12) | (im & 0xfff));
595 else
596 tcg_out32(s, (cond << 28) | 0x05100000 |
597 (rn << 16) | (rd << 12) | ((-im) & 0xfff));
598}
599
600static inline void tcg_out_st32_12(TCGContext *s, int cond,
601 int rd, int rn, tcg_target_long im)
602{
603 if (im >= 0)
604 tcg_out32(s, (cond << 28) | 0x05800000 |
605 (rn << 16) | (rd << 12) | (im & 0xfff));
606 else
607 tcg_out32(s, (cond << 28) | 0x05000000 |
608 (rn << 16) | (rd << 12) | ((-im) & 0xfff));
609}
610
611static inline void tcg_out_ld32_r(TCGContext *s, int cond,
612 int rd, int rn, int rm)
613{
614 tcg_out32(s, (cond << 28) | 0x07900000 |
615 (rn << 16) | (rd << 12) | rm);
616}
617
618static inline void tcg_out_st32_r(TCGContext *s, int cond,
619 int rd, int rn, int rm)
620{
621 tcg_out32(s, (cond << 28) | 0x07800000 |
622 (rn << 16) | (rd << 12) | rm);
623}
624
3979144c
PB		 625/* Register pre-increment with base writeback. */
626static inline void tcg_out_ld32_rwb(TCGContext *s, int cond,
627 int rd, int rn, int rm)
628{
629 tcg_out32(s, (cond << 28) | 0x07b00000 |
630 (rn << 16) | (rd << 12) | rm);
631}
632
633static inline void tcg_out_st32_rwb(TCGContext *s, int cond,
634 int rd, int rn, int rm)
635{
636 tcg_out32(s, (cond << 28) | 0x07a00000 |
637 (rn << 16) | (rd << 12) | rm);
638}
639
811d4cf4
AZ		 640static inline void tcg_out_ld16u_8(TCGContext *s, int cond,
641 int rd, int rn, tcg_target_long im)
642{
643 if (im >= 0)
644 tcg_out32(s, (cond << 28) | 0x01d000b0 |
645 (rn << 16) | (rd << 12) |
646 ((im & 0xf0) << 4) | (im & 0xf));
647 else
648 tcg_out32(s, (cond << 28) | 0x015000b0 |
649 (rn << 16) | (rd << 12) |
650 (((-im) & 0xf0) << 4) | ((-im) & 0xf));
651}
652
f694a27e 653static inline void tcg_out_st16_8(TCGContext *s, int cond,
811d4cf4
AZ		 654 int rd, int rn, tcg_target_long im)
655{
656 if (im >= 0)
657 tcg_out32(s, (cond << 28) | 0x01c000b0 |
658 (rn << 16) | (rd << 12) |
659 ((im & 0xf0) << 4) | (im & 0xf));
660 else
661 tcg_out32(s, (cond << 28) | 0x014000b0 |
662 (rn << 16) | (rd << 12) |
663 (((-im) & 0xf0) << 4) | ((-im) & 0xf));
664}
665
666static inline void tcg_out_ld16u_r(TCGContext *s, int cond,
667 int rd, int rn, int rm)
668{
669 tcg_out32(s, (cond << 28) | 0x019000b0 |
670 (rn << 16) | (rd << 12) | rm);
671}
672
f694a27e 673static inline void tcg_out_st16_r(TCGContext *s, int cond,
811d4cf4
AZ		 674 int rd, int rn, int rm)
675{
676 tcg_out32(s, (cond << 28) | 0x018000b0 |
677 (rn << 16) | (rd << 12) | rm);
678}
679
680static inline void tcg_out_ld16s_8(TCGContext *s, int cond,
681 int rd, int rn, tcg_target_long im)
682{
683 if (im >= 0)
684 tcg_out32(s, (cond << 28) | 0x01d000f0 |
685 (rn << 16) | (rd << 12) |
686 ((im & 0xf0) << 4) | (im & 0xf));
687 else
688 tcg_out32(s, (cond << 28) | 0x015000f0 |
689 (rn << 16) | (rd << 12) |
690 (((-im) & 0xf0) << 4) | ((-im) & 0xf));
691}
692
811d4cf4
AZ		 693static inline void tcg_out_ld16s_r(TCGContext *s, int cond,
694 int rd, int rn, int rm)
695{
696 tcg_out32(s, (cond << 28) | 0x019000f0 |
697 (rn << 16) | (rd << 12) | rm);
698}
699
811d4cf4
AZ		 700static inline void tcg_out_ld8_12(TCGContext *s, int cond,
701 int rd, int rn, tcg_target_long im)
702{
703 if (im >= 0)
704 tcg_out32(s, (cond << 28) | 0x05d00000 |
705 (rn << 16) | (rd << 12) | (im & 0xfff));
706 else
707 tcg_out32(s, (cond << 28) | 0x05500000 |
708 (rn << 16) | (rd << 12) | ((-im) & 0xfff));
709}
710
711static inline void tcg_out_st8_12(TCGContext *s, int cond,
712 int rd, int rn, tcg_target_long im)
713{
714 if (im >= 0)
715 tcg_out32(s, (cond << 28) | 0x05c00000 |
716 (rn << 16) | (rd << 12) | (im & 0xfff));
717 else
718 tcg_out32(s, (cond << 28) | 0x05400000 |
719 (rn << 16) | (rd << 12) | ((-im) & 0xfff));
720}
721
722static inline void tcg_out_ld8_r(TCGContext *s, int cond,
723 int rd, int rn, int rm)
724{
725 tcg_out32(s, (cond << 28) | 0x07d00000 |
726 (rn << 16) | (rd << 12) | rm);
727}
728
729static inline void tcg_out_st8_r(TCGContext *s, int cond,
730 int rd, int rn, int rm)
731{
732 tcg_out32(s, (cond << 28) | 0x07c00000 |
733 (rn << 16) | (rd << 12) | rm);
734}
735
736static inline void tcg_out_ld8s_8(TCGContext *s, int cond,
737 int rd, int rn, tcg_target_long im)
738{
739 if (im >= 0)
740 tcg_out32(s, (cond << 28) | 0x01d000d0 |
741 (rn << 16) | (rd << 12) |
742 ((im & 0xf0) << 4) | (im & 0xf));
743 else
744 tcg_out32(s, (cond << 28) | 0x015000d0 |
745 (rn << 16) | (rd << 12) |
746 (((-im) & 0xf0) << 4) | ((-im) & 0xf));
747}
748
811d4cf4
AZ		 749static inline void tcg_out_ld8s_r(TCGContext *s, int cond,
750 int rd, int rn, int rm)
751{
204c1674 752 tcg_out32(s, (cond << 28) | 0x019000d0 |
811d4cf4
AZ		 753 (rn << 16) | (rd << 12) | rm);
754}
755
811d4cf4
AZ		 756static inline void tcg_out_ld32u(TCGContext *s, int cond,
757 int rd, int rn, int32_t offset)
758{
759 if (offset > 0xfff || offset < -0xfff) {
760 tcg_out_movi32(s, cond, TCG_REG_R8, offset);
761 tcg_out_ld32_r(s, cond, rd, rn, TCG_REG_R8);
762 } else
763 tcg_out_ld32_12(s, cond, rd, rn, offset);
764}
765
766static inline void tcg_out_st32(TCGContext *s, int cond,
767 int rd, int rn, int32_t offset)
768{
769 if (offset > 0xfff || offset < -0xfff) {
770 tcg_out_movi32(s, cond, TCG_REG_R8, offset);
771 tcg_out_st32_r(s, cond, rd, rn, TCG_REG_R8);
772 } else
773 tcg_out_st32_12(s, cond, rd, rn, offset);
774}
775
776static inline void tcg_out_ld16u(TCGContext *s, int cond,
777 int rd, int rn, int32_t offset)
778{
779 if (offset > 0xff || offset < -0xff) {
780 tcg_out_movi32(s, cond, TCG_REG_R8, offset);
781 tcg_out_ld16u_r(s, cond, rd, rn, TCG_REG_R8);
782 } else
783 tcg_out_ld16u_8(s, cond, rd, rn, offset);
784}
785
786static inline void tcg_out_ld16s(TCGContext *s, int cond,
787 int rd, int rn, int32_t offset)
788{
789 if (offset > 0xff || offset < -0xff) {
790 tcg_out_movi32(s, cond, TCG_REG_R8, offset);
791 tcg_out_ld16s_r(s, cond, rd, rn, TCG_REG_R8);
792 } else
793 tcg_out_ld16s_8(s, cond, rd, rn, offset);
794}
795
f694a27e 796static inline void tcg_out_st16(TCGContext *s, int cond,
811d4cf4
AZ		 797 int rd, int rn, int32_t offset)
798{
799 if (offset > 0xff || offset < -0xff) {
800 tcg_out_movi32(s, cond, TCG_REG_R8, offset);
f694a27e 801 tcg_out_st16_r(s, cond, rd, rn, TCG_REG_R8);
811d4cf4 802 } else
f694a27e 803 tcg_out_st16_8(s, cond, rd, rn, offset);
811d4cf4
AZ		 804}
805
806static inline void tcg_out_ld8u(TCGContext *s, int cond,
807 int rd, int rn, int32_t offset)
808{
809 if (offset > 0xfff || offset < -0xfff) {
810 tcg_out_movi32(s, cond, TCG_REG_R8, offset);
811 tcg_out_ld8_r(s, cond, rd, rn, TCG_REG_R8);
812 } else
813 tcg_out_ld8_12(s, cond, rd, rn, offset);
814}
815
816static inline void tcg_out_ld8s(TCGContext *s, int cond,
817 int rd, int rn, int32_t offset)
818{
819 if (offset > 0xff || offset < -0xff) {
820 tcg_out_movi32(s, cond, TCG_REG_R8, offset);
821 tcg_out_ld8s_r(s, cond, rd, rn, TCG_REG_R8);
822 } else
823 tcg_out_ld8s_8(s, cond, rd, rn, offset);
824}
825
f694a27e 826static inline void tcg_out_st8(TCGContext *s, int cond,
811d4cf4
AZ		 827 int rd, int rn, int32_t offset)
828{
829 if (offset > 0xfff || offset < -0xfff) {
830 tcg_out_movi32(s, cond, TCG_REG_R8, offset);
831 tcg_out_st8_r(s, cond, rd, rn, TCG_REG_R8);
832 } else
833 tcg_out_st8_12(s, cond, rd, rn, offset);
834}
835
836static inline void tcg_out_goto(TCGContext *s, int cond, uint32_t addr)
837{
838 int32_t val;
839
840 val = addr - (tcg_target_long) s->code_ptr;
841 if (val - 8 < 0x01fffffd && val - 8 > -0x01fffffd)
842 tcg_out_b(s, cond, val);
843 else {
844#if 1
845 tcg_abort();
846#else
847 if (cond == COND_AL) {
c8d80cef 848 tcg_out_ld32_12(s, COND_AL, TCG_REG_PC, TCG_REG_PC, -4);
811d4cf4
AZ		 849 tcg_out32(s, addr); /* XXX: This is l->u.value, can we use it? */
850 } else {
851 tcg_out_movi32(s, cond, TCG_REG_R8, val - 8);
852 tcg_out_dat_reg(s, cond, ARITH_ADD,
c8d80cef
AJ		 853 TCG_REG_PC, TCG_REG_PC,
854 TCG_REG_R8, SHIFT_IMM_LSL(0));
811d4cf4
AZ		 855 }
856#endif
857 }
858}
859
860static inline void tcg_out_call(TCGContext *s, int cond, uint32_t addr)
861{
862 int32_t val;
863
811d4cf4
AZ		 864 val = addr - (tcg_target_long) s->code_ptr;
865 if (val < 0x01fffffd && val > -0x01fffffd)
866 tcg_out_bl(s, cond, val);
867 else {
868#if 1
869 tcg_abort();
870#else
871 if (cond == COND_AL) {
c8d80cef
AJ		 872 tcg_out_dat_imm(s, cond, ARITH_ADD, TCG_REG_R14, TCG_REG_PC, 4);
873 tcg_out_ld32_12(s, COND_AL, TCG_REG_PC, TCG_REG_PC, -4);
811d4cf4
AZ		 874 tcg_out32(s, addr); /* XXX: This is l->u.value, can we use it? */
875 } else {
876 tcg_out_movi32(s, cond, TCG_REG_R9, addr);
c8d80cef
AJ		 877 tcg_out_dat_reg(s, cond, ARITH_MOV, TCG_REG_R14, 0,
878 TCG_REG_PC, SHIFT_IMM_LSL(0));
811d4cf4
AZ		 879 tcg_out_bx(s, cond, TCG_REG_R9);
880 }
881#endif
882 }
811d4cf4
AZ		 883}
884
885static inline void tcg_out_callr(TCGContext *s, int cond, int arg)
886{
23401b58
AJ		 887 if (use_armv5_instructions) {
888 tcg_out_blx(s, cond, arg);
889 } else {
890 tcg_out_dat_reg(s, cond, ARITH_MOV, TCG_REG_R14, 0,
891 TCG_REG_PC, SHIFT_IMM_LSL(0));
892 tcg_out_bx(s, cond, arg);
893 }
811d4cf4
AZ		 894}
895
896static inline void tcg_out_goto_label(TCGContext *s, int cond, int label_index)
897{
898 TCGLabel *l = &s->labels[label_index];
899
900 if (l->has_value)
901 tcg_out_goto(s, cond, l->u.value);
902 else if (cond == COND_AL) {
c8d80cef 903 tcg_out_ld32_12(s, COND_AL, TCG_REG_PC, TCG_REG_PC, -4);
811d4cf4
AZ		 904 tcg_out_reloc(s, s->code_ptr, R_ARM_ABS32, label_index, 31337);
905 s->code_ptr += 4;
906 } else {
907 /* Probably this should be preferred even for COND_AL... */
908 tcg_out_reloc(s, s->code_ptr, R_ARM_PC24, label_index, 31337);
e936243a 909 tcg_out_b_noaddr(s, cond);
811d4cf4
AZ		 910 }
911}
912
811d4cf4 913#ifdef CONFIG_SOFTMMU
79383c9c
BS		 914
915#include "../../softmmu_defs.h"
811d4cf4
AZ		 916
917static void *qemu_ld_helpers[4] = {
918 __ldb_mmu,
919 __ldw_mmu,
920 __ldl_mmu,
921 __ldq_mmu,
922};
923
924static void *qemu_st_helpers[4] = {
925 __stb_mmu,
926 __stw_mmu,
927 __stl_mmu,
928 __stq_mmu,
929};
930#endif
931
3979144c
PB		 932#define TLB_SHIFT (CPU_TLB_ENTRY_BITS + CPU_TLB_BITS)
933
7e0d9562 934static inline void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int opc)
811d4cf4 935{
67dcab73 936 int addr_reg, data_reg, data_reg2, bswap;
811d4cf4
AZ		 937#ifdef CONFIG_SOFTMMU
938 int mem_index, s_bits;
939# if TARGET_LONG_BITS == 64
940 int addr_reg2;
941# endif
811d4cf4 942 uint32_t *label_ptr;
811d4cf4
AZ		 943#endif
944
67dcab73
AJ		 945#ifdef TARGET_WORDS_BIGENDIAN
946 bswap = 1;
947#else
948 bswap = 0;
949#endif
811d4cf4
AZ		 950 data_reg = *args++;
951 if (opc == 3)
952 data_reg2 = *args++;
953 else
d89c682f 954 data_reg2 = 0; /* suppress warning */
811d4cf4 955 addr_reg = *args++;
811d4cf4 956#ifdef CONFIG_SOFTMMU
aef3a282
AZ		 957# if TARGET_LONG_BITS == 64
958 addr_reg2 = *args++;
959# endif
811d4cf4
AZ		 960 mem_index = *args;
961 s_bits = opc & 3;
962
91a3c1b0 963 /* Should generate something like the following:
3979144c 964 * shr r8, addr_reg, #TARGET_PAGE_BITS
91a3c1b0 965 * and r0, r8, #(CPU_TLB_SIZE - 1) @ Assumption: CPU_TLB_BITS <= 8
3979144c 966 * add r0, env, r0 lsl #CPU_TLB_ENTRY_BITS
91a3c1b0
AZ		 967 */
968# if CPU_TLB_BITS > 8
969# error
970# endif
c8d80cef
AJ		 971 tcg_out_dat_reg(s, COND_AL, ARITH_MOV, TCG_REG_R8,
972 0, addr_reg, SHIFT_IMM_LSR(TARGET_PAGE_BITS));
811d4cf4 973 tcg_out_dat_imm(s, COND_AL, ARITH_AND,
c8d80cef
AJ		 974 TCG_REG_R0, TCG_REG_R8, CPU_TLB_SIZE - 1);
975 tcg_out_dat_reg(s, COND_AL, ARITH_ADD, TCG_REG_R0, TCG_AREG0,
976 TCG_REG_R0, SHIFT_IMM_LSL(CPU_TLB_ENTRY_BITS));
91a3c1b0
AZ		 977 /* In the
978 * ldr r1 [r0, #(offsetof(CPUState, tlb_table[mem_index][0].addr_read))]
979 * below, the offset is likely to exceed 12 bits if mem_index != 0 and
980 * not exceed otherwise, so use an
981 * add r0, r0, #(mem_index * sizeof *CPUState.tlb_table)
982 * before.
983 */
225b4376 984 if (mem_index)
c8d80cef 985 tcg_out_dat_imm(s, COND_AL, ARITH_ADD, TCG_REG_R0, TCG_REG_R0,
225b4376
AZ		 986 (mem_index << (TLB_SHIFT & 1)) |
987 ((16 - (TLB_SHIFT >> 1)) << 8));
c8d80cef 988 tcg_out_ld32_12(s, COND_AL, TCG_REG_R1, TCG_REG_R0,
225b4376 989 offsetof(CPUState, tlb_table[0][0].addr_read));
c8d80cef
AJ		 990 tcg_out_dat_reg(s, COND_AL, ARITH_CMP, 0, TCG_REG_R1,
991 TCG_REG_R8, SHIFT_IMM_LSL(TARGET_PAGE_BITS));
3979144c
PB		 992 /* Check alignment. */
993 if (s_bits)
994 tcg_out_dat_imm(s, COND_EQ, ARITH_TST,
995 0, addr_reg, (1 << s_bits) - 1);
811d4cf4
AZ		 996# if TARGET_LONG_BITS == 64
997 /* XXX: possibly we could use a block data load or writeback in
998 * the first access. */
c8d80cef 999 tcg_out_ld32_12(s, COND_EQ, TCG_REG_R1, TCG_REG_R0,
225b4376 1000 offsetof(CPUState, tlb_table[0][0].addr_read) + 4);
c8d80cef
AJ		 1001 tcg_out_dat_reg(s, COND_EQ, ARITH_CMP, 0,
1002 TCG_REG_R1, addr_reg2, SHIFT_IMM_LSL(0));
811d4cf4 1003# endif
c8d80cef 1004 tcg_out_ld32_12(s, COND_EQ, TCG_REG_R1, TCG_REG_R0,
225b4376 1005 offsetof(CPUState, tlb_table[0][0].addend));
811d4cf4
AZ		 1006
1007 switch (opc) {
1008 case 0:
c8d80cef 1009 tcg_out_ld8_r(s, COND_EQ, data_reg, addr_reg, TCG_REG_R1);
811d4cf4
AZ		 1010 break;
1011 case 0 | 4:
c8d80cef 1012 tcg_out_ld8s_r(s, COND_EQ, data_reg, addr_reg, TCG_REG_R1);
811d4cf4
AZ		 1013 break;
1014 case 1:
c8d80cef 1015 tcg_out_ld16u_r(s, COND_EQ, data_reg, addr_reg, TCG_REG_R1);
67dcab73
AJ		 1016 if (bswap) {
1017 tcg_out_bswap16(s, COND_EQ, data_reg, data_reg);
1018 }
811d4cf4
AZ		 1019 break;
1020 case 1 | 4:
67dcab73
AJ		 1021 if (bswap) {
1022 tcg_out_ld16u_r(s, COND_EQ, data_reg, addr_reg, TCG_REG_R1);
1023 tcg_out_bswap16s(s, COND_EQ, data_reg, data_reg);
1024 } else {
1025 tcg_out_ld16s_r(s, COND_EQ, data_reg, addr_reg, TCG_REG_R1);
1026 }
811d4cf4
AZ		 1027 break;
1028 case 2:
1029 default:
c8d80cef 1030 tcg_out_ld32_r(s, COND_EQ, data_reg, addr_reg, TCG_REG_R1);
67dcab73
AJ		 1031 if (bswap) {
1032 tcg_out_bswap32(s, COND_EQ, data_reg, data_reg);
1033 }
811d4cf4
AZ		 1034 break;
1035 case 3:
67dcab73
AJ		 1036 if (bswap) {
1037 tcg_out_ld32_rwb(s, COND_EQ, data_reg2, TCG_REG_R1, addr_reg);
1038 tcg_out_ld32_12(s, COND_EQ, data_reg, TCG_REG_R1, 4);
1039 tcg_out_bswap32(s, COND_EQ, data_reg2, data_reg2);
1040 tcg_out_bswap32(s, COND_EQ, data_reg, data_reg);
1041 } else {
1042 tcg_out_ld32_rwb(s, COND_EQ, data_reg, TCG_REG_R1, addr_reg);
1043 tcg_out_ld32_12(s, COND_EQ, data_reg2, TCG_REG_R1, 4);
1044 }
811d4cf4
AZ		 1045 break;
1046 }
1047
1048 label_ptr = (void *) s->code_ptr;
c69806ab 1049 tcg_out_b_noaddr(s, COND_EQ);
811d4cf4 1050
811d4cf4 1051 /* TODO: move this code to where the constants pool will be */
c8d80cef 1052 if (addr_reg != TCG_REG_R0) {
7e0d9562 1053 tcg_out_dat_reg(s, COND_AL, ARITH_MOV,
c8d80cef
AJ		 1054 TCG_REG_R0, 0, addr_reg, SHIFT_IMM_LSL(0));
1055 }
811d4cf4 1056# if TARGET_LONG_BITS == 32
7e0d9562 1057 tcg_out_dat_imm(s, COND_AL, ARITH_MOV, TCG_REG_R1, 0, mem_index);
811d4cf4 1058# else
2633a2d0
AJ		 1059 tcg_out_dat_reg(s, COND_AL, ARITH_MOV,
1060 TCG_REG_R1, 0, addr_reg2, SHIFT_IMM_LSL(0));
7e0d9562 1061 tcg_out_dat_imm(s, COND_AL, ARITH_MOV, TCG_REG_R2, 0, mem_index);
811d4cf4 1062# endif
7e0d9562 1063 tcg_out_bl(s, COND_AL, (tcg_target_long) qemu_ld_helpers[s_bits] -
811d4cf4
AZ		 1064 (tcg_target_long) s->code_ptr);
1065
1066 switch (opc) {
1067 case 0 | 4:
e854b6d3 1068 tcg_out_ext8s(s, COND_AL, data_reg, TCG_REG_R0);
811d4cf4
AZ		 1069 break;
1070 case 1 | 4:
e854b6d3 1071 tcg_out_ext16s(s, COND_AL, data_reg, TCG_REG_R0);
811d4cf4
AZ		 1072 break;
1073 case 0:
1074 case 1:
1075 case 2:
1076 default:
c8d80cef 1077 if (data_reg != TCG_REG_R0) {
7e0d9562 1078 tcg_out_dat_reg(s, COND_AL, ARITH_MOV,
c8d80cef
AJ		 1079 data_reg, 0, TCG_REG_R0, SHIFT_IMM_LSL(0));
1080 }
811d4cf4
AZ		 1081 break;
1082 case 3:
c8d80cef 1083 if (data_reg != TCG_REG_R0) {
7e0d9562 1084 tcg_out_dat_reg(s, COND_AL, ARITH_MOV,
c8d80cef
AJ		 1085 data_reg, 0, TCG_REG_R0, SHIFT_IMM_LSL(0));
1086 }
1087 if (data_reg2 != TCG_REG_R1) {
7e0d9562 1088 tcg_out_dat_reg(s, COND_AL, ARITH_MOV,
c8d80cef
AJ		 1089 data_reg2, 0, TCG_REG_R1, SHIFT_IMM_LSL(0));
1090 }
811d4cf4
AZ		 1091 break;
1092 }
1093
c69806ab 1094 reloc_pc24(label_ptr, (tcg_target_long)s->code_ptr);
379f6698
PB		 1095#else /* !CONFIG_SOFTMMU */
1096 if (GUEST_BASE) {
1097 uint32_t offset = GUEST_BASE;
1098 int i;
1099 int rot;
1100
1101 while (offset) {
1102 i = ctz32(offset) & ~1;
1103 rot = ((32 - i) << 7) & 0xf00;
1104
c8d80cef 1105 tcg_out_dat_imm(s, COND_AL, ARITH_ADD, TCG_REG_R8, addr_reg,
379f6698 1106 ((offset >> i) & 0xff) | rot);
c8d80cef 1107 addr_reg = TCG_REG_R8;
379f6698
PB		 1108 offset &= ~(0xff << i);
1109 }
1110 }
811d4cf4
AZ		 1111 switch (opc) {
1112 case 0:
1113 tcg_out_ld8_12(s, COND_AL, data_reg, addr_reg, 0);
1114 break;
1115 case 0 | 4:
1116 tcg_out_ld8s_8(s, COND_AL, data_reg, addr_reg, 0);
1117 break;
1118 case 1:
1119 tcg_out_ld16u_8(s, COND_AL, data_reg, addr_reg, 0);
67dcab73
AJ		 1120 if (bswap) {
1121 tcg_out_bswap16(s, COND_AL, data_reg, data_reg);
1122 }
811d4cf4
AZ		 1123 break;
1124 case 1 | 4:
67dcab73
AJ		 1125 if (bswap) {
1126 tcg_out_ld16u_8(s, COND_AL, data_reg, addr_reg, 0);
1127 tcg_out_bswap16s(s, COND_AL, data_reg, data_reg);
1128 } else {
1129 tcg_out_ld16s_8(s, COND_AL, data_reg, addr_reg, 0);
1130 }
811d4cf4
AZ		 1131 break;
1132 case 2:
1133 default:
1134 tcg_out_ld32_12(s, COND_AL, data_reg, addr_reg, 0);
67dcab73
AJ		 1135 if (bswap) {
1136 tcg_out_bswap32(s, COND_AL, data_reg, data_reg);
1137 }
811d4cf4
AZ		 1138 break;
1139 case 3:
eae6ce52
AZ		 1140 /* TODO: use block load -
1141 * check that data_reg2 > data_reg or the other way */
419bafa5 1142 if (data_reg == addr_reg) {
67dcab73
AJ		 1143 tcg_out_ld32_12(s, COND_AL, data_reg2, addr_reg, bswap ? 0 : 4);
1144 tcg_out_ld32_12(s, COND_AL, data_reg, addr_reg, bswap ? 4 : 0);
419bafa5 1145 } else {
67dcab73
AJ		 1146 tcg_out_ld32_12(s, COND_AL, data_reg, addr_reg, bswap ? 4 : 0);
1147 tcg_out_ld32_12(s, COND_AL, data_reg2, addr_reg, bswap ? 0 : 4);
1148 }
1149 if (bswap) {
1150 tcg_out_bswap32(s, COND_AL, data_reg, data_reg);
1151 tcg_out_bswap32(s, COND_AL, data_reg2, data_reg2);
419bafa5 1152 }
811d4cf4
AZ		 1153 break;
1154 }
1155#endif
1156}
1157
7e0d9562 1158static inline void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int opc)
811d4cf4 1159{
67dcab73 1160 int addr_reg, data_reg, data_reg2, bswap;
811d4cf4
AZ		 1161#ifdef CONFIG_SOFTMMU
1162 int mem_index, s_bits;
1163# if TARGET_LONG_BITS == 64
1164 int addr_reg2;
1165# endif
811d4cf4 1166 uint32_t *label_ptr;
811d4cf4
AZ		 1167#endif
1168
67dcab73
AJ		 1169#ifdef TARGET_WORDS_BIGENDIAN
1170 bswap = 1;
1171#else
1172 bswap = 0;
1173#endif
811d4cf4
AZ		 1174 data_reg = *args++;
1175 if (opc == 3)
1176 data_reg2 = *args++;
1177 else
d89c682f 1178 data_reg2 = 0; /* suppress warning */
811d4cf4 1179 addr_reg = *args++;
811d4cf4 1180#ifdef CONFIG_SOFTMMU
aef3a282
AZ		 1181# if TARGET_LONG_BITS == 64
1182 addr_reg2 = *args++;
1183# endif
811d4cf4
AZ		 1184 mem_index = *args;
1185 s_bits = opc & 3;
1186
91a3c1b0 1187 /* Should generate something like the following:
3979144c 1188 * shr r8, addr_reg, #TARGET_PAGE_BITS
91a3c1b0 1189 * and r0, r8, #(CPU_TLB_SIZE - 1) @ Assumption: CPU_TLB_BITS <= 8
3979144c 1190 * add r0, env, r0 lsl #CPU_TLB_ENTRY_BITS
91a3c1b0 1191 */
811d4cf4 1192 tcg_out_dat_reg(s, COND_AL, ARITH_MOV,
c8d80cef 1193 TCG_REG_R8, 0, addr_reg, SHIFT_IMM_LSR(TARGET_PAGE_BITS));
811d4cf4 1194 tcg_out_dat_imm(s, COND_AL, ARITH_AND,
c8d80cef
AJ		 1195 TCG_REG_R0, TCG_REG_R8, CPU_TLB_SIZE - 1);
1196 tcg_out_dat_reg(s, COND_AL, ARITH_ADD, TCG_REG_R0,
1197 TCG_AREG0, TCG_REG_R0, SHIFT_IMM_LSL(CPU_TLB_ENTRY_BITS));
91a3c1b0
AZ		 1198 /* In the
1199 * ldr r1 [r0, #(offsetof(CPUState, tlb_table[mem_index][0].addr_write))]
1200 * below, the offset is likely to exceed 12 bits if mem_index != 0 and
1201 * not exceed otherwise, so use an
1202 * add r0, r0, #(mem_index * sizeof *CPUState.tlb_table)
1203 * before.
1204 */
225b4376 1205 if (mem_index)
c8d80cef 1206 tcg_out_dat_imm(s, COND_AL, ARITH_ADD, TCG_REG_R0, TCG_REG_R0,
225b4376
AZ		 1207 (mem_index << (TLB_SHIFT & 1)) |
1208 ((16 - (TLB_SHIFT >> 1)) << 8));
c8d80cef 1209 tcg_out_ld32_12(s, COND_AL, TCG_REG_R1, TCG_REG_R0,
225b4376 1210 offsetof(CPUState, tlb_table[0][0].addr_write));
c8d80cef
AJ		 1211 tcg_out_dat_reg(s, COND_AL, ARITH_CMP, 0, TCG_REG_R1,
1212 TCG_REG_R8, SHIFT_IMM_LSL(TARGET_PAGE_BITS));
3979144c
PB		 1213 /* Check alignment. */
1214 if (s_bits)
1215 tcg_out_dat_imm(s, COND_EQ, ARITH_TST,
1216 0, addr_reg, (1 << s_bits) - 1);
811d4cf4
AZ		 1217# if TARGET_LONG_BITS == 64
1218 /* XXX: possibly we could use a block data load or writeback in
1219 * the first access. */
c8d80cef
AJ		 1220 tcg_out_ld32_12(s, COND_EQ, TCG_REG_R1, TCG_REG_R0,
1221 offsetof(CPUState, tlb_table[0][0].addr_write) + 4);
1222 tcg_out_dat_reg(s, COND_EQ, ARITH_CMP, 0,
1223 TCG_REG_R1, addr_reg2, SHIFT_IMM_LSL(0));
811d4cf4 1224# endif
c8d80cef 1225 tcg_out_ld32_12(s, COND_EQ, TCG_REG_R1, TCG_REG_R0,
225b4376 1226 offsetof(CPUState, tlb_table[0][0].addend));
811d4cf4
AZ		 1227
1228 switch (opc) {
1229 case 0:
c8d80cef 1230 tcg_out_st8_r(s, COND_EQ, data_reg, addr_reg, TCG_REG_R1);
811d4cf4 1231 break;
811d4cf4 1232 case 1:
67dcab73
AJ		 1233 if (bswap) {
1234 tcg_out_bswap16(s, COND_EQ, TCG_REG_R0, data_reg);
1235 tcg_out_st16_r(s, COND_EQ, TCG_REG_R0, addr_reg, TCG_REG_R1);
1236 } else {
1237 tcg_out_st16_r(s, COND_EQ, data_reg, addr_reg, TCG_REG_R1);
1238 }
811d4cf4
AZ		 1239 break;
1240 case 2:
1241 default:
67dcab73
AJ		 1242 if (bswap) {
1243 tcg_out_bswap32(s, COND_EQ, TCG_REG_R0, data_reg);
1244 tcg_out_st32_r(s, COND_EQ, TCG_REG_R0, addr_reg, TCG_REG_R1);
1245 } else {
1246 tcg_out_st32_r(s, COND_EQ, data_reg, addr_reg, TCG_REG_R1);
1247 }
811d4cf4
AZ		 1248 break;
1249 case 3:
67dcab73
AJ		 1250 if (bswap) {
1251 tcg_out_bswap32(s, COND_EQ, TCG_REG_R0, data_reg2);
1252 tcg_out_st32_rwb(s, COND_EQ, TCG_REG_R0, TCG_REG_R1, addr_reg);
1253 tcg_out_bswap32(s, COND_EQ, TCG_REG_R0, data_reg);
9a3abc21 1254 tcg_out_st32_12(s, COND_EQ, TCG_REG_R0, TCG_REG_R1, 4);
67dcab73
AJ		 1255 } else {
1256 tcg_out_st32_rwb(s, COND_EQ, data_reg, TCG_REG_R1, addr_reg);
1257 tcg_out_st32_12(s, COND_EQ, data_reg2, TCG_REG_R1, 4);
1258 }
811d4cf4
AZ		 1259 break;
1260 }
1261
1262 label_ptr = (void *) s->code_ptr;
c69806ab 1263 tcg_out_b_noaddr(s, COND_EQ);
811d4cf4 1264
811d4cf4 1265 /* TODO: move this code to where the constants pool will be */
2633a2d0
AJ		 1266 tcg_out_dat_reg(s, COND_AL, ARITH_MOV,
1267 TCG_REG_R0, 0, addr_reg, SHIFT_IMM_LSL(0));
811d4cf4
AZ		 1268# if TARGET_LONG_BITS == 32
1269 switch (opc) {
1270 case 0:
e854b6d3 1271 tcg_out_ext8u(s, COND_AL, TCG_REG_R1, data_reg);
7e0d9562 1272 tcg_out_dat_imm(s, COND_AL, ARITH_MOV, TCG_REG_R2, 0, mem_index);
811d4cf4
AZ		 1273 break;
1274 case 1:
e854b6d3 1275 tcg_out_ext16u(s, COND_AL, TCG_REG_R1, data_reg);
7e0d9562 1276 tcg_out_dat_imm(s, COND_AL, ARITH_MOV, TCG_REG_R2, 0, mem_index);
811d4cf4
AZ		 1277 break;
1278 case 2:
2633a2d0
AJ		 1279 tcg_out_dat_reg(s, COND_AL, ARITH_MOV,
1280 TCG_REG_R1, 0, data_reg, SHIFT_IMM_LSL(0));
7e0d9562 1281 tcg_out_dat_imm(s, COND_AL, ARITH_MOV, TCG_REG_R2, 0, mem_index);
811d4cf4
AZ		 1282 break;
1283 case 3:
bf5675ef
AJ		 1284 tcg_out_dat_imm(s, COND_AL, ARITH_MOV, TCG_REG_R8, 0, mem_index);
1285 tcg_out32(s, (COND_AL << 28) | 0x052d8010); /* str r8, [sp, #-0x10]! */
1286 if (data_reg != TCG_REG_R2) {
7e0d9562 1287 tcg_out_dat_reg(s, COND_AL, ARITH_MOV,
bf5675ef
AJ		 1288 TCG_REG_R2, 0, data_reg, SHIFT_IMM_LSL(0));
1289 }
1290 if (data_reg2 != TCG_REG_R3) {
1291 tcg_out_dat_reg(s, COND_AL, ARITH_MOV,
1292 TCG_REG_R3, 0, data_reg2, SHIFT_IMM_LSL(0));
c8d80cef 1293 }
811d4cf4
AZ		 1294 break;
1295 }
1296# else
2633a2d0
AJ		 1297 tcg_out_dat_reg(s, COND_AL, ARITH_MOV,
1298 TCG_REG_R1, 0, addr_reg2, SHIFT_IMM_LSL(0));
811d4cf4
AZ		 1299 switch (opc) {
1300 case 0:
e854b6d3 1301 tcg_out_ext8u(s, COND_AL, TCG_REG_R2, data_reg);
7e0d9562 1302 tcg_out_dat_imm(s, COND_AL, ARITH_MOV, TCG_REG_R3, 0, mem_index);
811d4cf4
AZ		 1303 break;
1304 case 1:
e854b6d3 1305 tcg_out_ext16u(s, COND_AL, TCG_REG_R2, data_reg);
7e0d9562 1306 tcg_out_dat_imm(s, COND_AL, ARITH_MOV, TCG_REG_R3, 0, mem_index);
811d4cf4
AZ		 1307 break;
1308 case 2:
c8d80cef 1309 if (data_reg != TCG_REG_R2) {
7e0d9562 1310 tcg_out_dat_reg(s, COND_AL, ARITH_MOV,
c8d80cef
AJ		 1311 TCG_REG_R2, 0, data_reg, SHIFT_IMM_LSL(0));
1312 }
7e0d9562 1313 tcg_out_dat_imm(s, COND_AL, ARITH_MOV, TCG_REG_R3, 0, mem_index);
811d4cf4
AZ		 1314 break;
1315 case 3:
7e0d9562
AJ		 1316 tcg_out_dat_imm(s, COND_AL, ARITH_MOV, TCG_REG_R8, 0, mem_index);
1317 tcg_out32(s, (COND_AL << 28) | 0x052d8010); /* str r8, [sp, #-0x10]! */
c8d80cef 1318 if (data_reg != TCG_REG_R2) {
7e0d9562 1319 tcg_out_dat_reg(s, COND_AL, ARITH_MOV,
c8d80cef
AJ		 1320 TCG_REG_R2, 0, data_reg, SHIFT_IMM_LSL(0));
1321 }
1322 if (data_reg2 != TCG_REG_R3) {
7e0d9562 1323 tcg_out_dat_reg(s, COND_AL, ARITH_MOV,
c8d80cef
AJ		 1324 TCG_REG_R3, 0, data_reg2, SHIFT_IMM_LSL(0));
1325 }
811d4cf4
AZ		 1326 break;
1327 }
1328# endif
1329
7e0d9562 1330 tcg_out_bl(s, COND_AL, (tcg_target_long) qemu_st_helpers[s_bits] -
811d4cf4 1331 (tcg_target_long) s->code_ptr);
811d4cf4 1332 if (opc == 3)
7e0d9562 1333 tcg_out_dat_imm(s, COND_AL, ARITH_ADD, TCG_REG_R13, TCG_REG_R13, 0x10);
811d4cf4 1334
c69806ab 1335 reloc_pc24(label_ptr, (tcg_target_long)s->code_ptr);
379f6698
PB		 1336#else /* !CONFIG_SOFTMMU */
1337 if (GUEST_BASE) {
1338 uint32_t offset = GUEST_BASE;
1339 int i;
1340 int rot;
1341
1342 while (offset) {
1343 i = ctz32(offset) & ~1;
1344 rot = ((32 - i) << 7) & 0xf00;
1345
67dcab73 1346 tcg_out_dat_imm(s, COND_AL, ARITH_ADD, TCG_REG_R1, addr_reg,
379f6698 1347 ((offset >> i) & 0xff) | rot);
67dcab73 1348 addr_reg = TCG_REG_R1;
379f6698
PB		 1349 offset &= ~(0xff << i);
1350 }
1351 }
811d4cf4
AZ		 1352 switch (opc) {
1353 case 0:
1354 tcg_out_st8_12(s, COND_AL, data_reg, addr_reg, 0);
1355 break;
811d4cf4 1356 case 1:
67dcab73
AJ		 1357 if (bswap) {
1358 tcg_out_bswap16(s, COND_AL, TCG_REG_R0, data_reg);
1359 tcg_out_st16_8(s, COND_AL, TCG_REG_R0, addr_reg, 0);
1360 } else {
1361 tcg_out_st16_8(s, COND_AL, data_reg, addr_reg, 0);
1362 }
811d4cf4
AZ		 1363 break;
1364 case 2:
1365 default:
67dcab73
AJ		 1366 if (bswap) {
1367 tcg_out_bswap32(s, COND_AL, TCG_REG_R0, data_reg);
1368 tcg_out_st32_12(s, COND_AL, TCG_REG_R0, addr_reg, 0);
1369 } else {
1370 tcg_out_st32_12(s, COND_AL, data_reg, addr_reg, 0);
1371 }
811d4cf4
AZ		 1372 break;
1373 case 3:
eae6ce52
AZ		 1374 /* TODO: use block store -
1375 * check that data_reg2 > data_reg or the other way */
67dcab73
AJ		 1376 if (bswap) {
1377 tcg_out_bswap32(s, COND_AL, TCG_REG_R0, data_reg2);
1378 tcg_out_st32_12(s, COND_AL, TCG_REG_R0, addr_reg, 0);
1379 tcg_out_bswap32(s, COND_AL, TCG_REG_R0, data_reg);
1380 tcg_out_st32_12(s, COND_AL, TCG_REG_R0, addr_reg, 4);
1381 } else {
1382 tcg_out_st32_12(s, COND_AL, data_reg, addr_reg, 0);
1383 tcg_out_st32_12(s, COND_AL, data_reg2, addr_reg, 4);
1384 }
811d4cf4
AZ		 1385 break;
1386 }
1387#endif
1388}
1389
811d4cf4
AZ		 1390static uint8_t *tb_ret_addr;
1391
a9751609 1392static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
811d4cf4
AZ		 1393 const TCGArg *args, const int *const_args)
1394{
1395 int c;
1396
1397 switch (opc) {
1398 case INDEX_op_exit_tb:
fe33867b
AZ		 1399 {
1400 uint8_t *ld_ptr = s->code_ptr;
1401 if (args[0] >> 8)
c8d80cef 1402 tcg_out_ld32_12(s, COND_AL, TCG_REG_R0, TCG_REG_PC, 0);
fe33867b 1403 else
c8d80cef 1404 tcg_out_dat_imm(s, COND_AL, ARITH_MOV, TCG_REG_R0, 0, args[0]);
fe33867b
AZ		 1405 tcg_out_goto(s, COND_AL, (tcg_target_ulong) tb_ret_addr);
1406 if (args[0] >> 8) {
1407 *ld_ptr = (uint8_t) (s->code_ptr - ld_ptr) - 8;
1408 tcg_out32(s, args[0]);
1409 }
1410 }
811d4cf4
AZ		 1411 break;
1412 case INDEX_op_goto_tb:
1413 if (s->tb_jmp_offset) {
1414 /* Direct jump method */
fe33867b 1415#if defined(USE_DIRECT_JUMP)
811d4cf4 1416 s->tb_jmp_offset[args[0]] = s->code_ptr - s->code_buf;
c69806ab 1417 tcg_out_b_noaddr(s, COND_AL);
811d4cf4 1418#else
c8d80cef 1419 tcg_out_ld32_12(s, COND_AL, TCG_REG_PC, TCG_REG_PC, -4);
811d4cf4
AZ		 1420 s->tb_jmp_offset[args[0]] = s->code_ptr - s->code_buf;
1421 tcg_out32(s, 0);
1422#endif
1423 } else {
1424 /* Indirect jump method */
1425#if 1
1426 c = (int) (s->tb_next + args[0]) - ((int) s->code_ptr + 8);
1427 if (c > 0xfff || c < -0xfff) {
1428 tcg_out_movi32(s, COND_AL, TCG_REG_R0,
1429 (tcg_target_long) (s->tb_next + args[0]));
c8d80cef 1430 tcg_out_ld32_12(s, COND_AL, TCG_REG_PC, TCG_REG_R0, 0);
811d4cf4 1431 } else
c8d80cef 1432 tcg_out_ld32_12(s, COND_AL, TCG_REG_PC, TCG_REG_PC, c);
811d4cf4 1433#else
c8d80cef
AJ		 1434 tcg_out_ld32_12(s, COND_AL, TCG_REG_R0, TCG_REG_PC, 0);
1435 tcg_out_ld32_12(s, COND_AL, TCG_REG_PC, TCG_REG_R0, 0);
811d4cf4
AZ		 1436 tcg_out32(s, (tcg_target_long) (s->tb_next + args[0]));
1437#endif
1438 }
1439 s->tb_next_offset[args[0]] = s->code_ptr - s->code_buf;
1440 break;
1441 case INDEX_op_call:
1442 if (const_args[0])
1443 tcg_out_call(s, COND_AL, args[0]);
1444 else
1445 tcg_out_callr(s, COND_AL, args[0]);
1446 break;
1447 case INDEX_op_jmp:
1448 if (const_args[0])
1449 tcg_out_goto(s, COND_AL, args[0]);
1450 else
1451 tcg_out_bx(s, COND_AL, args[0]);
1452 break;
1453 case INDEX_op_br:
1454 tcg_out_goto_label(s, COND_AL, args[0]);
1455 break;
1456
1457 case INDEX_op_ld8u_i32:
1458 tcg_out_ld8u(s, COND_AL, args[0], args[1], args[2]);
1459 break;
1460 case INDEX_op_ld8s_i32:
1461 tcg_out_ld8s(s, COND_AL, args[0], args[1], args[2]);
1462 break;
1463 case INDEX_op_ld16u_i32:
1464 tcg_out_ld16u(s, COND_AL, args[0], args[1], args[2]);
1465 break;
1466 case INDEX_op_ld16s_i32:
1467 tcg_out_ld16s(s, COND_AL, args[0], args[1], args[2]);
1468 break;
1469 case INDEX_op_ld_i32:
1470 tcg_out_ld32u(s, COND_AL, args[0], args[1], args[2]);
1471 break;
1472 case INDEX_op_st8_i32:
f694a27e 1473 tcg_out_st8(s, COND_AL, args[0], args[1], args[2]);
811d4cf4
AZ		 1474 break;
1475 case INDEX_op_st16_i32:
f694a27e 1476 tcg_out_st16(s, COND_AL, args[0], args[1], args[2]);
811d4cf4
AZ		 1477 break;
1478 case INDEX_op_st_i32:
1479 tcg_out_st32(s, COND_AL, args[0], args[1], args[2]);
1480 break;
1481
1482 case INDEX_op_mov_i32:
1483 tcg_out_dat_reg(s, COND_AL, ARITH_MOV,
1484 args[0], 0, args[1], SHIFT_IMM_LSL(0));
1485 break;
1486 case INDEX_op_movi_i32:
1487 tcg_out_movi32(s, COND_AL, args[0], args[1]);
1488 break;
1489 case INDEX_op_add_i32:
1490 c = ARITH_ADD;
1491 goto gen_arith;
1492 case INDEX_op_sub_i32:
1493 c = ARITH_SUB;
1494 goto gen_arith;
1495 case INDEX_op_and_i32:
1496 c = ARITH_AND;
1497 goto gen_arith;
932234f6
AJ		 1498 case INDEX_op_andc_i32:
1499 c = ARITH_BIC;
1500 goto gen_arith;
811d4cf4
AZ		 1501 case INDEX_op_or_i32:
1502 c = ARITH_ORR;
1503 goto gen_arith;
1504 case INDEX_op_xor_i32:
1505 c = ARITH_EOR;
1506 /* Fall through. */
1507 gen_arith:
94953e6d
LD		 1508 if (const_args[2]) {
1509 int rot;
1510 rot = encode_imm(args[2]);
cb4e581f 1511 tcg_out_dat_imm(s, COND_AL, c,
94953e6d
LD		 1512 args[0], args[1], rotl(args[2], rot) | (rot << 7));
1513 } else
cb4e581f
LD		 1514 tcg_out_dat_reg(s, COND_AL, c,
1515 args[0], args[1], args[2], SHIFT_IMM_LSL(0));
811d4cf4
AZ		 1516 break;
1517 case INDEX_op_add2_i32:
1518 tcg_out_dat_reg2(s, COND_AL, ARITH_ADD, ARITH_ADC,
1519 args[0], args[1], args[2], args[3],
1520 args[4], args[5], SHIFT_IMM_LSL(0));
1521 break;
1522 case INDEX_op_sub2_i32:
1523 tcg_out_dat_reg2(s, COND_AL, ARITH_SUB, ARITH_SBC,
1524 args[0], args[1], args[2], args[3],
1525 args[4], args[5], SHIFT_IMM_LSL(0));
1526 break;
650bbb36
AZ		 1527 case INDEX_op_neg_i32:
1528 tcg_out_dat_imm(s, COND_AL, ARITH_RSB, args[0], args[1], 0);
1529 break;
f878d2d2
LD		 1530 case INDEX_op_not_i32:
1531 tcg_out_dat_reg(s, COND_AL,
1532 ARITH_MVN, args[0], 0, args[1], SHIFT_IMM_LSL(0));
1533 break;
811d4cf4
AZ		 1534 case INDEX_op_mul_i32:
1535 tcg_out_mul32(s, COND_AL, args[0], args[1], args[2]);
1536 break;
1537 case INDEX_op_mulu2_i32:
1538 tcg_out_umull32(s, COND_AL, args[0], args[1], args[2], args[3]);
1539 break;
811d4cf4
AZ		 1540 /* XXX: Perhaps args[2] & 0x1f is wrong */
1541 case INDEX_op_shl_i32:
1542 c = const_args[2] ?
1543 SHIFT_IMM_LSL(args[2] & 0x1f) : SHIFT_REG_LSL(args[2]);
1544 goto gen_shift32;
1545 case INDEX_op_shr_i32:
1546 c = const_args[2] ? (args[2] & 0x1f) ? SHIFT_IMM_LSR(args[2] & 0x1f) :
1547 SHIFT_IMM_LSL(0) : SHIFT_REG_LSR(args[2]);
1548 goto gen_shift32;
1549 case INDEX_op_sar_i32:
1550 c = const_args[2] ? (args[2] & 0x1f) ? SHIFT_IMM_ASR(args[2] & 0x1f) :
1551 SHIFT_IMM_LSL(0) : SHIFT_REG_ASR(args[2]);
293579e5
AJ		 1552 goto gen_shift32;
1553 case INDEX_op_rotr_i32:
1554 c = const_args[2] ? (args[2] & 0x1f) ? SHIFT_IMM_ROR(args[2] & 0x1f) :
1555 SHIFT_IMM_LSL(0) : SHIFT_REG_ROR(args[2]);
811d4cf4
AZ		 1556 /* Fall through. */
1557 gen_shift32:
1558 tcg_out_dat_reg(s, COND_AL, ARITH_MOV, args[0], 0, args[1], c);
1559 break;
1560
293579e5
AJ		 1561 case INDEX_op_rotl_i32:
1562 if (const_args[2]) {
1563 tcg_out_dat_reg(s, COND_AL, ARITH_MOV, args[0], 0, args[1],
1564 ((0x20 - args[2]) & 0x1f) ?
1565 SHIFT_IMM_ROR((0x20 - args[2]) & 0x1f) :
1566 SHIFT_IMM_LSL(0));
1567 } else {
1568 tcg_out_dat_imm(s, COND_AL, ARITH_RSB, TCG_REG_R8, args[1], 0x20);
1569 tcg_out_dat_reg(s, COND_AL, ARITH_MOV, args[0], 0, args[1],
1570 SHIFT_REG_ROR(TCG_REG_R8));
1571 }
1572 break;
1573
811d4cf4 1574 case INDEX_op_brcond_i32:
023e77f8
AJ		 1575 if (const_args[1]) {
1576 int rot;
1577 rot = encode_imm(args[1]);
c8d80cef
AJ		 1578 tcg_out_dat_imm(s, COND_AL, ARITH_CMP, 0,
1579 args[0], rotl(args[1], rot) | (rot << 7));
023e77f8
AJ		 1580 } else {
1581 tcg_out_dat_reg(s, COND_AL, ARITH_CMP, 0,
1582 args[0], args[1], SHIFT_IMM_LSL(0));
1583 }
811d4cf4
AZ		 1584 tcg_out_goto_label(s, tcg_cond_to_arm_cond[args[2]], args[3]);
1585 break;
1586 case INDEX_op_brcond2_i32:
1587 /* The resulting conditions are:
1588 * TCG_COND_EQ --> a0 == a2 && a1 == a3,
1589 * TCG_COND_NE --> (a0 != a2 && a1 == a3) || a1 != a3,
1590 * TCG_COND_LT(U) --> (a0 < a2 && a1 == a3) || a1 < a3,
1591 * TCG_COND_GE(U) --> (a0 >= a2 && a1 == a3) || (a1 >= a3 && a1 != a3),
1592 * TCG_COND_LE(U) --> (a0 <= a2 && a1 == a3) || (a1 <= a3 && a1 != a3),
1593 * TCG_COND_GT(U) --> (a0 > a2 && a1 == a3) || a1 > a3,
1594 */
1595 tcg_out_dat_reg(s, COND_AL, ARITH_CMP, 0,
1596 args[1], args[3], SHIFT_IMM_LSL(0));
1597 tcg_out_dat_reg(s, COND_EQ, ARITH_CMP, 0,
1598 args[0], args[2], SHIFT_IMM_LSL(0));
1599 tcg_out_goto_label(s, tcg_cond_to_arm_cond[args[4]], args[5]);
1600 break;
f72a6cd7 1601 case INDEX_op_setcond_i32:
023e77f8
AJ		 1602 if (const_args[2]) {
1603 int rot;
1604 rot = encode_imm(args[2]);
c8d80cef
AJ		 1605 tcg_out_dat_imm(s, COND_AL, ARITH_CMP, 0,
1606 args[1], rotl(args[2], rot) | (rot << 7));
023e77f8
AJ		 1607 } else {
1608 tcg_out_dat_reg(s, COND_AL, ARITH_CMP, 0,
1609 args[1], args[2], SHIFT_IMM_LSL(0));
1610 }
f72a6cd7
AJ		 1611 tcg_out_dat_imm(s, tcg_cond_to_arm_cond[args[3]],
1612 ARITH_MOV, args[0], 0, 1);
1613 tcg_out_dat_imm(s, tcg_cond_to_arm_cond[tcg_invert_cond(args[3])],
1614 ARITH_MOV, args[0], 0, 0);
1615 break;
e0404769
AJ		 1616 case INDEX_op_setcond2_i32:
1617 /* See brcond2_i32 comment */
1618 tcg_out_dat_reg(s, COND_AL, ARITH_CMP, 0,
1619 args[2], args[4], SHIFT_IMM_LSL(0));
1620 tcg_out_dat_reg(s, COND_EQ, ARITH_CMP, 0,
1621 args[1], args[3], SHIFT_IMM_LSL(0));
1622 tcg_out_dat_imm(s, tcg_cond_to_arm_cond[args[5]],
1623 ARITH_MOV, args[0], 0, 1);
1624 tcg_out_dat_imm(s, tcg_cond_to_arm_cond[tcg_invert_cond(args[5])],
1625 ARITH_MOV, args[0], 0, 0);
b525f0a9 1626 break;
811d4cf4
AZ		 1627
1628 case INDEX_op_qemu_ld8u:
7e0d9562 1629 tcg_out_qemu_ld(s, args, 0);
811d4cf4
AZ		 1630 break;
1631 case INDEX_op_qemu_ld8s:
7e0d9562 1632 tcg_out_qemu_ld(s, args, 0 | 4);
811d4cf4
AZ		 1633 break;
1634 case INDEX_op_qemu_ld16u:
7e0d9562 1635 tcg_out_qemu_ld(s, args, 1);
811d4cf4
AZ		 1636 break;
1637 case INDEX_op_qemu_ld16s:
7e0d9562 1638 tcg_out_qemu_ld(s, args, 1 | 4);
811d4cf4 1639 break;
86feb1c8 1640 case INDEX_op_qemu_ld32:
7e0d9562 1641 tcg_out_qemu_ld(s, args, 2);
811d4cf4
AZ		 1642 break;
1643 case INDEX_op_qemu_ld64:
7e0d9562 1644 tcg_out_qemu_ld(s, args, 3);
811d4cf4 1645 break;
650bbb36 1646
811d4cf4 1647 case INDEX_op_qemu_st8:
7e0d9562 1648 tcg_out_qemu_st(s, args, 0);
811d4cf4
AZ		 1649 break;
1650 case INDEX_op_qemu_st16:
7e0d9562 1651 tcg_out_qemu_st(s, args, 1);
811d4cf4
AZ		 1652 break;
1653 case INDEX_op_qemu_st32:
7e0d9562 1654 tcg_out_qemu_st(s, args, 2);
811d4cf4
AZ		 1655 break;
1656 case INDEX_op_qemu_st64:
7e0d9562 1657 tcg_out_qemu_st(s, args, 3);
811d4cf4
AZ		 1658 break;
1659
244b1e81
AJ		 1660 case INDEX_op_bswap16_i32:
1661 tcg_out_bswap16(s, COND_AL, args[0], args[1]);
1662 break;
1663 case INDEX_op_bswap32_i32:
1664 tcg_out_bswap32(s, COND_AL, args[0], args[1]);
1665 break;
1666
811d4cf4 1667 case INDEX_op_ext8s_i32:
9517094f 1668 tcg_out_ext8s(s, COND_AL, args[0], args[1]);
811d4cf4
AZ		 1669 break;
1670 case INDEX_op_ext16s_i32:
9517094f
AJ		 1671 tcg_out_ext16s(s, COND_AL, args[0], args[1]);
1672 break;
1673 case INDEX_op_ext16u_i32:
1674 tcg_out_ext16u(s, COND_AL, args[0], args[1]);
811d4cf4
AZ		 1675 break;
1676
1677 default:
1678 tcg_abort();
1679 }
1680}
1681
1682static const TCGTargetOpDef arm_op_defs[] = {
1683 { INDEX_op_exit_tb, { } },
1684 { INDEX_op_goto_tb, { } },
1685 { INDEX_op_call, { "ri" } },
1686 { INDEX_op_jmp, { "ri" } },
1687 { INDEX_op_br, { } },
1688
1689 { INDEX_op_mov_i32, { "r", "r" } },
1690 { INDEX_op_movi_i32, { "r" } },
1691
1692 { INDEX_op_ld8u_i32, { "r", "r" } },
1693 { INDEX_op_ld8s_i32, { "r", "r" } },
1694 { INDEX_op_ld16u_i32, { "r", "r" } },
1695 { INDEX_op_ld16s_i32, { "r", "r" } },
1696 { INDEX_op_ld_i32, { "r", "r" } },
1697 { INDEX_op_st8_i32, { "r", "r" } },
1698 { INDEX_op_st16_i32, { "r", "r" } },
1699 { INDEX_op_st_i32, { "r", "r" } },
1700
1701 /* TODO: "r", "r", "ri" */
cb4e581f
LD		 1702 { INDEX_op_add_i32, { "r", "r", "rI" } },
1703 { INDEX_op_sub_i32, { "r", "r", "rI" } },
811d4cf4
AZ		 1704 { INDEX_op_mul_i32, { "r", "r", "r" } },
1705 { INDEX_op_mulu2_i32, { "r", "r", "r", "r" } },
cb4e581f 1706 { INDEX_op_and_i32, { "r", "r", "rI" } },
932234f6 1707 { INDEX_op_andc_i32, { "r", "r", "rI" } },
cb4e581f
LD		 1708 { INDEX_op_or_i32, { "r", "r", "rI" } },
1709 { INDEX_op_xor_i32, { "r", "r", "rI" } },
650bbb36 1710 { INDEX_op_neg_i32, { "r", "r" } },
f878d2d2 1711 { INDEX_op_not_i32, { "r", "r" } },
811d4cf4
AZ		 1712
1713 { INDEX_op_shl_i32, { "r", "r", "ri" } },
1714 { INDEX_op_shr_i32, { "r", "r", "ri" } },
1715 { INDEX_op_sar_i32, { "r", "r", "ri" } },
293579e5
AJ		 1716 { INDEX_op_rotl_i32, { "r", "r", "ri" } },
1717 { INDEX_op_rotr_i32, { "r", "r", "ri" } },
811d4cf4 1718
023e77f8
AJ		 1719 { INDEX_op_brcond_i32, { "r", "rI" } },
1720 { INDEX_op_setcond_i32, { "r", "r", "rI" } },
811d4cf4
AZ		 1721
1722 /* TODO: "r", "r", "r", "r", "ri", "ri" */
1723 { INDEX_op_add2_i32, { "r", "r", "r", "r", "r", "r" } },
1724 { INDEX_op_sub2_i32, { "r", "r", "r", "r", "r", "r" } },
1725 { INDEX_op_brcond2_i32, { "r", "r", "r", "r" } },
e0404769 1726 { INDEX_op_setcond2_i32, { "r", "r", "r", "r", "r" } },
811d4cf4 1727
26c5d372 1728#if TARGET_LONG_BITS == 32
67dcab73
AJ		 1729 { INDEX_op_qemu_ld8u, { "r", "l" } },
1730 { INDEX_op_qemu_ld8s, { "r", "l" } },
1731 { INDEX_op_qemu_ld16u, { "r", "l" } },
1732 { INDEX_op_qemu_ld16s, { "r", "l" } },
1733 { INDEX_op_qemu_ld32, { "r", "l" } },
1734 { INDEX_op_qemu_ld64, { "L", "L", "l" } },
1735
1736 { INDEX_op_qemu_st8, { "s", "s" } },
1737 { INDEX_op_qemu_st16, { "s", "s" } },
1738 { INDEX_op_qemu_st32, { "s", "s" } },
bf5675ef 1739 { INDEX_op_qemu_st64, { "S", "S", "s" } },
26c5d372 1740#else
67dcab73
AJ		 1741 { INDEX_op_qemu_ld8u, { "r", "l", "l" } },
1742 { INDEX_op_qemu_ld8s, { "r", "l", "l" } },
1743 { INDEX_op_qemu_ld16u, { "r", "l", "l" } },
1744 { INDEX_op_qemu_ld16s, { "r", "l", "l" } },
1745 { INDEX_op_qemu_ld32, { "r", "l", "l" } },
1746 { INDEX_op_qemu_ld64, { "L", "L", "l", "l" } },
1747
1748 { INDEX_op_qemu_st8, { "s", "s", "s" } },
1749 { INDEX_op_qemu_st16, { "s", "s", "s" } },
1750 { INDEX_op_qemu_st32, { "s", "s", "s" } },
bf5675ef 1751 { INDEX_op_qemu_st64, { "S", "S", "s", "s" } },
26c5d372 1752#endif
811d4cf4 1753
244b1e81
AJ		 1754 { INDEX_op_bswap16_i32, { "r", "r" } },
1755 { INDEX_op_bswap32_i32, { "r", "r" } },
1756
811d4cf4
AZ		 1757 { INDEX_op_ext8s_i32, { "r", "r" } },
1758 { INDEX_op_ext16s_i32, { "r", "r" } },
9517094f 1759 { INDEX_op_ext16u_i32, { "r", "r" } },
811d4cf4
AZ		 1760
1761 { -1 },
1762};
1763
e4d58b41 1764static void tcg_target_init(TCGContext *s)
811d4cf4 1765{
20cb400d 1766#if !defined(CONFIG_USER_ONLY)
811d4cf4
AZ		 1767 /* fail safe */
1768 if ((1 << CPU_TLB_ENTRY_BITS) != sizeof(CPUTLBEntry))
1769 tcg_abort();
20cb400d 1770#endif
811d4cf4 1771
e4a7d5e8 1772 tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0, 0xffff);
811d4cf4 1773 tcg_regset_set32(tcg_target_call_clobber_regs, 0,
e4a7d5e8
AJ		 1774 (1 << TCG_REG_R0) |
1775 (1 << TCG_REG_R1) |
1776 (1 << TCG_REG_R2) |
1777 (1 << TCG_REG_R3) |
1778 (1 << TCG_REG_R12) |
1779 (1 << TCG_REG_R14));
811d4cf4
AZ		 1780
1781 tcg_regset_clear(s->reserved_regs);
811d4cf4
AZ		 1782 tcg_regset_set_reg(s->reserved_regs, TCG_REG_CALL_STACK);
1783 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R8);
e4a7d5e8 1784 tcg_regset_set_reg(s->reserved_regs, TCG_REG_PC);
811d4cf4
AZ		 1785
1786 tcg_add_target_add_op_defs(arm_op_defs);
1787}
1788
1789static inline void tcg_out_ld(TCGContext *s, TCGType type, int arg,
1790 int arg1, tcg_target_long arg2)
1791{
1792 tcg_out_ld32u(s, COND_AL, arg, arg1, arg2);
1793}
1794
1795static inline void tcg_out_st(TCGContext *s, TCGType type, int arg,
1796 int arg1, tcg_target_long arg2)
1797{
1798 tcg_out_st32(s, COND_AL, arg, arg1, arg2);
1799}
1800
2d69f359 1801static void tcg_out_addi(TCGContext *s, int reg, tcg_target_long val)
811d4cf4
AZ		 1802{
1803 if (val > 0)
1804 if (val < 0x100)
1805 tcg_out_dat_imm(s, COND_AL, ARITH_ADD, reg, reg, val);
1806 else
1807 tcg_abort();
1808 else if (val < 0) {
1809 if (val > -0x100)
1810 tcg_out_dat_imm(s, COND_AL, ARITH_SUB, reg, reg, -val);
1811 else
1812 tcg_abort();
1813 }
1814}
1815
3b6dac34 1816static inline void tcg_out_mov(TCGContext *s, TCGType type, int ret, int arg)
811d4cf4
AZ		 1817{
1818 tcg_out_dat_reg(s, COND_AL, ARITH_MOV, ret, 0, arg, SHIFT_IMM_LSL(0));
1819}
1820
1821static inline void tcg_out_movi(TCGContext *s, TCGType type,
1822 int ret, tcg_target_long arg)
1823{
1824 tcg_out_movi32(s, COND_AL, ret, arg);
1825}
1826
e4d58b41 1827static void tcg_target_qemu_prologue(TCGContext *s)
811d4cf4 1828{
9e97d8e9
AJ		 1829 /* There is no need to save r7, it is used to store the address
1830 of the env structure and is not modified by GCC. */
4e17eae9 1831
9e97d8e9
AJ		 1832 /* stmdb sp!, { r4 - r6, r8 - r11, lr } */
1833 tcg_out32(s, (COND_AL << 28) | 0x092d4f70);
811d4cf4
AZ		 1834
1835 tcg_out_bx(s, COND_AL, TCG_REG_R0);
1836 tb_ret_addr = s->code_ptr;
1837
9e97d8e9
AJ		 1838 /* ldmia sp!, { r4 - r6, r8 - r11, pc } */
1839 tcg_out32(s, (COND_AL << 28) | 0x08bd8f70);
811d4cf4 1840}
Qemu copy for testing