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afa05235 AJ |
1 | /* |
2 | * Tiny Code Generator for QEMU | |
3 | * | |
4 | * Copyright (c) 2008-2009 Arnaud Patard <arnaud.patard@rtp-net.org> | |
5 | * Copyright (c) 2009 Aurelien Jarno <aurelien@aurel32.net> | |
6 | * Based on i386/tcg-target.c - Copyright (c) 2008 Fabrice Bellard | |
7 | * | |
8 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
9 | * of this software and associated documentation files (the "Software"), to deal | |
10 | * in the Software without restriction, including without limitation the rights | |
11 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
12 | * copies of the Software, and to permit persons to whom the Software is | |
13 | * furnished to do so, subject to the following conditions: | |
14 | * | |
15 | * The above copyright notice and this permission notice shall be included in | |
16 | * all copies or substantial portions of the Software. | |
17 | * | |
18 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
19 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
20 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
21 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
22 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
23 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
24 | * THE SOFTWARE. | |
25 | */ | |
cb9c377f | 26 | #ifndef TCG_TARGET_MIPS |
afa05235 AJ |
27 | #define TCG_TARGET_MIPS 1 |
28 | ||
afa05235 AJ |
29 | #ifdef __MIPSEB__ |
30 | # define TCG_TARGET_WORDS_BIGENDIAN | |
31 | #endif | |
32 | ||
33 | #define TCG_TARGET_NB_REGS 32 | |
34 | ||
771142c2 | 35 | typedef enum { |
afa05235 AJ |
36 | TCG_REG_ZERO = 0, |
37 | TCG_REG_AT, | |
38 | TCG_REG_V0, | |
39 | TCG_REG_V1, | |
40 | TCG_REG_A0, | |
41 | TCG_REG_A1, | |
42 | TCG_REG_A2, | |
43 | TCG_REG_A3, | |
44 | TCG_REG_T0, | |
45 | TCG_REG_T1, | |
46 | TCG_REG_T2, | |
47 | TCG_REG_T3, | |
48 | TCG_REG_T4, | |
49 | TCG_REG_T5, | |
50 | TCG_REG_T6, | |
51 | TCG_REG_T7, | |
52 | TCG_REG_S0, | |
53 | TCG_REG_S1, | |
54 | TCG_REG_S2, | |
55 | TCG_REG_S3, | |
56 | TCG_REG_S4, | |
57 | TCG_REG_S5, | |
58 | TCG_REG_S6, | |
59 | TCG_REG_S7, | |
60 | TCG_REG_T8, | |
61 | TCG_REG_T9, | |
62 | TCG_REG_K0, | |
63 | TCG_REG_K1, | |
64 | TCG_REG_GP, | |
65 | TCG_REG_SP, | |
66 | TCG_REG_FP, | |
67 | TCG_REG_RA, | |
771142c2 | 68 | } TCGReg; |
afa05235 AJ |
69 | |
70 | #define TCG_CT_CONST_ZERO 0x100 | |
71 | #define TCG_CT_CONST_U16 0x200 | |
72 | #define TCG_CT_CONST_S16 0x400 | |
73 | ||
74 | /* used for function call generation */ | |
75 | #define TCG_REG_CALL_STACK TCG_REG_SP | |
76 | #define TCG_TARGET_STACK_ALIGN 8 | |
77 | #define TCG_TARGET_CALL_STACK_OFFSET 16 | |
78 | #define TCG_TARGET_CALL_ALIGN_ARGS 1 | |
79 | ||
80 | /* optional instructions */ | |
25c4d9cc RH |
81 | #define TCG_TARGET_HAS_div_i32 1 |
82 | #define TCG_TARGET_HAS_not_i32 1 | |
83 | #define TCG_TARGET_HAS_nor_i32 1 | |
25c4d9cc RH |
84 | #define TCG_TARGET_HAS_ext8s_i32 1 |
85 | #define TCG_TARGET_HAS_ext16s_i32 1 | |
25c4d9cc RH |
86 | #define TCG_TARGET_HAS_andc_i32 0 |
87 | #define TCG_TARGET_HAS_orc_i32 0 | |
88 | #define TCG_TARGET_HAS_eqv_i32 0 | |
89 | #define TCG_TARGET_HAS_nand_i32 0 | |
7d7c4930 AJ |
90 | |
91 | /* optional instructions only implemented on MIPS4, MIPS32 and Loongson 2 */ | |
8f06bf69 AJ |
92 | #if (defined(__mips_isa_rev) && (__mips_isa_rev >= 1)) || \ |
93 | defined(_MIPS_ARCH_LOONGSON2E) || defined(_MIPS_ARCH_LOONGSON2F) || \ | |
94 | defined(_MIPS_ARCH_MIPS4) | |
7d7c4930 AJ |
95 | #define TCG_TARGET_HAS_movcond_i32 1 |
96 | #else | |
ffc5ea09 | 97 | #define TCG_TARGET_HAS_movcond_i32 0 |
7d7c4930 | 98 | #endif |
afa05235 | 99 | |
c1cf85c9 | 100 | /* optional instructions only implemented on MIPS32R2 */ |
8f06bf69 | 101 | #if defined(__mips_isa_rev) && (__mips_isa_rev >= 2) |
c1cf85c9 AJ |
102 | #define TCG_TARGET_HAS_bswap16_i32 1 |
103 | #define TCG_TARGET_HAS_bswap32_i32 1 | |
9a152519 | 104 | #define TCG_TARGET_HAS_rot_i32 1 |
04f71aa3 | 105 | #define TCG_TARGET_HAS_deposit_i32 1 |
c1cf85c9 AJ |
106 | #else |
107 | #define TCG_TARGET_HAS_bswap16_i32 0 | |
108 | #define TCG_TARGET_HAS_bswap32_i32 0 | |
9a152519 | 109 | #define TCG_TARGET_HAS_rot_i32 0 |
04f71aa3 | 110 | #define TCG_TARGET_HAS_deposit_i32 0 |
c1cf85c9 AJ |
111 | #endif |
112 | ||
afa05235 | 113 | /* optional instructions automatically implemented */ |
25c4d9cc RH |
114 | #define TCG_TARGET_HAS_neg_i32 0 /* sub rd, zero, rt */ |
115 | #define TCG_TARGET_HAS_ext8u_i32 0 /* andi rt, rs, 0xff */ | |
116 | #define TCG_TARGET_HAS_ext16u_i32 0 /* andi rt, rs, 0xffff */ | |
afa05235 | 117 | |
60bf84cf | 118 | #define TCG_AREG0 TCG_REG_S0 |
afa05235 | 119 | |
03938c13 B |
120 | #ifdef __OpenBSD__ |
121 | #include <machine/sysarch.h> | |
122 | #else | |
afa05235 | 123 | #include <sys/cachectl.h> |
03938c13 | 124 | #endif |
afa05235 | 125 | |
dba4f1bc SW |
126 | static inline void flush_icache_range(tcg_target_ulong start, |
127 | tcg_target_ulong stop) | |
afa05235 AJ |
128 | { |
129 | cacheflush ((void *)start, stop-start, ICACHE); | |
130 | } | |
cb9c377f PB |
131 | |
132 | #endif |