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TCGify the simplest FP instructions.
[qemu.git] / tcg / ppc / tcg-target.c
CommitLineData
2662e13f
FB		 1/*
2 * Tiny Code Generator for QEMU
3 *
4 * Copyright (c) 2008 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
25static uint8_t *tb_ret_addr;
26
2662e13f
FB		 27#define FAST_PATH
28#if TARGET_PHYS_ADDR_BITS <= 32
29#define ADDEND_OFFSET 0
30#else
31#define ADDEND_OFFSET 4
32#endif
33
34static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
35 "r0",
36 "r1",
37 "rp",
38 "r3",
39 "r4",
40 "r5",
41 "r6",
42 "r7",
43 "r8",
44 "r9",
45 "r10",
46 "r11",
47 "r12",
48 "r13",
49 "r14",
50 "r15",
51 "r16",
52 "r17",
53 "r18",
54 "r19",
55 "r20",
56 "r21",
57 "r22",
58 "r23",
59 "r24",
60 "r25",
61 "r26",
62 "r27",
63 "r28",
64 "r29",
65 "r30",
66 "r31"
67};
68
69static const int tcg_target_reg_alloc_order[] = {
70 TCG_REG_R0,
71 TCG_REG_R1,
72 TCG_REG_R2,
73 TCG_REG_R3,
74 TCG_REG_R4,
75 TCG_REG_R5,
76 TCG_REG_R6,
77 TCG_REG_R7,
78 TCG_REG_R8,
79 TCG_REG_R9,
80 TCG_REG_R10,
81 TCG_REG_R11,
82 TCG_REG_R12,
83 TCG_REG_R13,
84 TCG_REG_R14,
85 TCG_REG_R15,
86 TCG_REG_R16,
87 TCG_REG_R17,
88 TCG_REG_R18,
89 TCG_REG_R19,
90 TCG_REG_R20,
91 TCG_REG_R21,
92 TCG_REG_R22,
93 TCG_REG_R23,
94 TCG_REG_R24,
95 TCG_REG_R25,
96 TCG_REG_R26,
97 TCG_REG_R27,
98 TCG_REG_R28,
99 TCG_REG_R29,
100 TCG_REG_R30,
101 TCG_REG_R31
102};
103
104static const int tcg_target_call_iarg_regs[] = {
105 TCG_REG_R3,
106 TCG_REG_R4,
107 TCG_REG_R5,
108 TCG_REG_R6,
109 TCG_REG_R7,
110 TCG_REG_R8,
111 TCG_REG_R9,
112 TCG_REG_R10
113};
114
115static const int tcg_target_call_oarg_regs[2] = {
116 TCG_REG_R3,
117 TCG_REG_R4
118};
119
120static const int tcg_target_callee_save_regs[] = {
fa4fbfb9 121 TCG_REG_R13, /* should r13 be saved? */
2662e13f
FB		 122 TCG_REG_R14,
123 TCG_REG_R15,
124 TCG_REG_R16,
125 TCG_REG_R17,
126 TCG_REG_R18,
127 TCG_REG_R19,
128 TCG_REG_R20,
129 TCG_REG_R21,
130 TCG_REG_R22,
131 TCG_REG_R23,
132 TCG_REG_R28,
133 TCG_REG_R29,
134 TCG_REG_R30,
135 TCG_REG_R31
136};
137
138static uint32_t reloc_pc24_val (void *pc, tcg_target_long target)
139{
932a6909
FB		 140 tcg_target_long disp;
141
142 disp = target - (tcg_target_long) pc;
143 if ((disp << 6) >> 6 != disp)
144 tcg_abort ();
145
146 return disp & 0x3fffffc;
2662e13f
FB		 147}
148
149static void reloc_pc24 (void *pc, tcg_target_long target)
150{
151 *(uint32_t *) pc = (*(uint32_t *) pc & ~0x3fffffc)
152 | reloc_pc24_val (pc, target);
153}
154
155static uint16_t reloc_pc14_val (void *pc, tcg_target_long target)
156{
932a6909
FB		 157 tcg_target_long disp;
158
159 disp = target - (tcg_target_long) pc;
160 if (disp != (int16_t) disp)
161 tcg_abort ();
162
163 return disp & 0xfffc;
2662e13f
FB		 164}
165
166static void reloc_pc14 (void *pc, tcg_target_long target)
167{
168 *(uint32_t *) pc = (*(uint32_t *) pc & ~0xfffc)
169 | reloc_pc14_val (pc, target);
170}
171
172static void patch_reloc(uint8_t *code_ptr, int type,
173 tcg_target_long value, tcg_target_long addend)
174{
175 value += addend;
176 switch (type) {
177 case R_PPC_REL14:
178 reloc_pc14 (code_ptr, value);
179 break;
180 case R_PPC_REL24:
181 reloc_pc24 (code_ptr, value);
182 break;
183 default:
184 tcg_abort();
185 }
186}
187
188/* maximum number of register used for input function arguments */
189static int tcg_target_get_call_iarg_regs_count(int flags)
190{
191 return sizeof (tcg_target_call_iarg_regs) / sizeof (tcg_target_call_iarg_regs[0]);
192}
193
194/* parse target specific constraints */
195static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
196{
197 const char *ct_str;
198
199 ct_str = *pct_str;
200 switch (ct_str[0]) {
398ce98e 201 case 'A': case 'B': case 'C': case 'D':
202 ct->ct |= TCG_CT_REG;
203 tcg_regset_set_reg(ct->u.regs, 3 + ct_str[0] - 'A');
204 break;
2662e13f
FB		 205 case 'r':
206 ct->ct |= TCG_CT_REG;
207 tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
208 break;
209 case 'L': /* qemu_ld constraint */
210 ct->ct |= TCG_CT_REG;
211 tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
212 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);
213 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R4);
214 break;
215 case 'K': /* qemu_st[8..32] constraint */
216 ct->ct |= TCG_CT_REG;
217 tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
218 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);
219 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R4);
220 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R5);
221#if TARGET_LONG_BITS == 64
222 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R6);
223#endif
224 break;
225 case 'M': /* qemu_st64 constraint */
226 ct->ct |= TCG_CT_REG;
227 tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
228 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);
229 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R4);
230 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R5);
231 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R6);
232 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R7);
233 break;
2662e13f
FB		 234 default:
235 return -1;
236 }
237 ct_str++;
238 *pct_str = ct_str;
239 return 0;
240}
241
242/* test if a constant matches the constraint */
243static int tcg_target_const_match(tcg_target_long val,
244 const TCGArgConstraint *arg_ct)
245{
246 int ct;
247
248 ct = arg_ct->ct;
249 if (ct & TCG_CT_CONST)
250 return 1;
2662e13f
FB		 251 return 0;
252}
253
254#define OPCD(opc) ((opc)<<26)
255#define XO31(opc) (OPCD(31)|((opc)<<1))
256#define XO19(opc) (OPCD(19)|((opc)<<1))
257
258#define B OPCD(18)
259#define BC OPCD(16)
260#define LBZ OPCD(34)
261#define LHZ OPCD(40)
262#define LHA OPCD(42)
263#define LWZ OPCD(32)
264#define STB OPCD(38)
265#define STH OPCD(44)
266#define STW OPCD(36)
267
268#define ADDI OPCD(14)
269#define ADDIS OPCD(15)
270#define ORI OPCD(24)
271#define ORIS OPCD(25)
272#define XORI OPCD(26)
273#define XORIS OPCD(27)
274#define ANDI OPCD(28)
275#define ANDIS OPCD(29)
276#define MULLI OPCD( 7)
277#define CMPLI OPCD(10)
278#define CMPI OPCD(11)
279
280#define LWZU OPCD(33)
281#define STWU OPCD(37)
282
283#define RLWINM OPCD(21)
284
285#define BCLR XO19(16)
286#define BCCTR XO19(528)
287#define CRAND XO19(257)
288
289#define EXTSB XO31(954)
290#define EXTSH XO31(922)
291#define ADD XO31(266)
292#define ADDE XO31(138)
293#define ADDC XO31( 10)
294#define AND XO31( 28)
295#define SUBF XO31( 40)
296#define SUBFC XO31( 8)
297#define SUBFE XO31(136)
298#define OR XO31(444)
299#define XOR XO31(316)
300#define MULLW XO31(235)
301#define MULHWU XO31( 11)
302#define DIVW XO31(491)
303#define DIVWU XO31(459)
304#define CMP XO31( 0)
305#define CMPL XO31( 32)
306#define LHBRX XO31(790)
307#define LWBRX XO31(534)
308#define STHBRX XO31(918)
309#define STWBRX XO31(662)
310#define MFSPR XO31(339)
311#define MTSPR XO31(467)
312#define SRAWI XO31(824)
313#define NEG XO31(104)
314
315#define LBZX XO31( 87)
316#define LHZX XO31(276)
317#define LHAX XO31(343)
318#define LWZX XO31( 23)
319#define STBX XO31(215)
320#define STHX XO31(407)
321#define STWX XO31(151)
322
323#define SPR(a,b) ((((a)<<5)|(b))<<11)
324#define LR SPR(8, 0)
325#define CTR SPR(9, 0)
326
327#define SLW XO31( 24)
328#define SRW XO31(536)
329#define SRAW XO31(792)
330
331#define LMW OPCD(46)
332#define STMW OPCD(47)
333
334#define TW XO31(4)
335#define TRAP (TW | TO (31))
336
337#define RT(r) ((r)<<21)
338#define RS(r) ((r)<<21)
339#define RA(r) ((r)<<16)
340#define RB(r) ((r)<<11)
341#define TO(t) ((t)<<21)
342#define SH(s) ((s)<<11)
343#define MB(b) ((b)<<6)
344#define ME(e) ((e)<<1)
345#define BO(o) ((o)<<21)
346
347#define LK 1
348
349#define TAB(t,a,b) (RT(t) | RA(a) | RB(b))
350#define SAB(s,a,b) (RS(s) | RA(a) | RB(b))
351
352#define BF(n) ((n)<<23)
353#define BI(n, c) (((c)+((n)*4))<<16)
354#define BT(n, c) (((c)+((n)*4))<<21)
355#define BA(n, c) (((c)+((n)*4))<<16)
356#define BB(n, c) (((c)+((n)*4))<<11)
357
358#define BO_COND_TRUE BO (12)
359#define BO_COND_FALSE BO (4)
360#define BO_ALWAYS BO (20)
361
362enum {
363 CR_LT,
364 CR_GT,
365 CR_EQ,
366 CR_SO
367};
368
369static const uint32_t tcg_to_bc[10] = {
370 [TCG_COND_EQ] = BC | BI (7, CR_EQ) | BO_COND_TRUE,
371 [TCG_COND_NE] = BC | BI (7, CR_EQ) | BO_COND_FALSE,
372 [TCG_COND_LT] = BC | BI (7, CR_LT) | BO_COND_TRUE,
373 [TCG_COND_GE] = BC | BI (7, CR_LT) | BO_COND_FALSE,
374 [TCG_COND_LE] = BC | BI (7, CR_GT) | BO_COND_FALSE,
375 [TCG_COND_GT] = BC | BI (7, CR_GT) | BO_COND_TRUE,
376 [TCG_COND_LTU] = BC | BI (7, CR_LT) | BO_COND_TRUE,
377 [TCG_COND_GEU] = BC | BI (7, CR_LT) | BO_COND_FALSE,
378 [TCG_COND_LEU] = BC | BI (7, CR_GT) | BO_COND_FALSE,
379 [TCG_COND_GTU] = BC | BI (7, CR_GT) | BO_COND_TRUE,
380};
381
382static void tcg_out_mov(TCGContext *s, int ret, int arg)
383{
384 tcg_out32 (s, OR | SAB (arg, ret, arg));
385}
386
387static void tcg_out_movi(TCGContext *s, TCGType type,
388 int ret, tcg_target_long arg)
389{
390 if (arg == (int16_t) arg)
391 tcg_out32 (s, ADDI | RT (ret) | RA (0) | (arg & 0xffff));
392 else {
393 tcg_out32 (s, ADDIS | RT (ret) | RA (0) | ((arg >> 16) & 0xffff));
394 if (arg & 0xffff)
0a878c47 395 tcg_out32 (s, ORI | RS (ret) | RA (ret) | (arg & 0xffff));
2662e13f
FB		 396 }
397}
398
399static void tcg_out_ldst (TCGContext *s, int ret, int addr,
400 int offset, int op1, int op2)
401{
402 if (offset == (int16_t) offset)
403 tcg_out32 (s, op1 | RT (ret) | RA (addr) | (offset & 0xffff));
404 else {
405 tcg_out_movi (s, TCG_TYPE_I32, 0, offset);
406 tcg_out32 (s, op2 | RT (ret) | RA (addr) | RB (0));
407 }
408}
409
932a6909
FB		 410static void tcg_out_b (TCGContext *s, int mask, tcg_target_long target)
411{
412 tcg_target_long disp;
413
414 disp = target - (tcg_target_long) s->code_ptr;
415 if ((disp << 6) >> 6 == disp)
416 tcg_out32 (s, B | disp | mask);
417 else {
418 tcg_out_movi (s, TCG_TYPE_I32, 0, (tcg_target_long) target);
419 tcg_out32 (s, MTSPR | RS (0) | CTR);
420 tcg_out32 (s, BCCTR | BO_ALWAYS | mask);
421 }
422}
423
2662e13f
FB		 424#if defined(CONFIG_SOFTMMU)
425extern void __ldb_mmu(void);
426extern void __ldw_mmu(void);
427extern void __ldl_mmu(void);
428extern void __ldq_mmu(void);
429
430extern void __stb_mmu(void);
431extern void __stw_mmu(void);
432extern void __stl_mmu(void);
433extern void __stq_mmu(void);
434
435static void *qemu_ld_helpers[4] = {
436 __ldb_mmu,
437 __ldw_mmu,
438 __ldl_mmu,
439 __ldq_mmu,
440};
441
442static void *qemu_st_helpers[4] = {
443 __stb_mmu,
444 __stw_mmu,
445 __stl_mmu,
446 __stq_mmu,
447};
448#endif
449
450static void tcg_out_qemu_ld (TCGContext *s, const TCGArg *args, int opc)
451{
452 int addr_reg, data_reg, data_reg2, r0, mem_index, s_bits, bswap;
453#ifdef CONFIG_SOFTMMU
454 int r1, r2;
455 void *label1_ptr, *label2_ptr;
456#endif
457#if TARGET_LONG_BITS == 64
458 int addr_reg2;
459#endif
460
461 data_reg = *args++;
462 if (opc == 3)
463 data_reg2 = *args++;
464 else
465 data_reg2 = 0;
466 addr_reg = *args++;
467#if TARGET_LONG_BITS == 64
468 addr_reg2 = *args++;
469#endif
470 mem_index = *args;
471 s_bits = opc & 3;
472
473#ifdef CONFIG_SOFTMMU
474 r0 = 3;
475 r1 = 4;
476 r2 = 0;
477
478 tcg_out32 (s, (RLWINM
479 | RA (r0)
480 | RS (addr_reg)
481 | SH (32 - (TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS))
482 | MB (32 - (CPU_TLB_BITS + CPU_TLB_ENTRY_BITS))
483 | ME (31 - CPU_TLB_ENTRY_BITS)
484 )
485 );
486 tcg_out32 (s, ADD | RT (r0) | RA (r0) | RB (TCG_AREG0));
487 tcg_out32 (s, (LWZU
488 | RT (r1)
489 | RA (r0)
490 | offsetof (CPUState, tlb_table[mem_index][0].addr_read)
491 )
492 );
493 tcg_out32 (s, (RLWINM
494 | RA (r2)
495 | RS (addr_reg)
496 | SH (0)
497 | MB ((32 - s_bits) & 31)
498 | ME (31 - TARGET_PAGE_BITS)
499 )
500 );
501
502 tcg_out32 (s, CMP | BF (7) | RA (r2) | RB (r1));
503#if TARGET_LONG_BITS == 64
504 tcg_out32 (s, LWZ | RT (r1) | RA (r0) | 4);
505 tcg_out32 (s, CMP | BF (6) | RA (addr_reg2) | RB (r1));
506 tcg_out32 (s, CRAND | BT (7, CR_EQ) | BA (6, CR_EQ) | BB (7, CR_EQ));
507#endif
508
509 label1_ptr = s->code_ptr;
510#ifdef FAST_PATH
511 tcg_out32 (s, BC | BI (7, CR_EQ) | BO_COND_TRUE);
512#endif
513
514 /* slow path */
515#if TARGET_LONG_BITS == 32
516 tcg_out_mov (s, 3, addr_reg);
517 tcg_out_movi (s, TCG_TYPE_I32, 4, mem_index);
518#else
519 tcg_out_mov (s, 3, addr_reg2);
520 tcg_out_mov (s, 4, addr_reg);
521 tcg_out_movi (s, TCG_TYPE_I32, 5, mem_index);
522#endif
523
932a6909 524 tcg_out_b (s, LK, (tcg_target_long) qemu_ld_helpers[s_bits]);
2662e13f
FB		 525 switch (opc) {
526 case 0|4:
527 tcg_out32 (s, EXTSB | RA (data_reg) | RS (3));
528 break;
529 case 1|4:
530 tcg_out32 (s, EXTSH | RA (data_reg) | RS (3));
531 break;
532 case 0:
533 case 1:
534 case 2:
535 if (data_reg != 3)
536 tcg_out_mov (s, data_reg, 3);
537 break;
538 case 3:
539 if (data_reg == 3) {
540 if (data_reg2 == 4) {
541 tcg_out_mov (s, 0, 4);
542 tcg_out_mov (s, 4, 3);
543 tcg_out_mov (s, 3, 0);
544 }
545 else {
546 tcg_out_mov (s, data_reg2, 3);
547 tcg_out_mov (s, 3, 4);
548 }
549 }
550 else {
551 if (data_reg != 4) tcg_out_mov (s, data_reg, 4);
552 if (data_reg2 != 3) tcg_out_mov (s, data_reg2, 3);
553 }
554 break;
555 }
556 label2_ptr = s->code_ptr;
557 tcg_out32 (s, B);
558
559 /* label1: fast path */
560#ifdef FAST_PATH
561 reloc_pc14 (label1_ptr, (tcg_target_long) s->code_ptr);
562#endif
563
564 /* r0 now contains &env->tlb_table[mem_index][index].addr_read */
565 tcg_out32 (s, (LWZ
566 | RT (r0)
567 | RA (r0)
568 | (ADDEND_OFFSET + offsetof (CPUTLBEntry, addend)
569 - offsetof (CPUTLBEntry, addr_read))
570 ));
571 /* r0 = env->tlb_table[mem_index][index].addend */
572 tcg_out32 (s, ADD | RT (r0) | RA (r0) | RB (addr_reg));
573 /* r0 = env->tlb_table[mem_index][index].addend + addr */
574
575#else /* !CONFIG_SOFTMMU */
576 r0 = addr_reg;
577#endif
578
579#ifdef TARGET_WORDS_BIGENDIAN
580 bswap = 0;
581#else
582 bswap = 1;
583#endif
584 switch (opc) {
585 default:
586 case 0:
587 tcg_out32 (s, LBZ | RT (data_reg) | RA (r0));
588 break;
589 case 0|4:
590 tcg_out32 (s, LBZ | RT (data_reg) | RA (r0));
591 tcg_out32 (s, EXTSB | RA (data_reg) | RS (data_reg));
592 break;
593 case 1:
594 if (bswap) tcg_out32 (s, LHBRX | RT (data_reg) | RB (r0));
595 else tcg_out32 (s, LHZ | RT (data_reg) | RA (r0));
596 break;
597 case 1|4:
598 if (bswap) {
599 tcg_out32 (s, LHBRX | RT (data_reg) | RB (r0));
600 tcg_out32 (s, EXTSH | RA (data_reg) | RS (data_reg));
601 }
602 else tcg_out32 (s, LHA | RT (data_reg) | RA (r0));
603 break;
604 case 2:
605 if (bswap) tcg_out32 (s, LWBRX | RT (data_reg) | RB (r0));
606 else tcg_out32 (s, LWZ | RT (data_reg)| RA (r0));
607 break;
608 case 3:
609 if (bswap) {
610 if (r0 == data_reg) {
611 tcg_out32 (s, LWBRX | RT (0) | RB (r0));
612 tcg_out32 (s, ADDI | RT (r0) | RA (r0) | 4);
613 tcg_out32 (s, LWBRX | RT (data_reg2) | RB (r0));
614 tcg_out_mov (s, data_reg, 0);
615 }
616 else {
617 tcg_out32 (s, LWBRX | RT (data_reg) | RB (r0));
618 tcg_out32 (s, ADDI | RT (r0) | RA (r0) | 4);
619 tcg_out32 (s, LWBRX | RT (data_reg2) | RB (r0));
620 }
621 }
622 else {
623 if (r0 == data_reg2) {
624 tcg_out32 (s, LWZ | RT (0) | RA (r0));
625 tcg_out32 (s, LWZ | RT (data_reg) | RA (r0) | 4);
626 tcg_out_mov (s, data_reg2, 0);
627 }
628 else {
629 tcg_out32 (s, LWZ | RT (data_reg2) | RA (r0));
630 tcg_out32 (s, LWZ | RT (data_reg) | RA (r0) | 4);
631 }
632 }
633 break;
634 }
635
636#ifdef CONFIG_SOFTMMU
637 reloc_pc24 (label2_ptr, (tcg_target_long) s->code_ptr);
638#endif
639}
640
641static void tcg_out_qemu_st (TCGContext *s, const TCGArg *args, int opc)
642{
643 int addr_reg, r0, r1, data_reg, data_reg2, mem_index, bswap;
644#ifdef CONFIG_SOFTMMU
645 int r2, ir;
646 void *label1_ptr, *label2_ptr;
647#endif
648#if TARGET_LONG_BITS == 64
649 int addr_reg2;
650#endif
651
652 data_reg = *args++;
653 if (opc == 3)
654 data_reg2 = *args++;
655 else
656 data_reg2 = 0;
657 addr_reg = *args++;
658#if TARGET_LONG_BITS == 64
659 addr_reg2 = *args++;
660#endif
661 mem_index = *args;
662
663#ifdef CONFIG_SOFTMMU
664 r0 = 3;
665 r1 = 4;
666 r2 = 0;
667
668 tcg_out32 (s, (RLWINM
669 | RA (r0)
670 | RS (addr_reg)
671 | SH (32 - (TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS))
672 | MB (32 - (CPU_TLB_ENTRY_BITS + CPU_TLB_BITS))
673 | ME (31 - CPU_TLB_ENTRY_BITS)
674 )
675 );
676 tcg_out32 (s, ADD | RT (r0) | RA (r0) | RB (TCG_AREG0));
677 tcg_out32 (s, (LWZU
678 | RT (r1)
679 | RA (r0)
680 | offsetof (CPUState, tlb_table[mem_index][0].addr_write)
681 )
682 );
683 tcg_out32 (s, (RLWINM
684 | RA (r2)
685 | RS (addr_reg)
686 | SH (0)
687 | MB ((32 - opc) & 31)
688 | ME (31 - TARGET_PAGE_BITS)
689 )
690 );
691
692 tcg_out32 (s, CMP | (7 << 23) | RA (r2) | RB (r1));
693#if TARGET_LONG_BITS == 64
694 tcg_out32 (s, LWZ | RT (r1) | RA (r0) | 4);
695 tcg_out32 (s, CMP | BF (6) | RA (addr_reg2) | RB (r1));
696 tcg_out32 (s, CRAND | BT (7, CR_EQ) | BA (6, CR_EQ) | BB (7, CR_EQ));
697#endif
698
699 label1_ptr = s->code_ptr;
700#ifdef FAST_PATH
701 tcg_out32 (s, BC | BI (7, CR_EQ) | BO_COND_TRUE);
702#endif
703
704 /* slow path */
705#if TARGET_LONG_BITS == 32
706 tcg_out_mov (s, 3, addr_reg);
707 ir = 4;
708#else
709 tcg_out_mov (s, 3, addr_reg2);
710 tcg_out_mov (s, 4, addr_reg);
711 ir = 5;
712#endif
713
714 switch (opc) {
715 case 0:
716 tcg_out32 (s, (RLWINM
717 | RA (ir)
718 | RS (data_reg)
719 | SH (0)
720 | MB (24)
721 | ME (31)));
722 break;
723 case 1:
724 tcg_out32 (s, (RLWINM
725 | RA (ir)
726 | RS (data_reg)
727 | SH (0)
728 | MB (16)
729 | ME (31)));
730 break;
731 case 2:
732 tcg_out_mov (s, ir, data_reg);
733 break;
734 case 3:
735 tcg_out_mov (s, 5, data_reg2);
736 tcg_out_mov (s, 6, data_reg);
737 ir = 6;
738 break;
739 }
740 ir++;
741
742 tcg_out_movi (s, TCG_TYPE_I32, ir, mem_index);
932a6909 743 tcg_out_b (s, LK, (tcg_target_long) qemu_st_helpers[opc]);
2662e13f
FB		 744 label2_ptr = s->code_ptr;
745 tcg_out32 (s, B);
746
747 /* label1: fast path */
748#ifdef FAST_PATH
749 reloc_pc14 (label1_ptr, (tcg_target_long) s->code_ptr);
750#endif
751
752 tcg_out32 (s, (LWZ
753 | RT (r0)
754 | RA (r0)
755 | (ADDEND_OFFSET + offsetof (CPUTLBEntry, addend)
756 - offsetof (CPUTLBEntry, addr_write))
757 ));
758 /* r0 = env->tlb_table[mem_index][index].addend */
759 tcg_out32 (s, ADD | RT (r0) | RA (r0) | RB (addr_reg));
760 /* r0 = env->tlb_table[mem_index][index].addend + addr */
761
762#else /* !CONFIG_SOFTMMU */
763 r1 = 4;
764 r0 = addr_reg;
765#endif
766
767#ifdef TARGET_WORDS_BIGENDIAN
768 bswap = 0;
769#else
770 bswap = 1;
771#endif
772 switch (opc) {
773 case 0:
774 tcg_out32 (s, STB | RS (data_reg) | RA (r0));
775 break;
776 case 1:
777 if (bswap) tcg_out32 (s, STHBRX | RS (data_reg) | RA (0) | RB (r0));
778 else tcg_out32 (s, STH | RS (data_reg) | RA (r0));
779 break;
780 case 2:
781 if (bswap) tcg_out32 (s, STWBRX | RS (data_reg) | RA (0) | RB (r0));
782 else tcg_out32 (s, STW | RS (data_reg) | RA (r0));
783 break;
784 case 3:
785 if (bswap) {
786 tcg_out32 (s, ADDI | RT (r1) | RA (r0) | 4);
787 tcg_out32 (s, STWBRX | RS (data_reg) | RA (0) | RB (r0));
788 tcg_out32 (s, STWBRX | RS (data_reg2) | RA (0) | RB (r1));
789 }
790 else {
791 tcg_out32 (s, STW | RS (data_reg2) | RA (r0));
792 tcg_out32 (s, STW | RS (data_reg) | RA (r0) | 4);
793 }
794 break;
795 }
796
797#ifdef CONFIG_SOFTMMU
798 reloc_pc24 (label2_ptr, (tcg_target_long) s->code_ptr);
799#endif
800}
801
802void tcg_target_qemu_prologue (TCGContext *s)
803{
0d5bd363 804 int i, frame_size;
2662e13f
FB		 805
806 frame_size = 0
807 + 4 /* back chain */
808 + 4 /* LR */
809 + TCG_STATIC_CALL_ARGS_SIZE
810 + ARRAY_SIZE (tcg_target_callee_save_regs) * 4
811 ;
812 frame_size = (frame_size + 15) & ~15;
813
814 tcg_out32 (s, MFSPR | RT (0) | LR);
815 tcg_out32 (s, STWU | RS (1) | RA (1) | (-frame_size & 0xffff));
816 for (i = 0; i < ARRAY_SIZE (tcg_target_callee_save_regs); ++i)
817 tcg_out32 (s, (STW
818 | RS (tcg_target_callee_save_regs[i])
819 | RA (1)
820 | (i * 4 + 8 + TCG_STATIC_CALL_ARGS_SIZE)
821 )
822 );
823 tcg_out32 (s, STW | RS (0) | RA (1) | (frame_size - 4));
824
825 tcg_out32 (s, MTSPR | RS (3) | CTR);
826 tcg_out32 (s, BCCTR | BO_ALWAYS);
827 tb_ret_addr = s->code_ptr;
828
829 for (i = 0; i < ARRAY_SIZE (tcg_target_callee_save_regs); ++i)
830 tcg_out32 (s, (LWZ
831 | RT (tcg_target_callee_save_regs[i])
832 | RA (1)
833 | (i * 4 + 8 + TCG_STATIC_CALL_ARGS_SIZE)
834 )
835 );
836 tcg_out32 (s, LWZ | RT (0) | RA (1) | (frame_size - 4));
837 tcg_out32 (s, MTSPR | RS (0) | LR);
838 tcg_out32 (s, ADDI | RT (1) | RA (1) | frame_size);
839 tcg_out32 (s, BCLR | BO_ALWAYS);
840}
841
842static void tcg_out_ld (TCGContext *s, TCGType type, int ret, int arg1,
843 tcg_target_long arg2)
844{
845 tcg_out_ldst (s, ret, arg1, arg2, LWZ, LWZX);
846}
847
848static void tcg_out_st (TCGContext *s, TCGType type, int arg, int arg1,
849 tcg_target_long arg2)
850{
851 tcg_out_ldst (s, arg, arg1, arg2, STW, STWX);
852}
853
854static void ppc_addi (TCGContext *s, int rt, int ra, tcg_target_long si)
855{
856 if (!si && rt == ra)
857 return;
858
859 if (si == (int16_t) si)
860 tcg_out32 (s, ADDI | RT (rt) | RA (ra) | (si & 0xffff));
861 else {
862 uint16_t h = ((si >> 16) & 0xffff) + ((uint16_t) si >> 15);
863 tcg_out32 (s, ADDIS | RT (rt) | RA (ra) | h);
864 tcg_out32 (s, ADDI | RT (rt) | RA (rt) | (si & 0xffff));
865 }
866}
867
868static void tcg_out_addi(TCGContext *s, int reg, tcg_target_long val)
869{
870 ppc_addi (s, reg, reg, val);
871}
872
873static void tcg_out_brcond(TCGContext *s, int cond,
874 TCGArg arg1, TCGArg arg2, int const_arg2,
875 int label_index)
876{
877 TCGLabel *l = &s->labels[label_index];
878 int imm;
879 uint32_t op;
880
2662e13f 881 switch (cond) {
f3f478a7
FB		 882 case TCG_COND_EQ:
883 case TCG_COND_NE:
884 if (const_arg2) {
885 if ((int16_t) arg2 == arg2) {
886 op = CMPI;
887 imm = 1;
888 break;
889 }
890 else if ((uint16_t) arg2 == arg2) {
891 op = CMPLI;
892 imm = 1;
893 break;
894 }
895 }
896 op = CMPL;
897 imm = 0;
898 break;
899
900 case TCG_COND_LT:
901 case TCG_COND_GE:
902 case TCG_COND_LE:
903 case TCG_COND_GT:
904 if (const_arg2) {
905 if ((int16_t) arg2 == arg2) {
906 op = CMPI;
907 imm = 1;
908 break;
909 }
910 }
911 op = CMP;
912 imm = 0;
913 break;
914
915 case TCG_COND_LTU:
916 case TCG_COND_GEU:
917 case TCG_COND_LEU:
918 case TCG_COND_GTU:
919 if (const_arg2) {
920 if ((uint16_t) arg2 == arg2) {
921 op = CMPLI;
922 imm = 1;
923 break;
924 }
925 }
926 op = CMPL;
927 imm = 0;
928 break;
929
2662e13f
FB		 930 default:
931 tcg_abort ();
932 }
933 op |= BF (7);
934
935 if (imm)
936 tcg_out32 (s, op | RA (arg1) | (arg2 & 0xffff));
937 else {
938 if (const_arg2) {
939 tcg_out_movi (s, TCG_TYPE_I32, 0, arg2);
940 tcg_out32 (s, op | RA (arg1) | RB (0));
941 }
942 else
943 tcg_out32 (s, op | RA (arg1) | RB (arg2));
944 }
945
0a878c47 946 if (l->has_value)
2662e13f
FB		 947 tcg_out32 (s, tcg_to_bc[cond] | reloc_pc14_val (s->code_ptr,
948 l->u.value));
2662e13f 949 else {
0a878c47 950 uint16_t val = *(uint16_t *) &s->code_ptr[2];
951
952 /* Thanks to Andrzej Zaborowski */
953 tcg_out32 (s, tcg_to_bc[cond] | (val & 0xfffc));
2662e13f
FB		 954 tcg_out_reloc (s, s->code_ptr - 4, R_PPC_REL14, label_index, 0);
955 }
956}
957
958/* brcond2 is taken verbatim from i386 tcg-target */
959/* XXX: we implement it at the target level to avoid having to
960 handle cross basic blocks temporaries */
961static void tcg_out_brcond2(TCGContext *s,
962 const TCGArg *args, const int *const_args)
963{
964 int label_next;
965 label_next = gen_new_label();
966 switch(args[4]) {
967 case TCG_COND_EQ:
968 tcg_out_brcond(s, TCG_COND_NE, args[0], args[2], const_args[2], label_next);
969 tcg_out_brcond(s, TCG_COND_EQ, args[1], args[3], const_args[3], args[5]);
970 break;
971 case TCG_COND_NE:
972 tcg_out_brcond(s, TCG_COND_NE, args[0], args[2], const_args[2], args[5]);
973 tcg_out_brcond(s, TCG_COND_NE, args[1], args[3], const_args[3], args[5]);
974 break;
975 case TCG_COND_LT:
976 tcg_out_brcond(s, TCG_COND_LT, args[1], args[3], const_args[3], args[5]);
977 tcg_out_brcond(s, TCG_COND_NE, args[1], args[3], const_args[3], label_next);
978 tcg_out_brcond(s, TCG_COND_LT, args[0], args[2], const_args[2], args[5]);
979 break;
980 case TCG_COND_LE:
981 tcg_out_brcond(s, TCG_COND_LT, args[1], args[3], const_args[3], args[5]);
982 tcg_out_brcond(s, TCG_COND_NE, args[1], args[3], const_args[3], label_next);
983 tcg_out_brcond(s, TCG_COND_LE, args[0], args[2], const_args[2], args[5]);
984 break;
985 case TCG_COND_GT:
986 tcg_out_brcond(s, TCG_COND_GT, args[1], args[3], const_args[3], args[5]);
987 tcg_out_brcond(s, TCG_COND_NE, args[1], args[3], const_args[3], label_next);
988 tcg_out_brcond(s, TCG_COND_GT, args[0], args[2], const_args[2], args[5]);
989 break;
990 case TCG_COND_GE:
991 tcg_out_brcond(s, TCG_COND_GT, args[1], args[3], const_args[3], args[5]);
992 tcg_out_brcond(s, TCG_COND_NE, args[1], args[3], const_args[3], label_next);
993 tcg_out_brcond(s, TCG_COND_GE, args[0], args[2], const_args[2], args[5]);
994 break;
995 case TCG_COND_LTU:
996 tcg_out_brcond(s, TCG_COND_LTU, args[1], args[3], const_args[3], args[5]);
997 tcg_out_brcond(s, TCG_COND_NE, args[1], args[3], const_args[3], label_next);
998 tcg_out_brcond(s, TCG_COND_LTU, args[0], args[2], const_args[2], args[5]);
999 break;
1000 case TCG_COND_LEU:
1001 tcg_out_brcond(s, TCG_COND_LTU, args[1], args[3], const_args[3], args[5]);
1002 tcg_out_brcond(s, TCG_COND_NE, args[1], args[3], const_args[3], label_next);
1003 tcg_out_brcond(s, TCG_COND_LEU, args[0], args[2], const_args[2], args[5]);
1004 break;
1005 case TCG_COND_GTU:
1006 tcg_out_brcond(s, TCG_COND_GTU, args[1], args[3], const_args[3], args[5]);
1007 tcg_out_brcond(s, TCG_COND_NE, args[1], args[3], const_args[3], label_next);
1008 tcg_out_brcond(s, TCG_COND_GTU, args[0], args[2], const_args[2], args[5]);
1009 break;
1010 case TCG_COND_GEU:
1011 tcg_out_brcond(s, TCG_COND_GTU, args[1], args[3], const_args[3], args[5]);
1012 tcg_out_brcond(s, TCG_COND_NE, args[1], args[3], const_args[3], label_next);
1013 tcg_out_brcond(s, TCG_COND_GEU, args[0], args[2], const_args[2], args[5]);
1014 break;
1015 default:
1016 tcg_abort();
1017 }
1018 tcg_out_label(s, label_next, (tcg_target_long)s->code_ptr);
1019}
1020
1021static void tcg_out_op(TCGContext *s, int opc, const TCGArg *args,
1022 const int *const_args)
1023{
1024 switch (opc) {
1025 case INDEX_op_exit_tb:
1026 tcg_out_movi (s, TCG_TYPE_I32, TCG_REG_R3, args[0]);
932a6909 1027 tcg_out_b (s, 0, (tcg_target_long) tb_ret_addr);
2662e13f
FB		 1028 break;
1029 case INDEX_op_goto_tb:
1030 if (s->tb_jmp_offset) {
1031 /* direct jump method */
932a6909 1032
2662e13f 1033 s->tb_jmp_offset[args[0]] = s->code_ptr - s->code_buf;
0a878c47 1034 s->code_ptr += 16;
932a6909
FB		 1035 }
1036 else {
2662e13f
FB		 1037 tcg_abort ();
1038 }
1039 s->tb_next_offset[args[0]] = s->code_ptr - s->code_buf;
1040 break;
1041 case INDEX_op_br:
1042 {
1043 TCGLabel *l = &s->labels[args[0]];
1044
1045 if (l->has_value) {
932a6909 1046 tcg_out_b (s, 0, l->u.value);
2662e13f
FB		 1047 }
1048 else {
0a878c47 1049 uint32_t val = *(uint32_t *) s->code_ptr;
1050
1051 /* Thanks to Andrzej Zaborowski */
1052 tcg_out32 (s, B | (val & 0x3fffffc));
2662e13f
FB		 1053 tcg_out_reloc (s, s->code_ptr - 4, R_PPC_REL24, args[0], 0);
1054 }
1055 }
1056 break;
1057 case INDEX_op_call:
1058 if (const_args[0]) {
932a6909 1059 tcg_out_b (s, LK, args[0]);
2662e13f
FB		 1060 }
1061 else {
1062 tcg_out32 (s, MTSPR | RS (args[0]) | LR);
1063 tcg_out32 (s, BCLR | BO_ALWAYS | LK);
1064 }
1065 break;
1066 case INDEX_op_jmp:
1067 if (const_args[0]) {
932a6909 1068 tcg_out_b (s, 0, args[0]);
2662e13f
FB		 1069 }
1070 else {
1071 tcg_out32 (s, MTSPR | RS (args[0]) | CTR);
1072 tcg_out32 (s, BCCTR | BO_ALWAYS);
1073 }
1074 break;
1075 case INDEX_op_movi_i32:
1076 tcg_out_movi(s, TCG_TYPE_I32, args[0], args[1]);
1077 break;
1078 case INDEX_op_ld8u_i32:
1079 tcg_out_ldst (s, args[0], args[1], args[2], LBZ, LBZX);
1080 break;
1081 case INDEX_op_ld8s_i32:
1082 tcg_out_ldst (s, args[0], args[1], args[2], LBZ, LBZX);
1083 tcg_out32 (s, EXTSB | RS (args[0]) | RA (args[0]));
1084 break;
1085 case INDEX_op_ld16u_i32:
1086 tcg_out_ldst (s, args[0], args[1], args[2], LHZ, LHZX);
1087 break;
1088 case INDEX_op_ld16s_i32:
1089 tcg_out_ldst (s, args[0], args[1], args[2], LHA, LHAX);
1090 break;
1091 case INDEX_op_ld_i32:
1092 tcg_out_ldst (s, args[0], args[1], args[2], LWZ, LWZX);
1093 break;
1094 case INDEX_op_st8_i32:
1095 tcg_out_ldst (s, args[0], args[1], args[2], STB, STBX);
1096 break;
1097 case INDEX_op_st16_i32:
1098 tcg_out_ldst (s, args[0], args[1], args[2], STH, STHX);
1099 break;
1100 case INDEX_op_st_i32:
1101 tcg_out_ldst (s, args[0], args[1], args[2], STW, STWX);
1102 break;
1103
1104 case INDEX_op_add_i32:
1105 if (const_args[2])
1106 ppc_addi (s, args[0], args[1], args[2]);
1107 else
1108 tcg_out32 (s, ADD | TAB (args[0], args[1], args[2]));
1109 break;
1110 case INDEX_op_sub_i32:
1111 if (const_args[2])
1112 ppc_addi (s, args[0], args[1], -args[2]);
1113 else
1114 tcg_out32 (s, SUBF | TAB (args[0], args[2], args[1]));
1115 break;
1116
1117 case INDEX_op_and_i32:
1118 if (const_args[2]) {
1119 if (!args[2])
1120 tcg_out_movi (s, TCG_TYPE_I32, args[0], 0);
1121 else {
1122 if ((args[2] & 0xffff) == args[2])
1123 tcg_out32 (s, ANDI | RS (args[1]) | RA (args[0]) | args[2]);
1124 else if ((args[2] & 0xffff0000) == args[2])
1125 tcg_out32 (s, ANDIS | RS (args[1]) | RA (args[0])
1126 | ((args[2] >> 16) & 0xffff));
1127 else if (args[2] == 0xffffffff) {
1128 if (args[0] != args[1])
1129 tcg_out_mov (s, args[0], args[1]);
1130 }
1131 else {
1132 tcg_out_movi (s, TCG_TYPE_I32, 0, args[2]);
1133 tcg_out32 (s, AND | SAB (args[1], args[0], 0));
1134 }
1135 }
1136 }
1137 else
1138 tcg_out32 (s, AND | SAB (args[1], args[0], args[2]));
1139 break;
1140 case INDEX_op_or_i32:
1141 if (const_args[2]) {
1142 if (args[2]) {
1143 if (args[2] & 0xffff) {
932a6909
FB		 1144 tcg_out32 (s, ORI | RS (args[1]) | RA (args[0])
1145 | (args[2] & 0xffff));
2662e13f
FB		 1146 if (args[2] >> 16)
1147 tcg_out32 (s, ORIS | RS (args[0]) | RA (args[0])
1148 | ((args[2] >> 16) & 0xffff));
1149 }
1150 else {
1151 tcg_out32 (s, ORIS | RS (args[1]) | RA (args[0])
1152 | ((args[2] >> 16) & 0xffff));
1153 }
1154 }
1155 else {
1156 if (args[0] != args[1])
1157 tcg_out_mov (s, args[0], args[1]);
1158 }
1159 }
1160 else
1161 tcg_out32 (s, OR | SAB (args[1], args[0], args[2]));
1162 break;
1163 case INDEX_op_xor_i32:
1164 if (const_args[2]) {
1165 if (args[2]) {
1166 if ((args[2] & 0xffff) == args[2])
1167 tcg_out32 (s, XORI | RS (args[1]) | RA (args[0])
1168 | (args[2] & 0xffff));
1169 else if ((args[2] & 0xffff0000) == args[2])
1170 tcg_out32 (s, XORIS | RS (args[1]) | RA (args[0])
1171 | ((args[2] >> 16) & 0xffff));
1172 else {
1173 tcg_out_movi (s, TCG_TYPE_I32, 0, args[2]);
1174 tcg_out32 (s, XOR | SAB (args[1], args[0], 0));
1175 }
1176 }
1177 else {
1178 if (args[0] != args[1])
1179 tcg_out_mov (s, args[0], args[1]);
1180 }
1181 }
1182 else
1183 tcg_out32 (s, XOR | SAB (args[1], args[0], args[2]));
1184 break;
1185
1186 case INDEX_op_mul_i32:
1187 if (const_args[2]) {
1188 if (args[2] == (int16_t) args[2])
1189 tcg_out32 (s, MULLI | RT (args[0]) | RA (args[1])
1190 | (args[2] & 0xffff));
1191 else {
1192 tcg_out_movi (s, TCG_TYPE_I32, 0, args[2]);
1193 tcg_out32 (s, MULLW | TAB (args[0], args[1], 0));
1194 }
1195 }
1196 else
1197 tcg_out32 (s, MULLW | TAB (args[0], args[1], args[2]));
1198 break;
77b73de6 1199
1200 case INDEX_op_div_i32:
1201 tcg_out32 (s, DIVW | TAB (args[0], args[1], args[2]));
1202 break;
1203
1204 case INDEX_op_divu_i32:
1205 tcg_out32 (s, DIVWU | TAB (args[0], args[1], args[2]));
1206 break;
1207
1208 case INDEX_op_rem_i32:
1209 tcg_out32 (s, DIVW | TAB (0, args[1], args[2]));
1210 tcg_out32 (s, MULLW | TAB (0, 0, args[2]));
1211 tcg_out32 (s, SUBF | TAB (args[0], 0, args[1]));
1212 break;
1213
1214 case INDEX_op_remu_i32:
1215 tcg_out32 (s, DIVWU | TAB (0, args[1], args[2]));
1216 tcg_out32 (s, MULLW | TAB (0, 0, args[2]));
1217 tcg_out32 (s, SUBF | TAB (args[0], 0, args[1]));
1218 break;
1219
2662e13f
FB		 1220 case INDEX_op_mulu2_i32:
1221 if (args[0] == args[2] || args[0] == args[3]) {
1222 tcg_out32 (s, MULLW | TAB (0, args[2], args[3]));
1223 tcg_out32 (s, MULHWU | TAB (args[1], args[2], args[3]));
1224 tcg_out_mov (s, args[0], 0);
1225 }
1226 else {
1227 tcg_out32 (s, MULLW | TAB (args[0], args[2], args[3]));
1228 tcg_out32 (s, MULHWU | TAB (args[1], args[2], args[3]));
1229 }
1230 break;
2662e13f
FB		 1231
1232 case INDEX_op_shl_i32:
1233 if (const_args[2]) {
1234 if (args[2])
1235 tcg_out32 (s, (RLWINM
1236 | RA (args[0])
1237 | RS (args[1])
1238 | SH (args[2])
1239 | MB (0)
1240 | ME (31 - args[2])
1241 )
1242 );
1243 else
1244 tcg_out_mov (s, args[0], args[1]);
1245 }
1246 else
1247 tcg_out32 (s, SLW | SAB (args[1], args[0], args[2]));
1248 break;
1249 case INDEX_op_shr_i32:
1250 if (const_args[2]) {
1251 if (args[2])
1252 tcg_out32 (s, (RLWINM
1253 | RA (args[0])
1254 | RS (args[1])
1255 | SH (32 - args[2])
1256 | MB (args[2])
1257 | ME (31)
1258 )
1259 );
1260 else
1261 tcg_out_mov (s, args[0], args[1]);
1262 }
1263 else
1264 tcg_out32 (s, SRW | SAB (args[1], args[0], args[2]));
1265 break;
1266 case INDEX_op_sar_i32:
1267 if (const_args[2])
1268 tcg_out32 (s, SRAWI | RS (args[1]) | RA (args[0]) | SH (args[2]));
1269 else
1270 tcg_out32 (s, SRAW | SAB (args[1], args[0], args[2]));
1271 break;
1272
1273 case INDEX_op_add2_i32:
1274 if (args[0] == args[3] || args[0] == args[5]) {
1275 tcg_out32 (s, ADDC | TAB (0, args[2], args[4]));
1276 tcg_out32 (s, ADDE | TAB (args[1], args[3], args[5]));
1277 tcg_out_mov (s, args[0], 0);
1278 }
1279 else {
1280 tcg_out32 (s, ADDC | TAB (args[0], args[2], args[4]));
1281 tcg_out32 (s, ADDE | TAB (args[1], args[3], args[5]));
1282 }
1283 break;
1284 case INDEX_op_sub2_i32:
1285 if (args[0] == args[3] || args[0] == args[5]) {
1286 tcg_out32 (s, SUBFC | TAB (0, args[4], args[2]));
1287 tcg_out32 (s, SUBFE | TAB (args[1], args[5], args[3]));
1288 tcg_out_mov (s, args[0], 0);
1289 }
1290 else {
1291 tcg_out32 (s, SUBFC | TAB (args[0], args[4], args[2]));
1292 tcg_out32 (s, SUBFE | TAB (args[1], args[5], args[3]));
1293 }
1294 break;
1295
1296 case INDEX_op_brcond_i32:
1297 /*
1298 args[0] = r0
1299 args[1] = r1
1300 args[2] = cond
1301 args[3] = r1 is const
1302 args[4] = label_index
1303 */
1304 tcg_out_brcond (s, args[2], args[0], args[1], const_args[1], args[3]);
1305 break;
1306 case INDEX_op_brcond2_i32:
1307 tcg_out_brcond2(s, args, const_args);
1308 break;
1309
1310 case INDEX_op_neg_i32:
1311 tcg_out32 (s, NEG | RT (args[0]) | RA (args[1]));
1312 break;
1313
1314 case INDEX_op_qemu_ld8u:
1315 tcg_out_qemu_ld(s, args, 0);
1316 break;
1317 case INDEX_op_qemu_ld8s:
1318 tcg_out_qemu_ld(s, args, 0 | 4);
1319 break;
1320 case INDEX_op_qemu_ld16u:
1321 tcg_out_qemu_ld(s, args, 1);
1322 break;
1323 case INDEX_op_qemu_ld16s:
1324 tcg_out_qemu_ld(s, args, 1 | 4);
1325 break;
1326 case INDEX_op_qemu_ld32u:
1327 tcg_out_qemu_ld(s, args, 2);
1328 break;
1329 case INDEX_op_qemu_ld64:
1330 tcg_out_qemu_ld(s, args, 3);
1331 break;
1332 case INDEX_op_qemu_st8:
1333 tcg_out_qemu_st(s, args, 0);
1334 break;
1335 case INDEX_op_qemu_st16:
1336 tcg_out_qemu_st(s, args, 1);
1337 break;
1338 case INDEX_op_qemu_st32:
1339 tcg_out_qemu_st(s, args, 2);
1340 break;
1341 case INDEX_op_qemu_st64:
1342 tcg_out_qemu_st(s, args, 3);
1343 break;
1344
1345 default:
1346 tcg_dump_ops (s, stderr);
1347 tcg_abort ();
1348 }
1349}
1350
1351static const TCGTargetOpDef ppc_op_defs[] = {
1352 { INDEX_op_exit_tb, { } },
1353 { INDEX_op_goto_tb, { } },
932a6909
FB		 1354 { INDEX_op_call, { "ri" } },
1355 { INDEX_op_jmp, { "ri" } },
2662e13f
FB		 1356 { INDEX_op_br, { } },
1357
1358 { INDEX_op_mov_i32, { "r", "r" } },
1359 { INDEX_op_movi_i32, { "r" } },
1360 { INDEX_op_ld8u_i32, { "r", "r" } },
1361 { INDEX_op_ld8s_i32, { "r", "r" } },
1362 { INDEX_op_ld16u_i32, { "r", "r" } },
1363 { INDEX_op_ld16s_i32, { "r", "r" } },
1364 { INDEX_op_ld_i32, { "r", "r" } },
1365 { INDEX_op_st8_i32, { "r", "r" } },
1366 { INDEX_op_st16_i32, { "r", "r" } },
1367 { INDEX_op_st_i32, { "r", "r" } },
1368
1369 { INDEX_op_add_i32, { "r", "r", "ri" } },
1370 { INDEX_op_mul_i32, { "r", "r", "ri" } },
77b73de6 1371 { INDEX_op_div_i32, { "r", "r", "r" } },
1372 { INDEX_op_divu_i32, { "r", "r", "r" } },
1373 { INDEX_op_rem_i32, { "r", "r", "r" } },
1374 { INDEX_op_remu_i32, { "r", "r", "r" } },
2662e13f 1375 { INDEX_op_mulu2_i32, { "r", "r", "r", "r" } },
2662e13f
FB		 1376 { INDEX_op_sub_i32, { "r", "r", "ri" } },
1377 { INDEX_op_and_i32, { "r", "r", "ri" } },
1378 { INDEX_op_or_i32, { "r", "r", "ri" } },
1379 { INDEX_op_xor_i32, { "r", "r", "ri" } },
1380
1381 { INDEX_op_shl_i32, { "r", "r", "ri" } },
1382 { INDEX_op_shr_i32, { "r", "r", "ri" } },
1383 { INDEX_op_sar_i32, { "r", "r", "ri" } },
1384
1385 { INDEX_op_brcond_i32, { "r", "ri" } },
1386
1387 { INDEX_op_add2_i32, { "r", "r", "r", "r", "r", "r" } },
1388 { INDEX_op_sub2_i32, { "r", "r", "r", "r", "r", "r" } },
1389 { INDEX_op_brcond2_i32, { "r", "r", "r", "r" } },
1390
1391 { INDEX_op_neg_i32, { "r", "r" } },
1392
1393#if TARGET_LONG_BITS == 32
1394 { INDEX_op_qemu_ld8u, { "r", "L" } },
1395 { INDEX_op_qemu_ld8s, { "r", "L" } },
1396 { INDEX_op_qemu_ld16u, { "r", "L" } },
1397 { INDEX_op_qemu_ld16s, { "r", "L" } },
1398 { INDEX_op_qemu_ld32u, { "r", "L" } },
1399 { INDEX_op_qemu_ld32s, { "r", "L" } },
1400 { INDEX_op_qemu_ld64, { "r", "r", "L" } },
1401
1402 { INDEX_op_qemu_st8, { "K", "K" } },
1403 { INDEX_op_qemu_st16, { "K", "K" } },
1404 { INDEX_op_qemu_st32, { "K", "K" } },
1405 { INDEX_op_qemu_st64, { "M", "M", "M" } },
1406#else
1407 { INDEX_op_qemu_ld8u, { "r", "L", "L" } },
1408 { INDEX_op_qemu_ld8s, { "r", "L", "L" } },
1409 { INDEX_op_qemu_ld16u, { "r", "L", "L" } },
1410 { INDEX_op_qemu_ld16s, { "r", "L", "L" } },
1411 { INDEX_op_qemu_ld32u, { "r", "L", "L" } },
1412 { INDEX_op_qemu_ld32s, { "r", "L", "L" } },
1413 { INDEX_op_qemu_ld64, { "r", "L", "L", "L" } },
1414
1415 { INDEX_op_qemu_st8, { "K", "K", "K" } },
1416 { INDEX_op_qemu_st16, { "K", "K", "K" } },
1417 { INDEX_op_qemu_st32, { "K", "K", "K" } },
1418 { INDEX_op_qemu_st64, { "M", "M", "M", "M" } },
1419#endif
1420
1421 { -1 },
1422};
1423
1424void tcg_target_init(TCGContext *s)
1425{
1426 tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0, 0xffffffff);
1427 tcg_regset_set32(tcg_target_call_clobber_regs, 0,
1428 (1 << TCG_REG_R0) |
1429 (1 << TCG_REG_R3) |
1430 (1 << TCG_REG_R4) |
1431 (1 << TCG_REG_R5) |
1432 (1 << TCG_REG_R6) |
1433 (1 << TCG_REG_R7) |
1434 (1 << TCG_REG_R8) |
1435 (1 << TCG_REG_R9) |
1436 (1 << TCG_REG_R10) |
1437 (1 << TCG_REG_R11) |
1438 (1 << TCG_REG_R12)
1439 );
1440
1441 tcg_regset_clear(s->reserved_regs);
1442 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R0);
1443 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R1);
1444 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R2);
1445
1446 tcg_add_target_add_op_defs(ppc_op_defs);
1447}
Qemu copy for testing