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2662e13f
FB		 1/*
2 * Tiny Code Generator for QEMU
3 *
4 * Copyright (c) 2008 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
25static uint8_t *tb_ret_addr;
26
6ec85236 27#ifdef _CALL_DARWIN
bf6bca52 28#define LINKAGE_AREA_SIZE 24
2946898b 29#define LR_OFFSET 8
6ec85236 30#elif defined _CALL_AIX
b29fe3ed 31#define LINKAGE_AREA_SIZE 52
32#define LR_OFFSET 8
f9bf2987 33#else
34#define LINKAGE_AREA_SIZE 8
2946898b 35#define LR_OFFSET 4
f9bf2987 36#endif
37
2662e13f 38#define FAST_PATH
35f6b599 39
f6548c0a 40#ifndef GUEST_BASE
41#define GUEST_BASE 0
42#endif
43
44#ifdef CONFIG_USE_GUEST_BASE
45#define TCG_GUEST_BASE_REG 30
46#else
47#define TCG_GUEST_BASE_REG 0
48#endif
49
d4a9eb1f 50#ifndef NDEBUG
2662e13f
FB		 51static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
52 "r0",
53 "r1",
54 "rp",
55 "r3",
56 "r4",
57 "r5",
58 "r6",
59 "r7",
60 "r8",
61 "r9",
62 "r10",
63 "r11",
64 "r12",
65 "r13",
66 "r14",
67 "r15",
68 "r16",
69 "r17",
70 "r18",
71 "r19",
72 "r20",
73 "r21",
74 "r22",
75 "r23",
76 "r24",
77 "r25",
78 "r26",
79 "r27",
80 "r28",
81 "r29",
82 "r30",
83 "r31"
84};
d4a9eb1f 85#endif
2662e13f
FB		 86
87static const int tcg_target_reg_alloc_order[] = {
a35e86c5 88 TCG_REG_R14,
89 TCG_REG_R15,
90 TCG_REG_R16,
91 TCG_REG_R17,
92 TCG_REG_R18,
93 TCG_REG_R19,
94 TCG_REG_R20,
95 TCG_REG_R21,
96 TCG_REG_R22,
97 TCG_REG_R23,
98 TCG_REG_R28,
99 TCG_REG_R29,
100 TCG_REG_R30,
101 TCG_REG_R31,
6ec85236 102#ifdef _CALL_DARWIN
f9bf2987 103 TCG_REG_R2,
104#endif
2662e13f
FB		 105 TCG_REG_R3,
106 TCG_REG_R4,
107 TCG_REG_R5,
108 TCG_REG_R6,
109 TCG_REG_R7,
110 TCG_REG_R8,
111 TCG_REG_R9,
112 TCG_REG_R10,
6ec85236 113#ifndef _CALL_DARWIN
2662e13f 114 TCG_REG_R11,
f9bf2987 115#endif
2662e13f 116 TCG_REG_R12,
6ec85236 117#ifndef _CALL_SYSV
2662e13f 118 TCG_REG_R13,
5db3ee79 119#endif
2662e13f
FB		 120 TCG_REG_R24,
121 TCG_REG_R25,
122 TCG_REG_R26,
a35e86c5 123 TCG_REG_R27
2662e13f
FB		 124};
125
126static const int tcg_target_call_iarg_regs[] = {
127 TCG_REG_R3,
128 TCG_REG_R4,
129 TCG_REG_R5,
130 TCG_REG_R6,
131 TCG_REG_R7,
132 TCG_REG_R8,
133 TCG_REG_R9,
134 TCG_REG_R10
135};
136
137static const int tcg_target_call_oarg_regs[2] = {
138 TCG_REG_R3,
139 TCG_REG_R4
140};
141
142static const int tcg_target_callee_save_regs[] = {
6ec85236 143#ifdef _CALL_DARWIN
f9bf2987 144 TCG_REG_R11,
145 TCG_REG_R13,
b29fe3ed 146#endif
6ec85236 147#ifdef _CALL_AIX
b29fe3ed 148 TCG_REG_R13,
f9bf2987 149#endif
2662e13f
FB		 150 TCG_REG_R14,
151 TCG_REG_R15,
152 TCG_REG_R16,
153 TCG_REG_R17,
154 TCG_REG_R18,
155 TCG_REG_R19,
156 TCG_REG_R20,
157 TCG_REG_R21,
158 TCG_REG_R22,
159 TCG_REG_R23,
eb2eb1dc 160 TCG_REG_R24,
161 TCG_REG_R25,
162 TCG_REG_R26,
163 /* TCG_REG_R27, */ /* currently used for the global env, so no
164 need to save */
2662e13f
FB		 165 TCG_REG_R28,
166 TCG_REG_R29,
167 TCG_REG_R30,
168 TCG_REG_R31
169};
170
171static uint32_t reloc_pc24_val (void *pc, tcg_target_long target)
172{
932a6909
FB		 173 tcg_target_long disp;
174
175 disp = target - (tcg_target_long) pc;
176 if ((disp << 6) >> 6 != disp)
177 tcg_abort ();
178
179 return disp & 0x3fffffc;
2662e13f
FB		 180}
181
182static void reloc_pc24 (void *pc, tcg_target_long target)
183{
184 *(uint32_t *) pc = (*(uint32_t *) pc & ~0x3fffffc)
185 | reloc_pc24_val (pc, target);
186}
187
188static uint16_t reloc_pc14_val (void *pc, tcg_target_long target)
189{
932a6909
FB		 190 tcg_target_long disp;
191
192 disp = target - (tcg_target_long) pc;
193 if (disp != (int16_t) disp)
194 tcg_abort ();
195
196 return disp & 0xfffc;
2662e13f
FB		 197}
198
199static void reloc_pc14 (void *pc, tcg_target_long target)
200{
201 *(uint32_t *) pc = (*(uint32_t *) pc & ~0xfffc)
202 | reloc_pc14_val (pc, target);
203}
204
205static void patch_reloc(uint8_t *code_ptr, int type,
206 tcg_target_long value, tcg_target_long addend)
207{
208 value += addend;
209 switch (type) {
210 case R_PPC_REL14:
211 reloc_pc14 (code_ptr, value);
212 break;
213 case R_PPC_REL24:
214 reloc_pc24 (code_ptr, value);
215 break;
216 default:
217 tcg_abort();
218 }
219}
220
221/* maximum number of register used for input function arguments */
222static int tcg_target_get_call_iarg_regs_count(int flags)
223{
b1503cda 224 return ARRAY_SIZE (tcg_target_call_iarg_regs);
2662e13f
FB		 225}
226
227/* parse target specific constraints */
228static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
229{
230 const char *ct_str;
231
232 ct_str = *pct_str;
233 switch (ct_str[0]) {
398ce98e 234 case 'A': case 'B': case 'C': case 'D':
235 ct->ct |= TCG_CT_REG;
236 tcg_regset_set_reg(ct->u.regs, 3 + ct_str[0] - 'A');
237 break;
2662e13f
FB		 238 case 'r':
239 ct->ct |= TCG_CT_REG;
240 tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
241 break;
70fa887c 242#ifdef CONFIG_SOFTMMU
2662e13f
FB		 243 case 'L': /* qemu_ld constraint */
244 ct->ct |= TCG_CT_REG;
245 tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
246 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);
247 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R4);
248 break;
249 case 'K': /* qemu_st[8..32] constraint */
250 ct->ct |= TCG_CT_REG;
251 tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
252 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);
253 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R4);
254 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R5);
255#if TARGET_LONG_BITS == 64
256 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R6);
257#endif
258 break;
259 case 'M': /* qemu_st64 constraint */
260 ct->ct |= TCG_CT_REG;
261 tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
262 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);
263 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R4);
264 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R5);
265 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R6);
266 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R7);
267 break;
70fa887c 268#else
269 case 'L':
270 case 'K':
271 ct->ct |= TCG_CT_REG;
272 tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
273 break;
274 case 'M':
275 ct->ct |= TCG_CT_REG;
276 tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
277 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);
278 break;
279#endif
2662e13f
FB		 280 default:
281 return -1;
282 }
283 ct_str++;
284 *pct_str = ct_str;
285 return 0;
286}
287
288/* test if a constant matches the constraint */
289static int tcg_target_const_match(tcg_target_long val,
290 const TCGArgConstraint *arg_ct)
291{
292 int ct;
293
294 ct = arg_ct->ct;
295 if (ct & TCG_CT_CONST)
296 return 1;
2662e13f
FB		 297 return 0;
298}
299
300#define OPCD(opc) ((opc)<<26)
301#define XO31(opc) (OPCD(31)|((opc)<<1))
302#define XO19(opc) (OPCD(19)|((opc)<<1))
303
304#define B OPCD(18)
305#define BC OPCD(16)
306#define LBZ OPCD(34)
307#define LHZ OPCD(40)
308#define LHA OPCD(42)
309#define LWZ OPCD(32)
310#define STB OPCD(38)
311#define STH OPCD(44)
312#define STW OPCD(36)
313
b0809bf7 314#define ADDIC OPCD(12)
2662e13f
FB		 315#define ADDI OPCD(14)
316#define ADDIS OPCD(15)
317#define ORI OPCD(24)
318#define ORIS OPCD(25)
319#define XORI OPCD(26)
320#define XORIS OPCD(27)
321#define ANDI OPCD(28)
322#define ANDIS OPCD(29)
323#define MULLI OPCD( 7)
324#define CMPLI OPCD(10)
325#define CMPI OPCD(11)
d616cf1d 326#define SUBFIC OPCD( 8)
2662e13f
FB		 327
328#define LWZU OPCD(33)
329#define STWU OPCD(37)
330
331#define RLWINM OPCD(21)
65fe043e 332#define RLWNM OPCD(23)
2662e13f 333
c596defd 334#define BCLR XO19( 16)
2662e13f
FB		 335#define BCCTR XO19(528)
336#define CRAND XO19(257)
c596defd 337#define CRANDC XO19(129)
338#define CRNAND XO19(225)
339#define CROR XO19(449)
b0809bf7 340#define CRNOR XO19( 33)
2662e13f
FB		 341
342#define EXTSB XO31(954)
343#define EXTSH XO31(922)
344#define ADD XO31(266)
345#define ADDE XO31(138)
346#define ADDC XO31( 10)
347#define AND XO31( 28)
348#define SUBF XO31( 40)
349#define SUBFC XO31( 8)
350#define SUBFE XO31(136)
351#define OR XO31(444)
352#define XOR XO31(316)
353#define MULLW XO31(235)
354#define MULHWU XO31( 11)
355#define DIVW XO31(491)
356#define DIVWU XO31(459)
357#define CMP XO31( 0)
358#define CMPL XO31( 32)
359#define LHBRX XO31(790)
360#define LWBRX XO31(534)
361#define STHBRX XO31(918)
362#define STWBRX XO31(662)
363#define MFSPR XO31(339)
364#define MTSPR XO31(467)
365#define SRAWI XO31(824)
366#define NEG XO31(104)
b0809bf7 367#define MFCR XO31( 19)
368#define CNTLZW XO31( 26)
65fe043e 369#define NOR XO31(124)
370#define ANDC XO31( 60)
371#define ORC XO31(412)
aa77bebd 372#define EQV XO31(284)
373#define NAND XO31(476)
2662e13f
FB		 374
375#define LBZX XO31( 87)
4f4a67ae 376#define LHZX XO31(279)
2662e13f
FB		 377#define LHAX XO31(343)
378#define LWZX XO31( 23)
379#define STBX XO31(215)
380#define STHX XO31(407)
381#define STWX XO31(151)
382
383#define SPR(a,b) ((((a)<<5)|(b))<<11)
384#define LR SPR(8, 0)
385#define CTR SPR(9, 0)
386
387#define SLW XO31( 24)
388#define SRW XO31(536)
389#define SRAW XO31(792)
390
2662e13f
FB		 391#define TW XO31(4)
392#define TRAP (TW | TO (31))
393
394#define RT(r) ((r)<<21)
395#define RS(r) ((r)<<21)
396#define RA(r) ((r)<<16)
397#define RB(r) ((r)<<11)
398#define TO(t) ((t)<<21)
399#define SH(s) ((s)<<11)
400#define MB(b) ((b)<<6)
401#define ME(e) ((e)<<1)
402#define BO(o) ((o)<<21)
403
404#define LK 1
405
406#define TAB(t,a,b) (RT(t) | RA(a) | RB(b))
407#define SAB(s,a,b) (RS(s) | RA(a) | RB(b))
408
409#define BF(n) ((n)<<23)
410#define BI(n, c) (((c)+((n)*4))<<16)
411#define BT(n, c) (((c)+((n)*4))<<21)
412#define BA(n, c) (((c)+((n)*4))<<16)
413#define BB(n, c) (((c)+((n)*4))<<11)
414
415#define BO_COND_TRUE BO (12)
416#define BO_COND_FALSE BO (4)
417#define BO_ALWAYS BO (20)
418
419enum {
420 CR_LT,
421 CR_GT,
422 CR_EQ,
423 CR_SO
424};
425
426static const uint32_t tcg_to_bc[10] = {
427 [TCG_COND_EQ] = BC | BI (7, CR_EQ) | BO_COND_TRUE,
428 [TCG_COND_NE] = BC | BI (7, CR_EQ) | BO_COND_FALSE,
429 [TCG_COND_LT] = BC | BI (7, CR_LT) | BO_COND_TRUE,
430 [TCG_COND_GE] = BC | BI (7, CR_LT) | BO_COND_FALSE,
431 [TCG_COND_LE] = BC | BI (7, CR_GT) | BO_COND_FALSE,
432 [TCG_COND_GT] = BC | BI (7, CR_GT) | BO_COND_TRUE,
433 [TCG_COND_LTU] = BC | BI (7, CR_LT) | BO_COND_TRUE,
434 [TCG_COND_GEU] = BC | BI (7, CR_LT) | BO_COND_FALSE,
435 [TCG_COND_LEU] = BC | BI (7, CR_GT) | BO_COND_FALSE,
436 [TCG_COND_GTU] = BC | BI (7, CR_GT) | BO_COND_TRUE,
437};
438
439static void tcg_out_mov(TCGContext *s, int ret, int arg)
440{
441 tcg_out32 (s, OR | SAB (arg, ret, arg));
442}
443
444static void tcg_out_movi(TCGContext *s, TCGType type,
445 int ret, tcg_target_long arg)
446{
447 if (arg == (int16_t) arg)
448 tcg_out32 (s, ADDI | RT (ret) | RA (0) | (arg & 0xffff));
449 else {
450 tcg_out32 (s, ADDIS | RT (ret) | RA (0) | ((arg >> 16) & 0xffff));
451 if (arg & 0xffff)
0a878c47 452 tcg_out32 (s, ORI | RS (ret) | RA (ret) | (arg & 0xffff));
2662e13f
FB		 453 }
454}
455
456static void tcg_out_ldst (TCGContext *s, int ret, int addr,
457 int offset, int op1, int op2)
458{
459 if (offset == (int16_t) offset)
460 tcg_out32 (s, op1 | RT (ret) | RA (addr) | (offset & 0xffff));
461 else {
462 tcg_out_movi (s, TCG_TYPE_I32, 0, offset);
463 tcg_out32 (s, op2 | RT (ret) | RA (addr) | RB (0));
464 }
465}
466
932a6909
FB		 467static void tcg_out_b (TCGContext *s, int mask, tcg_target_long target)
468{
469 tcg_target_long disp;
470
471 disp = target - (tcg_target_long) s->code_ptr;
472 if ((disp << 6) >> 6 == disp)
8c5e95d8 473 tcg_out32 (s, B | (disp & 0x3fffffc) | mask);
932a6909
FB		 474 else {
475 tcg_out_movi (s, TCG_TYPE_I32, 0, (tcg_target_long) target);
476 tcg_out32 (s, MTSPR | RS (0) | CTR);
477 tcg_out32 (s, BCCTR | BO_ALWAYS | mask);
478 }
479}
480
b29fe3ed 481static void tcg_out_call (TCGContext *s, tcg_target_long arg, int const_arg)
482{
6ec85236 483#ifdef _CALL_AIX
b29fe3ed 484 int reg;
485
486 if (const_arg) {
487 reg = 2;
488 tcg_out_movi (s, TCG_TYPE_I32, reg, arg);
489 }
490 else reg = arg;
491
492 tcg_out32 (s, LWZ | RT (0) | RA (reg));
493 tcg_out32 (s, MTSPR | RA (0) | CTR);
494 tcg_out32 (s, LWZ | RT (2) | RA (reg) | 4);
495 tcg_out32 (s, BCCTR | BO_ALWAYS | LK);
d9370327 496#else
497 if (const_arg) {
498 tcg_out_b (s, LK, arg);
499 }
500 else {
501 tcg_out32 (s, MTSPR | RS (arg) | LR);
502 tcg_out32 (s, BCLR | BO_ALWAYS | LK);
503 }
b29fe3ed 504#endif
d9370327 505}
b29fe3ed 506
2662e13f 507#if defined(CONFIG_SOFTMMU)
79383c9c
BS		 508
509#include "../../softmmu_defs.h"
2662e13f
FB		 510
511static void *qemu_ld_helpers[4] = {
512 __ldb_mmu,
513 __ldw_mmu,
514 __ldl_mmu,
515 __ldq_mmu,
516};
517
518static void *qemu_st_helpers[4] = {
519 __stb_mmu,
520 __stw_mmu,
521 __stl_mmu,
522 __stq_mmu,
523};
524#endif
525
526static void tcg_out_qemu_ld (TCGContext *s, const TCGArg *args, int opc)
527{
f6548c0a 528 int addr_reg, data_reg, data_reg2, r0, r1, rbase, mem_index, s_bits, bswap;
2662e13f 529#ifdef CONFIG_SOFTMMU
f8edcbaa 530 int r2;
2662e13f
FB		 531 void *label1_ptr, *label2_ptr;
532#endif
533#if TARGET_LONG_BITS == 64
534 int addr_reg2;
535#endif
536
537 data_reg = *args++;
538 if (opc == 3)
539 data_reg2 = *args++;
540 else
541 data_reg2 = 0;
542 addr_reg = *args++;
543#if TARGET_LONG_BITS == 64
544 addr_reg2 = *args++;
545#endif
546 mem_index = *args;
547 s_bits = opc & 3;
548
549#ifdef CONFIG_SOFTMMU
550 r0 = 3;
551 r1 = 4;
552 r2 = 0;
f6548c0a 553 rbase = 0;
2662e13f
FB		 554
555 tcg_out32 (s, (RLWINM
556 | RA (r0)
557 | RS (addr_reg)
558 | SH (32 - (TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS))
559 | MB (32 - (CPU_TLB_BITS + CPU_TLB_ENTRY_BITS))
560 | ME (31 - CPU_TLB_ENTRY_BITS)
561 )
562 );
563 tcg_out32 (s, ADD | RT (r0) | RA (r0) | RB (TCG_AREG0));
564 tcg_out32 (s, (LWZU
565 | RT (r1)
566 | RA (r0)
567 | offsetof (CPUState, tlb_table[mem_index][0].addr_read)
568 )
569 );
570 tcg_out32 (s, (RLWINM
571 | RA (r2)
572 | RS (addr_reg)
573 | SH (0)
574 | MB ((32 - s_bits) & 31)
575 | ME (31 - TARGET_PAGE_BITS)
576 )
577 );
578
579 tcg_out32 (s, CMP | BF (7) | RA (r2) | RB (r1));
580#if TARGET_LONG_BITS == 64
581 tcg_out32 (s, LWZ | RT (r1) | RA (r0) | 4);
582 tcg_out32 (s, CMP | BF (6) | RA (addr_reg2) | RB (r1));
583 tcg_out32 (s, CRAND | BT (7, CR_EQ) | BA (6, CR_EQ) | BB (7, CR_EQ));
584#endif
585
586 label1_ptr = s->code_ptr;
587#ifdef FAST_PATH
588 tcg_out32 (s, BC | BI (7, CR_EQ) | BO_COND_TRUE);
589#endif
590
591 /* slow path */
592#if TARGET_LONG_BITS == 32
593 tcg_out_mov (s, 3, addr_reg);
594 tcg_out_movi (s, TCG_TYPE_I32, 4, mem_index);
595#else
596 tcg_out_mov (s, 3, addr_reg2);
597 tcg_out_mov (s, 4, addr_reg);
598 tcg_out_movi (s, TCG_TYPE_I32, 5, mem_index);
599#endif
600
b29fe3ed 601 tcg_out_call (s, (tcg_target_long) qemu_ld_helpers[s_bits], 1);
2662e13f
FB		 602 switch (opc) {
603 case 0|4:
604 tcg_out32 (s, EXTSB | RA (data_reg) | RS (3));
605 break;
606 case 1|4:
607 tcg_out32 (s, EXTSH | RA (data_reg) | RS (3));
608 break;
609 case 0:
610 case 1:
611 case 2:
612 if (data_reg != 3)
613 tcg_out_mov (s, data_reg, 3);
614 break;
615 case 3:
616 if (data_reg == 3) {
617 if (data_reg2 == 4) {
618 tcg_out_mov (s, 0, 4);
619 tcg_out_mov (s, 4, 3);
620 tcg_out_mov (s, 3, 0);
621 }
622 else {
623 tcg_out_mov (s, data_reg2, 3);
624 tcg_out_mov (s, 3, 4);
625 }
626 }
627 else {
628 if (data_reg != 4) tcg_out_mov (s, data_reg, 4);
629 if (data_reg2 != 3) tcg_out_mov (s, data_reg2, 3);
630 }
631 break;
632 }
633 label2_ptr = s->code_ptr;
634 tcg_out32 (s, B);
635
636 /* label1: fast path */
637#ifdef FAST_PATH
638 reloc_pc14 (label1_ptr, (tcg_target_long) s->code_ptr);
639#endif
640
641 /* r0 now contains &env->tlb_table[mem_index][index].addr_read */
642 tcg_out32 (s, (LWZ
643 | RT (r0)
644 | RA (r0)
355b1943 645 | (offsetof (CPUTLBEntry, addend)
2662e13f
FB		 646 - offsetof (CPUTLBEntry, addr_read))
647 ));
648 /* r0 = env->tlb_table[mem_index][index].addend */
649 tcg_out32 (s, ADD | RT (r0) | RA (r0) | RB (addr_reg));
650 /* r0 = env->tlb_table[mem_index][index].addend + addr */
651
652#else /* !CONFIG_SOFTMMU */
653 r0 = addr_reg;
f8edcbaa 654 r1 = 3;
f6548c0a 655 rbase = GUEST_BASE ? TCG_GUEST_BASE_REG : 0;
2662e13f
FB		 656#endif
657
658#ifdef TARGET_WORDS_BIGENDIAN
659 bswap = 0;
660#else
661 bswap = 1;
662#endif
f6548c0a 663
2662e13f
FB		 664 switch (opc) {
665 default:
666 case 0:
f6548c0a 667 tcg_out32 (s, LBZX | TAB (data_reg, rbase, r0));
2662e13f
FB		 668 break;
669 case 0|4:
f6548c0a 670 tcg_out32 (s, LBZX | TAB (data_reg, rbase, r0));
2662e13f
FB		 671 tcg_out32 (s, EXTSB | RA (data_reg) | RS (data_reg));
672 break;
673 case 1:
f6548c0a 674 if (bswap)
675 tcg_out32 (s, LHBRX | TAB (data_reg, rbase, r0));
676 else
677 tcg_out32 (s, LHZX | TAB (data_reg, rbase, r0));
2662e13f
FB		 678 break;
679 case 1|4:
680 if (bswap) {
f6548c0a 681 tcg_out32 (s, LHBRX | TAB (data_reg, rbase, r0));
2662e13f
FB		 682 tcg_out32 (s, EXTSH | RA (data_reg) | RS (data_reg));
683 }
f6548c0a 684 else tcg_out32 (s, LHAX | TAB (data_reg, rbase, r0));
2662e13f
FB		 685 break;
686 case 2:
f6548c0a 687 if (bswap)
688 tcg_out32 (s, LWBRX | TAB (data_reg, rbase, r0));
689 else
690 tcg_out32 (s, LWZX | TAB (data_reg, rbase, r0));
2662e13f
FB		 691 break;
692 case 3:
693 if (bswap) {
f6548c0a 694 tcg_out32 (s, ADDI | RT (r1) | RA (r0) | 4);
695 tcg_out32 (s, LWBRX | TAB (data_reg, rbase, r0));
696 tcg_out32 (s, LWBRX | TAB (data_reg2, rbase, r1));
2662e13f
FB		 697 }
698 else {
f6548c0a 699#ifdef CONFIG_USE_GUEST_BASE
700 tcg_out32 (s, ADDI | RT (r1) | RA (r0) | 4);
701 tcg_out32 (s, LWZX | TAB (data_reg2, rbase, r0));
702 tcg_out32 (s, LWZX | TAB (data_reg, rbase, r1));
703#else
2662e13f
FB		 704 if (r0 == data_reg2) {
705 tcg_out32 (s, LWZ | RT (0) | RA (r0));
706 tcg_out32 (s, LWZ | RT (data_reg) | RA (r0) | 4);
707 tcg_out_mov (s, data_reg2, 0);
708 }
709 else {
710 tcg_out32 (s, LWZ | RT (data_reg2) | RA (r0));
711 tcg_out32 (s, LWZ | RT (data_reg) | RA (r0) | 4);
712 }
f6548c0a 713#endif
2662e13f
FB		 714 }
715 break;
716 }
717
718#ifdef CONFIG_SOFTMMU
719 reloc_pc24 (label2_ptr, (tcg_target_long) s->code_ptr);
720#endif
721}
722
723static void tcg_out_qemu_st (TCGContext *s, const TCGArg *args, int opc)
724{
f6548c0a 725 int addr_reg, r0, r1, data_reg, data_reg2, mem_index, bswap, rbase;
2662e13f
FB		 726#ifdef CONFIG_SOFTMMU
727 int r2, ir;
728 void *label1_ptr, *label2_ptr;
729#endif
730#if TARGET_LONG_BITS == 64
731 int addr_reg2;
732#endif
733
734 data_reg = *args++;
735 if (opc == 3)
736 data_reg2 = *args++;
737 else
738 data_reg2 = 0;
739 addr_reg = *args++;
740#if TARGET_LONG_BITS == 64
741 addr_reg2 = *args++;
742#endif
743 mem_index = *args;
744
745#ifdef CONFIG_SOFTMMU
746 r0 = 3;
747 r1 = 4;
748 r2 = 0;
f6548c0a 749 rbase = 0;
2662e13f
FB		 750
751 tcg_out32 (s, (RLWINM
752 | RA (r0)
753 | RS (addr_reg)
754 | SH (32 - (TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS))
755 | MB (32 - (CPU_TLB_ENTRY_BITS + CPU_TLB_BITS))
756 | ME (31 - CPU_TLB_ENTRY_BITS)
757 )
758 );
759 tcg_out32 (s, ADD | RT (r0) | RA (r0) | RB (TCG_AREG0));
760 tcg_out32 (s, (LWZU
761 | RT (r1)
762 | RA (r0)
763 | offsetof (CPUState, tlb_table[mem_index][0].addr_write)
764 )
765 );
766 tcg_out32 (s, (RLWINM
767 | RA (r2)
768 | RS (addr_reg)
769 | SH (0)
770 | MB ((32 - opc) & 31)
771 | ME (31 - TARGET_PAGE_BITS)
772 )
773 );
774
775 tcg_out32 (s, CMP | (7 << 23) | RA (r2) | RB (r1));
776#if TARGET_LONG_BITS == 64
777 tcg_out32 (s, LWZ | RT (r1) | RA (r0) | 4);
778 tcg_out32 (s, CMP | BF (6) | RA (addr_reg2) | RB (r1));
779 tcg_out32 (s, CRAND | BT (7, CR_EQ) | BA (6, CR_EQ) | BB (7, CR_EQ));
780#endif
781
782 label1_ptr = s->code_ptr;
783#ifdef FAST_PATH
784 tcg_out32 (s, BC | BI (7, CR_EQ) | BO_COND_TRUE);
785#endif
786
787 /* slow path */
788#if TARGET_LONG_BITS == 32
789 tcg_out_mov (s, 3, addr_reg);
790 ir = 4;
791#else
792 tcg_out_mov (s, 3, addr_reg2);
793 tcg_out_mov (s, 4, addr_reg);
f9bf2987 794#ifdef TCG_TARGET_CALL_ALIGN_ARGS
2662e13f 795 ir = 5;
f9bf2987 796#else
797 ir = 4;
798#endif
2662e13f
FB		 799#endif
800
801 switch (opc) {
802 case 0:
803 tcg_out32 (s, (RLWINM
804 | RA (ir)
805 | RS (data_reg)
806 | SH (0)
807 | MB (24)
808 | ME (31)));
809 break;
810 case 1:
811 tcg_out32 (s, (RLWINM
812 | RA (ir)
813 | RS (data_reg)
814 | SH (0)
815 | MB (16)
816 | ME (31)));
817 break;
818 case 2:
819 tcg_out_mov (s, ir, data_reg);
820 break;
821 case 3:
f9bf2987 822#ifdef TCG_TARGET_CALL_ALIGN_ARGS
823 ir = 5;
824#endif
825 tcg_out_mov (s, ir++, data_reg2);
826 tcg_out_mov (s, ir, data_reg);
2662e13f
FB		 827 break;
828 }
829 ir++;
830
831 tcg_out_movi (s, TCG_TYPE_I32, ir, mem_index);
b29fe3ed 832 tcg_out_call (s, (tcg_target_long) qemu_st_helpers[opc], 1);
2662e13f
FB		 833 label2_ptr = s->code_ptr;
834 tcg_out32 (s, B);
835
836 /* label1: fast path */
837#ifdef FAST_PATH
838 reloc_pc14 (label1_ptr, (tcg_target_long) s->code_ptr);
839#endif
840
841 tcg_out32 (s, (LWZ
842 | RT (r0)
843 | RA (r0)
355b1943 844 | (offsetof (CPUTLBEntry, addend)
2662e13f
FB		 845 - offsetof (CPUTLBEntry, addr_write))
846 ));
847 /* r0 = env->tlb_table[mem_index][index].addend */
848 tcg_out32 (s, ADD | RT (r0) | RA (r0) | RB (addr_reg));
849 /* r0 = env->tlb_table[mem_index][index].addend + addr */
850
851#else /* !CONFIG_SOFTMMU */
2662e13f 852 r0 = addr_reg;
f6548c0a 853 r1 = 3;
a71836de 854 rbase = GUEST_BASE ? TCG_GUEST_BASE_REG : 0;
2662e13f
FB		 855#endif
856
857#ifdef TARGET_WORDS_BIGENDIAN
858 bswap = 0;
859#else
860 bswap = 1;
861#endif
862 switch (opc) {
863 case 0:
f6548c0a 864 tcg_out32 (s, STBX | SAB (data_reg, rbase, r0));
2662e13f
FB		 865 break;
866 case 1:
f6548c0a 867 if (bswap)
868 tcg_out32 (s, STHBRX | SAB (data_reg, rbase, r0));
869 else
870 tcg_out32 (s, STHX | SAB (data_reg, rbase, r0));
2662e13f
FB		 871 break;
872 case 2:
f6548c0a 873 if (bswap)
874 tcg_out32 (s, STWBRX | SAB (data_reg, rbase, r0));
875 else
876 tcg_out32 (s, STWX | SAB (data_reg, rbase, r0));
2662e13f
FB		 877 break;
878 case 3:
879 if (bswap) {
880 tcg_out32 (s, ADDI | RT (r1) | RA (r0) | 4);
f6548c0a 881 tcg_out32 (s, STWBRX | SAB (data_reg, rbase, r0));
882 tcg_out32 (s, STWBRX | SAB (data_reg2, rbase, r1));
2662e13f
FB		 883 }
884 else {
f6548c0a 885#ifdef CONFIG_USE_GUEST_BASE
886 tcg_out32 (s, STWX | SAB (data_reg2, rbase, r0));
887 tcg_out32 (s, ADDI | RT (r1) | RA (r0) | 4);
888 tcg_out32 (s, STWX | SAB (data_reg, rbase, r1));
889#else
2662e13f
FB		 890 tcg_out32 (s, STW | RS (data_reg2) | RA (r0));
891 tcg_out32 (s, STW | RS (data_reg) | RA (r0) | 4);
f6548c0a 892#endif
2662e13f
FB		 893 }
894 break;
895 }
896
897#ifdef CONFIG_SOFTMMU
898 reloc_pc24 (label2_ptr, (tcg_target_long) s->code_ptr);
899#endif
900}
901
902void tcg_target_qemu_prologue (TCGContext *s)
903{
0d5bd363 904 int i, frame_size;
2662e13f
FB		 905
906 frame_size = 0
f9bf2987 907 + LINKAGE_AREA_SIZE
2662e13f
FB		 908 + TCG_STATIC_CALL_ARGS_SIZE
909 + ARRAY_SIZE (tcg_target_callee_save_regs) * 4
910 ;
911 frame_size = (frame_size + 15) & ~15;
912
6ec85236 913#ifdef _CALL_AIX
b29fe3ed 914 {
915 uint32_t addr;
916
917 /* First emit adhoc function descriptor */
918 addr = (uint32_t) s->code_ptr + 12;
919 tcg_out32 (s, addr); /* entry point */
920 s->code_ptr += 8; /* skip TOC and environment pointer */
921 }
922#endif
2662e13f
FB		 923 tcg_out32 (s, MFSPR | RT (0) | LR);
924 tcg_out32 (s, STWU | RS (1) | RA (1) | (-frame_size & 0xffff));
925 for (i = 0; i < ARRAY_SIZE (tcg_target_callee_save_regs); ++i)
926 tcg_out32 (s, (STW
927 | RS (tcg_target_callee_save_regs[i])
928 | RA (1)
f9bf2987 929 | (i * 4 + LINKAGE_AREA_SIZE + TCG_STATIC_CALL_ARGS_SIZE)
2662e13f
FB		 930 )
931 );
2946898b 932 tcg_out32 (s, STW | RS (0) | RA (1) | (frame_size + LR_OFFSET));
2662e13f 933
f6548c0a 934#ifdef CONFIG_USE_GUEST_BASE
935 tcg_out_movi (s, TCG_TYPE_I32, TCG_GUEST_BASE_REG, GUEST_BASE);
936#endif
937
2662e13f
FB		 938 tcg_out32 (s, MTSPR | RS (3) | CTR);
939 tcg_out32 (s, BCCTR | BO_ALWAYS);
940 tb_ret_addr = s->code_ptr;
941
942 for (i = 0; i < ARRAY_SIZE (tcg_target_callee_save_regs); ++i)
943 tcg_out32 (s, (LWZ
944 | RT (tcg_target_callee_save_regs[i])
945 | RA (1)
f9bf2987 946 | (i * 4 + LINKAGE_AREA_SIZE + TCG_STATIC_CALL_ARGS_SIZE)
2662e13f
FB		 947 )
948 );
2946898b 949 tcg_out32 (s, LWZ | RT (0) | RA (1) | (frame_size + LR_OFFSET));
2662e13f
FB		 950 tcg_out32 (s, MTSPR | RS (0) | LR);
951 tcg_out32 (s, ADDI | RT (1) | RA (1) | frame_size);
952 tcg_out32 (s, BCLR | BO_ALWAYS);
953}
954
955static void tcg_out_ld (TCGContext *s, TCGType type, int ret, int arg1,
956 tcg_target_long arg2)
957{
958 tcg_out_ldst (s, ret, arg1, arg2, LWZ, LWZX);
959}
960
961static void tcg_out_st (TCGContext *s, TCGType type, int arg, int arg1,
962 tcg_target_long arg2)
963{
964 tcg_out_ldst (s, arg, arg1, arg2, STW, STWX);
965}
966
967static void ppc_addi (TCGContext *s, int rt, int ra, tcg_target_long si)
968{
969 if (!si && rt == ra)
970 return;
971
972 if (si == (int16_t) si)
973 tcg_out32 (s, ADDI | RT (rt) | RA (ra) | (si & 0xffff));
974 else {
975 uint16_t h = ((si >> 16) & 0xffff) + ((uint16_t) si >> 15);
976 tcg_out32 (s, ADDIS | RT (rt) | RA (ra) | h);
977 tcg_out32 (s, ADDI | RT (rt) | RA (rt) | (si & 0xffff));
978 }
979}
980
981static void tcg_out_addi(TCGContext *s, int reg, tcg_target_long val)
982{
983 ppc_addi (s, reg, reg, val);
984}
985
c596defd 986static void tcg_out_cmp (TCGContext *s, int cond, TCGArg arg1, TCGArg arg2,
987 int const_arg2, int cr)
2662e13f 988{
2662e13f
FB		 989 int imm;
990 uint32_t op;
991
2662e13f 992 switch (cond) {
f3f478a7
FB		 993 case TCG_COND_EQ:
994 case TCG_COND_NE:
995 if (const_arg2) {
996 if ((int16_t) arg2 == arg2) {
997 op = CMPI;
998 imm = 1;
999 break;
1000 }
1001 else if ((uint16_t) arg2 == arg2) {
1002 op = CMPLI;
1003 imm = 1;
1004 break;
1005 }
1006 }
1007 op = CMPL;
1008 imm = 0;
1009 break;
1010
1011 case TCG_COND_LT:
1012 case TCG_COND_GE:
1013 case TCG_COND_LE:
1014 case TCG_COND_GT:
1015 if (const_arg2) {
1016 if ((int16_t) arg2 == arg2) {
1017 op = CMPI;
1018 imm = 1;
1019 break;
1020 }
1021 }
1022 op = CMP;
1023 imm = 0;
1024 break;
1025
1026 case TCG_COND_LTU:
1027 case TCG_COND_GEU:
1028 case TCG_COND_LEU:
1029 case TCG_COND_GTU:
1030 if (const_arg2) {
1031 if ((uint16_t) arg2 == arg2) {
1032 op = CMPLI;
1033 imm = 1;
1034 break;
1035 }
1036 }
1037 op = CMPL;
1038 imm = 0;
1039 break;
1040
2662e13f
FB		 1041 default:
1042 tcg_abort ();
1043 }
c596defd 1044 op |= BF (cr);
2662e13f
FB		 1045
1046 if (imm)
1047 tcg_out32 (s, op | RA (arg1) | (arg2 & 0xffff));
1048 else {
1049 if (const_arg2) {
1050 tcg_out_movi (s, TCG_TYPE_I32, 0, arg2);
1051 tcg_out32 (s, op | RA (arg1) | RB (0));
1052 }
1053 else
1054 tcg_out32 (s, op | RA (arg1) | RB (arg2));
1055 }
1056
c596defd 1057}
1058
1059static void tcg_out_bc (TCGContext *s, int bc, int label_index)
1060{
1061 TCGLabel *l = &s->labels[label_index];
1062
0a878c47 1063 if (l->has_value)
c596defd 1064 tcg_out32 (s, bc | reloc_pc14_val (s->code_ptr, l->u.value));
2662e13f 1065 else {
0a878c47 1066 uint16_t val = *(uint16_t *) &s->code_ptr[2];
1067
1068 /* Thanks to Andrzej Zaborowski */
c596defd 1069 tcg_out32 (s, bc | (val & 0xfffc));
2662e13f
FB		 1070 tcg_out_reloc (s, s->code_ptr - 4, R_PPC_REL14, label_index, 0);
1071 }
1072}
1073
b0809bf7 1074static void tcg_out_cr7eq_from_cond (TCGContext *s, const TCGArg *args,
1075 const int *const_args)
c596defd 1076{
8a56e840
RH		 1077 TCGCond cond = args[4];
1078 int op;
c596defd 1079 struct { int bit1; int bit2; int cond2; } bits[] = {
1080 [TCG_COND_LT ] = { CR_LT, CR_LT, TCG_COND_LT },
1081 [TCG_COND_LE ] = { CR_LT, CR_GT, TCG_COND_LT },
1082 [TCG_COND_GT ] = { CR_GT, CR_GT, TCG_COND_GT },
1083 [TCG_COND_GE ] = { CR_GT, CR_LT, TCG_COND_GT },
1084 [TCG_COND_LTU] = { CR_LT, CR_LT, TCG_COND_LTU },
1085 [TCG_COND_LEU] = { CR_LT, CR_GT, TCG_COND_LTU },
1086 [TCG_COND_GTU] = { CR_GT, CR_GT, TCG_COND_GTU },
1087 [TCG_COND_GEU] = { CR_GT, CR_LT, TCG_COND_GTU },
1088 }, *b = &bits[cond];
1089
1090 switch (cond) {
2662e13f 1091 case TCG_COND_EQ:
2662e13f 1092 case TCG_COND_NE:
e924c485 1093 op = (cond == TCG_COND_EQ) ? CRAND : CRNAND;
1094 tcg_out_cmp (s, cond, args[0], args[2], const_args[2], 6);
1095 tcg_out_cmp (s, cond, args[1], args[3], const_args[3], 7);
1096 tcg_out32 (s, op | BT (7, CR_EQ) | BA (6, CR_EQ) | BB (7, CR_EQ));
2662e13f
FB		 1097 break;
1098 case TCG_COND_LT:
2662e13f 1099 case TCG_COND_LE:
2662e13f 1100 case TCG_COND_GT:
2662e13f 1101 case TCG_COND_GE:
2662e13f 1102 case TCG_COND_LTU:
2662e13f 1103 case TCG_COND_LEU:
2662e13f 1104 case TCG_COND_GTU:
2662e13f 1105 case TCG_COND_GEU:
c596defd 1106 op = (b->bit1 != b->bit2) ? CRANDC : CRAND;
1107 tcg_out_cmp (s, b->cond2, args[1], args[3], const_args[3], 5);
1108 tcg_out_cmp (s, TCG_COND_EQ, args[1], args[3], const_args[3], 6);
1109 tcg_out_cmp (s, cond, args[0], args[2], const_args[2], 7);
1110 tcg_out32 (s, op | BT (7, CR_EQ) | BA (6, CR_EQ) | BB (7, b->bit2));
1111 tcg_out32 (s, CROR | BT (7, CR_EQ) | BA (5, b->bit1) | BB (7, CR_EQ));
2662e13f
FB		 1112 break;
1113 default:
1114 tcg_abort();
1115 }
b0809bf7 1116}
1117
8a56e840 1118static void tcg_out_setcond (TCGContext *s, TCGCond cond, TCGArg arg0,
b0809bf7 1119 TCGArg arg1, TCGArg arg2, int const_arg2)
1120{
1121 int crop, sh, arg;
1122
1123 switch (cond) {
1124 case TCG_COND_EQ:
1125 if (const_arg2) {
1126 if (!arg2) {
1127 arg = arg1;
1128 }
1129 else {
1130 arg = 0;
1131 if ((uint16_t) arg2 == arg2) {
1132 tcg_out32 (s, XORI | RS (arg1) | RA (0) | arg2);
1133 }
1134 else {
1135 tcg_out_movi (s, TCG_TYPE_I32, 0, arg2);
1136 tcg_out32 (s, XOR | SAB (arg1, 0, 0));
1137 }
1138 }
1139 }
1140 else {
1141 arg = 0;
1142 tcg_out32 (s, XOR | SAB (arg1, 0, arg2));
1143 }
1144 tcg_out32 (s, CNTLZW | RS (arg) | RA (0));
1145 tcg_out32 (s, (RLWINM
1146 | RA (arg0)
1147 | RS (0)
1148 | SH (27)
1149 | MB (5)
1150 | ME (31)
1151 )
1152 );
27a7797b 1153 break;
b0809bf7 1154
1155 case TCG_COND_NE:
1156 if (const_arg2) {
1157 if (!arg2) {
1158 arg = arg1;
1159 }
1160 else {
1161 arg = 0;
1162 if ((uint16_t) arg2 == arg2) {
1163 tcg_out32 (s, XORI | RS (arg1) | RA (0) | arg2);
1164 }
1165 else {
1166 tcg_out_movi (s, TCG_TYPE_I32, 0, arg2);
1167 tcg_out32 (s, XOR | SAB (arg1, 0, 0));
1168 }
1169 }
1170 }
1171 else {
1172 arg = 0;
1173 tcg_out32 (s, XOR | SAB (arg1, 0, arg2));
1174 }
1175
1176 if (arg == arg1 && arg1 == arg0) {
1177 tcg_out32 (s, ADDIC | RT (0) | RA (arg) | 0xffff);
1178 tcg_out32 (s, SUBFE | TAB (arg0, 0, arg));
1179 }
1180 else {
1181 tcg_out32 (s, ADDIC | RT (arg0) | RA (arg) | 0xffff);
1182 tcg_out32 (s, SUBFE | TAB (arg0, arg0, arg));
1183 }
27a7797b 1184 break;
1185
1186 case TCG_COND_GT:
1187 case TCG_COND_GTU:
1188 sh = 30;
1189 crop = 0;
1190 goto crtest;
b0809bf7 1191
b0809bf7 1192 case TCG_COND_LT:
27a7797b 1193 case TCG_COND_LTU:
b0809bf7 1194 sh = 29;
1195 crop = 0;
27a7797b 1196 goto crtest;
b0809bf7 1197
b0809bf7 1198 case TCG_COND_GE:
27a7797b 1199 case TCG_COND_GEU:
b0809bf7 1200 sh = 31;
1201 crop = CRNOR | BT (7, CR_EQ) | BA (7, CR_LT) | BB (7, CR_LT);
27a7797b 1202 goto crtest;
b0809bf7 1203
b0809bf7 1204 case TCG_COND_LE:
27a7797b 1205 case TCG_COND_LEU:
b0809bf7 1206 sh = 31;
1207 crop = CRNOR | BT (7, CR_EQ) | BA (7, CR_GT) | BB (7, CR_GT);
27a7797b 1208 crtest:
1209 tcg_out_cmp (s, cond, arg1, arg2, const_arg2, 7);
1210 if (crop) tcg_out32 (s, crop);
1211 tcg_out32 (s, MFCR | RT (0));
1212 tcg_out32 (s, (RLWINM
1213 | RA (arg0)
1214 | RS (0)
1215 | SH (sh)
1216 | MB (31)
1217 | ME (31)
1218 )
1219 );
b0809bf7 1220 break;
1221
1222 default:
1223 tcg_abort ();
1224 }
b0809bf7 1225}
1226
1227static void tcg_out_setcond2 (TCGContext *s, const TCGArg *args,
1228 const int *const_args)
1229{
1230 tcg_out_cr7eq_from_cond (s, args + 1, const_args + 1);
1231 tcg_out32 (s, MFCR | RT (0));
1232 tcg_out32 (s, (RLWINM
1233 | RA (args[0])
1234 | RS (0)
1235 | SH (31)
1236 | MB (31)
1237 | ME (31)
1238 )
1239 );
1240}
1241
8a56e840 1242static void tcg_out_brcond (TCGContext *s, TCGCond cond,
b0809bf7 1243 TCGArg arg1, TCGArg arg2, int const_arg2,
1244 int label_index)
1245{
1246 tcg_out_cmp (s, cond, arg1, arg2, const_arg2, 7);
1247 tcg_out_bc (s, tcg_to_bc[cond], label_index);
1248}
1249
1250/* XXX: we implement it at the target level to avoid having to
1251 handle cross basic blocks temporaries */
1252static void tcg_out_brcond2 (TCGContext *s, const TCGArg *args,
1253 const int *const_args)
1254{
1255 tcg_out_cr7eq_from_cond (s, args, const_args);
1256 tcg_out_bc (s, (BC | BI (7, CR_EQ) | BO_COND_TRUE), args[5]);
2662e13f
FB		 1257}
1258
52781543 1259void ppc_tb_set_jmp_target (unsigned long jmp_addr, unsigned long addr)
1260{
1261 uint32_t *ptr;
1262 long disp = addr - jmp_addr;
1263 unsigned long patch_size;
1264
1265 ptr = (uint32_t *)jmp_addr;
1266
1267 if ((disp << 6) >> 6 != disp) {
1268 ptr[0] = 0x3c000000 | (addr >> 16); /* lis 0,addr@ha */
1269 ptr[1] = 0x60000000 | (addr & 0xffff); /* la 0,addr@l(0) */
1270 ptr[2] = 0x7c0903a6; /* mtctr 0 */
1271 ptr[3] = 0x4e800420; /* brctr */
1272 patch_size = 16;
1273 } else {
1274 /* patch the branch destination */
1275 if (disp != 16) {
1276 *ptr = 0x48000000 | (disp & 0x03fffffc); /* b disp */
1277 patch_size = 4;
1278 } else {
1279 ptr[0] = 0x60000000; /* nop */
1280 ptr[1] = 0x60000000;
1281 ptr[2] = 0x60000000;
1282 ptr[3] = 0x60000000;
1283 patch_size = 16;
1284 }
1285 }
1286 /* flush icache */
1287 flush_icache_range(jmp_addr, jmp_addr + patch_size);
1288}
1289
a9751609 1290static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
2662e13f
FB		 1291 const int *const_args)
1292{
1293 switch (opc) {
1294 case INDEX_op_exit_tb:
1295 tcg_out_movi (s, TCG_TYPE_I32, TCG_REG_R3, args[0]);
932a6909 1296 tcg_out_b (s, 0, (tcg_target_long) tb_ret_addr);
2662e13f
FB		 1297 break;
1298 case INDEX_op_goto_tb:
1299 if (s->tb_jmp_offset) {
1300 /* direct jump method */
932a6909 1301
2662e13f 1302 s->tb_jmp_offset[args[0]] = s->code_ptr - s->code_buf;
0a878c47 1303 s->code_ptr += 16;
932a6909
FB		 1304 }
1305 else {
2662e13f
FB		 1306 tcg_abort ();
1307 }
1308 s->tb_next_offset[args[0]] = s->code_ptr - s->code_buf;
1309 break;
1310 case INDEX_op_br:
1311 {
1312 TCGLabel *l = &s->labels[args[0]];
1313
1314 if (l->has_value) {
932a6909 1315 tcg_out_b (s, 0, l->u.value);
2662e13f
FB		 1316 }
1317 else {
0a878c47 1318 uint32_t val = *(uint32_t *) s->code_ptr;
1319
1320 /* Thanks to Andrzej Zaborowski */
1321 tcg_out32 (s, B | (val & 0x3fffffc));
2662e13f
FB		 1322 tcg_out_reloc (s, s->code_ptr - 4, R_PPC_REL24, args[0], 0);
1323 }
1324 }
1325 break;
1326 case INDEX_op_call:
b29fe3ed 1327 tcg_out_call (s, args[0], const_args[0]);
2662e13f
FB		 1328 break;
1329 case INDEX_op_jmp:
1330 if (const_args[0]) {
932a6909 1331 tcg_out_b (s, 0, args[0]);
2662e13f
FB		 1332 }
1333 else {
1334 tcg_out32 (s, MTSPR | RS (args[0]) | CTR);
1335 tcg_out32 (s, BCCTR | BO_ALWAYS);
1336 }
1337 break;
1338 case INDEX_op_movi_i32:
1339 tcg_out_movi(s, TCG_TYPE_I32, args[0], args[1]);
1340 break;
1341 case INDEX_op_ld8u_i32:
1342 tcg_out_ldst (s, args[0], args[1], args[2], LBZ, LBZX);
1343 break;
1344 case INDEX_op_ld8s_i32:
1345 tcg_out_ldst (s, args[0], args[1], args[2], LBZ, LBZX);
1346 tcg_out32 (s, EXTSB | RS (args[0]) | RA (args[0]));
1347 break;
1348 case INDEX_op_ld16u_i32:
1349 tcg_out_ldst (s, args[0], args[1], args[2], LHZ, LHZX);
1350 break;
1351 case INDEX_op_ld16s_i32:
1352 tcg_out_ldst (s, args[0], args[1], args[2], LHA, LHAX);
1353 break;
1354 case INDEX_op_ld_i32:
1355 tcg_out_ldst (s, args[0], args[1], args[2], LWZ, LWZX);
1356 break;
1357 case INDEX_op_st8_i32:
1358 tcg_out_ldst (s, args[0], args[1], args[2], STB, STBX);
1359 break;
1360 case INDEX_op_st16_i32:
1361 tcg_out_ldst (s, args[0], args[1], args[2], STH, STHX);
1362 break;
1363 case INDEX_op_st_i32:
1364 tcg_out_ldst (s, args[0], args[1], args[2], STW, STWX);
1365 break;
1366
1367 case INDEX_op_add_i32:
1368 if (const_args[2])
1369 ppc_addi (s, args[0], args[1], args[2]);
1370 else
1371 tcg_out32 (s, ADD | TAB (args[0], args[1], args[2]));
1372 break;
1373 case INDEX_op_sub_i32:
1374 if (const_args[2])
1375 ppc_addi (s, args[0], args[1], -args[2]);
1376 else
1377 tcg_out32 (s, SUBF | TAB (args[0], args[2], args[1]));
1378 break;
1379
1380 case INDEX_op_and_i32:
1381 if (const_args[2]) {
c45851c4 1382 uint32_t c;
1383
1384 c = args[2];
1385
1386 if (!c) {
1387 tcg_out_movi (s, TCG_TYPE_I32, args[0], 0);
1388 break;
1389 }
1390#ifdef __PPU__
1391 uint32_t t, n;
1392 int mb, me;
1393
1394 n = c ^ -(c & 1);
1395 t = n + (n & -n);
1396
1397 if ((t & (t - 1)) == 0) {
1398 int lzc, tzc;
1399
1400 if ((c & 0x80000001) == 0x80000001) {
1401 lzc = clz32 (n);
1402 tzc = ctz32 (n);
1403
1404 mb = 32 - tzc;
1405 me = lzc - 1;
1406 }
1407 else {
1408 lzc = clz32 (c);
1409 tzc = ctz32 (c);
1410
1411 mb = lzc;
1412 me = 31 - tzc;
1413 }
1414
1415 tcg_out32 (s, (RLWINM
1416 | RA (args[0])
1417 | RS (args[1])
1418 | SH (0)
1419 | MB (mb)
1420 | ME (me)
1421 )
1422 );
1423 }
1424 else
1425#endif /* !__PPU__ */
1426 {
1427 if ((c & 0xffff) == c)
1428 tcg_out32 (s, ANDI | RS (args[1]) | RA (args[0]) | c);
1429 else if ((c & 0xffff0000) == c)
1430 tcg_out32 (s, ANDIS | RS (args[1]) | RA (args[0])
1431 | ((c >> 16) & 0xffff));
1432 else {
1433 tcg_out_movi (s, TCG_TYPE_I32, 0, c);
1434 tcg_out32 (s, AND | SAB (args[1], args[0], 0));
1435 }
2662e13f
FB		 1436 }
1437 }
1438 else
1439 tcg_out32 (s, AND | SAB (args[1], args[0], args[2]));
1440 break;
1441 case INDEX_op_or_i32:
1442 if (const_args[2]) {
000a2d86 1443 if (args[2] & 0xffff) {
1444 tcg_out32 (s, ORI | RS (args[1]) | RA (args[0])
1445 | (args[2] & 0xffff));
1446 if (args[2] >> 16)
1447 tcg_out32 (s, ORIS | RS (args[0]) | RA (args[0])
2662e13f 1448 | ((args[2] >> 16) & 0xffff));
2662e13f
FB		 1449 }
1450 else {
000a2d86 1451 tcg_out32 (s, ORIS | RS (args[1]) | RA (args[0])
1452 | ((args[2] >> 16) & 0xffff));
2662e13f
FB		 1453 }
1454 }
1455 else
1456 tcg_out32 (s, OR | SAB (args[1], args[0], args[2]));
1457 break;
1458 case INDEX_op_xor_i32:
1459 if (const_args[2]) {
000a2d86 1460 if ((args[2] & 0xffff) == args[2])
1461 tcg_out32 (s, XORI | RS (args[1]) | RA (args[0])
1462 | (args[2] & 0xffff));
1463 else if ((args[2] & 0xffff0000) == args[2])
1464 tcg_out32 (s, XORIS | RS (args[1]) | RA (args[0])
1465 | ((args[2] >> 16) & 0xffff));
2662e13f 1466 else {
000a2d86 1467 tcg_out_movi (s, TCG_TYPE_I32, 0, args[2]);
1468 tcg_out32 (s, XOR | SAB (args[1], args[0], 0));
2662e13f
FB		 1469 }
1470 }
1471 else
1472 tcg_out32 (s, XOR | SAB (args[1], args[0], args[2]));
1473 break;
65fe043e 1474 case INDEX_op_andc_i32:
1475 tcg_out32 (s, ANDC | SAB (args[1], args[0], args[2]));
1476 break;
1477 case INDEX_op_orc_i32:
1478 tcg_out32 (s, ORC | SAB (args[1], args[0], args[2]));
1479 break;
aa77bebd 1480 case INDEX_op_eqv_i32:
1481 tcg_out32 (s, EQV | SAB (args[1], args[0], args[2]));
1482 break;
1483 case INDEX_op_nand_i32:
1484 tcg_out32 (s, NAND | SAB (args[1], args[0], args[2]));
1485 break;
1486 case INDEX_op_nor_i32:
1487 tcg_out32 (s, NOR | SAB (args[1], args[0], args[2]));
1488 break;
2662e13f
FB		 1489
1490 case INDEX_op_mul_i32:
1491 if (const_args[2]) {
1492 if (args[2] == (int16_t) args[2])
1493 tcg_out32 (s, MULLI | RT (args[0]) | RA (args[1])
1494 | (args[2] & 0xffff));
1495 else {
1496 tcg_out_movi (s, TCG_TYPE_I32, 0, args[2]);
1497 tcg_out32 (s, MULLW | TAB (args[0], args[1], 0));
1498 }
1499 }
1500 else
1501 tcg_out32 (s, MULLW | TAB (args[0], args[1], args[2]));
1502 break;
77b73de6 1503
1504 case INDEX_op_div_i32:
1505 tcg_out32 (s, DIVW | TAB (args[0], args[1], args[2]));
1506 break;
1507
1508 case INDEX_op_divu_i32:
1509 tcg_out32 (s, DIVWU | TAB (args[0], args[1], args[2]));
1510 break;
1511
1512 case INDEX_op_rem_i32:
1513 tcg_out32 (s, DIVW | TAB (0, args[1], args[2]));
1514 tcg_out32 (s, MULLW | TAB (0, 0, args[2]));
1515 tcg_out32 (s, SUBF | TAB (args[0], 0, args[1]));
1516 break;
1517
1518 case INDEX_op_remu_i32:
1519 tcg_out32 (s, DIVWU | TAB (0, args[1], args[2]));
1520 tcg_out32 (s, MULLW | TAB (0, 0, args[2]));
1521 tcg_out32 (s, SUBF | TAB (args[0], 0, args[1]));
1522 break;
1523
2662e13f
FB		 1524 case INDEX_op_mulu2_i32:
1525 if (args[0] == args[2] || args[0] == args[3]) {
1526 tcg_out32 (s, MULLW | TAB (0, args[2], args[3]));
1527 tcg_out32 (s, MULHWU | TAB (args[1], args[2], args[3]));
1528 tcg_out_mov (s, args[0], 0);
1529 }
1530 else {
1531 tcg_out32 (s, MULLW | TAB (args[0], args[2], args[3]));
1532 tcg_out32 (s, MULHWU | TAB (args[1], args[2], args[3]));
1533 }
1534 break;
2662e13f
FB		 1535
1536 case INDEX_op_shl_i32:
1537 if (const_args[2]) {
000a2d86 1538 tcg_out32 (s, (RLWINM
1539 | RA (args[0])
1540 | RS (args[1])
1541 | SH (args[2])
1542 | MB (0)
1543 | ME (31 - args[2])
1544 )
1545 );
2662e13f
FB		 1546 }
1547 else
1548 tcg_out32 (s, SLW | SAB (args[1], args[0], args[2]));
1549 break;
1550 case INDEX_op_shr_i32:
1551 if (const_args[2]) {
000a2d86 1552 tcg_out32 (s, (RLWINM
1553 | RA (args[0])
1554 | RS (args[1])
1555 | SH (32 - args[2])
1556 | MB (args[2])
1557 | ME (31)
1558 )
1559 );
2662e13f
FB		 1560 }
1561 else
1562 tcg_out32 (s, SRW | SAB (args[1], args[0], args[2]));
1563 break;
1564 case INDEX_op_sar_i32:
1565 if (const_args[2])
1566 tcg_out32 (s, SRAWI | RS (args[1]) | RA (args[0]) | SH (args[2]));
1567 else
1568 tcg_out32 (s, SRAW | SAB (args[1], args[0], args[2]));
1569 break;
65fe043e 1570 case INDEX_op_rotl_i32:
1571 {
1572 int op = 0
1573 | RA (args[0])
1574 | RS (args[1])
1575 | MB (0)
1576 | ME (31)
1577 | (const_args[2] ? RLWINM | SH (args[2])
1578 : RLWNM | RB (args[2]))
1579 ;
1580 tcg_out32 (s, op);
1581 }
1582 break;
1583 case INDEX_op_rotr_i32:
1584 if (const_args[2]) {
1585 if (!args[2]) {
98b8d951 1586 tcg_out_mov (s, args[0], args[1]);
65fe043e 1587 }
1588 else {
1589 tcg_out32 (s, RLWINM
1590 | RA (args[0])
1591 | RS (args[1])
1592 | SH (32 - args[2])
1593 | MB (0)
1594 | ME (31)
1595 );
1596 }
1597 }
1598 else {
d616cf1d 1599 tcg_out32 (s, SUBFIC | RT (0) | RA (args[2]) | 32);
65fe043e 1600 tcg_out32 (s, RLWNM
1601 | RA (args[0])
1602 | RS (args[1])
1603 | RB (0)
1604 | MB (0)
1605 | ME (31)
1606 );
1607 }
1608 break;
2662e13f
FB		 1609
1610 case INDEX_op_add2_i32:
1611 if (args[0] == args[3] || args[0] == args[5]) {
1612 tcg_out32 (s, ADDC | TAB (0, args[2], args[4]));
1613 tcg_out32 (s, ADDE | TAB (args[1], args[3], args[5]));
1614 tcg_out_mov (s, args[0], 0);
1615 }
1616 else {
1617 tcg_out32 (s, ADDC | TAB (args[0], args[2], args[4]));
1618 tcg_out32 (s, ADDE | TAB (args[1], args[3], args[5]));
1619 }
1620 break;
1621 case INDEX_op_sub2_i32:
1622 if (args[0] == args[3] || args[0] == args[5]) {
1623 tcg_out32 (s, SUBFC | TAB (0, args[4], args[2]));
1624 tcg_out32 (s, SUBFE | TAB (args[1], args[5], args[3]));
1625 tcg_out_mov (s, args[0], 0);
1626 }
1627 else {
1628 tcg_out32 (s, SUBFC | TAB (args[0], args[4], args[2]));
1629 tcg_out32 (s, SUBFE | TAB (args[1], args[5], args[3]));
1630 }
1631 break;
1632
1633 case INDEX_op_brcond_i32:
1634 /*
1635 args[0] = r0
1636 args[1] = r1
1637 args[2] = cond
1638 args[3] = r1 is const
1639 args[4] = label_index
1640 */
1641 tcg_out_brcond (s, args[2], args[0], args[1], const_args[1], args[3]);
1642 break;
1643 case INDEX_op_brcond2_i32:
1644 tcg_out_brcond2(s, args, const_args);
1645 break;
1646
1647 case INDEX_op_neg_i32:
1648 tcg_out32 (s, NEG | RT (args[0]) | RA (args[1]));
1649 break;
1650
65fe043e 1651 case INDEX_op_not_i32:
36368cf0 1652 tcg_out32 (s, NOR | SAB (args[1], args[0], args[1]));
65fe043e 1653 break;
1654
2662e13f
FB		 1655 case INDEX_op_qemu_ld8u:
1656 tcg_out_qemu_ld(s, args, 0);
1657 break;
1658 case INDEX_op_qemu_ld8s:
1659 tcg_out_qemu_ld(s, args, 0 | 4);
1660 break;
1661 case INDEX_op_qemu_ld16u:
1662 tcg_out_qemu_ld(s, args, 1);
1663 break;
1664 case INDEX_op_qemu_ld16s:
1665 tcg_out_qemu_ld(s, args, 1 | 4);
1666 break;
86feb1c8 1667 case INDEX_op_qemu_ld32:
2662e13f
FB		 1668 tcg_out_qemu_ld(s, args, 2);
1669 break;
1670 case INDEX_op_qemu_ld64:
1671 tcg_out_qemu_ld(s, args, 3);
1672 break;
1673 case INDEX_op_qemu_st8:
1674 tcg_out_qemu_st(s, args, 0);
1675 break;
1676 case INDEX_op_qemu_st16:
1677 tcg_out_qemu_st(s, args, 1);
1678 break;
1679 case INDEX_op_qemu_st32:
1680 tcg_out_qemu_st(s, args, 2);
1681 break;
1682 case INDEX_op_qemu_st64:
1683 tcg_out_qemu_st(s, args, 3);
1684 break;
1685
e46b9681 1686 case INDEX_op_ext8s_i32:
1687 tcg_out32 (s, EXTSB | RS (args[1]) | RA (args[0]));
1688 break;
65fe043e 1689 case INDEX_op_ext8u_i32:
1690 tcg_out32 (s, RLWINM
1691 | RA (args[0])
1692 | RS (args[1])
1693 | SH (0)
1694 | MB (24)
1695 | ME (31)
1696 );
1697 break;
e46b9681 1698 case INDEX_op_ext16s_i32:
1699 tcg_out32 (s, EXTSH | RS (args[1]) | RA (args[0]));
1700 break;
65fe043e 1701 case INDEX_op_ext16u_i32:
1702 tcg_out32 (s, RLWINM
1703 | RA (args[0])
1704 | RS (args[1])
1705 | SH (0)
1706 | MB (16)
1707 | ME (31)
1708 );
1709 break;
e46b9681 1710
b0809bf7 1711 case INDEX_op_setcond_i32:
1712 tcg_out_setcond (s, args[3], args[0], args[1], args[2], const_args[2]);
1713 break;
1714 case INDEX_op_setcond2_i32:
1715 tcg_out_setcond2 (s, args, const_args);
1716 break;
1717
2662e13f
FB		 1718 default:
1719 tcg_dump_ops (s, stderr);
1720 tcg_abort ();
1721 }
1722}
1723
1724static const TCGTargetOpDef ppc_op_defs[] = {
1725 { INDEX_op_exit_tb, { } },
1726 { INDEX_op_goto_tb, { } },
932a6909
FB		 1727 { INDEX_op_call, { "ri" } },
1728 { INDEX_op_jmp, { "ri" } },
2662e13f
FB		 1729 { INDEX_op_br, { } },
1730
1731 { INDEX_op_mov_i32, { "r", "r" } },
1732 { INDEX_op_movi_i32, { "r" } },
1733 { INDEX_op_ld8u_i32, { "r", "r" } },
1734 { INDEX_op_ld8s_i32, { "r", "r" } },
1735 { INDEX_op_ld16u_i32, { "r", "r" } },
1736 { INDEX_op_ld16s_i32, { "r", "r" } },
1737 { INDEX_op_ld_i32, { "r", "r" } },
1738 { INDEX_op_st8_i32, { "r", "r" } },
1739 { INDEX_op_st16_i32, { "r", "r" } },
1740 { INDEX_op_st_i32, { "r", "r" } },
1741
1742 { INDEX_op_add_i32, { "r", "r", "ri" } },
1743 { INDEX_op_mul_i32, { "r", "r", "ri" } },
77b73de6 1744 { INDEX_op_div_i32, { "r", "r", "r" } },
1745 { INDEX_op_divu_i32, { "r", "r", "r" } },
1746 { INDEX_op_rem_i32, { "r", "r", "r" } },
1747 { INDEX_op_remu_i32, { "r", "r", "r" } },
2662e13f 1748 { INDEX_op_mulu2_i32, { "r", "r", "r", "r" } },
2662e13f
FB		 1749 { INDEX_op_sub_i32, { "r", "r", "ri" } },
1750 { INDEX_op_and_i32, { "r", "r", "ri" } },
1751 { INDEX_op_or_i32, { "r", "r", "ri" } },
1752 { INDEX_op_xor_i32, { "r", "r", "ri" } },
1753
1754 { INDEX_op_shl_i32, { "r", "r", "ri" } },
1755 { INDEX_op_shr_i32, { "r", "r", "ri" } },
1756 { INDEX_op_sar_i32, { "r", "r", "ri" } },
1757
65fe043e 1758 { INDEX_op_rotl_i32, { "r", "r", "ri" } },
1759 { INDEX_op_rotr_i32, { "r", "r", "ri" } },
1760
2662e13f
FB		 1761 { INDEX_op_brcond_i32, { "r", "ri" } },
1762
1763 { INDEX_op_add2_i32, { "r", "r", "r", "r", "r", "r" } },
1764 { INDEX_op_sub2_i32, { "r", "r", "r", "r", "r", "r" } },
1765 { INDEX_op_brcond2_i32, { "r", "r", "r", "r" } },
1766
1767 { INDEX_op_neg_i32, { "r", "r" } },
65fe043e 1768 { INDEX_op_not_i32, { "r", "r" } },
1769
1770 { INDEX_op_andc_i32, { "r", "r", "r" } },
1771 { INDEX_op_orc_i32, { "r", "r", "r" } },
aa77bebd 1772 { INDEX_op_eqv_i32, { "r", "r", "r" } },
1773 { INDEX_op_nand_i32, { "r", "r", "r" } },
1774 { INDEX_op_nor_i32, { "r", "r", "r" } },
2662e13f 1775
b0809bf7 1776 { INDEX_op_setcond_i32, { "r", "r", "ri" } },
1777 { INDEX_op_setcond2_i32, { "r", "r", "r", "ri", "ri" } },
1778
2662e13f
FB		 1779#if TARGET_LONG_BITS == 32
1780 { INDEX_op_qemu_ld8u, { "r", "L" } },
1781 { INDEX_op_qemu_ld8s, { "r", "L" } },
1782 { INDEX_op_qemu_ld16u, { "r", "L" } },
1783 { INDEX_op_qemu_ld16s, { "r", "L" } },
86feb1c8 1784 { INDEX_op_qemu_ld32, { "r", "L" } },
2662e13f
FB		 1785 { INDEX_op_qemu_ld64, { "r", "r", "L" } },
1786
1787 { INDEX_op_qemu_st8, { "K", "K" } },
1788 { INDEX_op_qemu_st16, { "K", "K" } },
1789 { INDEX_op_qemu_st32, { "K", "K" } },
1790 { INDEX_op_qemu_st64, { "M", "M", "M" } },
1791#else
1792 { INDEX_op_qemu_ld8u, { "r", "L", "L" } },
1793 { INDEX_op_qemu_ld8s, { "r", "L", "L" } },
1794 { INDEX_op_qemu_ld16u, { "r", "L", "L" } },
1795 { INDEX_op_qemu_ld16s, { "r", "L", "L" } },
86feb1c8 1796 { INDEX_op_qemu_ld32, { "r", "L", "L" } },
2662e13f
FB		 1797 { INDEX_op_qemu_ld64, { "r", "L", "L", "L" } },
1798
1799 { INDEX_op_qemu_st8, { "K", "K", "K" } },
1800 { INDEX_op_qemu_st16, { "K", "K", "K" } },
1801 { INDEX_op_qemu_st32, { "K", "K", "K" } },
1802 { INDEX_op_qemu_st64, { "M", "M", "M", "M" } },
1803#endif
1804
e46b9681 1805 { INDEX_op_ext8s_i32, { "r", "r" } },
65fe043e 1806 { INDEX_op_ext8u_i32, { "r", "r" } },
e46b9681 1807 { INDEX_op_ext16s_i32, { "r", "r" } },
65fe043e 1808 { INDEX_op_ext16u_i32, { "r", "r" } },
e46b9681 1809
2662e13f
FB		 1810 { -1 },
1811};
1812
1813void tcg_target_init(TCGContext *s)
1814{
1815 tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0, 0xffffffff);
1816 tcg_regset_set32(tcg_target_call_clobber_regs, 0,
1817 (1 << TCG_REG_R0) |
6ec85236 1818#ifdef _CALL_DARWIN
f9bf2987 1819 (1 << TCG_REG_R2) |
1820#endif
2662e13f
FB		 1821 (1 << TCG_REG_R3) |
1822 (1 << TCG_REG_R4) |
1823 (1 << TCG_REG_R5) |
1824 (1 << TCG_REG_R6) |
1825 (1 << TCG_REG_R7) |
1826 (1 << TCG_REG_R8) |
1827 (1 << TCG_REG_R9) |
1828 (1 << TCG_REG_R10) |
1829 (1 << TCG_REG_R11) |
1830 (1 << TCG_REG_R12)
1831 );
1832
1833 tcg_regset_clear(s->reserved_regs);
1834 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R0);
1835 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R1);
6ec85236 1836#ifndef _CALL_DARWIN
2662e13f 1837 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R2);
f9bf2987 1838#endif
6ec85236 1839#ifdef _CALL_SYSV
5db3ee79 1840 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R13);
1841#endif
f6548c0a 1842#ifdef CONFIG_USE_GUEST_BASE
1843 tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG);
1844#endif
2662e13f
FB		 1845
1846 tcg_add_target_add_op_defs(ppc_op_defs);
1847}
Qemu copy for testing