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[qemu.git] / tcg / sparc / tcg-target.c
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8289b279
BS		 1/*
2 * Tiny Code Generator for QEMU
3 *
4 * Copyright (c) 2008 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
d4a9eb1f 25#ifndef NDEBUG
8289b279
BS		 26static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
27 "%g0",
28 "%g1",
29 "%g2",
30 "%g3",
31 "%g4",
32 "%g5",
33 "%g6",
34 "%g7",
35 "%o0",
36 "%o1",
37 "%o2",
38 "%o3",
39 "%o4",
40 "%o5",
41 "%o6",
42 "%o7",
43 "%l0",
44 "%l1",
45 "%l2",
46 "%l3",
47 "%l4",
48 "%l5",
49 "%l6",
50 "%l7",
51 "%i0",
52 "%i1",
53 "%i2",
54 "%i3",
55 "%i4",
56 "%i5",
57 "%i6",
58 "%i7",
59};
d4a9eb1f 60#endif
8289b279 61
0954d0d9 62static const int tcg_target_reg_alloc_order[] = {
8289b279
BS		 63 TCG_REG_L0,
64 TCG_REG_L1,
65 TCG_REG_L2,
66 TCG_REG_L3,
67 TCG_REG_L4,
68 TCG_REG_L5,
69 TCG_REG_L6,
70 TCG_REG_L7,
71 TCG_REG_I0,
72 TCG_REG_I1,
73 TCG_REG_I2,
74 TCG_REG_I3,
75 TCG_REG_I4,
8289b279
BS		 76};
77
78static const int tcg_target_call_iarg_regs[6] = {
79 TCG_REG_O0,
80 TCG_REG_O1,
81 TCG_REG_O2,
82 TCG_REG_O3,
83 TCG_REG_O4,
84 TCG_REG_O5,
85};
86
87static const int tcg_target_call_oarg_regs[2] = {
88 TCG_REG_O0,
89 TCG_REG_O1,
90};
91
57e49b40 92static inline int check_fit_tl(tcg_target_long val, unsigned int bits)
f5ef6aac 93{
57e49b40
BS		 94 return (val << ((sizeof(tcg_target_long) * 8 - bits))
95 >> (sizeof(tcg_target_long) * 8 - bits)) == val;
96}
97
98static inline int check_fit_i32(uint32_t val, unsigned int bits)
99{
100 return ((val << (32 - bits)) >> (32 - bits)) == val;
f5ef6aac
BS		 101}
102
8289b279 103static void patch_reloc(uint8_t *code_ptr, int type,
f54b3f92 104 tcg_target_long value, tcg_target_long addend)
8289b279 105{
f54b3f92 106 value += addend;
8289b279
BS		 107 switch (type) {
108 case R_SPARC_32:
109 if (value != (uint32_t)value)
110 tcg_abort();
111 *(uint32_t *)code_ptr = value;
112 break;
f5ef6aac
BS		 113 case R_SPARC_WDISP22:
114 value -= (long)code_ptr;
115 value >>= 2;
57e49b40 116 if (!check_fit_tl(value, 22))
f5ef6aac
BS		 117 tcg_abort();
118 *(uint32_t *)code_ptr = ((*(uint32_t *)code_ptr) & ~0x3fffff) | value;
119 break;
1da92db2
BS		 120 case R_SPARC_WDISP19:
121 value -= (long)code_ptr;
122 value >>= 2;
123 if (!check_fit_tl(value, 19))
124 tcg_abort();
125 *(uint32_t *)code_ptr = ((*(uint32_t *)code_ptr) & ~0x7ffff) | value;
126 break;
8289b279
BS		 127 default:
128 tcg_abort();
129 }
130}
131
132/* maximum number of register used for input function arguments */
133static inline int tcg_target_get_call_iarg_regs_count(int flags)
134{
135 return 6;
136}
137
138/* parse target specific constraints */
139static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
140{
141 const char *ct_str;
142
143 ct_str = *pct_str;
144 switch (ct_str[0]) {
145 case 'r':
5e143c43
RH		 146 ct->ct |= TCG_CT_REG;
147 tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
148 break;
8289b279
BS		 149 case 'L': /* qemu_ld/st constraint */
150 ct->ct |= TCG_CT_REG;
151 tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
53c37487
BS		 152 // Helper args
153 tcg_regset_reset_reg(ct->u.regs, TCG_REG_O0);
154 tcg_regset_reset_reg(ct->u.regs, TCG_REG_O1);
155 tcg_regset_reset_reg(ct->u.regs, TCG_REG_O2);
8289b279
BS		 156 break;
157 case 'I':
158 ct->ct |= TCG_CT_CONST_S11;
159 break;
160 case 'J':
161 ct->ct |= TCG_CT_CONST_S13;
162 break;
163 default:
164 return -1;
165 }
166 ct_str++;
167 *pct_str = ct_str;
168 return 0;
169}
170
8289b279
BS		 171/* test if a constant matches the constraint */
172static inline int tcg_target_const_match(tcg_target_long val,
173 const TCGArgConstraint *arg_ct)
174{
175 int ct;
176
177 ct = arg_ct->ct;
178 if (ct & TCG_CT_CONST)
179 return 1;
57e49b40 180 else if ((ct & TCG_CT_CONST_S11) && check_fit_tl(val, 11))
8289b279 181 return 1;
57e49b40 182 else if ((ct & TCG_CT_CONST_S13) && check_fit_tl(val, 13))
8289b279
BS		 183 return 1;
184 else
185 return 0;
186}
187
188#define INSN_OP(x) ((x) << 30)
189#define INSN_OP2(x) ((x) << 22)
190#define INSN_OP3(x) ((x) << 19)
191#define INSN_OPF(x) ((x) << 5)
192#define INSN_RD(x) ((x) << 25)
193#define INSN_RS1(x) ((x) << 14)
194#define INSN_RS2(x) (x)
8384dd67 195#define INSN_ASI(x) ((x) << 5)
8289b279 196
dbfe80e1 197#define INSN_IMM11(x) ((1 << 13) | ((x) & 0x7ff))
8289b279 198#define INSN_IMM13(x) ((1 << 13) | ((x) & 0x1fff))
1da92db2 199#define INSN_OFF19(x) (((x) >> 2) & 0x07ffff)
b3db8758 200#define INSN_OFF22(x) (((x) >> 2) & 0x3fffff)
8289b279 201
b3db8758 202#define INSN_COND(x, a) (((x) << 25) | ((a) << 29))
cf7c2ca5
BS		 203#define COND_N 0x0
204#define COND_E 0x1
205#define COND_LE 0x2
206#define COND_L 0x3
207#define COND_LEU 0x4
208#define COND_CS 0x5
209#define COND_NEG 0x6
210#define COND_VS 0x7
b3db8758 211#define COND_A 0x8
cf7c2ca5
BS		 212#define COND_NE 0x9
213#define COND_G 0xa
214#define COND_GE 0xb
215#define COND_GU 0xc
216#define COND_CC 0xd
217#define COND_POS 0xe
218#define COND_VC 0xf
b3db8758 219#define BA (INSN_OP(0) | INSN_COND(COND_A, 0) | INSN_OP2(0x2))
8289b279 220
dbfe80e1
RH		 221#define MOVCC_ICC (1 << 18)
222#define MOVCC_XCC (1 << 18 | 1 << 12)
223
8289b279 224#define ARITH_ADD (INSN_OP(2) | INSN_OP3(0x00))
7a3766f3 225#define ARITH_ADDCC (INSN_OP(2) | INSN_OP3(0x10))
8289b279 226#define ARITH_AND (INSN_OP(2) | INSN_OP3(0x01))
dc69960d 227#define ARITH_ANDN (INSN_OP(2) | INSN_OP3(0x05))
8289b279 228#define ARITH_OR (INSN_OP(2) | INSN_OP3(0x02))
9a7f3228 229#define ARITH_ORCC (INSN_OP(2) | INSN_OP3(0x12))
be6551b1 230#define ARITH_ORN (INSN_OP(2) | INSN_OP3(0x06))
8289b279 231#define ARITH_XOR (INSN_OP(2) | INSN_OP3(0x03))
f5ef6aac
BS		 232#define ARITH_SUB (INSN_OP(2) | INSN_OP3(0x04))
233#define ARITH_SUBCC (INSN_OP(2) | INSN_OP3(0x14))
8289b279
BS		 234#define ARITH_ADDX (INSN_OP(2) | INSN_OP3(0x10))
235#define ARITH_SUBX (INSN_OP(2) | INSN_OP3(0x0c))
236#define ARITH_UMUL (INSN_OP(2) | INSN_OP3(0x0a))
237#define ARITH_UDIV (INSN_OP(2) | INSN_OP3(0x0e))
238#define ARITH_SDIV (INSN_OP(2) | INSN_OP3(0x0f))
239#define ARITH_MULX (INSN_OP(2) | INSN_OP3(0x09))
240#define ARITH_UDIVX (INSN_OP(2) | INSN_OP3(0x0d))
241#define ARITH_SDIVX (INSN_OP(2) | INSN_OP3(0x2d))
dbfe80e1 242#define ARITH_MOVCC (INSN_OP(2) | INSN_OP3(0x2c))
8289b279
BS		 243
244#define SHIFT_SLL (INSN_OP(2) | INSN_OP3(0x25))
245#define SHIFT_SRL (INSN_OP(2) | INSN_OP3(0x26))
246#define SHIFT_SRA (INSN_OP(2) | INSN_OP3(0x27))
247
248#define SHIFT_SLLX (INSN_OP(2) | INSN_OP3(0x25) | (1 << 12))
249#define SHIFT_SRLX (INSN_OP(2) | INSN_OP3(0x26) | (1 << 12))
250#define SHIFT_SRAX (INSN_OP(2) | INSN_OP3(0x27) | (1 << 12))
251
7a3766f3 252#define RDY (INSN_OP(2) | INSN_OP3(0x28) | INSN_RS1(0))
583d1215 253#define WRY (INSN_OP(2) | INSN_OP3(0x30) | INSN_RD(0))
8289b279
BS		 254#define JMPL (INSN_OP(2) | INSN_OP3(0x38))
255#define SAVE (INSN_OP(2) | INSN_OP3(0x3c))
256#define RESTORE (INSN_OP(2) | INSN_OP3(0x3d))
257#define SETHI (INSN_OP(0) | INSN_OP2(0x4))
258#define CALL INSN_OP(1)
259#define LDUB (INSN_OP(3) | INSN_OP3(0x01))
260#define LDSB (INSN_OP(3) | INSN_OP3(0x09))
261#define LDUH (INSN_OP(3) | INSN_OP3(0x02))
262#define LDSH (INSN_OP(3) | INSN_OP3(0x0a))
263#define LDUW (INSN_OP(3) | INSN_OP3(0x00))
264#define LDSW (INSN_OP(3) | INSN_OP3(0x08))
265#define LDX (INSN_OP(3) | INSN_OP3(0x0b))
266#define STB (INSN_OP(3) | INSN_OP3(0x05))
267#define STH (INSN_OP(3) | INSN_OP3(0x06))
268#define STW (INSN_OP(3) | INSN_OP3(0x04))
269#define STX (INSN_OP(3) | INSN_OP3(0x0e))
8384dd67
BS		 270#define LDUBA (INSN_OP(3) | INSN_OP3(0x11))
271#define LDSBA (INSN_OP(3) | INSN_OP3(0x19))
272#define LDUHA (INSN_OP(3) | INSN_OP3(0x12))
273#define LDSHA (INSN_OP(3) | INSN_OP3(0x1a))
274#define LDUWA (INSN_OP(3) | INSN_OP3(0x10))
275#define LDSWA (INSN_OP(3) | INSN_OP3(0x18))
276#define LDXA (INSN_OP(3) | INSN_OP3(0x1b))
277#define STBA (INSN_OP(3) | INSN_OP3(0x15))
278#define STHA (INSN_OP(3) | INSN_OP3(0x16))
279#define STWA (INSN_OP(3) | INSN_OP3(0x14))
280#define STXA (INSN_OP(3) | INSN_OP3(0x1e))
281
282#ifndef ASI_PRIMARY_LITTLE
283#define ASI_PRIMARY_LITTLE 0x88
284#endif
8289b279 285
26cc915c
BS		 286static inline void tcg_out_arith(TCGContext *s, int rd, int rs1, int rs2,
287 int op)
288{
289 tcg_out32(s, op | INSN_RD(rd) | INSN_RS1(rs1) |
290 INSN_RS2(rs2));
291}
292
6f41b777
BS		 293static inline void tcg_out_arithi(TCGContext *s, int rd, int rs1,
294 uint32_t offset, int op)
26cc915c
BS		 295{
296 tcg_out32(s, op | INSN_RD(rd) | INSN_RS1(rs1) |
297 INSN_IMM13(offset));
298}
299
ba225198
RH		 300static void tcg_out_arithc(TCGContext *s, int rd, int rs1,
301 int val2, int val2const, int op)
302{
303 tcg_out32(s, op | INSN_RD(rd) | INSN_RS1(rs1)
304 | (val2const ? INSN_IMM13(val2) : INSN_RS2(val2)));
305}
306
3b6dac34 307static inline void tcg_out_mov(TCGContext *s, TCGType type, int ret, int arg)
8289b279 308{
26cc915c
BS		 309 tcg_out_arith(s, ret, arg, TCG_REG_G0, ARITH_OR);
310}
311
312static inline void tcg_out_sethi(TCGContext *s, int ret, uint32_t arg)
313{
314 tcg_out32(s, SETHI | INSN_RD(ret) | ((arg & 0xfffffc00) >> 10));
8289b279
BS		 315}
316
b101234a
BS		 317static inline void tcg_out_movi_imm13(TCGContext *s, int ret, uint32_t arg)
318{
319 tcg_out_arithi(s, ret, TCG_REG_G0, arg, ARITH_OR);
320}
321
322static inline void tcg_out_movi_imm32(TCGContext *s, int ret, uint32_t arg)
8289b279 323{
4a09aa89 324 if (check_fit_tl(arg, 13))
b101234a 325 tcg_out_movi_imm13(s, ret, arg);
8289b279 326 else {
26cc915c 327 tcg_out_sethi(s, ret, arg);
8289b279 328 if (arg & 0x3ff)
b101234a 329 tcg_out_arithi(s, ret, ret, arg & 0x3ff, ARITH_OR);
8289b279
BS		 330 }
331}
332
b101234a
BS		 333static inline void tcg_out_movi(TCGContext *s, TCGType type,
334 int ret, tcg_target_long arg)
335{
43172207
RH		 336 /* All 32-bit constants, as well as 64-bit constants with
337 no high bits set go through movi_imm32. */
338 if (TCG_TARGET_REG_BITS == 32
339 || type == TCG_TYPE_I32
340 || (arg & ~(tcg_target_long)0xffffffff) == 0) {
341 tcg_out_movi_imm32(s, ret, arg);
342 } else if (check_fit_tl(arg, 13)) {
343 /* A 13-bit constant sign-extended to 64-bits. */
344 tcg_out_movi_imm13(s, ret, arg);
345 } else if (check_fit_tl(arg, 32)) {
346 /* A 32-bit constant sign-extended to 64-bits. */
347 tcg_out_sethi(s, ret, ~arg);
348 tcg_out_arithi(s, ret, ret, (arg & 0x3ff) | -0x400, ARITH_XOR);
349 } else {
350 tcg_out_movi_imm32(s, TCG_REG_I4, arg >> (TCG_TARGET_REG_BITS / 2));
d795eb86 351 tcg_out_arithi(s, TCG_REG_I4, TCG_REG_I4, 32, SHIFT_SLLX);
b101234a 352 tcg_out_movi_imm32(s, ret, arg);
d795eb86 353 tcg_out_arith(s, ret, ret, TCG_REG_I4, ARITH_OR);
6f41b777 354 }
b101234a
BS		 355}
356
8289b279
BS		 357static inline void tcg_out_ld_raw(TCGContext *s, int ret,
358 tcg_target_long arg)
359{
26cc915c 360 tcg_out_sethi(s, ret, arg);
8289b279
BS		 361 tcg_out32(s, LDUW | INSN_RD(ret) | INSN_RS1(ret) |
362 INSN_IMM13(arg & 0x3ff));
363}
364
b3db8758
BS		 365static inline void tcg_out_ld_ptr(TCGContext *s, int ret,
366 tcg_target_long arg)
367{
b101234a
BS		 368 if (!check_fit_tl(arg, 10))
369 tcg_out_movi(s, TCG_TYPE_PTR, ret, arg & ~0x3ffULL);
a212ea75
RH		 370 if (TCG_TARGET_REG_BITS == 64) {
371 tcg_out32(s, LDX | INSN_RD(ret) | INSN_RS1(ret) |
372 INSN_IMM13(arg & 0x3ff));
373 } else {
374 tcg_out32(s, LDUW | INSN_RD(ret) | INSN_RS1(ret) |
375 INSN_IMM13(arg & 0x3ff));
376 }
b3db8758
BS		 377}
378
8289b279
BS		 379static inline void tcg_out_ldst(TCGContext *s, int ret, int addr, int offset, int op)
380{
57e49b40 381 if (check_fit_tl(offset, 13))
8289b279
BS		 382 tcg_out32(s, op | INSN_RD(ret) | INSN_RS1(addr) |
383 INSN_IMM13(offset));
cf7c2ca5
BS		 384 else {
385 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_I5, offset);
386 tcg_out32(s, op | INSN_RD(ret) | INSN_RS1(TCG_REG_I5) |
387 INSN_RS2(addr));
388 }
8289b279
BS		 389}
390
8384dd67
BS		 391static inline void tcg_out_ldst_asi(TCGContext *s, int ret, int addr,
392 int offset, int op, int asi)
393{
394 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_I5, offset);
395 tcg_out32(s, op | INSN_RD(ret) | INSN_RS1(TCG_REG_I5) |
396 INSN_ASI(asi) | INSN_RS2(addr));
397}
398
e4d5434c 399static inline void tcg_out_ld(TCGContext *s, TCGType type, int ret,
8289b279
BS		 400 int arg1, tcg_target_long arg2)
401{
7d551702
BS		 402 if (type == TCG_TYPE_I32)
403 tcg_out_ldst(s, ret, arg1, arg2, LDUW);
404 else
405 tcg_out_ldst(s, ret, arg1, arg2, LDX);
8289b279
BS		 406}
407
e4d5434c 408static inline void tcg_out_st(TCGContext *s, TCGType type, int arg,
8289b279
BS		 409 int arg1, tcg_target_long arg2)
410{
7d551702
BS		 411 if (type == TCG_TYPE_I32)
412 tcg_out_ldst(s, arg, arg1, arg2, STW);
413 else
414 tcg_out_ldst(s, arg, arg1, arg2, STX);
8289b279
BS		 415}
416
583d1215 417static inline void tcg_out_sety(TCGContext *s, int rs)
8289b279 418{
583d1215 419 tcg_out32(s, WRY | INSN_RS1(TCG_REG_G0) | INSN_RS2(rs));
8289b279
BS		 420}
421
7a3766f3
RH		 422static inline void tcg_out_rdy(TCGContext *s, int rd)
423{
424 tcg_out32(s, RDY | INSN_RD(rd));
425}
426
8289b279
BS		 427static inline void tcg_out_addi(TCGContext *s, int reg, tcg_target_long val)
428{
429 if (val != 0) {
57e49b40 430 if (check_fit_tl(val, 13))
8289b279 431 tcg_out_arithi(s, reg, reg, val, ARITH_ADD);
f5ef6aac
BS		 432 else {
433 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_I5, val);
434 tcg_out_arith(s, reg, reg, TCG_REG_I5, ARITH_ADD);
435 }
8289b279
BS		 436 }
437}
438
53c37487
BS		 439static inline void tcg_out_andi(TCGContext *s, int reg, tcg_target_long val)
440{
441 if (val != 0) {
442 if (check_fit_tl(val, 13))
443 tcg_out_arithi(s, reg, reg, val, ARITH_AND);
444 else {
445 tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_I5, val);
446 tcg_out_arith(s, reg, reg, TCG_REG_I5, ARITH_AND);
447 }
448 }
449}
450
583d1215
RH		 451static void tcg_out_div32(TCGContext *s, int rd, int rs1,
452 int val2, int val2const, int uns)
453{
454 /* Load Y with the sign/zero extension of RS1 to 64-bits. */
455 if (uns) {
456 tcg_out_sety(s, TCG_REG_G0);
457 } else {
458 tcg_out_arithi(s, TCG_REG_I5, rs1, 31, SHIFT_SRA);
459 tcg_out_sety(s, TCG_REG_I5);
460 }
461
462 tcg_out_arithc(s, rd, rs1, val2, val2const,
463 uns ? ARITH_UDIV : ARITH_SDIV);
464}
465
8289b279
BS		 466static inline void tcg_out_nop(TCGContext *s)
467{
26cc915c 468 tcg_out_sethi(s, TCG_REG_G0, 0);
8289b279
BS		 469}
470
1da92db2 471static void tcg_out_branch_i32(TCGContext *s, int opc, int label_index)
cf7c2ca5
BS		 472{
473 int32_t val;
474 TCGLabel *l = &s->labels[label_index];
475
476 if (l->has_value) {
477 val = l->u.value - (tcg_target_long)s->code_ptr;
f5ef6aac 478 tcg_out32(s, (INSN_OP(0) | INSN_COND(opc, 0) | INSN_OP2(0x2)
cf7c2ca5 479 | INSN_OFF22(l->u.value - (unsigned long)s->code_ptr)));
f5ef6aac
BS		 480 } else {
481 tcg_out_reloc(s, s->code_ptr, R_SPARC_WDISP22, label_index, 0);
482 tcg_out32(s, (INSN_OP(0) | INSN_COND(opc, 0) | INSN_OP2(0x2) | 0));
483 }
cf7c2ca5
BS		 484}
485
a212ea75 486#if TCG_TARGET_REG_BITS == 64
1da92db2
BS		 487static void tcg_out_branch_i64(TCGContext *s, int opc, int label_index)
488{
489 int32_t val;
490 TCGLabel *l = &s->labels[label_index];
491
492 if (l->has_value) {
493 val = l->u.value - (tcg_target_long)s->code_ptr;
494 tcg_out32(s, (INSN_OP(0) | INSN_COND(opc, 0) | INSN_OP2(0x1) |
495 (0x5 << 19) |
496 INSN_OFF19(l->u.value - (unsigned long)s->code_ptr)));
497 } else {
498 tcg_out_reloc(s, s->code_ptr, R_SPARC_WDISP19, label_index, 0);
499 tcg_out32(s, (INSN_OP(0) | INSN_COND(opc, 0) | INSN_OP2(0x1) |
500 (0x5 << 19) | 0));
501 }
502}
503#endif
504
cf7c2ca5
BS		 505static const uint8_t tcg_cond_to_bcond[10] = {
506 [TCG_COND_EQ] = COND_E,
507 [TCG_COND_NE] = COND_NE,
508 [TCG_COND_LT] = COND_L,
509 [TCG_COND_GE] = COND_GE,
510 [TCG_COND_LE] = COND_LE,
511 [TCG_COND_GT] = COND_G,
512 [TCG_COND_LTU] = COND_CS,
513 [TCG_COND_GEU] = COND_CC,
514 [TCG_COND_LEU] = COND_LEU,
515 [TCG_COND_GTU] = COND_GU,
516};
517
56f4927e
RH		 518static void tcg_out_cmp(TCGContext *s, TCGArg c1, TCGArg c2, int c2const)
519{
ba225198 520 tcg_out_arithc(s, TCG_REG_G0, c1, c2, c2const, ARITH_SUBCC);
56f4927e
RH		 521}
522
8a56e840 523static void tcg_out_brcond_i32(TCGContext *s, TCGCond cond,
1da92db2
BS		 524 TCGArg arg1, TCGArg arg2, int const_arg2,
525 int label_index)
cf7c2ca5 526{
56f4927e 527 tcg_out_cmp(s, arg1, arg2, const_arg2);
1da92db2 528 tcg_out_branch_i32(s, tcg_cond_to_bcond[cond], label_index);
cf7c2ca5
BS		 529 tcg_out_nop(s);
530}
531
a212ea75 532#if TCG_TARGET_REG_BITS == 64
8a56e840 533static void tcg_out_brcond_i64(TCGContext *s, TCGCond cond,
1da92db2
BS		 534 TCGArg arg1, TCGArg arg2, int const_arg2,
535 int label_index)
536{
56f4927e 537 tcg_out_cmp(s, arg1, arg2, const_arg2);
1da92db2
BS		 538 tcg_out_branch_i64(s, tcg_cond_to_bcond[cond], label_index);
539 tcg_out_nop(s);
540}
56f4927e 541#else
8a56e840 542static void tcg_out_brcond2_i32(TCGContext *s, TCGCond cond,
56f4927e
RH		 543 TCGArg al, TCGArg ah,
544 TCGArg bl, int blconst,
545 TCGArg bh, int bhconst, int label_dest)
546{
547 int cc, label_next = gen_new_label();
548
549 tcg_out_cmp(s, ah, bh, bhconst);
550
551 /* Note that we fill one of the delay slots with the second compare. */
552 switch (cond) {
553 case TCG_COND_EQ:
554 cc = INSN_COND(tcg_cond_to_bcond[TCG_COND_NE], 0);
555 tcg_out_branch_i32(s, cc, label_next);
556 tcg_out_cmp(s, al, bl, blconst);
557 cc = INSN_COND(tcg_cond_to_bcond[TCG_COND_EQ], 0);
558 tcg_out_branch_i32(s, cc, label_dest);
559 break;
560
561 case TCG_COND_NE:
562 cc = INSN_COND(tcg_cond_to_bcond[TCG_COND_NE], 0);
563 tcg_out_branch_i32(s, cc, label_dest);
564 tcg_out_cmp(s, al, bl, blconst);
565 tcg_out_branch_i32(s, cc, label_dest);
566 break;
567
568 default:
569 /* ??? One could fairly easily special-case 64-bit unsigned
570 compares against 32-bit zero-extended constants. For instance,
571 we know that (unsigned)AH < 0 is false and need not emit it.
572 Similarly, (unsigned)AH > 0 being true implies AH != 0, so the
573 second branch will never be taken. */
574 cc = INSN_COND(tcg_cond_to_bcond[cond], 0);
575 tcg_out_branch_i32(s, cc, label_dest);
576 tcg_out_nop(s);
577 cc = INSN_COND(tcg_cond_to_bcond[TCG_COND_NE], 0);
578 tcg_out_branch_i32(s, cc, label_next);
579 tcg_out_cmp(s, al, bl, blconst);
580 cc = INSN_COND(tcg_cond_to_bcond[tcg_unsigned_cond(cond)], 0);
581 tcg_out_branch_i32(s, cc, label_dest);
582 break;
583 }
584 tcg_out_nop(s);
585
586 tcg_out_label(s, label_next, (tcg_target_long)s->code_ptr);
587}
1da92db2
BS		 588#endif
589
8a56e840 590static void tcg_out_setcond_i32(TCGContext *s, TCGCond cond, TCGArg ret,
dbfe80e1
RH		 591 TCGArg c1, TCGArg c2, int c2const)
592{
593 TCGArg t;
594
595 /* For 32-bit comparisons, we can play games with ADDX/SUBX. */
596 switch (cond) {
597 case TCG_COND_EQ:
598 case TCG_COND_NE:
599 if (c2 != 0) {
600 tcg_out_arithc(s, ret, c1, c2, c2const, ARITH_XOR);
601 }
602 c1 = TCG_REG_G0, c2 = ret, c2const = 0;
603 cond = (cond == TCG_COND_EQ ? TCG_COND_LEU : TCG_COND_LTU);
604 break;
605
606 case TCG_COND_GTU:
607 case TCG_COND_GEU:
608 if (c2const && c2 != 0) {
609 tcg_out_movi_imm13(s, TCG_REG_I5, c2);
610 c2 = TCG_REG_I5;
611 }
612 t = c1, c1 = c2, c2 = t, c2const = 0;
613 cond = tcg_swap_cond(cond);
614 break;
615
616 case TCG_COND_LTU:
617 case TCG_COND_LEU:
618 break;
619
620 default:
621 tcg_out_cmp(s, c1, c2, c2const);
622#if defined(__sparc_v9__) || defined(__sparc_v8plus__)
623 tcg_out_movi_imm13(s, ret, 0);
624 tcg_out32 (s, ARITH_MOVCC | INSN_RD(ret)
625 | INSN_RS1(tcg_cond_to_bcond[cond])
626 | MOVCC_ICC | INSN_IMM11(1));
627#else
628 t = gen_new_label();
629 tcg_out_branch_i32(s, INSN_COND(tcg_cond_to_bcond[cond], 1), t);
630 tcg_out_movi_imm13(s, ret, 1);
631 tcg_out_movi_imm13(s, ret, 0);
632 tcg_out_label(s, t, (tcg_target_long)s->code_ptr);
633#endif
634 return;
635 }
636
637 tcg_out_cmp(s, c1, c2, c2const);
638 if (cond == TCG_COND_LTU) {
639 tcg_out_arithi(s, ret, TCG_REG_G0, 0, ARITH_ADDX);
640 } else {
641 tcg_out_arithi(s, ret, TCG_REG_G0, -1, ARITH_SUBX);
642 }
643}
644
645#if TCG_TARGET_REG_BITS == 64
8a56e840 646static void tcg_out_setcond_i64(TCGContext *s, TCGCond cond, TCGArg ret,
dbfe80e1
RH		 647 TCGArg c1, TCGArg c2, int c2const)
648{
649 tcg_out_cmp(s, c1, c2, c2const);
650 tcg_out_movi_imm13(s, ret, 0);
651 tcg_out32 (s, ARITH_MOVCC | INSN_RD(ret)
652 | INSN_RS1(tcg_cond_to_bcond[cond])
653 | MOVCC_XCC | INSN_IMM11(1));
654}
655#else
8a56e840 656static void tcg_out_setcond2_i32(TCGContext *s, TCGCond cond, TCGArg ret,
dbfe80e1
RH		 657 TCGArg al, TCGArg ah,
658 TCGArg bl, int blconst,
659 TCGArg bh, int bhconst)
660{
661 int lab;
662
663 switch (cond) {
664 case TCG_COND_EQ:
665 tcg_out_setcond_i32(s, TCG_COND_EQ, TCG_REG_I5, al, bl, blconst);
666 tcg_out_setcond_i32(s, TCG_COND_EQ, ret, ah, bh, bhconst);
667 tcg_out_arith(s, ret, ret, TCG_REG_I5, ARITH_AND);
668 break;
669
670 case TCG_COND_NE:
671 tcg_out_setcond_i32(s, TCG_COND_NE, TCG_REG_I5, al, al, blconst);
672 tcg_out_setcond_i32(s, TCG_COND_NE, ret, ah, bh, bhconst);
673 tcg_out_arith(s, ret, ret, TCG_REG_I5, ARITH_OR);
674 break;
675
676 default:
677 lab = gen_new_label();
678
679 tcg_out_cmp(s, ah, bh, bhconst);
680 tcg_out_branch_i32(s, INSN_COND(tcg_cond_to_bcond[cond], 1), lab);
681 tcg_out_movi_imm13(s, ret, 1);
682 tcg_out_branch_i32(s, INSN_COND(COND_NE, 1), lab);
683 tcg_out_movi_imm13(s, ret, 0);
684
685 tcg_out_setcond_i32(s, tcg_unsigned_cond(cond), ret, al, bl, blconst);
686
687 tcg_out_label(s, lab, (tcg_target_long)s->code_ptr);
688 break;
689 }
690}
691#endif
692
7d551702 693/* Generate global QEMU prologue and epilogue code */
e4d58b41 694static void tcg_target_qemu_prologue(TCGContext *s)
b3db8758 695{
f44c9960
BS		 696 tcg_set_frame(s, TCG_REG_I6, TCG_TARGET_CALL_STACK_OFFSET,
697 CPU_TEMP_BUF_NLONGS * (int)sizeof(long));
b3db8758 698 tcg_out32(s, SAVE | INSN_RD(TCG_REG_O6) | INSN_RS1(TCG_REG_O6) |
f44c9960
BS		 699 INSN_IMM13(-(TCG_TARGET_STACK_MINFRAME +
700 CPU_TEMP_BUF_NLONGS * (int)sizeof(long))));
cea5f9a2 701 tcg_out32(s, JMPL | INSN_RD(TCG_REG_G0) | INSN_RS1(TCG_REG_I1) |
7d551702 702 INSN_RS2(TCG_REG_G0));
cea5f9a2 703 tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, TCG_REG_I0);
b3db8758
BS		 704}
705
f5ef6aac 706#if defined(CONFIG_SOFTMMU)
f5ef6aac 707
79383c9c 708#include "../../softmmu_defs.h"
f5ef6aac 709
9a7f3228 710static const void * const qemu_ld_helpers[4] = {
f5ef6aac
BS		 711 __ldb_mmu,
712 __ldw_mmu,
713 __ldl_mmu,
714 __ldq_mmu,
715};
716
9a7f3228 717static const void * const qemu_st_helpers[4] = {
f5ef6aac
BS		 718 __stb_mmu,
719 __stw_mmu,
720 __stl_mmu,
721 __stq_mmu,
722};
723#endif
724
bffe1431
BS		 725#if TARGET_LONG_BITS == 32
726#define TARGET_LD_OP LDUW
727#else
728#define TARGET_LD_OP LDX
729#endif
730
65850a02 731#if defined(CONFIG_SOFTMMU)
355b1943 732#if HOST_LONG_BITS == 32
65850a02
BS		 733#define TARGET_ADDEND_LD_OP LDUW
734#else
735#define TARGET_ADDEND_LD_OP LDX
736#endif
737#endif
9d0efc88 738
bffe1431
BS		 739#ifdef __arch64__
740#define HOST_LD_OP LDX
741#define HOST_ST_OP STX
742#define HOST_SLL_OP SHIFT_SLLX
743#define HOST_SRA_OP SHIFT_SRAX
744#else
745#define HOST_LD_OP LDUW
746#define HOST_ST_OP STW
747#define HOST_SLL_OP SHIFT_SLL
748#define HOST_SRA_OP SHIFT_SRA
749#endif
750
f5ef6aac
BS		 751static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args,
752 int opc)
753{
56fc64df 754 int addr_reg, data_reg, arg0, arg1, arg2, mem_index, s_bits;
f5ef6aac 755#if defined(CONFIG_SOFTMMU)
53c37487 756 uint32_t *label1_ptr, *label2_ptr;
f5ef6aac
BS		 757#endif
758
759 data_reg = *args++;
760 addr_reg = *args++;
761 mem_index = *args;
762 s_bits = opc & 3;
763
53c37487
BS		 764 arg0 = TCG_REG_O0;
765 arg1 = TCG_REG_O1;
56fc64df 766 arg2 = TCG_REG_O2;
f5ef6aac 767
f5ef6aac 768#if defined(CONFIG_SOFTMMU)
56fc64df
BS		 769 /* srl addr_reg, x, arg1 */
770 tcg_out_arithi(s, arg1, addr_reg, TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS,
f5ef6aac 771 SHIFT_SRL);
56fc64df
BS		 772 /* and addr_reg, x, arg0 */
773 tcg_out_arithi(s, arg0, addr_reg, TARGET_PAGE_MASK | ((1 << s_bits) - 1),
f5ef6aac
BS		 774 ARITH_AND);
775
56fc64df
BS		 776 /* and arg1, x, arg1 */
777 tcg_out_andi(s, arg1, (CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS);
f5ef6aac 778
56fc64df
BS		 779 /* add arg1, x, arg1 */
780 tcg_out_addi(s, arg1, offsetof(CPUState,
781 tlb_table[mem_index][0].addr_read));
53c37487 782
56fc64df
BS		 783 /* add env, arg1, arg1 */
784 tcg_out_arith(s, arg1, TCG_AREG0, arg1, ARITH_ADD);
f5ef6aac 785
56fc64df 786 /* ld [arg1], arg2 */
bffe1431 787 tcg_out32(s, TARGET_LD_OP | INSN_RD(arg2) | INSN_RS1(arg1) |
56fc64df 788 INSN_RS2(TCG_REG_G0));
f5ef6aac 789
56fc64df
BS		 790 /* subcc arg0, arg2, %g0 */
791 tcg_out_arith(s, TCG_REG_G0, arg0, arg2, ARITH_SUBCC);
f5ef6aac
BS		 792
793 /* will become:
1da92db2
BS		 794 be label1
795 or
796 be,pt %xcc label1 */
53c37487 797 label1_ptr = (uint32_t *)s->code_ptr;
f5ef6aac
BS		 798 tcg_out32(s, 0);
799
53c37487 800 /* mov (delay slot) */
3b6dac34 801 tcg_out_mov(s, TCG_TYPE_PTR, arg0, addr_reg);
f5ef6aac 802
bffe1431
BS		 803 /* mov */
804 tcg_out_movi(s, TCG_TYPE_I32, arg1, mem_index);
805
f5ef6aac 806 /* XXX: move that code at the end of the TB */
53c37487 807 /* qemu_ld_helper[s_bits](arg0, arg1) */
f5ef6aac
BS		 808 tcg_out32(s, CALL | ((((tcg_target_ulong)qemu_ld_helpers[s_bits]
809 - (tcg_target_ulong)s->code_ptr) >> 2)
810 & 0x3fffffff));
bffe1431
BS		 811 /* Store AREG0 in stack to avoid ugly glibc bugs that mangle
812 global registers */
813 // delay slot
814 tcg_out_ldst(s, TCG_AREG0, TCG_REG_CALL_STACK,
f843e528
BS		 815 TCG_TARGET_CALL_STACK_OFFSET - TCG_STATIC_CALL_ARGS_SIZE -
816 sizeof(long), HOST_ST_OP);
bffe1431 817 tcg_out_ldst(s, TCG_AREG0, TCG_REG_CALL_STACK,
f843e528
BS		 818 TCG_TARGET_CALL_STACK_OFFSET - TCG_STATIC_CALL_ARGS_SIZE -
819 sizeof(long), HOST_LD_OP);
f5ef6aac 820
53c37487 821 /* data_reg = sign_extend(arg0) */
f5ef6aac
BS		 822 switch(opc) {
823 case 0 | 4:
53c37487 824 /* sll arg0, 24/56, data_reg */
56fc64df 825 tcg_out_arithi(s, data_reg, arg0, (int)sizeof(tcg_target_long) * 8 - 8,
bffe1431 826 HOST_SLL_OP);
53c37487 827 /* sra data_reg, 24/56, data_reg */
56fc64df 828 tcg_out_arithi(s, data_reg, data_reg,
bffe1431 829 (int)sizeof(tcg_target_long) * 8 - 8, HOST_SRA_OP);
f5ef6aac
BS		 830 break;
831 case 1 | 4:
53c37487 832 /* sll arg0, 16/48, data_reg */
56fc64df 833 tcg_out_arithi(s, data_reg, arg0,
bffe1431 834 (int)sizeof(tcg_target_long) * 8 - 16, HOST_SLL_OP);
53c37487 835 /* sra data_reg, 16/48, data_reg */
56fc64df 836 tcg_out_arithi(s, data_reg, data_reg,
bffe1431 837 (int)sizeof(tcg_target_long) * 8 - 16, HOST_SRA_OP);
f5ef6aac
BS		 838 break;
839 case 2 | 4:
53c37487 840 /* sll arg0, 32, data_reg */
bffe1431 841 tcg_out_arithi(s, data_reg, arg0, 32, HOST_SLL_OP);
53c37487 842 /* sra data_reg, 32, data_reg */
bffe1431 843 tcg_out_arithi(s, data_reg, data_reg, 32, HOST_SRA_OP);
f5ef6aac
BS		 844 break;
845 case 0:
846 case 1:
847 case 2:
848 case 3:
849 default:
850 /* mov */
3b6dac34 851 tcg_out_mov(s, TCG_TYPE_REG, data_reg, arg0);
f5ef6aac
BS		 852 break;
853 }
854
855 /* will become:
856 ba label2 */
53c37487 857 label2_ptr = (uint32_t *)s->code_ptr;
f5ef6aac
BS		 858 tcg_out32(s, 0);
859
53c37487
BS		 860 /* nop (delay slot */
861 tcg_out_nop(s);
862
f5ef6aac 863 /* label1: */
1da92db2
BS		 864#if TARGET_LONG_BITS == 32
865 /* be label1 */
53c37487
BS		 866 *label1_ptr = (INSN_OP(0) | INSN_COND(COND_E, 0) | INSN_OP2(0x2) |
867 INSN_OFF22((unsigned long)s->code_ptr -
868 (unsigned long)label1_ptr));
1da92db2
BS		 869#else
870 /* be,pt %xcc label1 */
871 *label1_ptr = (INSN_OP(0) | INSN_COND(COND_E, 0) | INSN_OP2(0x1) |
872 (0x5 << 19) | INSN_OFF19((unsigned long)s->code_ptr -
873 (unsigned long)label1_ptr));
874#endif
f5ef6aac 875
56fc64df
BS		 876 /* ld [arg1 + x], arg1 */
877 tcg_out_ldst(s, arg1, arg1, offsetof(CPUTLBEntry, addend) -
9d0efc88 878 offsetof(CPUTLBEntry, addr_read), TARGET_ADDEND_LD_OP);
90cbed46
BS		 879
880#if TARGET_LONG_BITS == 32
881 /* and addr_reg, x, arg0 */
882 tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_I5, 0xffffffff);
883 tcg_out_arith(s, arg0, addr_reg, TCG_REG_I5, ARITH_AND);
884 /* add arg0, arg1, arg0 */
885 tcg_out_arith(s, arg0, arg0, arg1, ARITH_ADD);
886#else
56fc64df
BS		 887 /* add addr_reg, arg1, arg0 */
888 tcg_out_arith(s, arg0, addr_reg, arg1, ARITH_ADD);
90cbed46
BS		 889#endif
890
f5ef6aac 891#else
56fc64df 892 arg0 = addr_reg;
f5ef6aac
BS		 893#endif
894
f5ef6aac
BS		 895 switch(opc) {
896 case 0:
56fc64df
BS		 897 /* ldub [arg0], data_reg */
898 tcg_out_ldst(s, data_reg, arg0, 0, LDUB);
f5ef6aac
BS		 899 break;
900 case 0 | 4:
56fc64df
BS		 901 /* ldsb [arg0], data_reg */
902 tcg_out_ldst(s, data_reg, arg0, 0, LDSB);
f5ef6aac
BS		 903 break;
904 case 1:
8384dd67 905#ifdef TARGET_WORDS_BIGENDIAN
56fc64df
BS		 906 /* lduh [arg0], data_reg */
907 tcg_out_ldst(s, data_reg, arg0, 0, LDUH);
8384dd67 908#else
56fc64df
BS		 909 /* lduha [arg0] ASI_PRIMARY_LITTLE, data_reg */
910 tcg_out_ldst_asi(s, data_reg, arg0, 0, LDUHA, ASI_PRIMARY_LITTLE);
8384dd67 911#endif
f5ef6aac
BS		 912 break;
913 case 1 | 4:
8384dd67 914#ifdef TARGET_WORDS_BIGENDIAN
56fc64df
BS		 915 /* ldsh [arg0], data_reg */
916 tcg_out_ldst(s, data_reg, arg0, 0, LDSH);
8384dd67 917#else
56fc64df
BS		 918 /* ldsha [arg0] ASI_PRIMARY_LITTLE, data_reg */
919 tcg_out_ldst_asi(s, data_reg, arg0, 0, LDSHA, ASI_PRIMARY_LITTLE);
8384dd67 920#endif
f5ef6aac
BS		 921 break;
922 case 2:
8384dd67 923#ifdef TARGET_WORDS_BIGENDIAN
56fc64df
BS		 924 /* lduw [arg0], data_reg */
925 tcg_out_ldst(s, data_reg, arg0, 0, LDUW);
8384dd67 926#else
56fc64df
BS		 927 /* lduwa [arg0] ASI_PRIMARY_LITTLE, data_reg */
928 tcg_out_ldst_asi(s, data_reg, arg0, 0, LDUWA, ASI_PRIMARY_LITTLE);
8384dd67 929#endif
f5ef6aac
BS		 930 break;
931 case 2 | 4:
8384dd67 932#ifdef TARGET_WORDS_BIGENDIAN
56fc64df
BS		 933 /* ldsw [arg0], data_reg */
934 tcg_out_ldst(s, data_reg, arg0, 0, LDSW);
8384dd67 935#else
56fc64df
BS		 936 /* ldswa [arg0] ASI_PRIMARY_LITTLE, data_reg */
937 tcg_out_ldst_asi(s, data_reg, arg0, 0, LDSWA, ASI_PRIMARY_LITTLE);
8384dd67 938#endif
f5ef6aac
BS		 939 break;
940 case 3:
8384dd67 941#ifdef TARGET_WORDS_BIGENDIAN
56fc64df
BS		 942 /* ldx [arg0], data_reg */
943 tcg_out_ldst(s, data_reg, arg0, 0, LDX);
8384dd67 944#else
56fc64df
BS		 945 /* ldxa [arg0] ASI_PRIMARY_LITTLE, data_reg */
946 tcg_out_ldst_asi(s, data_reg, arg0, 0, LDXA, ASI_PRIMARY_LITTLE);
8384dd67 947#endif
f5ef6aac
BS		 948 break;
949 default:
950 tcg_abort();
951 }
952
953#if defined(CONFIG_SOFTMMU)
954 /* label2: */
9a7f3228 955 *label2_ptr = (INSN_OP(0) | INSN_COND(COND_A, 0) | INSN_OP2(0x2) |
53c37487
BS		 956 INSN_OFF22((unsigned long)s->code_ptr -
957 (unsigned long)label2_ptr));
f5ef6aac
BS		 958#endif
959}
960
961static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args,
962 int opc)
963{
56fc64df 964 int addr_reg, data_reg, arg0, arg1, arg2, mem_index, s_bits;
f5ef6aac 965#if defined(CONFIG_SOFTMMU)
53c37487 966 uint32_t *label1_ptr, *label2_ptr;
f5ef6aac
BS		 967#endif
968
969 data_reg = *args++;
970 addr_reg = *args++;
971 mem_index = *args;
972
973 s_bits = opc;
974
53c37487
BS		 975 arg0 = TCG_REG_O0;
976 arg1 = TCG_REG_O1;
977 arg2 = TCG_REG_O2;
f5ef6aac 978
f5ef6aac 979#if defined(CONFIG_SOFTMMU)
56fc64df
BS		 980 /* srl addr_reg, x, arg1 */
981 tcg_out_arithi(s, arg1, addr_reg, TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS,
f5ef6aac 982 SHIFT_SRL);
53c37487 983
56fc64df
BS		 984 /* and addr_reg, x, arg0 */
985 tcg_out_arithi(s, arg0, addr_reg, TARGET_PAGE_MASK | ((1 << s_bits) - 1),
f5ef6aac
BS		 986 ARITH_AND);
987
56fc64df
BS		 988 /* and arg1, x, arg1 */
989 tcg_out_andi(s, arg1, (CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS);
f5ef6aac 990
56fc64df
BS		 991 /* add arg1, x, arg1 */
992 tcg_out_addi(s, arg1, offsetof(CPUState,
993 tlb_table[mem_index][0].addr_write));
f5ef6aac 994
56fc64df
BS		 995 /* add env, arg1, arg1 */
996 tcg_out_arith(s, arg1, TCG_AREG0, arg1, ARITH_ADD);
f5ef6aac 997
56fc64df 998 /* ld [arg1], arg2 */
bffe1431 999 tcg_out32(s, TARGET_LD_OP | INSN_RD(arg2) | INSN_RS1(arg1) |
56fc64df 1000 INSN_RS2(TCG_REG_G0));
53c37487 1001
56fc64df
BS		 1002 /* subcc arg0, arg2, %g0 */
1003 tcg_out_arith(s, TCG_REG_G0, arg0, arg2, ARITH_SUBCC);
f5ef6aac
BS		 1004
1005 /* will become:
1da92db2
BS		 1006 be label1
1007 or
1008 be,pt %xcc label1 */
53c37487 1009 label1_ptr = (uint32_t *)s->code_ptr;
f5ef6aac 1010 tcg_out32(s, 0);
f5ef6aac 1011
53c37487 1012 /* mov (delay slot) */
3b6dac34 1013 tcg_out_mov(s, TCG_TYPE_PTR, arg0, addr_reg);
53c37487 1014
53c37487 1015 /* mov */
3b6dac34 1016 tcg_out_mov(s, TCG_TYPE_REG, arg1, data_reg);
53c37487 1017
bffe1431
BS		 1018 /* mov */
1019 tcg_out_movi(s, TCG_TYPE_I32, arg2, mem_index);
1020
53c37487
BS		 1021 /* XXX: move that code at the end of the TB */
1022 /* qemu_st_helper[s_bits](arg0, arg1, arg2) */
f5ef6aac
BS		 1023 tcg_out32(s, CALL | ((((tcg_target_ulong)qemu_st_helpers[s_bits]
1024 - (tcg_target_ulong)s->code_ptr) >> 2)
1025 & 0x3fffffff));
bffe1431
BS		 1026 /* Store AREG0 in stack to avoid ugly glibc bugs that mangle
1027 global registers */
1028 // delay slot
1029 tcg_out_ldst(s, TCG_AREG0, TCG_REG_CALL_STACK,
f843e528
BS		 1030 TCG_TARGET_CALL_STACK_OFFSET - TCG_STATIC_CALL_ARGS_SIZE -
1031 sizeof(long), HOST_ST_OP);
bffe1431 1032 tcg_out_ldst(s, TCG_AREG0, TCG_REG_CALL_STACK,
f843e528
BS		 1033 TCG_TARGET_CALL_STACK_OFFSET - TCG_STATIC_CALL_ARGS_SIZE -
1034 sizeof(long), HOST_LD_OP);
f5ef6aac
BS		 1035
1036 /* will become:
1037 ba label2 */
53c37487 1038 label2_ptr = (uint32_t *)s->code_ptr;
f5ef6aac
BS		 1039 tcg_out32(s, 0);
1040
53c37487
BS		 1041 /* nop (delay slot) */
1042 tcg_out_nop(s);
1043
1da92db2
BS		 1044#if TARGET_LONG_BITS == 32
1045 /* be label1 */
53c37487
BS		 1046 *label1_ptr = (INSN_OP(0) | INSN_COND(COND_E, 0) | INSN_OP2(0x2) |
1047 INSN_OFF22((unsigned long)s->code_ptr -
1048 (unsigned long)label1_ptr));
1da92db2
BS		 1049#else
1050 /* be,pt %xcc label1 */
1051 *label1_ptr = (INSN_OP(0) | INSN_COND(COND_E, 0) | INSN_OP2(0x1) |
1052 (0x5 << 19) | INSN_OFF19((unsigned long)s->code_ptr -
1053 (unsigned long)label1_ptr));
1054#endif
f5ef6aac 1055
56fc64df
BS		 1056 /* ld [arg1 + x], arg1 */
1057 tcg_out_ldst(s, arg1, arg1, offsetof(CPUTLBEntry, addend) -
9d0efc88 1058 offsetof(CPUTLBEntry, addr_write), TARGET_ADDEND_LD_OP);
53c37487 1059
90cbed46
BS		 1060#if TARGET_LONG_BITS == 32
1061 /* and addr_reg, x, arg0 */
1062 tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_I5, 0xffffffff);
1063 tcg_out_arith(s, arg0, addr_reg, TCG_REG_I5, ARITH_AND);
1064 /* add arg0, arg1, arg0 */
1065 tcg_out_arith(s, arg0, arg0, arg1, ARITH_ADD);
1066#else
56fc64df
BS		 1067 /* add addr_reg, arg1, arg0 */
1068 tcg_out_arith(s, arg0, addr_reg, arg1, ARITH_ADD);
90cbed46
BS		 1069#endif
1070
f5ef6aac 1071#else
56fc64df 1072 arg0 = addr_reg;
f5ef6aac
BS		 1073#endif
1074
f5ef6aac
BS		 1075 switch(opc) {
1076 case 0:
56fc64df
BS		 1077 /* stb data_reg, [arg0] */
1078 tcg_out_ldst(s, data_reg, arg0, 0, STB);
f5ef6aac
BS		 1079 break;
1080 case 1:
8384dd67 1081#ifdef TARGET_WORDS_BIGENDIAN
56fc64df
BS		 1082 /* sth data_reg, [arg0] */
1083 tcg_out_ldst(s, data_reg, arg0, 0, STH);
8384dd67 1084#else
56fc64df
BS		 1085 /* stha data_reg, [arg0] ASI_PRIMARY_LITTLE */
1086 tcg_out_ldst_asi(s, data_reg, arg0, 0, STHA, ASI_PRIMARY_LITTLE);
8384dd67 1087#endif
f5ef6aac
BS		 1088 break;
1089 case 2:
8384dd67 1090#ifdef TARGET_WORDS_BIGENDIAN
56fc64df
BS		 1091 /* stw data_reg, [arg0] */
1092 tcg_out_ldst(s, data_reg, arg0, 0, STW);
8384dd67 1093#else
56fc64df
BS		 1094 /* stwa data_reg, [arg0] ASI_PRIMARY_LITTLE */
1095 tcg_out_ldst_asi(s, data_reg, arg0, 0, STWA, ASI_PRIMARY_LITTLE);
8384dd67 1096#endif
f5ef6aac
BS		 1097 break;
1098 case 3:
8384dd67 1099#ifdef TARGET_WORDS_BIGENDIAN
56fc64df
BS		 1100 /* stx data_reg, [arg0] */
1101 tcg_out_ldst(s, data_reg, arg0, 0, STX);
8384dd67 1102#else
56fc64df
BS		 1103 /* stxa data_reg, [arg0] ASI_PRIMARY_LITTLE */
1104 tcg_out_ldst_asi(s, data_reg, arg0, 0, STXA, ASI_PRIMARY_LITTLE);
8384dd67 1105#endif
f5ef6aac
BS		 1106 break;
1107 default:
1108 tcg_abort();
1109 }
1110
1111#if defined(CONFIG_SOFTMMU)
1112 /* label2: */
9a7f3228 1113 *label2_ptr = (INSN_OP(0) | INSN_COND(COND_A, 0) | INSN_OP2(0x2) |
53c37487
BS		 1114 INSN_OFF22((unsigned long)s->code_ptr -
1115 (unsigned long)label2_ptr));
f5ef6aac
BS		 1116#endif
1117}
1118
a9751609 1119static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
8289b279
BS		 1120 const int *const_args)
1121{
1122 int c;
1123
1124 switch (opc) {
1125 case INDEX_op_exit_tb:
b3db8758
BS		 1126 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_I0, args[0]);
1127 tcg_out32(s, JMPL | INSN_RD(TCG_REG_G0) | INSN_RS1(TCG_REG_I7) |
8289b279 1128 INSN_IMM13(8));
b3db8758
BS		 1129 tcg_out32(s, RESTORE | INSN_RD(TCG_REG_G0) | INSN_RS1(TCG_REG_G0) |
1130 INSN_RS2(TCG_REG_G0));
8289b279
BS		 1131 break;
1132 case INDEX_op_goto_tb:
1133 if (s->tb_jmp_offset) {
1134 /* direct jump method */
26cc915c 1135 tcg_out_sethi(s, TCG_REG_I5, args[0] & 0xffffe000);
cf7c2ca5
BS		 1136 tcg_out32(s, JMPL | INSN_RD(TCG_REG_G0) | INSN_RS1(TCG_REG_I5) |
1137 INSN_IMM13((args[0] & 0x1fff)));
8289b279 1138 s->tb_jmp_offset[args[0]] = s->code_ptr - s->code_buf;
8289b279
BS		 1139 } else {
1140 /* indirect jump method */
b3db8758
BS		 1141 tcg_out_ld_ptr(s, TCG_REG_I5, (tcg_target_long)(s->tb_next + args[0]));
1142 tcg_out32(s, JMPL | INSN_RD(TCG_REG_G0) | INSN_RS1(TCG_REG_I5) |
1143 INSN_RS2(TCG_REG_G0));
8289b279 1144 }
53cd9273 1145 tcg_out_nop(s);
8289b279
BS		 1146 s->tb_next_offset[args[0]] = s->code_ptr - s->code_buf;
1147 break;
1148 case INDEX_op_call:
bffe1431
BS		 1149 if (const_args[0])
1150 tcg_out32(s, CALL | ((((tcg_target_ulong)args[0]
1151 - (tcg_target_ulong)s->code_ptr) >> 2)
1152 & 0x3fffffff));
1153 else {
1154 tcg_out_ld_ptr(s, TCG_REG_I5,
1155 (tcg_target_long)(s->tb_next + args[0]));
1156 tcg_out32(s, JMPL | INSN_RD(TCG_REG_O7) | INSN_RS1(TCG_REG_I5) |
1157 INSN_RS2(TCG_REG_G0));
8289b279 1158 }
bffe1431
BS		 1159 /* Store AREG0 in stack to avoid ugly glibc bugs that mangle
1160 global registers */
1161 // delay slot
1162 tcg_out_ldst(s, TCG_AREG0, TCG_REG_CALL_STACK,
f843e528
BS		 1163 TCG_TARGET_CALL_STACK_OFFSET - TCG_STATIC_CALL_ARGS_SIZE -
1164 sizeof(long), HOST_ST_OP);
bffe1431 1165 tcg_out_ldst(s, TCG_AREG0, TCG_REG_CALL_STACK,
f843e528
BS		 1166 TCG_TARGET_CALL_STACK_OFFSET - TCG_STATIC_CALL_ARGS_SIZE -
1167 sizeof(long), HOST_LD_OP);
8289b279
BS		 1168 break;
1169 case INDEX_op_jmp:
8289b279 1170 case INDEX_op_br:
1da92db2 1171 tcg_out_branch_i32(s, COND_A, args[0]);
f5ef6aac 1172 tcg_out_nop(s);
8289b279
BS		 1173 break;
1174 case INDEX_op_movi_i32:
1175 tcg_out_movi(s, TCG_TYPE_I32, args[0], (uint32_t)args[1]);
1176 break;
1177
a212ea75 1178#if TCG_TARGET_REG_BITS == 64
8289b279 1179#define OP_32_64(x) \
ba225198
RH		 1180 glue(glue(case INDEX_op_, x), _i32): \
1181 glue(glue(case INDEX_op_, x), _i64)
8289b279
BS		 1182#else
1183#define OP_32_64(x) \
ba225198 1184 glue(glue(case INDEX_op_, x), _i32)
8289b279 1185#endif
ba225198 1186 OP_32_64(ld8u):
8289b279
BS		 1187 tcg_out_ldst(s, args[0], args[1], args[2], LDUB);
1188 break;
ba225198 1189 OP_32_64(ld8s):
8289b279
BS		 1190 tcg_out_ldst(s, args[0], args[1], args[2], LDSB);
1191 break;
ba225198 1192 OP_32_64(ld16u):
8289b279
BS		 1193 tcg_out_ldst(s, args[0], args[1], args[2], LDUH);
1194 break;
ba225198 1195 OP_32_64(ld16s):
8289b279
BS		 1196 tcg_out_ldst(s, args[0], args[1], args[2], LDSH);
1197 break;
1198 case INDEX_op_ld_i32:
a212ea75 1199#if TCG_TARGET_REG_BITS == 64
53cd9273 1200 case INDEX_op_ld32u_i64:
8289b279
BS		 1201#endif
1202 tcg_out_ldst(s, args[0], args[1], args[2], LDUW);
1203 break;
ba225198 1204 OP_32_64(st8):
8289b279
BS		 1205 tcg_out_ldst(s, args[0], args[1], args[2], STB);
1206 break;
ba225198 1207 OP_32_64(st16):
8289b279
BS		 1208 tcg_out_ldst(s, args[0], args[1], args[2], STH);
1209 break;
1210 case INDEX_op_st_i32:
a212ea75 1211#if TCG_TARGET_REG_BITS == 64
53cd9273 1212 case INDEX_op_st32_i64:
8289b279
BS		 1213#endif
1214 tcg_out_ldst(s, args[0], args[1], args[2], STW);
1215 break;
ba225198 1216 OP_32_64(add):
53cd9273 1217 c = ARITH_ADD;
ba225198
RH		 1218 goto gen_arith;
1219 OP_32_64(sub):
8289b279 1220 c = ARITH_SUB;
ba225198
RH		 1221 goto gen_arith;
1222 OP_32_64(and):
8289b279 1223 c = ARITH_AND;
ba225198 1224 goto gen_arith;
dc69960d
RH		 1225 OP_32_64(andc):
1226 c = ARITH_ANDN;
1227 goto gen_arith;
ba225198 1228 OP_32_64(or):
8289b279 1229 c = ARITH_OR;
ba225198 1230 goto gen_arith;
18c8f7a3
RH		 1231 OP_32_64(orc):
1232 c = ARITH_ORN;
1233 goto gen_arith;
ba225198 1234 OP_32_64(xor):
8289b279 1235 c = ARITH_XOR;
ba225198 1236 goto gen_arith;
8289b279
BS		 1237 case INDEX_op_shl_i32:
1238 c = SHIFT_SLL;
ba225198 1239 goto gen_arith;
8289b279
BS		 1240 case INDEX_op_shr_i32:
1241 c = SHIFT_SRL;
ba225198 1242 goto gen_arith;
8289b279
BS		 1243 case INDEX_op_sar_i32:
1244 c = SHIFT_SRA;
ba225198 1245 goto gen_arith;
8289b279
BS		 1246 case INDEX_op_mul_i32:
1247 c = ARITH_UMUL;
ba225198 1248 goto gen_arith;
583d1215 1249
4b5a85c1
RH		 1250 OP_32_64(neg):
1251 c = ARITH_SUB;
1252 goto gen_arith1;
be6551b1
RH		 1253 OP_32_64(not):
1254 c = ARITH_ORN;
1255 goto gen_arith1;
4b5a85c1 1256
583d1215
RH		 1257 case INDEX_op_div_i32:
1258 tcg_out_div32(s, args[0], args[1], args[2], const_args[2], 0);
1259 break;
1260 case INDEX_op_divu_i32:
1261 tcg_out_div32(s, args[0], args[1], args[2], const_args[2], 1);
1262 break;
1263
1264 case INDEX_op_rem_i32:
1265 case INDEX_op_remu_i32:
1266 tcg_out_div32(s, TCG_REG_I5, args[1], args[2], const_args[2],
1267 opc == INDEX_op_remu_i32);
1268 tcg_out_arithc(s, TCG_REG_I5, TCG_REG_I5, args[2], const_args[2],
1269 ARITH_UMUL);
1270 tcg_out_arith(s, args[0], args[1], TCG_REG_I5, ARITH_SUB);
1271 break;
8289b279
BS		 1272
1273 case INDEX_op_brcond_i32:
1da92db2
BS		 1274 tcg_out_brcond_i32(s, args[2], args[0], args[1], const_args[1],
1275 args[3]);
8289b279 1276 break;
dbfe80e1
RH		 1277 case INDEX_op_setcond_i32:
1278 tcg_out_setcond_i32(s, args[3], args[0], args[1],
1279 args[2], const_args[2]);
1280 break;
1281
56f4927e
RH		 1282#if TCG_TARGET_REG_BITS == 32
1283 case INDEX_op_brcond2_i32:
1284 tcg_out_brcond2_i32(s, args[4], args[0], args[1],
1285 args[2], const_args[2],
1286 args[3], const_args[3], args[5]);
1287 break;
dbfe80e1
RH		 1288 case INDEX_op_setcond2_i32:
1289 tcg_out_setcond2_i32(s, args[5], args[0], args[1], args[2],
1290 args[3], const_args[3],
1291 args[4], const_args[4]);
1292 break;
7a3766f3
RH		 1293 case INDEX_op_add2_i32:
1294 tcg_out_arithc(s, args[0], args[2], args[4], const_args[4],
1295 ARITH_ADDCC);
1296 tcg_out_arithc(s, args[1], args[3], args[5], const_args[5],
1297 ARITH_ADDX);
1298 break;
1299 case INDEX_op_sub2_i32:
1300 tcg_out_arithc(s, args[0], args[2], args[4], const_args[4],
1301 ARITH_SUBCC);
1302 tcg_out_arithc(s, args[1], args[3], args[5], const_args[5],
1303 ARITH_SUBX);
1304 break;
1305 case INDEX_op_mulu2_i32:
1306 tcg_out_arithc(s, args[0], args[2], args[3], const_args[3],
1307 ARITH_UMUL);
1308 tcg_out_rdy(s, args[1]);
1309 break;
56f4927e 1310#endif
8289b279
BS		 1311
1312 case INDEX_op_qemu_ld8u:
f5ef6aac 1313 tcg_out_qemu_ld(s, args, 0);
8289b279
BS		 1314 break;
1315 case INDEX_op_qemu_ld8s:
f5ef6aac 1316 tcg_out_qemu_ld(s, args, 0 | 4);
8289b279
BS		 1317 break;
1318 case INDEX_op_qemu_ld16u:
f5ef6aac 1319 tcg_out_qemu_ld(s, args, 1);
8289b279
BS		 1320 break;
1321 case INDEX_op_qemu_ld16s:
f5ef6aac 1322 tcg_out_qemu_ld(s, args, 1 | 4);
8289b279 1323 break;
86feb1c8
RH		 1324 case INDEX_op_qemu_ld32:
1325#if TCG_TARGET_REG_BITS == 64
8289b279 1326 case INDEX_op_qemu_ld32u:
86feb1c8 1327#endif
f5ef6aac 1328 tcg_out_qemu_ld(s, args, 2);
8289b279 1329 break;
30c0c76c 1330#if TCG_TARGET_REG_BITS == 64
8289b279 1331 case INDEX_op_qemu_ld32s:
f5ef6aac 1332 tcg_out_qemu_ld(s, args, 2 | 4);
8289b279 1333 break;
30c0c76c 1334#endif
8289b279 1335 case INDEX_op_qemu_st8:
f5ef6aac 1336 tcg_out_qemu_st(s, args, 0);
8289b279
BS		 1337 break;
1338 case INDEX_op_qemu_st16:
f5ef6aac 1339 tcg_out_qemu_st(s, args, 1);
8289b279
BS		 1340 break;
1341 case INDEX_op_qemu_st32:
f5ef6aac 1342 tcg_out_qemu_st(s, args, 2);
8289b279
BS		 1343 break;
1344
a212ea75 1345#if TCG_TARGET_REG_BITS == 64
8289b279
BS		 1346 case INDEX_op_movi_i64:
1347 tcg_out_movi(s, TCG_TYPE_I64, args[0], args[1]);
1348 break;
53cd9273
BS		 1349 case INDEX_op_ld32s_i64:
1350 tcg_out_ldst(s, args[0], args[1], args[2], LDSW);
1351 break;
8289b279
BS		 1352 case INDEX_op_ld_i64:
1353 tcg_out_ldst(s, args[0], args[1], args[2], LDX);
1354 break;
1355 case INDEX_op_st_i64:
1356 tcg_out_ldst(s, args[0], args[1], args[2], STX);
1357 break;
1358 case INDEX_op_shl_i64:
1359 c = SHIFT_SLLX;
ba225198 1360 goto gen_arith;
8289b279
BS		 1361 case INDEX_op_shr_i64:
1362 c = SHIFT_SRLX;
ba225198 1363 goto gen_arith;
8289b279
BS		 1364 case INDEX_op_sar_i64:
1365 c = SHIFT_SRAX;
ba225198 1366 goto gen_arith;
8289b279
BS		 1367 case INDEX_op_mul_i64:
1368 c = ARITH_MULX;
ba225198 1369 goto gen_arith;
583d1215 1370 case INDEX_op_div_i64:
53cd9273 1371 c = ARITH_SDIVX;
ba225198 1372 goto gen_arith;
583d1215 1373 case INDEX_op_divu_i64:
8289b279 1374 c = ARITH_UDIVX;
ba225198 1375 goto gen_arith;
583d1215
RH		 1376 case INDEX_op_rem_i64:
1377 case INDEX_op_remu_i64:
1378 tcg_out_arithc(s, TCG_REG_I5, args[1], args[2], const_args[2],
1379 opc == INDEX_op_rem_i64 ? ARITH_SDIVX : ARITH_UDIVX);
1380 tcg_out_arithc(s, TCG_REG_I5, TCG_REG_I5, args[2], const_args[2],
1381 ARITH_MULX);
1382 tcg_out_arith(s, args[0], args[1], TCG_REG_I5, ARITH_SUB);
1383 break;
cc6dfecf
RH		 1384 case INDEX_op_ext32s_i64:
1385 if (const_args[1]) {
1386 tcg_out_movi(s, TCG_TYPE_I64, args[0], (int32_t)args[1]);
1387 } else {
1388 tcg_out_arithi(s, args[0], args[1], 0, SHIFT_SRA);
1389 }
1390 break;
1391 case INDEX_op_ext32u_i64:
1392 if (const_args[1]) {
1393 tcg_out_movi_imm32(s, args[0], args[1]);
1394 } else {
1395 tcg_out_arithi(s, args[0], args[1], 0, SHIFT_SRL);
1396 }
1397 break;
8289b279
BS		 1398
1399 case INDEX_op_brcond_i64:
1da92db2
BS		 1400 tcg_out_brcond_i64(s, args[2], args[0], args[1], const_args[1],
1401 args[3]);
8289b279 1402 break;
dbfe80e1
RH		 1403 case INDEX_op_setcond_i64:
1404 tcg_out_setcond_i64(s, args[3], args[0], args[1],
1405 args[2], const_args[2]);
1406 break;
1407
8289b279 1408 case INDEX_op_qemu_ld64:
f5ef6aac 1409 tcg_out_qemu_ld(s, args, 3);
8289b279
BS		 1410 break;
1411 case INDEX_op_qemu_st64:
f5ef6aac 1412 tcg_out_qemu_st(s, args, 3);
8289b279
BS		 1413 break;
1414
1415#endif
ba225198
RH		 1416 gen_arith:
1417 tcg_out_arithc(s, args[0], args[1], args[2], const_args[2], c);
53cd9273
BS		 1418 break;
1419
4b5a85c1
RH		 1420 gen_arith1:
1421 tcg_out_arithc(s, args[0], TCG_REG_G0, args[1], const_args[1], c);
1422 break;
1423
8289b279
BS		 1424 default:
1425 fprintf(stderr, "unknown opcode 0x%x\n", opc);
1426 tcg_abort();
1427 }
1428}
1429
1430static const TCGTargetOpDef sparc_op_defs[] = {
1431 { INDEX_op_exit_tb, { } },
b3db8758 1432 { INDEX_op_goto_tb, { } },
8289b279
BS		 1433 { INDEX_op_call, { "ri" } },
1434 { INDEX_op_jmp, { "ri" } },
1435 { INDEX_op_br, { } },
1436
1437 { INDEX_op_mov_i32, { "r", "r" } },
1438 { INDEX_op_movi_i32, { "r" } },
1439 { INDEX_op_ld8u_i32, { "r", "r" } },
1440 { INDEX_op_ld8s_i32, { "r", "r" } },
1441 { INDEX_op_ld16u_i32, { "r", "r" } },
1442 { INDEX_op_ld16s_i32, { "r", "r" } },
1443 { INDEX_op_ld_i32, { "r", "r" } },
1444 { INDEX_op_st8_i32, { "r", "r" } },
1445 { INDEX_op_st16_i32, { "r", "r" } },
1446 { INDEX_op_st_i32, { "r", "r" } },
1447
53cd9273
BS		 1448 { INDEX_op_add_i32, { "r", "r", "rJ" } },
1449 { INDEX_op_mul_i32, { "r", "r", "rJ" } },
583d1215
RH		 1450 { INDEX_op_div_i32, { "r", "r", "rJ" } },
1451 { INDEX_op_divu_i32, { "r", "r", "rJ" } },
1452 { INDEX_op_rem_i32, { "r", "r", "rJ" } },
1453 { INDEX_op_remu_i32, { "r", "r", "rJ" } },
53cd9273
BS		 1454 { INDEX_op_sub_i32, { "r", "r", "rJ" } },
1455 { INDEX_op_and_i32, { "r", "r", "rJ" } },
dc69960d 1456 { INDEX_op_andc_i32, { "r", "r", "rJ" } },
53cd9273 1457 { INDEX_op_or_i32, { "r", "r", "rJ" } },
18c8f7a3 1458 { INDEX_op_orc_i32, { "r", "r", "rJ" } },
53cd9273 1459 { INDEX_op_xor_i32, { "r", "r", "rJ" } },
8289b279 1460
53cd9273
BS		 1461 { INDEX_op_shl_i32, { "r", "r", "rJ" } },
1462 { INDEX_op_shr_i32, { "r", "r", "rJ" } },
1463 { INDEX_op_sar_i32, { "r", "r", "rJ" } },
8289b279 1464
4b5a85c1 1465 { INDEX_op_neg_i32, { "r", "rJ" } },
be6551b1 1466 { INDEX_op_not_i32, { "r", "rJ" } },
4b5a85c1 1467
56f4927e 1468 { INDEX_op_brcond_i32, { "r", "rJ" } },
dbfe80e1
RH		 1469 { INDEX_op_setcond_i32, { "r", "r", "rJ" } },
1470
56f4927e
RH		 1471#if TCG_TARGET_REG_BITS == 32
1472 { INDEX_op_brcond2_i32, { "r", "r", "rJ", "rJ" } },
dbfe80e1 1473 { INDEX_op_setcond2_i32, { "r", "r", "r", "rJ", "rJ" } },
7a3766f3
RH		 1474 { INDEX_op_add2_i32, { "r", "r", "r", "r", "rJ", "rJ" } },
1475 { INDEX_op_sub2_i32, { "r", "r", "r", "r", "rJ", "rJ" } },
1476 { INDEX_op_mulu2_i32, { "r", "r", "r", "rJ" } },
56f4927e 1477#endif
8289b279
BS		 1478
1479 { INDEX_op_qemu_ld8u, { "r", "L" } },
1480 { INDEX_op_qemu_ld8s, { "r", "L" } },
1481 { INDEX_op_qemu_ld16u, { "r", "L" } },
1482 { INDEX_op_qemu_ld16s, { "r", "L" } },
86feb1c8 1483 { INDEX_op_qemu_ld32, { "r", "L" } },
30c0c76c 1484#if TCG_TARGET_REG_BITS == 64
86feb1c8 1485 { INDEX_op_qemu_ld32u, { "r", "L" } },
8289b279 1486 { INDEX_op_qemu_ld32s, { "r", "L" } },
30c0c76c 1487#endif
8289b279
BS		 1488
1489 { INDEX_op_qemu_st8, { "L", "L" } },
1490 { INDEX_op_qemu_st16, { "L", "L" } },
1491 { INDEX_op_qemu_st32, { "L", "L" } },
1492
a212ea75 1493#if TCG_TARGET_REG_BITS == 64
8289b279
BS		 1494 { INDEX_op_mov_i64, { "r", "r" } },
1495 { INDEX_op_movi_i64, { "r" } },
1496 { INDEX_op_ld8u_i64, { "r", "r" } },
1497 { INDEX_op_ld8s_i64, { "r", "r" } },
1498 { INDEX_op_ld16u_i64, { "r", "r" } },
1499 { INDEX_op_ld16s_i64, { "r", "r" } },
1500 { INDEX_op_ld32u_i64, { "r", "r" } },
1501 { INDEX_op_ld32s_i64, { "r", "r" } },
1502 { INDEX_op_ld_i64, { "r", "r" } },
1503 { INDEX_op_st8_i64, { "r", "r" } },
1504 { INDEX_op_st16_i64, { "r", "r" } },
1505 { INDEX_op_st32_i64, { "r", "r" } },
1506 { INDEX_op_st_i64, { "r", "r" } },
56fc64df
BS		 1507 { INDEX_op_qemu_ld64, { "L", "L" } },
1508 { INDEX_op_qemu_st64, { "L", "L" } },
8289b279 1509
53cd9273
BS		 1510 { INDEX_op_add_i64, { "r", "r", "rJ" } },
1511 { INDEX_op_mul_i64, { "r", "r", "rJ" } },
583d1215
RH		 1512 { INDEX_op_div_i64, { "r", "r", "rJ" } },
1513 { INDEX_op_divu_i64, { "r", "r", "rJ" } },
1514 { INDEX_op_rem_i64, { "r", "r", "rJ" } },
1515 { INDEX_op_remu_i64, { "r", "r", "rJ" } },
53cd9273
BS		 1516 { INDEX_op_sub_i64, { "r", "r", "rJ" } },
1517 { INDEX_op_and_i64, { "r", "r", "rJ" } },
dc69960d 1518 { INDEX_op_andc_i64, { "r", "r", "rJ" } },
53cd9273 1519 { INDEX_op_or_i64, { "r", "r", "rJ" } },
18c8f7a3 1520 { INDEX_op_orc_i64, { "r", "r", "rJ" } },
53cd9273 1521 { INDEX_op_xor_i64, { "r", "r", "rJ" } },
8289b279 1522
53cd9273
BS		 1523 { INDEX_op_shl_i64, { "r", "r", "rJ" } },
1524 { INDEX_op_shr_i64, { "r", "r", "rJ" } },
1525 { INDEX_op_sar_i64, { "r", "r", "rJ" } },
4b5a85c1
RH		 1526
1527 { INDEX_op_neg_i64, { "r", "rJ" } },
be6551b1 1528 { INDEX_op_not_i64, { "r", "rJ" } },
4b5a85c1 1529
cc6dfecf
RH		 1530 { INDEX_op_ext32s_i64, { "r", "ri" } },
1531 { INDEX_op_ext32u_i64, { "r", "ri" } },
8289b279 1532
56f4927e 1533 { INDEX_op_brcond_i64, { "r", "rJ" } },
dbfe80e1 1534 { INDEX_op_setcond_i64, { "r", "r", "rJ" } },
8289b279
BS		 1535#endif
1536 { -1 },
1537};
1538
e4d58b41 1539static void tcg_target_init(TCGContext *s)
8289b279
BS		 1540{
1541 tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0, 0xffffffff);
a212ea75 1542#if TCG_TARGET_REG_BITS == 64
8289b279
BS		 1543 tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I64], 0, 0xffffffff);
1544#endif
1545 tcg_regset_set32(tcg_target_call_clobber_regs, 0,
b3db8758
BS		 1546 (1 << TCG_REG_G1) |
1547 (1 << TCG_REG_G2) |
1548 (1 << TCG_REG_G3) |
1549 (1 << TCG_REG_G4) |
1550 (1 << TCG_REG_G5) |
1551 (1 << TCG_REG_G6) |
1552 (1 << TCG_REG_G7) |
8289b279
BS		 1553 (1 << TCG_REG_O0) |
1554 (1 << TCG_REG_O1) |
1555 (1 << TCG_REG_O2) |
1556 (1 << TCG_REG_O3) |
1557 (1 << TCG_REG_O4) |
1558 (1 << TCG_REG_O5) |
8289b279
BS		 1559 (1 << TCG_REG_O7));
1560
1561 tcg_regset_clear(s->reserved_regs);
1562 tcg_regset_set_reg(s->reserved_regs, TCG_REG_G0);
a212ea75 1563#if TCG_TARGET_REG_BITS == 64
d795eb86
BS		 1564 tcg_regset_set_reg(s->reserved_regs, TCG_REG_I4); // for internal use
1565#endif
53cd9273 1566 tcg_regset_set_reg(s->reserved_regs, TCG_REG_I5); // for internal use
8289b279
BS		 1567 tcg_regset_set_reg(s->reserved_regs, TCG_REG_I6);
1568 tcg_regset_set_reg(s->reserved_regs, TCG_REG_I7);
1569 tcg_regset_set_reg(s->reserved_regs, TCG_REG_O6);
1570 tcg_regset_set_reg(s->reserved_regs, TCG_REG_O7);
1571 tcg_add_target_add_op_defs(sparc_op_defs);
1572}
Qemu copy for testing