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8289b279 BS |
1 | /* |
2 | * Tiny Code Generator for QEMU | |
3 | * | |
4 | * Copyright (c) 2008 Fabrice Bellard | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
24 | ||
3cf246f0 RH |
25 | #include "tcg-be-null.h" |
26 | ||
d4a9eb1f | 27 | #ifndef NDEBUG |
8289b279 BS |
28 | static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = { |
29 | "%g0", | |
30 | "%g1", | |
31 | "%g2", | |
32 | "%g3", | |
33 | "%g4", | |
34 | "%g5", | |
35 | "%g6", | |
36 | "%g7", | |
37 | "%o0", | |
38 | "%o1", | |
39 | "%o2", | |
40 | "%o3", | |
41 | "%o4", | |
42 | "%o5", | |
43 | "%o6", | |
44 | "%o7", | |
45 | "%l0", | |
46 | "%l1", | |
47 | "%l2", | |
48 | "%l3", | |
49 | "%l4", | |
50 | "%l5", | |
51 | "%l6", | |
52 | "%l7", | |
53 | "%i0", | |
54 | "%i1", | |
55 | "%i2", | |
56 | "%i3", | |
57 | "%i4", | |
58 | "%i5", | |
59 | "%i6", | |
60 | "%i7", | |
61 | }; | |
d4a9eb1f | 62 | #endif |
8289b279 | 63 | |
9f44adc5 RH |
64 | #ifdef __arch64__ |
65 | # define SPARC64 1 | |
66 | #else | |
67 | # define SPARC64 0 | |
68 | #endif | |
69 | ||
34b1a49c RH |
70 | /* Note that sparcv8plus can only hold 64 bit quantities in %g and %o |
71 | registers. These are saved manually by the kernel in full 64-bit | |
72 | slots. The %i and %l registers are saved by the register window | |
73 | mechanism, which only allocates space for 32 bits. Given that this | |
74 | window spill/fill can happen on any signal, we must consider the | |
75 | high bits of the %i and %l registers garbage at all times. */ | |
76 | #if SPARC64 | |
77 | # define ALL_64 0xffffffffu | |
78 | #else | |
79 | # define ALL_64 0xffffu | |
80 | #endif | |
81 | ||
375816f8 RH |
82 | /* Define some temporary registers. T2 is used for constant generation. */ |
83 | #define TCG_REG_T1 TCG_REG_G1 | |
84 | #define TCG_REG_T2 TCG_REG_O7 | |
85 | ||
c6f7e4fb | 86 | #ifdef CONFIG_USE_GUEST_BASE |
375816f8 | 87 | # define TCG_GUEST_BASE_REG TCG_REG_I5 |
c6f7e4fb RH |
88 | #else |
89 | # define TCG_GUEST_BASE_REG TCG_REG_G0 | |
90 | #endif | |
e141ab52 | 91 | |
0954d0d9 | 92 | static const int tcg_target_reg_alloc_order[] = { |
8289b279 BS |
93 | TCG_REG_L0, |
94 | TCG_REG_L1, | |
95 | TCG_REG_L2, | |
96 | TCG_REG_L3, | |
97 | TCG_REG_L4, | |
98 | TCG_REG_L5, | |
99 | TCG_REG_L6, | |
100 | TCG_REG_L7, | |
26adfb75 | 101 | |
8289b279 BS |
102 | TCG_REG_I0, |
103 | TCG_REG_I1, | |
104 | TCG_REG_I2, | |
105 | TCG_REG_I3, | |
106 | TCG_REG_I4, | |
375816f8 | 107 | TCG_REG_I5, |
26adfb75 RH |
108 | |
109 | TCG_REG_G2, | |
110 | TCG_REG_G3, | |
111 | TCG_REG_G4, | |
112 | TCG_REG_G5, | |
113 | ||
114 | TCG_REG_O0, | |
115 | TCG_REG_O1, | |
116 | TCG_REG_O2, | |
117 | TCG_REG_O3, | |
118 | TCG_REG_O4, | |
119 | TCG_REG_O5, | |
8289b279 BS |
120 | }; |
121 | ||
122 | static const int tcg_target_call_iarg_regs[6] = { | |
123 | TCG_REG_O0, | |
124 | TCG_REG_O1, | |
125 | TCG_REG_O2, | |
126 | TCG_REG_O3, | |
127 | TCG_REG_O4, | |
128 | TCG_REG_O5, | |
129 | }; | |
130 | ||
26a74ae3 | 131 | static const int tcg_target_call_oarg_regs[] = { |
8289b279 | 132 | TCG_REG_O0, |
e141ab52 BS |
133 | TCG_REG_O1, |
134 | TCG_REG_O2, | |
135 | TCG_REG_O3, | |
8289b279 BS |
136 | }; |
137 | ||
8289b279 BS |
138 | #define INSN_OP(x) ((x) << 30) |
139 | #define INSN_OP2(x) ((x) << 22) | |
140 | #define INSN_OP3(x) ((x) << 19) | |
141 | #define INSN_OPF(x) ((x) << 5) | |
142 | #define INSN_RD(x) ((x) << 25) | |
143 | #define INSN_RS1(x) ((x) << 14) | |
144 | #define INSN_RS2(x) (x) | |
8384dd67 | 145 | #define INSN_ASI(x) ((x) << 5) |
8289b279 | 146 | |
203342d8 | 147 | #define INSN_IMM10(x) ((1 << 13) | ((x) & 0x3ff)) |
dbfe80e1 | 148 | #define INSN_IMM11(x) ((1 << 13) | ((x) & 0x7ff)) |
8289b279 | 149 | #define INSN_IMM13(x) ((1 << 13) | ((x) & 0x1fff)) |
ab1339b9 | 150 | #define INSN_OFF16(x) ((((x) >> 2) & 0x3fff) | ((((x) >> 16) & 3) << 20)) |
1da92db2 | 151 | #define INSN_OFF19(x) (((x) >> 2) & 0x07ffff) |
a115f3ea | 152 | #define INSN_COND(x) ((x) << 25) |
8289b279 | 153 | |
cf7c2ca5 BS |
154 | #define COND_N 0x0 |
155 | #define COND_E 0x1 | |
156 | #define COND_LE 0x2 | |
157 | #define COND_L 0x3 | |
158 | #define COND_LEU 0x4 | |
159 | #define COND_CS 0x5 | |
160 | #define COND_NEG 0x6 | |
161 | #define COND_VS 0x7 | |
b3db8758 | 162 | #define COND_A 0x8 |
cf7c2ca5 BS |
163 | #define COND_NE 0x9 |
164 | #define COND_G 0xa | |
165 | #define COND_GE 0xb | |
166 | #define COND_GU 0xc | |
167 | #define COND_CC 0xd | |
168 | #define COND_POS 0xe | |
169 | #define COND_VC 0xf | |
a115f3ea | 170 | #define BA (INSN_OP(0) | INSN_COND(COND_A) | INSN_OP2(0x2)) |
8289b279 | 171 | |
ab1339b9 RH |
172 | #define RCOND_Z 1 |
173 | #define RCOND_LEZ 2 | |
174 | #define RCOND_LZ 3 | |
175 | #define RCOND_NZ 5 | |
176 | #define RCOND_GZ 6 | |
177 | #define RCOND_GEZ 7 | |
178 | ||
dbfe80e1 RH |
179 | #define MOVCC_ICC (1 << 18) |
180 | #define MOVCC_XCC (1 << 18 | 1 << 12) | |
181 | ||
a115f3ea RH |
182 | #define BPCC_ICC 0 |
183 | #define BPCC_XCC (2 << 20) | |
184 | #define BPCC_PT (1 << 19) | |
185 | #define BPCC_PN 0 | |
186 | #define BPCC_A (1 << 29) | |
187 | ||
ab1339b9 RH |
188 | #define BPR_PT BPCC_PT |
189 | ||
8289b279 | 190 | #define ARITH_ADD (INSN_OP(2) | INSN_OP3(0x00)) |
7a3766f3 | 191 | #define ARITH_ADDCC (INSN_OP(2) | INSN_OP3(0x10)) |
8289b279 | 192 | #define ARITH_AND (INSN_OP(2) | INSN_OP3(0x01)) |
dc69960d | 193 | #define ARITH_ANDN (INSN_OP(2) | INSN_OP3(0x05)) |
8289b279 | 194 | #define ARITH_OR (INSN_OP(2) | INSN_OP3(0x02)) |
9a7f3228 | 195 | #define ARITH_ORCC (INSN_OP(2) | INSN_OP3(0x12)) |
be6551b1 | 196 | #define ARITH_ORN (INSN_OP(2) | INSN_OP3(0x06)) |
8289b279 | 197 | #define ARITH_XOR (INSN_OP(2) | INSN_OP3(0x03)) |
f5ef6aac BS |
198 | #define ARITH_SUB (INSN_OP(2) | INSN_OP3(0x04)) |
199 | #define ARITH_SUBCC (INSN_OP(2) | INSN_OP3(0x14)) | |
c470b663 RH |
200 | #define ARITH_ADDC (INSN_OP(2) | INSN_OP3(0x08)) |
201 | #define ARITH_SUBC (INSN_OP(2) | INSN_OP3(0x0c)) | |
8289b279 | 202 | #define ARITH_UMUL (INSN_OP(2) | INSN_OP3(0x0a)) |
f4c16661 | 203 | #define ARITH_SMUL (INSN_OP(2) | INSN_OP3(0x0b)) |
8289b279 BS |
204 | #define ARITH_UDIV (INSN_OP(2) | INSN_OP3(0x0e)) |
205 | #define ARITH_SDIV (INSN_OP(2) | INSN_OP3(0x0f)) | |
206 | #define ARITH_MULX (INSN_OP(2) | INSN_OP3(0x09)) | |
207 | #define ARITH_UDIVX (INSN_OP(2) | INSN_OP3(0x0d)) | |
208 | #define ARITH_SDIVX (INSN_OP(2) | INSN_OP3(0x2d)) | |
dbfe80e1 | 209 | #define ARITH_MOVCC (INSN_OP(2) | INSN_OP3(0x2c)) |
203342d8 | 210 | #define ARITH_MOVR (INSN_OP(2) | INSN_OP3(0x2f)) |
8289b279 | 211 | |
90379ca8 | 212 | #define ARITH_ADDXC (INSN_OP(2) | INSN_OP3(0x36) | INSN_OPF(0x11)) |
de8301e5 | 213 | #define ARITH_UMULXHI (INSN_OP(2) | INSN_OP3(0x36) | INSN_OPF(0x16)) |
90379ca8 | 214 | |
8289b279 BS |
215 | #define SHIFT_SLL (INSN_OP(2) | INSN_OP3(0x25)) |
216 | #define SHIFT_SRL (INSN_OP(2) | INSN_OP3(0x26)) | |
217 | #define SHIFT_SRA (INSN_OP(2) | INSN_OP3(0x27)) | |
218 | ||
219 | #define SHIFT_SLLX (INSN_OP(2) | INSN_OP3(0x25) | (1 << 12)) | |
220 | #define SHIFT_SRLX (INSN_OP(2) | INSN_OP3(0x26) | (1 << 12)) | |
221 | #define SHIFT_SRAX (INSN_OP(2) | INSN_OP3(0x27) | (1 << 12)) | |
222 | ||
7a3766f3 | 223 | #define RDY (INSN_OP(2) | INSN_OP3(0x28) | INSN_RS1(0)) |
583d1215 | 224 | #define WRY (INSN_OP(2) | INSN_OP3(0x30) | INSN_RD(0)) |
8289b279 | 225 | #define JMPL (INSN_OP(2) | INSN_OP3(0x38)) |
8b66eefe | 226 | #define RETURN (INSN_OP(2) | INSN_OP3(0x39)) |
8289b279 BS |
227 | #define SAVE (INSN_OP(2) | INSN_OP3(0x3c)) |
228 | #define RESTORE (INSN_OP(2) | INSN_OP3(0x3d)) | |
229 | #define SETHI (INSN_OP(0) | INSN_OP2(0x4)) | |
230 | #define CALL INSN_OP(1) | |
231 | #define LDUB (INSN_OP(3) | INSN_OP3(0x01)) | |
232 | #define LDSB (INSN_OP(3) | INSN_OP3(0x09)) | |
233 | #define LDUH (INSN_OP(3) | INSN_OP3(0x02)) | |
234 | #define LDSH (INSN_OP(3) | INSN_OP3(0x0a)) | |
235 | #define LDUW (INSN_OP(3) | INSN_OP3(0x00)) | |
236 | #define LDSW (INSN_OP(3) | INSN_OP3(0x08)) | |
237 | #define LDX (INSN_OP(3) | INSN_OP3(0x0b)) | |
238 | #define STB (INSN_OP(3) | INSN_OP3(0x05)) | |
239 | #define STH (INSN_OP(3) | INSN_OP3(0x06)) | |
240 | #define STW (INSN_OP(3) | INSN_OP3(0x04)) | |
241 | #define STX (INSN_OP(3) | INSN_OP3(0x0e)) | |
8384dd67 BS |
242 | #define LDUBA (INSN_OP(3) | INSN_OP3(0x11)) |
243 | #define LDSBA (INSN_OP(3) | INSN_OP3(0x19)) | |
244 | #define LDUHA (INSN_OP(3) | INSN_OP3(0x12)) | |
245 | #define LDSHA (INSN_OP(3) | INSN_OP3(0x1a)) | |
246 | #define LDUWA (INSN_OP(3) | INSN_OP3(0x10)) | |
247 | #define LDSWA (INSN_OP(3) | INSN_OP3(0x18)) | |
248 | #define LDXA (INSN_OP(3) | INSN_OP3(0x1b)) | |
249 | #define STBA (INSN_OP(3) | INSN_OP3(0x15)) | |
250 | #define STHA (INSN_OP(3) | INSN_OP3(0x16)) | |
251 | #define STWA (INSN_OP(3) | INSN_OP3(0x14)) | |
252 | #define STXA (INSN_OP(3) | INSN_OP3(0x1e)) | |
253 | ||
254 | #ifndef ASI_PRIMARY_LITTLE | |
255 | #define ASI_PRIMARY_LITTLE 0x88 | |
256 | #endif | |
8289b279 | 257 | |
a0ce341a RH |
258 | #define LDUH_LE (LDUHA | INSN_ASI(ASI_PRIMARY_LITTLE)) |
259 | #define LDSH_LE (LDSHA | INSN_ASI(ASI_PRIMARY_LITTLE)) | |
260 | #define LDUW_LE (LDUWA | INSN_ASI(ASI_PRIMARY_LITTLE)) | |
261 | #define LDSW_LE (LDSWA | INSN_ASI(ASI_PRIMARY_LITTLE)) | |
262 | #define LDX_LE (LDXA | INSN_ASI(ASI_PRIMARY_LITTLE)) | |
263 | ||
264 | #define STH_LE (STHA | INSN_ASI(ASI_PRIMARY_LITTLE)) | |
265 | #define STW_LE (STWA | INSN_ASI(ASI_PRIMARY_LITTLE)) | |
266 | #define STX_LE (STXA | INSN_ASI(ASI_PRIMARY_LITTLE)) | |
267 | ||
90379ca8 RH |
268 | #ifndef use_vis3_instructions |
269 | bool use_vis3_instructions; | |
270 | #endif | |
271 | ||
425532d7 | 272 | static inline int check_fit_i64(int64_t val, unsigned int bits) |
a115f3ea | 273 | { |
425532d7 | 274 | return val == sextract64(val, 0, bits); |
a115f3ea RH |
275 | } |
276 | ||
425532d7 | 277 | static inline int check_fit_i32(int32_t val, unsigned int bits) |
a115f3ea | 278 | { |
425532d7 | 279 | return val == sextract32(val, 0, bits); |
a115f3ea RH |
280 | } |
281 | ||
425532d7 RH |
282 | #define check_fit_tl check_fit_i64 |
283 | #if SPARC64 | |
284 | # define check_fit_ptr check_fit_i64 | |
285 | #else | |
286 | # define check_fit_ptr check_fit_i32 | |
287 | #endif | |
288 | ||
abce5964 | 289 | static void patch_reloc(tcg_insn_unit *code_ptr, int type, |
2ba7fae2 | 290 | intptr_t value, intptr_t addend) |
a115f3ea RH |
291 | { |
292 | uint32_t insn; | |
abce5964 RH |
293 | |
294 | assert(addend == 0); | |
295 | value = tcg_ptr_byte_diff((tcg_insn_unit *)value, code_ptr); | |
296 | ||
a115f3ea | 297 | switch (type) { |
ab1339b9 | 298 | case R_SPARC_WDISP16: |
425532d7 | 299 | if (!check_fit_ptr(value >> 2, 16)) { |
ab1339b9 RH |
300 | tcg_abort(); |
301 | } | |
abce5964 | 302 | insn = *code_ptr; |
ab1339b9 RH |
303 | insn &= ~INSN_OFF16(-1); |
304 | insn |= INSN_OFF16(value); | |
abce5964 | 305 | *code_ptr = insn; |
ab1339b9 | 306 | break; |
a115f3ea | 307 | case R_SPARC_WDISP19: |
425532d7 | 308 | if (!check_fit_ptr(value >> 2, 19)) { |
a115f3ea RH |
309 | tcg_abort(); |
310 | } | |
abce5964 | 311 | insn = *code_ptr; |
a115f3ea RH |
312 | insn &= ~INSN_OFF19(-1); |
313 | insn |= INSN_OFF19(value); | |
abce5964 | 314 | *code_ptr = insn; |
a115f3ea RH |
315 | break; |
316 | default: | |
317 | tcg_abort(); | |
318 | } | |
319 | } | |
320 | ||
321 | /* parse target specific constraints */ | |
322 | static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str) | |
323 | { | |
324 | const char *ct_str; | |
325 | ||
326 | ct_str = *pct_str; | |
327 | switch (ct_str[0]) { | |
328 | case 'r': | |
329 | ct->ct |= TCG_CT_REG; | |
330 | tcg_regset_set32(ct->u.regs, 0, 0xffffffff); | |
331 | break; | |
34b1a49c | 332 | case 'R': |
a115f3ea | 333 | ct->ct |= TCG_CT_REG; |
34b1a49c RH |
334 | tcg_regset_set32(ct->u.regs, 0, ALL_64); |
335 | break; | |
336 | case 'A': /* qemu_ld/st address constraint */ | |
337 | ct->ct |= TCG_CT_REG; | |
338 | tcg_regset_set32(ct->u.regs, 0, | |
339 | TARGET_LONG_BITS == 64 ? ALL_64 : 0xffffffff); | |
340 | reserve_helpers: | |
a115f3ea RH |
341 | tcg_regset_reset_reg(ct->u.regs, TCG_REG_O0); |
342 | tcg_regset_reset_reg(ct->u.regs, TCG_REG_O1); | |
343 | tcg_regset_reset_reg(ct->u.regs, TCG_REG_O2); | |
344 | break; | |
34b1a49c RH |
345 | case 's': /* qemu_st data 32-bit constraint */ |
346 | ct->ct |= TCG_CT_REG; | |
347 | tcg_regset_set32(ct->u.regs, 0, 0xffffffff); | |
348 | goto reserve_helpers; | |
349 | case 'S': /* qemu_st data 64-bit constraint */ | |
350 | ct->ct |= TCG_CT_REG; | |
351 | tcg_regset_set32(ct->u.regs, 0, ALL_64); | |
352 | goto reserve_helpers; | |
a115f3ea RH |
353 | case 'I': |
354 | ct->ct |= TCG_CT_CONST_S11; | |
355 | break; | |
356 | case 'J': | |
357 | ct->ct |= TCG_CT_CONST_S13; | |
358 | break; | |
359 | case 'Z': | |
360 | ct->ct |= TCG_CT_CONST_ZERO; | |
361 | break; | |
362 | default: | |
363 | return -1; | |
364 | } | |
365 | ct_str++; | |
366 | *pct_str = ct_str; | |
367 | return 0; | |
368 | } | |
369 | ||
370 | /* test if a constant matches the constraint */ | |
f6c6afc1 | 371 | static inline int tcg_target_const_match(tcg_target_long val, TCGType type, |
a115f3ea RH |
372 | const TCGArgConstraint *arg_ct) |
373 | { | |
374 | int ct = arg_ct->ct; | |
375 | ||
376 | if (ct & TCG_CT_CONST) { | |
377 | return 1; | |
4b304cfa RH |
378 | } |
379 | ||
380 | if (type == TCG_TYPE_I32) { | |
381 | val = (int32_t)val; | |
382 | } | |
383 | ||
384 | if ((ct & TCG_CT_CONST_ZERO) && val == 0) { | |
a115f3ea RH |
385 | return 1; |
386 | } else if ((ct & TCG_CT_CONST_S11) && check_fit_tl(val, 11)) { | |
387 | return 1; | |
388 | } else if ((ct & TCG_CT_CONST_S13) && check_fit_tl(val, 13)) { | |
389 | return 1; | |
390 | } else { | |
391 | return 0; | |
392 | } | |
393 | } | |
394 | ||
35e2da15 RH |
395 | static inline void tcg_out_arith(TCGContext *s, TCGReg rd, TCGReg rs1, |
396 | TCGReg rs2, int op) | |
26cc915c | 397 | { |
35e2da15 | 398 | tcg_out32(s, op | INSN_RD(rd) | INSN_RS1(rs1) | INSN_RS2(rs2)); |
26cc915c BS |
399 | } |
400 | ||
35e2da15 RH |
401 | static inline void tcg_out_arithi(TCGContext *s, TCGReg rd, TCGReg rs1, |
402 | int32_t offset, int op) | |
26cc915c | 403 | { |
35e2da15 | 404 | tcg_out32(s, op | INSN_RD(rd) | INSN_RS1(rs1) | INSN_IMM13(offset)); |
26cc915c BS |
405 | } |
406 | ||
35e2da15 RH |
407 | static void tcg_out_arithc(TCGContext *s, TCGReg rd, TCGReg rs1, |
408 | int32_t val2, int val2const, int op) | |
ba225198 RH |
409 | { |
410 | tcg_out32(s, op | INSN_RD(rd) | INSN_RS1(rs1) | |
411 | | (val2const ? INSN_IMM13(val2) : INSN_RS2(val2))); | |
412 | } | |
413 | ||
2a534aff RH |
414 | static inline void tcg_out_mov(TCGContext *s, TCGType type, |
415 | TCGReg ret, TCGReg arg) | |
8289b279 | 416 | { |
dda73c78 RH |
417 | if (ret != arg) { |
418 | tcg_out_arith(s, ret, arg, TCG_REG_G0, ARITH_OR); | |
419 | } | |
26cc915c BS |
420 | } |
421 | ||
35e2da15 | 422 | static inline void tcg_out_sethi(TCGContext *s, TCGReg ret, uint32_t arg) |
26cc915c BS |
423 | { |
424 | tcg_out32(s, SETHI | INSN_RD(ret) | ((arg & 0xfffffc00) >> 10)); | |
8289b279 BS |
425 | } |
426 | ||
35e2da15 | 427 | static inline void tcg_out_movi_imm13(TCGContext *s, TCGReg ret, int32_t arg) |
b101234a BS |
428 | { |
429 | tcg_out_arithi(s, ret, TCG_REG_G0, arg, ARITH_OR); | |
430 | } | |
431 | ||
a9c7d27b RH |
432 | static void tcg_out_movi(TCGContext *s, TCGType type, |
433 | TCGReg ret, tcg_target_long arg) | |
8289b279 | 434 | { |
425532d7 | 435 | tcg_target_long hi, lo = (int32_t)arg; |
a9c7d27b | 436 | |
035b2398 RH |
437 | /* Make sure we test 32-bit constants for imm13 properly. */ |
438 | if (type == TCG_TYPE_I32) { | |
439 | arg = lo; | |
440 | } | |
441 | ||
a9c7d27b RH |
442 | /* A 13-bit constant sign-extended to 64-bits. */ |
443 | if (check_fit_tl(arg, 13)) { | |
b101234a | 444 | tcg_out_movi_imm13(s, ret, arg); |
a9c7d27b | 445 | return; |
8289b279 | 446 | } |
8289b279 | 447 | |
a9c7d27b | 448 | /* A 32-bit constant, or 32-bit zero-extended to 64-bits. */ |
34b1a49c | 449 | if (type == TCG_TYPE_I32 || arg == (uint32_t)arg) { |
a9c7d27b RH |
450 | tcg_out_sethi(s, ret, arg); |
451 | if (arg & 0x3ff) { | |
452 | tcg_out_arithi(s, ret, ret, arg & 0x3ff, ARITH_OR); | |
453 | } | |
454 | return; | |
455 | } | |
456 | ||
457 | /* A 32-bit constant sign-extended to 64-bits. */ | |
425532d7 | 458 | if (arg == lo) { |
43172207 RH |
459 | tcg_out_sethi(s, ret, ~arg); |
460 | tcg_out_arithi(s, ret, ret, (arg & 0x3ff) | -0x400, ARITH_XOR); | |
a9c7d27b RH |
461 | return; |
462 | } | |
463 | ||
464 | /* A 64-bit constant decomposed into 2 32-bit pieces. */ | |
425532d7 | 465 | if (check_fit_i32(lo, 13)) { |
34b1a49c | 466 | hi = (arg - lo) >> 32; |
a9c7d27b RH |
467 | tcg_out_movi(s, TCG_TYPE_I32, ret, hi); |
468 | tcg_out_arithi(s, ret, ret, 32, SHIFT_SLLX); | |
469 | tcg_out_arithi(s, ret, ret, lo, ARITH_ADD); | |
43172207 | 470 | } else { |
34b1a49c | 471 | hi = arg >> 32; |
a9c7d27b RH |
472 | tcg_out_movi(s, TCG_TYPE_I32, ret, hi); |
473 | tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_T2, lo); | |
375816f8 | 474 | tcg_out_arithi(s, ret, ret, 32, SHIFT_SLLX); |
375816f8 | 475 | tcg_out_arith(s, ret, ret, TCG_REG_T2, ARITH_OR); |
6f41b777 | 476 | } |
b101234a BS |
477 | } |
478 | ||
35e2da15 RH |
479 | static inline void tcg_out_ldst_rr(TCGContext *s, TCGReg data, TCGReg a1, |
480 | TCGReg a2, int op) | |
8289b279 | 481 | { |
a0ce341a | 482 | tcg_out32(s, op | INSN_RD(data) | INSN_RS1(a1) | INSN_RS2(a2)); |
8289b279 BS |
483 | } |
484 | ||
35e2da15 RH |
485 | static void tcg_out_ldst(TCGContext *s, TCGReg ret, TCGReg addr, |
486 | intptr_t offset, int op) | |
8289b279 | 487 | { |
425532d7 | 488 | if (check_fit_ptr(offset, 13)) { |
8289b279 BS |
489 | tcg_out32(s, op | INSN_RD(ret) | INSN_RS1(addr) | |
490 | INSN_IMM13(offset)); | |
a0ce341a | 491 | } else { |
375816f8 RH |
492 | tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_T1, offset); |
493 | tcg_out_ldst_rr(s, ret, addr, TCG_REG_T1, op); | |
cf7c2ca5 | 494 | } |
8289b279 BS |
495 | } |
496 | ||
2a534aff | 497 | static inline void tcg_out_ld(TCGContext *s, TCGType type, TCGReg ret, |
a05b5b9b | 498 | TCGReg arg1, intptr_t arg2) |
8289b279 | 499 | { |
a0ce341a | 500 | tcg_out_ldst(s, ret, arg1, arg2, (type == TCG_TYPE_I32 ? LDUW : LDX)); |
8289b279 BS |
501 | } |
502 | ||
2a534aff | 503 | static inline void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, |
a05b5b9b | 504 | TCGReg arg1, intptr_t arg2) |
8289b279 | 505 | { |
a0ce341a RH |
506 | tcg_out_ldst(s, arg, arg1, arg2, (type == TCG_TYPE_I32 ? STW : STX)); |
507 | } | |
508 | ||
35e2da15 | 509 | static void tcg_out_ld_ptr(TCGContext *s, TCGReg ret, uintptr_t arg) |
a0ce341a | 510 | { |
35e2da15 RH |
511 | tcg_out_movi(s, TCG_TYPE_PTR, ret, arg & ~0x3ff); |
512 | tcg_out_ld(s, TCG_TYPE_PTR, ret, ret, arg & 0x3ff); | |
8289b279 BS |
513 | } |
514 | ||
35e2da15 | 515 | static inline void tcg_out_sety(TCGContext *s, TCGReg rs) |
8289b279 | 516 | { |
583d1215 | 517 | tcg_out32(s, WRY | INSN_RS1(TCG_REG_G0) | INSN_RS2(rs)); |
8289b279 BS |
518 | } |
519 | ||
35e2da15 | 520 | static inline void tcg_out_rdy(TCGContext *s, TCGReg rd) |
7a3766f3 RH |
521 | { |
522 | tcg_out32(s, RDY | INSN_RD(rd)); | |
523 | } | |
524 | ||
35e2da15 RH |
525 | static void tcg_out_div32(TCGContext *s, TCGReg rd, TCGReg rs1, |
526 | int32_t val2, int val2const, int uns) | |
583d1215 RH |
527 | { |
528 | /* Load Y with the sign/zero extension of RS1 to 64-bits. */ | |
529 | if (uns) { | |
530 | tcg_out_sety(s, TCG_REG_G0); | |
531 | } else { | |
375816f8 RH |
532 | tcg_out_arithi(s, TCG_REG_T1, rs1, 31, SHIFT_SRA); |
533 | tcg_out_sety(s, TCG_REG_T1); | |
583d1215 RH |
534 | } |
535 | ||
536 | tcg_out_arithc(s, rd, rs1, val2, val2const, | |
537 | uns ? ARITH_UDIV : ARITH_SDIV); | |
538 | } | |
539 | ||
8289b279 BS |
540 | static inline void tcg_out_nop(TCGContext *s) |
541 | { | |
26cc915c | 542 | tcg_out_sethi(s, TCG_REG_G0, 0); |
8289b279 BS |
543 | } |
544 | ||
0aed257f | 545 | static const uint8_t tcg_cond_to_bcond[] = { |
cf7c2ca5 BS |
546 | [TCG_COND_EQ] = COND_E, |
547 | [TCG_COND_NE] = COND_NE, | |
548 | [TCG_COND_LT] = COND_L, | |
549 | [TCG_COND_GE] = COND_GE, | |
550 | [TCG_COND_LE] = COND_LE, | |
551 | [TCG_COND_GT] = COND_G, | |
552 | [TCG_COND_LTU] = COND_CS, | |
553 | [TCG_COND_GEU] = COND_CC, | |
554 | [TCG_COND_LEU] = COND_LEU, | |
555 | [TCG_COND_GTU] = COND_GU, | |
556 | }; | |
557 | ||
ab1339b9 RH |
558 | static const uint8_t tcg_cond_to_rcond[] = { |
559 | [TCG_COND_EQ] = RCOND_Z, | |
560 | [TCG_COND_NE] = RCOND_NZ, | |
561 | [TCG_COND_LT] = RCOND_LZ, | |
562 | [TCG_COND_GT] = RCOND_GZ, | |
563 | [TCG_COND_LE] = RCOND_LEZ, | |
564 | [TCG_COND_GE] = RCOND_GEZ | |
565 | }; | |
566 | ||
a115f3ea RH |
567 | static void tcg_out_bpcc0(TCGContext *s, int scond, int flags, int off19) |
568 | { | |
569 | tcg_out32(s, INSN_OP(0) | INSN_OP2(1) | INSN_COND(scond) | flags | off19); | |
570 | } | |
571 | ||
bec16311 | 572 | static void tcg_out_bpcc(TCGContext *s, int scond, int flags, TCGLabel *l) |
a115f3ea | 573 | { |
a115f3ea RH |
574 | int off19; |
575 | ||
576 | if (l->has_value) { | |
abce5964 | 577 | off19 = INSN_OFF19(tcg_pcrel_diff(s, l->u.value_ptr)); |
a115f3ea RH |
578 | } else { |
579 | /* Make sure to preserve destinations during retranslation. */ | |
abce5964 | 580 | off19 = *s->code_ptr & INSN_OFF19(-1); |
bec16311 | 581 | tcg_out_reloc(s, s->code_ptr, R_SPARC_WDISP19, l, 0); |
a115f3ea RH |
582 | } |
583 | tcg_out_bpcc0(s, scond, flags, off19); | |
584 | } | |
585 | ||
35e2da15 | 586 | static void tcg_out_cmp(TCGContext *s, TCGReg c1, int32_t c2, int c2const) |
56f4927e | 587 | { |
ba225198 | 588 | tcg_out_arithc(s, TCG_REG_G0, c1, c2, c2const, ARITH_SUBCC); |
56f4927e RH |
589 | } |
590 | ||
35e2da15 | 591 | static void tcg_out_brcond_i32(TCGContext *s, TCGCond cond, TCGReg arg1, |
bec16311 | 592 | int32_t arg2, int const_arg2, TCGLabel *l) |
cf7c2ca5 | 593 | { |
56f4927e | 594 | tcg_out_cmp(s, arg1, arg2, const_arg2); |
bec16311 | 595 | tcg_out_bpcc(s, tcg_cond_to_bcond[cond], BPCC_ICC | BPCC_PT, l); |
cf7c2ca5 BS |
596 | tcg_out_nop(s); |
597 | } | |
598 | ||
35e2da15 RH |
599 | static void tcg_out_movcc(TCGContext *s, TCGCond cond, int cc, TCGReg ret, |
600 | int32_t v1, int v1const) | |
ded37f0d RH |
601 | { |
602 | tcg_out32(s, ARITH_MOVCC | cc | INSN_RD(ret) | |
603 | | INSN_RS1(tcg_cond_to_bcond[cond]) | |
604 | | (v1const ? INSN_IMM11(v1) : INSN_RS2(v1))); | |
605 | } | |
606 | ||
35e2da15 RH |
607 | static void tcg_out_movcond_i32(TCGContext *s, TCGCond cond, TCGReg ret, |
608 | TCGReg c1, int32_t c2, int c2const, | |
609 | int32_t v1, int v1const) | |
ded37f0d RH |
610 | { |
611 | tcg_out_cmp(s, c1, c2, c2const); | |
612 | tcg_out_movcc(s, cond, MOVCC_ICC, ret, v1, v1const); | |
613 | } | |
614 | ||
35e2da15 | 615 | static void tcg_out_brcond_i64(TCGContext *s, TCGCond cond, TCGReg arg1, |
bec16311 | 616 | int32_t arg2, int const_arg2, TCGLabel *l) |
1da92db2 | 617 | { |
ab1339b9 RH |
618 | /* For 64-bit signed comparisons vs zero, we can avoid the compare. */ |
619 | if (arg2 == 0 && !is_unsigned_cond(cond)) { | |
ab1339b9 RH |
620 | int off16; |
621 | ||
622 | if (l->has_value) { | |
abce5964 | 623 | off16 = INSN_OFF16(tcg_pcrel_diff(s, l->u.value_ptr)); |
ab1339b9 RH |
624 | } else { |
625 | /* Make sure to preserve destinations during retranslation. */ | |
abce5964 | 626 | off16 = *s->code_ptr & INSN_OFF16(-1); |
bec16311 | 627 | tcg_out_reloc(s, s->code_ptr, R_SPARC_WDISP16, l, 0); |
ab1339b9 RH |
628 | } |
629 | tcg_out32(s, INSN_OP(0) | INSN_OP2(3) | BPR_PT | INSN_RS1(arg1) | |
630 | | INSN_COND(tcg_cond_to_rcond[cond]) | off16); | |
631 | } else { | |
632 | tcg_out_cmp(s, arg1, arg2, const_arg2); | |
bec16311 | 633 | tcg_out_bpcc(s, tcg_cond_to_bcond[cond], BPCC_XCC | BPCC_PT, l); |
ab1339b9 | 634 | } |
1da92db2 BS |
635 | tcg_out_nop(s); |
636 | } | |
ded37f0d | 637 | |
35e2da15 RH |
638 | static void tcg_out_movr(TCGContext *s, TCGCond cond, TCGReg ret, TCGReg c1, |
639 | int32_t v1, int v1const) | |
203342d8 RH |
640 | { |
641 | tcg_out32(s, ARITH_MOVR | INSN_RD(ret) | INSN_RS1(c1) | |
642 | | (tcg_cond_to_rcond[cond] << 10) | |
643 | | (v1const ? INSN_IMM10(v1) : INSN_RS2(v1))); | |
644 | } | |
645 | ||
35e2da15 RH |
646 | static void tcg_out_movcond_i64(TCGContext *s, TCGCond cond, TCGReg ret, |
647 | TCGReg c1, int32_t c2, int c2const, | |
648 | int32_t v1, int v1const) | |
ded37f0d | 649 | { |
203342d8 RH |
650 | /* For 64-bit signed comparisons vs zero, we can avoid the compare. |
651 | Note that the immediate range is one bit smaller, so we must check | |
652 | for that as well. */ | |
653 | if (c2 == 0 && !is_unsigned_cond(cond) | |
35e2da15 | 654 | && (!v1const || check_fit_i32(v1, 10))) { |
203342d8 RH |
655 | tcg_out_movr(s, cond, ret, c1, v1, v1const); |
656 | } else { | |
657 | tcg_out_cmp(s, c1, c2, c2const); | |
658 | tcg_out_movcc(s, cond, MOVCC_XCC, ret, v1, v1const); | |
659 | } | |
ded37f0d | 660 | } |
1da92db2 | 661 | |
35e2da15 RH |
662 | static void tcg_out_setcond_i32(TCGContext *s, TCGCond cond, TCGReg ret, |
663 | TCGReg c1, int32_t c2, int c2const) | |
dbfe80e1 | 664 | { |
c470b663 | 665 | /* For 32-bit comparisons, we can play games with ADDC/SUBC. */ |
dbfe80e1 | 666 | switch (cond) { |
7d458a75 RH |
667 | case TCG_COND_LTU: |
668 | case TCG_COND_GEU: | |
669 | /* The result of the comparison is in the carry bit. */ | |
670 | break; | |
671 | ||
dbfe80e1 RH |
672 | case TCG_COND_EQ: |
673 | case TCG_COND_NE: | |
7d458a75 | 674 | /* For equality, we can transform to inequality vs zero. */ |
dbfe80e1 | 675 | if (c2 != 0) { |
321b6c05 RH |
676 | tcg_out_arithc(s, TCG_REG_T1, c1, c2, c2const, ARITH_XOR); |
677 | c2 = TCG_REG_T1; | |
678 | } else { | |
679 | c2 = c1; | |
dbfe80e1 | 680 | } |
321b6c05 | 681 | c1 = TCG_REG_G0, c2const = 0; |
7d458a75 | 682 | cond = (cond == TCG_COND_EQ ? TCG_COND_GEU : TCG_COND_LTU); |
dbfe80e1 RH |
683 | break; |
684 | ||
685 | case TCG_COND_GTU: | |
dbfe80e1 | 686 | case TCG_COND_LEU: |
7d458a75 RH |
687 | /* If we don't need to load a constant into a register, we can |
688 | swap the operands on GTU/LEU. There's no benefit to loading | |
689 | the constant into a temporary register. */ | |
690 | if (!c2const || c2 == 0) { | |
35e2da15 | 691 | TCGReg t = c1; |
7d458a75 RH |
692 | c1 = c2; |
693 | c2 = t; | |
694 | c2const = 0; | |
695 | cond = tcg_swap_cond(cond); | |
696 | break; | |
697 | } | |
698 | /* FALLTHRU */ | |
dbfe80e1 RH |
699 | |
700 | default: | |
701 | tcg_out_cmp(s, c1, c2, c2const); | |
dbfe80e1 | 702 | tcg_out_movi_imm13(s, ret, 0); |
ded37f0d | 703 | tcg_out_movcc(s, cond, MOVCC_ICC, ret, 1, 1); |
dbfe80e1 RH |
704 | return; |
705 | } | |
706 | ||
707 | tcg_out_cmp(s, c1, c2, c2const); | |
708 | if (cond == TCG_COND_LTU) { | |
c470b663 | 709 | tcg_out_arithi(s, ret, TCG_REG_G0, 0, ARITH_ADDC); |
dbfe80e1 | 710 | } else { |
c470b663 | 711 | tcg_out_arithi(s, ret, TCG_REG_G0, -1, ARITH_SUBC); |
dbfe80e1 RH |
712 | } |
713 | } | |
714 | ||
35e2da15 RH |
715 | static void tcg_out_setcond_i64(TCGContext *s, TCGCond cond, TCGReg ret, |
716 | TCGReg c1, int32_t c2, int c2const) | |
dbfe80e1 | 717 | { |
9d6a7a85 RH |
718 | if (use_vis3_instructions) { |
719 | switch (cond) { | |
720 | case TCG_COND_NE: | |
721 | if (c2 != 0) { | |
722 | break; | |
723 | } | |
724 | c2 = c1, c2const = 0, c1 = TCG_REG_G0; | |
725 | /* FALLTHRU */ | |
726 | case TCG_COND_LTU: | |
727 | tcg_out_cmp(s, c1, c2, c2const); | |
728 | tcg_out_arith(s, ret, TCG_REG_G0, TCG_REG_G0, ARITH_ADDXC); | |
729 | return; | |
730 | default: | |
731 | break; | |
732 | } | |
733 | } | |
734 | ||
203342d8 RH |
735 | /* For 64-bit signed comparisons vs zero, we can avoid the compare |
736 | if the input does not overlap the output. */ | |
737 | if (c2 == 0 && !is_unsigned_cond(cond) && c1 != ret) { | |
738 | tcg_out_movi_imm13(s, ret, 0); | |
739 | tcg_out_movr(s, cond, ret, c1, 1, 1); | |
740 | } else { | |
741 | tcg_out_cmp(s, c1, c2, c2const); | |
742 | tcg_out_movi_imm13(s, ret, 0); | |
743 | tcg_out_movcc(s, cond, MOVCC_XCC, ret, 1, 1); | |
744 | } | |
dbfe80e1 | 745 | } |
4ec28e25 | 746 | |
609ac1e1 RH |
747 | static void tcg_out_addsub2_i32(TCGContext *s, TCGReg rl, TCGReg rh, |
748 | TCGReg al, TCGReg ah, int32_t bl, int blconst, | |
749 | int32_t bh, int bhconst, int opl, int oph) | |
4ec28e25 | 750 | { |
35e2da15 | 751 | TCGReg tmp = TCG_REG_T1; |
4ec28e25 RH |
752 | |
753 | /* Note that the low parts are fully consumed before tmp is set. */ | |
754 | if (rl != ah && (bhconst || rl != bh)) { | |
755 | tmp = rl; | |
756 | } | |
757 | ||
758 | tcg_out_arithc(s, tmp, al, bl, blconst, opl); | |
759 | tcg_out_arithc(s, rh, ah, bh, bhconst, oph); | |
760 | tcg_out_mov(s, TCG_TYPE_I32, rl, tmp); | |
761 | } | |
dbfe80e1 | 762 | |
609ac1e1 RH |
763 | static void tcg_out_addsub2_i64(TCGContext *s, TCGReg rl, TCGReg rh, |
764 | TCGReg al, TCGReg ah, int32_t bl, int blconst, | |
765 | int32_t bh, int bhconst, bool is_sub) | |
766 | { | |
767 | TCGReg tmp = TCG_REG_T1; | |
768 | ||
769 | /* Note that the low parts are fully consumed before tmp is set. */ | |
770 | if (rl != ah && (bhconst || rl != bh)) { | |
771 | tmp = rl; | |
772 | } | |
773 | ||
774 | tcg_out_arithc(s, tmp, al, bl, blconst, is_sub ? ARITH_SUBCC : ARITH_ADDCC); | |
775 | ||
90379ca8 RH |
776 | if (use_vis3_instructions && !is_sub) { |
777 | /* Note that ADDXC doesn't accept immediates. */ | |
778 | if (bhconst && bh != 0) { | |
779 | tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_T2, bh); | |
780 | bh = TCG_REG_T2; | |
781 | } | |
782 | tcg_out_arith(s, rh, ah, bh, ARITH_ADDXC); | |
783 | } else if (bh == TCG_REG_G0) { | |
609ac1e1 RH |
784 | /* If we have a zero, we can perform the operation in two insns, |
785 | with the arithmetic first, and a conditional move into place. */ | |
786 | if (rh == ah) { | |
787 | tcg_out_arithi(s, TCG_REG_T2, ah, 1, | |
788 | is_sub ? ARITH_SUB : ARITH_ADD); | |
789 | tcg_out_movcc(s, TCG_COND_LTU, MOVCC_XCC, rh, TCG_REG_T2, 0); | |
790 | } else { | |
791 | tcg_out_arithi(s, rh, ah, 1, is_sub ? ARITH_SUB : ARITH_ADD); | |
792 | tcg_out_movcc(s, TCG_COND_GEU, MOVCC_XCC, rh, ah, 0); | |
793 | } | |
794 | } else { | |
795 | /* Otherwise adjust BH as if there is carry into T2 ... */ | |
796 | if (bhconst) { | |
797 | tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_T2, bh + (is_sub ? -1 : 1)); | |
798 | } else { | |
799 | tcg_out_arithi(s, TCG_REG_T2, bh, 1, | |
800 | is_sub ? ARITH_SUB : ARITH_ADD); | |
801 | } | |
802 | /* ... smoosh T2 back to original BH if carry is clear ... */ | |
803 | tcg_out_movcc(s, TCG_COND_GEU, MOVCC_XCC, TCG_REG_T2, bh, bhconst); | |
804 | /* ... and finally perform the arithmetic with the new operand. */ | |
805 | tcg_out_arith(s, rh, ah, TCG_REG_T2, is_sub ? ARITH_SUB : ARITH_ADD); | |
806 | } | |
807 | ||
808 | tcg_out_mov(s, TCG_TYPE_I64, rl, tmp); | |
809 | } | |
810 | ||
4e9cf840 | 811 | static void tcg_out_call_nodelay(TCGContext *s, tcg_insn_unit *dest) |
aad2f06a | 812 | { |
abce5964 | 813 | ptrdiff_t disp = tcg_pcrel_diff(s, dest); |
aad2f06a RH |
814 | |
815 | if (disp == (int32_t)disp) { | |
816 | tcg_out32(s, CALL | (uint32_t)disp >> 2); | |
817 | } else { | |
abce5964 RH |
818 | uintptr_t desti = (uintptr_t)dest; |
819 | tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_T1, desti & ~0xfff); | |
820 | tcg_out_arithi(s, TCG_REG_O7, TCG_REG_T1, desti & 0xfff, JMPL); | |
aad2f06a RH |
821 | } |
822 | } | |
823 | ||
4e9cf840 RH |
824 | static void tcg_out_call(TCGContext *s, tcg_insn_unit *dest) |
825 | { | |
826 | tcg_out_call_nodelay(s, dest); | |
827 | tcg_out_nop(s); | |
828 | } | |
829 | ||
7ea5d725 | 830 | #ifdef CONFIG_SOFTMMU |
abce5964 RH |
831 | static tcg_insn_unit *qemu_ld_trampoline[16]; |
832 | static tcg_insn_unit *qemu_st_trampoline[16]; | |
7ea5d725 RH |
833 | |
834 | static void build_trampolines(TCGContext *s) | |
835 | { | |
abce5964 RH |
836 | static void * const qemu_ld_helpers[16] = { |
837 | [MO_UB] = helper_ret_ldub_mmu, | |
838 | [MO_SB] = helper_ret_ldsb_mmu, | |
839 | [MO_LEUW] = helper_le_lduw_mmu, | |
840 | [MO_LESW] = helper_le_ldsw_mmu, | |
841 | [MO_LEUL] = helper_le_ldul_mmu, | |
842 | [MO_LEQ] = helper_le_ldq_mmu, | |
843 | [MO_BEUW] = helper_be_lduw_mmu, | |
844 | [MO_BESW] = helper_be_ldsw_mmu, | |
845 | [MO_BEUL] = helper_be_ldul_mmu, | |
846 | [MO_BEQ] = helper_be_ldq_mmu, | |
7ea5d725 | 847 | }; |
abce5964 RH |
848 | static void * const qemu_st_helpers[16] = { |
849 | [MO_UB] = helper_ret_stb_mmu, | |
850 | [MO_LEUW] = helper_le_stw_mmu, | |
851 | [MO_LEUL] = helper_le_stl_mmu, | |
852 | [MO_LEQ] = helper_le_stq_mmu, | |
853 | [MO_BEUW] = helper_be_stw_mmu, | |
854 | [MO_BEUL] = helper_be_stl_mmu, | |
855 | [MO_BEQ] = helper_be_stq_mmu, | |
7ea5d725 RH |
856 | }; |
857 | ||
858 | int i; | |
859 | TCGReg ra; | |
7ea5d725 RH |
860 | |
861 | for (i = 0; i < 16; ++i) { | |
abce5964 | 862 | if (qemu_ld_helpers[i] == NULL) { |
7ea5d725 RH |
863 | continue; |
864 | } | |
865 | ||
866 | /* May as well align the trampoline. */ | |
abce5964 | 867 | while ((uintptr_t)s->code_ptr & 15) { |
7ea5d725 | 868 | tcg_out_nop(s); |
7ea5d725 | 869 | } |
abce5964 | 870 | qemu_ld_trampoline[i] = s->code_ptr; |
7ea5d725 | 871 | |
34b1a49c RH |
872 | if (SPARC64 || TARGET_LONG_BITS == 32) { |
873 | ra = TCG_REG_O3; | |
874 | } else { | |
875 | /* Install the high part of the address. */ | |
876 | tcg_out_arithi(s, TCG_REG_O1, TCG_REG_O2, 32, SHIFT_SRLX); | |
877 | ra = TCG_REG_O4; | |
878 | } | |
7ea5d725 RH |
879 | |
880 | /* Set the retaddr operand. */ | |
881 | tcg_out_mov(s, TCG_TYPE_PTR, ra, TCG_REG_O7); | |
882 | /* Set the env operand. */ | |
883 | tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_O0, TCG_AREG0); | |
884 | /* Tail call. */ | |
4e9cf840 | 885 | tcg_out_call_nodelay(s, qemu_ld_helpers[i]); |
7ea5d725 RH |
886 | tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_O7, ra); |
887 | } | |
888 | ||
889 | for (i = 0; i < 16; ++i) { | |
abce5964 | 890 | if (qemu_st_helpers[i] == NULL) { |
7ea5d725 RH |
891 | continue; |
892 | } | |
893 | ||
894 | /* May as well align the trampoline. */ | |
abce5964 | 895 | while ((uintptr_t)s->code_ptr & 15) { |
7ea5d725 | 896 | tcg_out_nop(s); |
7ea5d725 | 897 | } |
abce5964 | 898 | qemu_st_trampoline[i] = s->code_ptr; |
7ea5d725 | 899 | |
34b1a49c RH |
900 | if (SPARC64) { |
901 | ra = TCG_REG_O4; | |
902 | } else { | |
903 | ra = TCG_REG_O1; | |
904 | if (TARGET_LONG_BITS == 64) { | |
905 | /* Install the high part of the address. */ | |
906 | tcg_out_arithi(s, ra, ra + 1, 32, SHIFT_SRLX); | |
907 | ra += 2; | |
908 | } else { | |
909 | ra += 1; | |
910 | } | |
911 | if ((i & MO_SIZE) == MO_64) { | |
912 | /* Install the high part of the data. */ | |
913 | tcg_out_arithi(s, ra, ra + 1, 32, SHIFT_SRLX); | |
914 | ra += 2; | |
915 | } else { | |
916 | ra += 1; | |
917 | } | |
3972ef6f | 918 | /* Skip the oi argument. */ |
34b1a49c RH |
919 | ra += 1; |
920 | } | |
921 | ||
7ea5d725 RH |
922 | /* Set the retaddr operand. */ |
923 | if (ra >= TCG_REG_O6) { | |
924 | tcg_out_st(s, TCG_TYPE_PTR, TCG_REG_O7, TCG_REG_CALL_STACK, | |
925 | TCG_TARGET_CALL_STACK_OFFSET); | |
926 | ra = TCG_REG_G1; | |
927 | } | |
928 | tcg_out_mov(s, TCG_TYPE_PTR, ra, TCG_REG_O7); | |
929 | /* Set the env operand. */ | |
930 | tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_O0, TCG_AREG0); | |
931 | /* Tail call. */ | |
4e9cf840 | 932 | tcg_out_call_nodelay(s, qemu_st_helpers[i]); |
7ea5d725 RH |
933 | tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_O7, ra); |
934 | } | |
935 | } | |
936 | #endif | |
937 | ||
7d551702 | 938 | /* Generate global QEMU prologue and epilogue code */ |
e4d58b41 | 939 | static void tcg_target_qemu_prologue(TCGContext *s) |
b3db8758 | 940 | { |
4c3204cb RH |
941 | int tmp_buf_size, frame_size; |
942 | ||
943 | /* The TCG temp buffer is at the top of the frame, immediately | |
944 | below the frame pointer. */ | |
945 | tmp_buf_size = CPU_TEMP_BUF_NLONGS * (int)sizeof(long); | |
946 | tcg_set_frame(s, TCG_REG_I6, TCG_TARGET_STACK_BIAS - tmp_buf_size, | |
947 | tmp_buf_size); | |
948 | ||
949 | /* TCG_TARGET_CALL_STACK_OFFSET includes the stack bias, but is | |
950 | otherwise the minimal frame usable by callees. */ | |
951 | frame_size = TCG_TARGET_CALL_STACK_OFFSET - TCG_TARGET_STACK_BIAS; | |
952 | frame_size += TCG_STATIC_CALL_ARGS_SIZE + tmp_buf_size; | |
953 | frame_size += TCG_TARGET_STACK_ALIGN - 1; | |
954 | frame_size &= -TCG_TARGET_STACK_ALIGN; | |
b3db8758 | 955 | tcg_out32(s, SAVE | INSN_RD(TCG_REG_O6) | INSN_RS1(TCG_REG_O6) | |
4c3204cb | 956 | INSN_IMM13(-frame_size)); |
c6f7e4fb RH |
957 | |
958 | #ifdef CONFIG_USE_GUEST_BASE | |
959 | if (GUEST_BASE != 0) { | |
960 | tcg_out_movi(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, GUEST_BASE); | |
961 | tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG); | |
962 | } | |
963 | #endif | |
964 | ||
aad2f06a | 965 | tcg_out_arithi(s, TCG_REG_G0, TCG_REG_I1, 0, JMPL); |
0c554161 RH |
966 | /* delay slot */ |
967 | tcg_out_nop(s); | |
4c3204cb RH |
968 | |
969 | /* No epilogue required. We issue ret + restore directly in the TB. */ | |
7ea5d725 RH |
970 | |
971 | #ifdef CONFIG_SOFTMMU | |
972 | build_trampolines(s); | |
973 | #endif | |
b3db8758 BS |
974 | } |
975 | ||
f5ef6aac | 976 | #if defined(CONFIG_SOFTMMU) |
a0ce341a | 977 | /* Perform the TLB load and compare. |
bffe1431 | 978 | |
a0ce341a | 979 | Inputs: |
a8b12c10 | 980 | ADDRLO and ADDRHI contain the possible two parts of the address. |
a0ce341a RH |
981 | |
982 | MEM_INDEX and S_BITS are the memory context and log2 size of the load. | |
983 | ||
984 | WHICH is the offset into the CPUTLBEntry structure of the slot to read. | |
985 | This should be offsetof addr_read or addr_write. | |
986 | ||
987 | The result of the TLB comparison is in %[ix]cc. The sanitized address | |
988 | is in the returned register, maybe %o0. The TLB addend is in %o1. */ | |
989 | ||
34b1a49c RH |
990 | static TCGReg tcg_out_tlb_load(TCGContext *s, TCGReg addr, int mem_index, |
991 | TCGMemOp s_bits, int which) | |
a0ce341a | 992 | { |
a8b12c10 RH |
993 | const TCGReg r0 = TCG_REG_O0; |
994 | const TCGReg r1 = TCG_REG_O1; | |
995 | const TCGReg r2 = TCG_REG_O2; | |
a0ce341a RH |
996 | int tlb_ofs; |
997 | ||
d801a8f2 | 998 | /* Shift the page number down. */ |
34b1a49c | 999 | tcg_out_arithi(s, r1, addr, TARGET_PAGE_BITS, SHIFT_SRL); |
a0ce341a RH |
1000 | |
1001 | /* Mask out the page offset, except for the required alignment. */ | |
d801a8f2 RH |
1002 | tcg_out_movi(s, TCG_TYPE_TL, TCG_REG_T1, |
1003 | TARGET_PAGE_MASK | ((1 << s_bits) - 1)); | |
1004 | ||
1005 | /* Mask the tlb index. */ | |
1006 | tcg_out_arithi(s, r1, r1, CPU_TLB_SIZE - 1, ARITH_AND); | |
1007 | ||
1008 | /* Mask page, part 2. */ | |
1009 | tcg_out_arith(s, r0, addr, TCG_REG_T1, ARITH_AND); | |
a0ce341a | 1010 | |
d801a8f2 RH |
1011 | /* Shift the tlb index into place. */ |
1012 | tcg_out_arithi(s, r1, r1, CPU_TLB_ENTRY_BITS, SHIFT_SLL); | |
a0ce341a RH |
1013 | |
1014 | /* Relative to the current ENV. */ | |
1015 | tcg_out_arith(s, r1, TCG_AREG0, r1, ARITH_ADD); | |
1016 | ||
1017 | /* Find a base address that can load both tlb comparator and addend. */ | |
1018 | tlb_ofs = offsetof(CPUArchState, tlb_table[mem_index][0]); | |
425532d7 | 1019 | if (!check_fit_ptr(tlb_ofs + sizeof(CPUTLBEntry), 13)) { |
35e2da15 RH |
1020 | if (tlb_ofs & ~0x3ff) { |
1021 | tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_T1, tlb_ofs & ~0x3ff); | |
1022 | tcg_out_arith(s, r1, r1, TCG_REG_T1, ARITH_ADD); | |
1023 | } | |
d801a8f2 | 1024 | tlb_ofs &= 0x3ff; |
a0ce341a RH |
1025 | } |
1026 | ||
1027 | /* Load the tlb comparator and the addend. */ | |
1028 | tcg_out_ld(s, TCG_TYPE_TL, r2, r1, tlb_ofs + which); | |
1029 | tcg_out_ld(s, TCG_TYPE_PTR, r1, r1, tlb_ofs+offsetof(CPUTLBEntry, addend)); | |
1030 | ||
1031 | /* subcc arg0, arg2, %g0 */ | |
1032 | tcg_out_cmp(s, r0, r2, 0); | |
1033 | ||
1034 | /* If the guest address must be zero-extended, do so now. */ | |
9f44adc5 | 1035 | if (SPARC64 && TARGET_LONG_BITS == 32) { |
34b1a49c | 1036 | tcg_out_arithi(s, r0, addr, 0, SHIFT_SRL); |
a0ce341a RH |
1037 | return r0; |
1038 | } | |
34b1a49c | 1039 | return addr; |
a0ce341a RH |
1040 | } |
1041 | #endif /* CONFIG_SOFTMMU */ | |
1042 | ||
eef0d9e7 RH |
1043 | static const int qemu_ld_opc[16] = { |
1044 | [MO_UB] = LDUB, | |
1045 | [MO_SB] = LDSB, | |
1046 | ||
1047 | [MO_BEUW] = LDUH, | |
1048 | [MO_BESW] = LDSH, | |
1049 | [MO_BEUL] = LDUW, | |
1050 | [MO_BESL] = LDSW, | |
1051 | [MO_BEQ] = LDX, | |
1052 | ||
1053 | [MO_LEUW] = LDUH_LE, | |
1054 | [MO_LESW] = LDSH_LE, | |
1055 | [MO_LEUL] = LDUW_LE, | |
1056 | [MO_LESL] = LDSW_LE, | |
1057 | [MO_LEQ] = LDX_LE, | |
a0ce341a | 1058 | }; |
9d0efc88 | 1059 | |
eef0d9e7 RH |
1060 | static const int qemu_st_opc[16] = { |
1061 | [MO_UB] = STB, | |
1062 | ||
1063 | [MO_BEUW] = STH, | |
1064 | [MO_BEUL] = STW, | |
1065 | [MO_BEQ] = STX, | |
1066 | ||
1067 | [MO_LEUW] = STH_LE, | |
1068 | [MO_LEUL] = STW_LE, | |
1069 | [MO_LEQ] = STX_LE, | |
a0ce341a | 1070 | }; |
bffe1431 | 1071 | |
34b1a49c | 1072 | static void tcg_out_qemu_ld(TCGContext *s, TCGReg data, TCGReg addr, |
59227d5d | 1073 | TCGMemOpIdx oi, bool is_64) |
f5ef6aac | 1074 | { |
59227d5d | 1075 | TCGMemOp memop = get_memop(oi); |
34b1a49c | 1076 | #ifdef CONFIG_SOFTMMU |
59227d5d | 1077 | unsigned memi = get_mmuidx(oi); |
cab0a7ea | 1078 | TCGReg addrz, param; |
abce5964 RH |
1079 | tcg_insn_unit *func; |
1080 | tcg_insn_unit *label_ptr; | |
f5ef6aac | 1081 | |
2b7ec66f | 1082 | addrz = tcg_out_tlb_load(s, addr, memi, memop & MO_SIZE, |
cab0a7ea | 1083 | offsetof(CPUTLBEntry, addr_read)); |
a0ce341a | 1084 | |
34b1a49c RH |
1085 | /* The fast path is exactly one insn. Thus we can perform the |
1086 | entire TLB Hit in the (annulled) delay slot of the branch | |
1087 | over the TLB Miss case. */ | |
a0ce341a | 1088 | |
34b1a49c | 1089 | /* beq,a,pt %[xi]cc, label0 */ |
abce5964 | 1090 | label_ptr = s->code_ptr; |
34b1a49c RH |
1091 | tcg_out_bpcc0(s, COND_E, BPCC_A | BPCC_PT |
1092 | | (TARGET_LONG_BITS == 64 ? BPCC_XCC : BPCC_ICC), 0); | |
1093 | /* delay slot */ | |
2b7ec66f RH |
1094 | tcg_out_ldst_rr(s, data, addrz, TCG_REG_O1, |
1095 | qemu_ld_opc[memop & (MO_BSWAP | MO_SSIZE)]); | |
53c37487 | 1096 | |
a0ce341a | 1097 | /* TLB Miss. */ |
f5ef6aac | 1098 | |
7ea5d725 | 1099 | param = TCG_REG_O1; |
34b1a49c RH |
1100 | if (!SPARC64 && TARGET_LONG_BITS == 64) { |
1101 | /* Skip the high-part; we'll perform the extract in the trampoline. */ | |
1102 | param++; | |
a0ce341a | 1103 | } |
34b1a49c | 1104 | tcg_out_mov(s, TCG_TYPE_REG, param++, addr); |
f5ef6aac | 1105 | |
7ea5d725 RH |
1106 | /* We use the helpers to extend SB and SW data, leaving the case |
1107 | of SL needing explicit extending below. */ | |
2b7ec66f RH |
1108 | if ((memop & MO_SSIZE) == MO_SL) { |
1109 | func = qemu_ld_trampoline[memop & (MO_BSWAP | MO_SIZE)]; | |
7ea5d725 | 1110 | } else { |
2b7ec66f | 1111 | func = qemu_ld_trampoline[memop & (MO_BSWAP | MO_SSIZE)]; |
7ea5d725 | 1112 | } |
abce5964 | 1113 | assert(func != NULL); |
4e9cf840 | 1114 | tcg_out_call_nodelay(s, func); |
a0ce341a | 1115 | /* delay slot */ |
3972ef6f | 1116 | tcg_out_movi(s, TCG_TYPE_I32, param, oi); |
7ea5d725 | 1117 | |
34b1a49c RH |
1118 | /* Recall that all of the helpers return 64-bit results. |
1119 | Which complicates things for sparcv8plus. */ | |
1120 | if (SPARC64) { | |
1121 | /* We let the helper sign-extend SB and SW, but leave SL for here. */ | |
2b7ec66f | 1122 | if (is_64 && (memop & MO_SSIZE) == MO_SL) { |
34b1a49c RH |
1123 | tcg_out_arithi(s, data, TCG_REG_O0, 0, SHIFT_SRA); |
1124 | } else { | |
1125 | tcg_out_mov(s, TCG_TYPE_REG, data, TCG_REG_O0); | |
1126 | } | |
1127 | } else { | |
2b7ec66f | 1128 | if ((memop & MO_SIZE) == MO_64) { |
34b1a49c RH |
1129 | tcg_out_arithi(s, TCG_REG_O0, TCG_REG_O0, 32, SHIFT_SLLX); |
1130 | tcg_out_arithi(s, TCG_REG_O1, TCG_REG_O1, 0, SHIFT_SRL); | |
1131 | tcg_out_arith(s, data, TCG_REG_O0, TCG_REG_O1, ARITH_OR); | |
1132 | } else if (is_64) { | |
1133 | /* Re-extend from 32-bit rather than reassembling when we | |
1134 | know the high register must be an extension. */ | |
1135 | tcg_out_arithi(s, data, TCG_REG_O1, 0, | |
1136 | memop & MO_SIGN ? SHIFT_SRA : SHIFT_SRL); | |
1137 | } else { | |
1138 | tcg_out_mov(s, TCG_TYPE_I32, data, TCG_REG_O1); | |
a0ce341a | 1139 | } |
f5ef6aac BS |
1140 | } |
1141 | ||
abce5964 | 1142 | *label_ptr |= INSN_OFF19(tcg_ptr_byte_diff(s->code_ptr, label_ptr)); |
90cbed46 | 1143 | #else |
9f44adc5 | 1144 | if (SPARC64 && TARGET_LONG_BITS == 32) { |
34b1a49c RH |
1145 | tcg_out_arithi(s, TCG_REG_T1, addr, 0, SHIFT_SRL); |
1146 | addr = TCG_REG_T1; | |
f5ef6aac | 1147 | } |
34b1a49c RH |
1148 | tcg_out_ldst_rr(s, data, addr, |
1149 | (GUEST_BASE ? TCG_GUEST_BASE_REG : TCG_REG_G0), | |
2b7ec66f | 1150 | qemu_ld_opc[memop & (MO_BSWAP | MO_SSIZE)]); |
a0ce341a | 1151 | #endif /* CONFIG_SOFTMMU */ |
f5ef6aac BS |
1152 | } |
1153 | ||
34b1a49c | 1154 | static void tcg_out_qemu_st(TCGContext *s, TCGReg data, TCGReg addr, |
59227d5d | 1155 | TCGMemOpIdx oi) |
f5ef6aac | 1156 | { |
59227d5d | 1157 | TCGMemOp memop = get_memop(oi); |
34b1a49c | 1158 | #ifdef CONFIG_SOFTMMU |
59227d5d | 1159 | unsigned memi = get_mmuidx(oi); |
34b1a49c | 1160 | TCGReg addrz, param; |
abce5964 RH |
1161 | tcg_insn_unit *func; |
1162 | tcg_insn_unit *label_ptr; | |
f5ef6aac | 1163 | |
2b7ec66f | 1164 | addrz = tcg_out_tlb_load(s, addr, memi, memop & MO_SIZE, |
cab0a7ea | 1165 | offsetof(CPUTLBEntry, addr_write)); |
a0ce341a | 1166 | |
a0ce341a RH |
1167 | /* The fast path is exactly one insn. Thus we can perform the entire |
1168 | TLB Hit in the (annulled) delay slot of the branch over TLB Miss. */ | |
1169 | /* beq,a,pt %[xi]cc, label0 */ | |
abce5964 | 1170 | label_ptr = s->code_ptr; |
a115f3ea RH |
1171 | tcg_out_bpcc0(s, COND_E, BPCC_A | BPCC_PT |
1172 | | (TARGET_LONG_BITS == 64 ? BPCC_XCC : BPCC_ICC), 0); | |
a0ce341a | 1173 | /* delay slot */ |
2b7ec66f RH |
1174 | tcg_out_ldst_rr(s, data, addrz, TCG_REG_O1, |
1175 | qemu_st_opc[memop & (MO_BSWAP | MO_SIZE)]); | |
a0ce341a RH |
1176 | |
1177 | /* TLB Miss. */ | |
1178 | ||
7ea5d725 | 1179 | param = TCG_REG_O1; |
34b1a49c RH |
1180 | if (!SPARC64 && TARGET_LONG_BITS == 64) { |
1181 | /* Skip the high-part; we'll perform the extract in the trampoline. */ | |
1182 | param++; | |
a0ce341a | 1183 | } |
34b1a49c | 1184 | tcg_out_mov(s, TCG_TYPE_REG, param++, addr); |
2b7ec66f | 1185 | if (!SPARC64 && (memop & MO_SIZE) == MO_64) { |
34b1a49c RH |
1186 | /* Skip the high-part; we'll perform the extract in the trampoline. */ |
1187 | param++; | |
a0ce341a | 1188 | } |
34b1a49c | 1189 | tcg_out_mov(s, TCG_TYPE_REG, param++, data); |
53c37487 | 1190 | |
2b7ec66f | 1191 | func = qemu_st_trampoline[memop & (MO_BSWAP | MO_SIZE)]; |
abce5964 | 1192 | assert(func != NULL); |
4e9cf840 | 1193 | tcg_out_call_nodelay(s, func); |
a0ce341a | 1194 | /* delay slot */ |
3972ef6f | 1195 | tcg_out_movi(s, TCG_TYPE_I32, param, oi); |
f5ef6aac | 1196 | |
abce5964 | 1197 | *label_ptr |= INSN_OFF19(tcg_ptr_byte_diff(s->code_ptr, label_ptr)); |
8384dd67 | 1198 | #else |
9f44adc5 | 1199 | if (SPARC64 && TARGET_LONG_BITS == 32) { |
34b1a49c RH |
1200 | tcg_out_arithi(s, TCG_REG_T1, addr, 0, SHIFT_SRL); |
1201 | addr = TCG_REG_T1; | |
a0ce341a | 1202 | } |
34b1a49c | 1203 | tcg_out_ldst_rr(s, data, addr, |
c6f7e4fb | 1204 | (GUEST_BASE ? TCG_GUEST_BASE_REG : TCG_REG_G0), |
2b7ec66f | 1205 | qemu_st_opc[memop & (MO_BSWAP | MO_SIZE)]); |
a0ce341a | 1206 | #endif /* CONFIG_SOFTMMU */ |
f5ef6aac BS |
1207 | } |
1208 | ||
b357f902 RH |
1209 | static void tcg_out_op(TCGContext *s, TCGOpcode opc, |
1210 | const TCGArg args[TCG_MAX_OP_ARGS], | |
1211 | const int const_args[TCG_MAX_OP_ARGS]) | |
8289b279 | 1212 | { |
b357f902 RH |
1213 | TCGArg a0, a1, a2; |
1214 | int c, c2; | |
1215 | ||
1216 | /* Hoist the loads of the most common arguments. */ | |
1217 | a0 = args[0]; | |
1218 | a1 = args[1]; | |
1219 | a2 = args[2]; | |
1220 | c2 = const_args[2]; | |
8289b279 BS |
1221 | |
1222 | switch (opc) { | |
1223 | case INDEX_op_exit_tb: | |
b357f902 | 1224 | if (check_fit_ptr(a0, 13)) { |
8b66eefe | 1225 | tcg_out_arithi(s, TCG_REG_G0, TCG_REG_I7, 8, RETURN); |
b357f902 | 1226 | tcg_out_movi_imm13(s, TCG_REG_O0, a0); |
8b66eefe | 1227 | } else { |
b357f902 | 1228 | tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_I0, a0 & ~0x3ff); |
8b66eefe | 1229 | tcg_out_arithi(s, TCG_REG_G0, TCG_REG_I7, 8, RETURN); |
b357f902 | 1230 | tcg_out_arithi(s, TCG_REG_O0, TCG_REG_O0, a0 & 0x3ff, ARITH_OR); |
8b66eefe | 1231 | } |
8289b279 BS |
1232 | break; |
1233 | case INDEX_op_goto_tb: | |
1234 | if (s->tb_jmp_offset) { | |
1235 | /* direct jump method */ | |
abce5964 | 1236 | s->tb_jmp_offset[a0] = tcg_current_code_size(s); |
5bbd2cae | 1237 | /* Make sure to preserve links during retranslation. */ |
abce5964 | 1238 | tcg_out32(s, CALL | (*s->code_ptr & ~INSN_OP(-1))); |
8289b279 BS |
1239 | } else { |
1240 | /* indirect jump method */ | |
b357f902 | 1241 | tcg_out_ld_ptr(s, TCG_REG_T1, (uintptr_t)(s->tb_next + a0)); |
aad2f06a | 1242 | tcg_out_arithi(s, TCG_REG_G0, TCG_REG_T1, 0, JMPL); |
8289b279 | 1243 | } |
53cd9273 | 1244 | tcg_out_nop(s); |
abce5964 | 1245 | s->tb_next_offset[a0] = tcg_current_code_size(s); |
8289b279 | 1246 | break; |
8289b279 | 1247 | case INDEX_op_br: |
bec16311 | 1248 | tcg_out_bpcc(s, COND_A, BPCC_PT, arg_label(a0)); |
f5ef6aac | 1249 | tcg_out_nop(s); |
8289b279 | 1250 | break; |
8289b279 | 1251 | |
8289b279 | 1252 | #define OP_32_64(x) \ |
ba225198 RH |
1253 | glue(glue(case INDEX_op_, x), _i32): \ |
1254 | glue(glue(case INDEX_op_, x), _i64) | |
34b1a49c | 1255 | |
ba225198 | 1256 | OP_32_64(ld8u): |
b357f902 | 1257 | tcg_out_ldst(s, a0, a1, a2, LDUB); |
8289b279 | 1258 | break; |
ba225198 | 1259 | OP_32_64(ld8s): |
b357f902 | 1260 | tcg_out_ldst(s, a0, a1, a2, LDSB); |
8289b279 | 1261 | break; |
ba225198 | 1262 | OP_32_64(ld16u): |
b357f902 | 1263 | tcg_out_ldst(s, a0, a1, a2, LDUH); |
8289b279 | 1264 | break; |
ba225198 | 1265 | OP_32_64(ld16s): |
b357f902 | 1266 | tcg_out_ldst(s, a0, a1, a2, LDSH); |
8289b279 BS |
1267 | break; |
1268 | case INDEX_op_ld_i32: | |
53cd9273 | 1269 | case INDEX_op_ld32u_i64: |
b357f902 | 1270 | tcg_out_ldst(s, a0, a1, a2, LDUW); |
8289b279 | 1271 | break; |
ba225198 | 1272 | OP_32_64(st8): |
b357f902 | 1273 | tcg_out_ldst(s, a0, a1, a2, STB); |
8289b279 | 1274 | break; |
ba225198 | 1275 | OP_32_64(st16): |
b357f902 | 1276 | tcg_out_ldst(s, a0, a1, a2, STH); |
8289b279 BS |
1277 | break; |
1278 | case INDEX_op_st_i32: | |
53cd9273 | 1279 | case INDEX_op_st32_i64: |
b357f902 | 1280 | tcg_out_ldst(s, a0, a1, a2, STW); |
8289b279 | 1281 | break; |
ba225198 | 1282 | OP_32_64(add): |
53cd9273 | 1283 | c = ARITH_ADD; |
ba225198 RH |
1284 | goto gen_arith; |
1285 | OP_32_64(sub): | |
8289b279 | 1286 | c = ARITH_SUB; |
ba225198 RH |
1287 | goto gen_arith; |
1288 | OP_32_64(and): | |
8289b279 | 1289 | c = ARITH_AND; |
ba225198 | 1290 | goto gen_arith; |
dc69960d RH |
1291 | OP_32_64(andc): |
1292 | c = ARITH_ANDN; | |
1293 | goto gen_arith; | |
ba225198 | 1294 | OP_32_64(or): |
8289b279 | 1295 | c = ARITH_OR; |
ba225198 | 1296 | goto gen_arith; |
18c8f7a3 RH |
1297 | OP_32_64(orc): |
1298 | c = ARITH_ORN; | |
1299 | goto gen_arith; | |
ba225198 | 1300 | OP_32_64(xor): |
8289b279 | 1301 | c = ARITH_XOR; |
ba225198 | 1302 | goto gen_arith; |
8289b279 BS |
1303 | case INDEX_op_shl_i32: |
1304 | c = SHIFT_SLL; | |
1fd95946 RH |
1305 | do_shift32: |
1306 | /* Limit immediate shift count lest we create an illegal insn. */ | |
b357f902 | 1307 | tcg_out_arithc(s, a0, a1, a2 & 31, c2, c); |
1fd95946 | 1308 | break; |
8289b279 BS |
1309 | case INDEX_op_shr_i32: |
1310 | c = SHIFT_SRL; | |
1fd95946 | 1311 | goto do_shift32; |
8289b279 BS |
1312 | case INDEX_op_sar_i32: |
1313 | c = SHIFT_SRA; | |
1fd95946 | 1314 | goto do_shift32; |
8289b279 BS |
1315 | case INDEX_op_mul_i32: |
1316 | c = ARITH_UMUL; | |
ba225198 | 1317 | goto gen_arith; |
583d1215 | 1318 | |
4b5a85c1 RH |
1319 | OP_32_64(neg): |
1320 | c = ARITH_SUB; | |
1321 | goto gen_arith1; | |
be6551b1 RH |
1322 | OP_32_64(not): |
1323 | c = ARITH_ORN; | |
1324 | goto gen_arith1; | |
4b5a85c1 | 1325 | |
583d1215 | 1326 | case INDEX_op_div_i32: |
b357f902 | 1327 | tcg_out_div32(s, a0, a1, a2, c2, 0); |
583d1215 RH |
1328 | break; |
1329 | case INDEX_op_divu_i32: | |
b357f902 | 1330 | tcg_out_div32(s, a0, a1, a2, c2, 1); |
583d1215 RH |
1331 | break; |
1332 | ||
8289b279 | 1333 | case INDEX_op_brcond_i32: |
bec16311 | 1334 | tcg_out_brcond_i32(s, a2, a0, a1, const_args[1], arg_label(args[3])); |
8289b279 | 1335 | break; |
dbfe80e1 | 1336 | case INDEX_op_setcond_i32: |
b357f902 | 1337 | tcg_out_setcond_i32(s, args[3], a0, a1, a2, c2); |
dbfe80e1 | 1338 | break; |
ded37f0d | 1339 | case INDEX_op_movcond_i32: |
b357f902 | 1340 | tcg_out_movcond_i32(s, args[5], a0, a1, a2, c2, args[3], const_args[3]); |
ded37f0d | 1341 | break; |
dbfe80e1 | 1342 | |
7a3766f3 | 1343 | case INDEX_op_add2_i32: |
609ac1e1 RH |
1344 | tcg_out_addsub2_i32(s, args[0], args[1], args[2], args[3], |
1345 | args[4], const_args[4], args[5], const_args[5], | |
c470b663 | 1346 | ARITH_ADDCC, ARITH_ADDC); |
7a3766f3 RH |
1347 | break; |
1348 | case INDEX_op_sub2_i32: | |
609ac1e1 RH |
1349 | tcg_out_addsub2_i32(s, args[0], args[1], args[2], args[3], |
1350 | args[4], const_args[4], args[5], const_args[5], | |
c470b663 | 1351 | ARITH_SUBCC, ARITH_SUBC); |
7a3766f3 RH |
1352 | break; |
1353 | case INDEX_op_mulu2_i32: | |
f4c16661 RH |
1354 | c = ARITH_UMUL; |
1355 | goto do_mul2; | |
1356 | case INDEX_op_muls2_i32: | |
1357 | c = ARITH_SMUL; | |
1358 | do_mul2: | |
1359 | /* The 32-bit multiply insns produce a full 64-bit result. If the | |
1360 | destination register can hold it, we can avoid the slower RDY. */ | |
b357f902 RH |
1361 | tcg_out_arithc(s, a0, a2, args[3], const_args[3], c); |
1362 | if (SPARC64 || a0 <= TCG_REG_O7) { | |
1363 | tcg_out_arithi(s, a1, a0, 32, SHIFT_SRLX); | |
f4c16661 | 1364 | } else { |
b357f902 | 1365 | tcg_out_rdy(s, a1); |
f4c16661 | 1366 | } |
7a3766f3 | 1367 | break; |
8289b279 | 1368 | |
cab0a7ea | 1369 | case INDEX_op_qemu_ld_i32: |
59227d5d | 1370 | tcg_out_qemu_ld(s, a0, a1, a2, false); |
8289b279 | 1371 | break; |
cab0a7ea | 1372 | case INDEX_op_qemu_ld_i64: |
59227d5d | 1373 | tcg_out_qemu_ld(s, a0, a1, a2, true); |
8289b279 | 1374 | break; |
cab0a7ea | 1375 | case INDEX_op_qemu_st_i32: |
cab0a7ea | 1376 | case INDEX_op_qemu_st_i64: |
59227d5d | 1377 | tcg_out_qemu_st(s, a0, a1, a2); |
a0ce341a | 1378 | break; |
8289b279 | 1379 | |
53cd9273 | 1380 | case INDEX_op_ld32s_i64: |
b357f902 | 1381 | tcg_out_ldst(s, a0, a1, a2, LDSW); |
53cd9273 | 1382 | break; |
8289b279 | 1383 | case INDEX_op_ld_i64: |
b357f902 | 1384 | tcg_out_ldst(s, a0, a1, a2, LDX); |
8289b279 BS |
1385 | break; |
1386 | case INDEX_op_st_i64: | |
b357f902 | 1387 | tcg_out_ldst(s, a0, a1, a2, STX); |
8289b279 BS |
1388 | break; |
1389 | case INDEX_op_shl_i64: | |
1390 | c = SHIFT_SLLX; | |
1fd95946 RH |
1391 | do_shift64: |
1392 | /* Limit immediate shift count lest we create an illegal insn. */ | |
b357f902 | 1393 | tcg_out_arithc(s, a0, a1, a2 & 63, c2, c); |
1fd95946 | 1394 | break; |
8289b279 BS |
1395 | case INDEX_op_shr_i64: |
1396 | c = SHIFT_SRLX; | |
1fd95946 | 1397 | goto do_shift64; |
8289b279 BS |
1398 | case INDEX_op_sar_i64: |
1399 | c = SHIFT_SRAX; | |
1fd95946 | 1400 | goto do_shift64; |
8289b279 BS |
1401 | case INDEX_op_mul_i64: |
1402 | c = ARITH_MULX; | |
ba225198 | 1403 | goto gen_arith; |
583d1215 | 1404 | case INDEX_op_div_i64: |
53cd9273 | 1405 | c = ARITH_SDIVX; |
ba225198 | 1406 | goto gen_arith; |
583d1215 | 1407 | case INDEX_op_divu_i64: |
8289b279 | 1408 | c = ARITH_UDIVX; |
ba225198 | 1409 | goto gen_arith; |
4f2331e5 | 1410 | case INDEX_op_ext_i32_i64: |
cc6dfecf | 1411 | case INDEX_op_ext32s_i64: |
b357f902 | 1412 | tcg_out_arithi(s, a0, a1, 0, SHIFT_SRA); |
cc6dfecf | 1413 | break; |
4f2331e5 | 1414 | case INDEX_op_extu_i32_i64: |
cc6dfecf | 1415 | case INDEX_op_ext32u_i64: |
b357f902 | 1416 | tcg_out_arithi(s, a0, a1, 0, SHIFT_SRL); |
cc6dfecf | 1417 | break; |
609ad705 RH |
1418 | case INDEX_op_extrl_i64_i32: |
1419 | tcg_out_mov(s, TCG_TYPE_I32, a0, a1); | |
1420 | break; | |
1421 | case INDEX_op_extrh_i64_i32: | |
1422 | tcg_out_arithi(s, a0, a1, 32, SHIFT_SRLX); | |
a24fba93 | 1423 | break; |
8289b279 BS |
1424 | |
1425 | case INDEX_op_brcond_i64: | |
bec16311 | 1426 | tcg_out_brcond_i64(s, a2, a0, a1, const_args[1], arg_label(args[3])); |
8289b279 | 1427 | break; |
dbfe80e1 | 1428 | case INDEX_op_setcond_i64: |
b357f902 | 1429 | tcg_out_setcond_i64(s, args[3], a0, a1, a2, c2); |
dbfe80e1 | 1430 | break; |
ded37f0d | 1431 | case INDEX_op_movcond_i64: |
b357f902 | 1432 | tcg_out_movcond_i64(s, args[5], a0, a1, a2, c2, args[3], const_args[3]); |
ded37f0d | 1433 | break; |
609ac1e1 RH |
1434 | case INDEX_op_add2_i64: |
1435 | tcg_out_addsub2_i64(s, args[0], args[1], args[2], args[3], args[4], | |
1436 | const_args[4], args[5], const_args[5], false); | |
1437 | break; | |
1438 | case INDEX_op_sub2_i64: | |
1439 | tcg_out_addsub2_i64(s, args[0], args[1], args[2], args[3], args[4], | |
1440 | const_args[4], args[5], const_args[5], true); | |
1441 | break; | |
de8301e5 RH |
1442 | case INDEX_op_muluh_i64: |
1443 | tcg_out_arith(s, args[0], args[1], args[2], ARITH_UMULXHI); | |
1444 | break; | |
34b1a49c | 1445 | |
ba225198 | 1446 | gen_arith: |
b357f902 | 1447 | tcg_out_arithc(s, a0, a1, a2, c2, c); |
53cd9273 BS |
1448 | break; |
1449 | ||
4b5a85c1 | 1450 | gen_arith1: |
b357f902 | 1451 | tcg_out_arithc(s, a0, TCG_REG_G0, a1, const_args[1], c); |
4b5a85c1 RH |
1452 | break; |
1453 | ||
96d0ee7f | 1454 | case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ |
98b90bab | 1455 | case INDEX_op_mov_i64: |
96d0ee7f | 1456 | case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi. */ |
98b90bab | 1457 | case INDEX_op_movi_i64: |
96d0ee7f | 1458 | case INDEX_op_call: /* Always emitted via tcg_out_call. */ |
8289b279 | 1459 | default: |
8289b279 BS |
1460 | tcg_abort(); |
1461 | } | |
1462 | } | |
1463 | ||
1464 | static const TCGTargetOpDef sparc_op_defs[] = { | |
1465 | { INDEX_op_exit_tb, { } }, | |
b3db8758 | 1466 | { INDEX_op_goto_tb, { } }, |
8289b279 BS |
1467 | { INDEX_op_br, { } }, |
1468 | ||
8289b279 BS |
1469 | { INDEX_op_ld8u_i32, { "r", "r" } }, |
1470 | { INDEX_op_ld8s_i32, { "r", "r" } }, | |
1471 | { INDEX_op_ld16u_i32, { "r", "r" } }, | |
1472 | { INDEX_op_ld16s_i32, { "r", "r" } }, | |
1473 | { INDEX_op_ld_i32, { "r", "r" } }, | |
89269f6c RH |
1474 | { INDEX_op_st8_i32, { "rZ", "r" } }, |
1475 | { INDEX_op_st16_i32, { "rZ", "r" } }, | |
1476 | { INDEX_op_st_i32, { "rZ", "r" } }, | |
1477 | ||
1478 | { INDEX_op_add_i32, { "r", "rZ", "rJ" } }, | |
1479 | { INDEX_op_mul_i32, { "r", "rZ", "rJ" } }, | |
1480 | { INDEX_op_div_i32, { "r", "rZ", "rJ" } }, | |
1481 | { INDEX_op_divu_i32, { "r", "rZ", "rJ" } }, | |
89269f6c RH |
1482 | { INDEX_op_sub_i32, { "r", "rZ", "rJ" } }, |
1483 | { INDEX_op_and_i32, { "r", "rZ", "rJ" } }, | |
1484 | { INDEX_op_andc_i32, { "r", "rZ", "rJ" } }, | |
1485 | { INDEX_op_or_i32, { "r", "rZ", "rJ" } }, | |
1486 | { INDEX_op_orc_i32, { "r", "rZ", "rJ" } }, | |
1487 | { INDEX_op_xor_i32, { "r", "rZ", "rJ" } }, | |
1488 | ||
1489 | { INDEX_op_shl_i32, { "r", "rZ", "rJ" } }, | |
1490 | { INDEX_op_shr_i32, { "r", "rZ", "rJ" } }, | |
1491 | { INDEX_op_sar_i32, { "r", "rZ", "rJ" } }, | |
8289b279 | 1492 | |
4b5a85c1 | 1493 | { INDEX_op_neg_i32, { "r", "rJ" } }, |
be6551b1 | 1494 | { INDEX_op_not_i32, { "r", "rJ" } }, |
4b5a85c1 | 1495 | |
89269f6c RH |
1496 | { INDEX_op_brcond_i32, { "rZ", "rJ" } }, |
1497 | { INDEX_op_setcond_i32, { "r", "rZ", "rJ" } }, | |
1498 | { INDEX_op_movcond_i32, { "r", "rZ", "rJ", "rI", "0" } }, | |
dbfe80e1 | 1499 | |
89269f6c RH |
1500 | { INDEX_op_add2_i32, { "r", "r", "rZ", "rZ", "rJ", "rJ" } }, |
1501 | { INDEX_op_sub2_i32, { "r", "r", "rZ", "rZ", "rJ", "rJ" } }, | |
1502 | { INDEX_op_mulu2_i32, { "r", "r", "rZ", "rJ" } }, | |
f4c16661 | 1503 | { INDEX_op_muls2_i32, { "r", "r", "rZ", "rJ" } }, |
8289b279 | 1504 | |
34b1a49c RH |
1505 | { INDEX_op_ld8u_i64, { "R", "r" } }, |
1506 | { INDEX_op_ld8s_i64, { "R", "r" } }, | |
1507 | { INDEX_op_ld16u_i64, { "R", "r" } }, | |
1508 | { INDEX_op_ld16s_i64, { "R", "r" } }, | |
1509 | { INDEX_op_ld32u_i64, { "R", "r" } }, | |
1510 | { INDEX_op_ld32s_i64, { "R", "r" } }, | |
1511 | { INDEX_op_ld_i64, { "R", "r" } }, | |
1512 | { INDEX_op_st8_i64, { "RZ", "r" } }, | |
1513 | { INDEX_op_st16_i64, { "RZ", "r" } }, | |
1514 | { INDEX_op_st32_i64, { "RZ", "r" } }, | |
1515 | { INDEX_op_st_i64, { "RZ", "r" } }, | |
1516 | ||
1517 | { INDEX_op_add_i64, { "R", "RZ", "RJ" } }, | |
1518 | { INDEX_op_mul_i64, { "R", "RZ", "RJ" } }, | |
1519 | { INDEX_op_div_i64, { "R", "RZ", "RJ" } }, | |
1520 | { INDEX_op_divu_i64, { "R", "RZ", "RJ" } }, | |
1521 | { INDEX_op_sub_i64, { "R", "RZ", "RJ" } }, | |
1522 | { INDEX_op_and_i64, { "R", "RZ", "RJ" } }, | |
1523 | { INDEX_op_andc_i64, { "R", "RZ", "RJ" } }, | |
1524 | { INDEX_op_or_i64, { "R", "RZ", "RJ" } }, | |
1525 | { INDEX_op_orc_i64, { "R", "RZ", "RJ" } }, | |
1526 | { INDEX_op_xor_i64, { "R", "RZ", "RJ" } }, | |
1527 | ||
1528 | { INDEX_op_shl_i64, { "R", "RZ", "RJ" } }, | |
1529 | { INDEX_op_shr_i64, { "R", "RZ", "RJ" } }, | |
1530 | { INDEX_op_sar_i64, { "R", "RZ", "RJ" } }, | |
1531 | ||
1532 | { INDEX_op_neg_i64, { "R", "RJ" } }, | |
1533 | { INDEX_op_not_i64, { "R", "RJ" } }, | |
1534 | ||
4f2331e5 AJ |
1535 | { INDEX_op_ext32s_i64, { "R", "R" } }, |
1536 | { INDEX_op_ext32u_i64, { "R", "R" } }, | |
1537 | { INDEX_op_ext_i32_i64, { "R", "r" } }, | |
1538 | { INDEX_op_extu_i32_i64, { "R", "r" } }, | |
609ad705 RH |
1539 | { INDEX_op_extrl_i64_i32, { "r", "R" } }, |
1540 | { INDEX_op_extrh_i64_i32, { "r", "R" } }, | |
34b1a49c RH |
1541 | |
1542 | { INDEX_op_brcond_i64, { "RZ", "RJ" } }, | |
1543 | { INDEX_op_setcond_i64, { "R", "RZ", "RJ" } }, | |
1544 | { INDEX_op_movcond_i64, { "R", "RZ", "RJ", "RI", "0" } }, | |
1545 | ||
609ac1e1 RH |
1546 | { INDEX_op_add2_i64, { "R", "R", "RZ", "RZ", "RJ", "RI" } }, |
1547 | { INDEX_op_sub2_i64, { "R", "R", "RZ", "RZ", "RJ", "RI" } }, | |
de8301e5 | 1548 | { INDEX_op_muluh_i64, { "R", "RZ", "RZ" } }, |
609ac1e1 | 1549 | |
34b1a49c RH |
1550 | { INDEX_op_qemu_ld_i32, { "r", "A" } }, |
1551 | { INDEX_op_qemu_ld_i64, { "R", "A" } }, | |
ebd0c614 RH |
1552 | { INDEX_op_qemu_st_i32, { "sZ", "A" } }, |
1553 | { INDEX_op_qemu_st_i64, { "SZ", "A" } }, | |
a0ce341a | 1554 | |
8289b279 BS |
1555 | { -1 }, |
1556 | }; | |
1557 | ||
e4d58b41 | 1558 | static void tcg_target_init(TCGContext *s) |
8289b279 | 1559 | { |
90379ca8 RH |
1560 | /* Only probe for the platform and capabilities if we havn't already |
1561 | determined maximum values at compile time. */ | |
1562 | #ifndef use_vis3_instructions | |
1563 | { | |
1564 | unsigned long hwcap = qemu_getauxval(AT_HWCAP); | |
1565 | use_vis3_instructions = (hwcap & HWCAP_SPARC_VIS3) != 0; | |
1566 | } | |
1567 | #endif | |
1568 | ||
8289b279 | 1569 | tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0, 0xffffffff); |
34b1a49c RH |
1570 | tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I64], 0, ALL_64); |
1571 | ||
8289b279 | 1572 | tcg_regset_set32(tcg_target_call_clobber_regs, 0, |
b3db8758 BS |
1573 | (1 << TCG_REG_G1) | |
1574 | (1 << TCG_REG_G2) | | |
1575 | (1 << TCG_REG_G3) | | |
1576 | (1 << TCG_REG_G4) | | |
1577 | (1 << TCG_REG_G5) | | |
1578 | (1 << TCG_REG_G6) | | |
1579 | (1 << TCG_REG_G7) | | |
8289b279 BS |
1580 | (1 << TCG_REG_O0) | |
1581 | (1 << TCG_REG_O1) | | |
1582 | (1 << TCG_REG_O2) | | |
1583 | (1 << TCG_REG_O3) | | |
1584 | (1 << TCG_REG_O4) | | |
1585 | (1 << TCG_REG_O5) | | |
8289b279 BS |
1586 | (1 << TCG_REG_O7)); |
1587 | ||
1588 | tcg_regset_clear(s->reserved_regs); | |
375816f8 RH |
1589 | tcg_regset_set_reg(s->reserved_regs, TCG_REG_G0); /* zero */ |
1590 | tcg_regset_set_reg(s->reserved_regs, TCG_REG_G6); /* reserved for os */ | |
1591 | tcg_regset_set_reg(s->reserved_regs, TCG_REG_G7); /* thread pointer */ | |
1592 | tcg_regset_set_reg(s->reserved_regs, TCG_REG_I6); /* frame pointer */ | |
1593 | tcg_regset_set_reg(s->reserved_regs, TCG_REG_I7); /* return address */ | |
1594 | tcg_regset_set_reg(s->reserved_regs, TCG_REG_O6); /* stack pointer */ | |
1595 | tcg_regset_set_reg(s->reserved_regs, TCG_REG_T1); /* for internal use */ | |
1596 | tcg_regset_set_reg(s->reserved_regs, TCG_REG_T2); /* for internal use */ | |
1597 | ||
8289b279 BS |
1598 | tcg_add_target_add_op_defs(sparc_op_defs); |
1599 | } | |
cb1977d3 | 1600 | |
9f44adc5 | 1601 | #if SPARC64 |
cb1977d3 | 1602 | # define ELF_HOST_MACHINE EM_SPARCV9 |
9b9c37c3 | 1603 | #else |
cb1977d3 RH |
1604 | # define ELF_HOST_MACHINE EM_SPARC32PLUS |
1605 | # define ELF_HOST_FLAGS EF_SPARC_32PLUS | |
cb1977d3 RH |
1606 | #endif |
1607 | ||
cb1977d3 | 1608 | typedef struct { |
ae18b28d | 1609 | DebugFrameHeader h; |
9f44adc5 | 1610 | uint8_t fde_def_cfa[SPARC64 ? 4 : 2]; |
497a22eb RH |
1611 | uint8_t fde_win_save; |
1612 | uint8_t fde_ret_save[3]; | |
cb1977d3 RH |
1613 | } DebugFrame; |
1614 | ||
ae18b28d RH |
1615 | static const DebugFrame debug_frame = { |
1616 | .h.cie.len = sizeof(DebugFrameCIE)-4, /* length after .len member */ | |
1617 | .h.cie.id = -1, | |
1618 | .h.cie.version = 1, | |
1619 | .h.cie.code_align = 1, | |
1620 | .h.cie.data_align = -sizeof(void *) & 0x7f, | |
1621 | .h.cie.return_column = 15, /* o7 */ | |
cb1977d3 | 1622 | |
497a22eb | 1623 | /* Total FDE size does not include the "len" member. */ |
ae18b28d | 1624 | .h.fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, h.fde.cie_offset), |
497a22eb RH |
1625 | |
1626 | .fde_def_cfa = { | |
9f44adc5 | 1627 | #if SPARC64 |
cb1977d3 RH |
1628 | 12, 30, /* DW_CFA_def_cfa i6, 2047 */ |
1629 | (2047 & 0x7f) | 0x80, (2047 >> 7) | |
1630 | #else | |
1631 | 13, 30 /* DW_CFA_def_cfa_register i6 */ | |
1632 | #endif | |
1633 | }, | |
497a22eb RH |
1634 | .fde_win_save = 0x2d, /* DW_CFA_GNU_window_save */ |
1635 | .fde_ret_save = { 9, 15, 31 }, /* DW_CFA_register o7, i7 */ | |
cb1977d3 RH |
1636 | }; |
1637 | ||
1638 | void tcg_register_jit(void *buf, size_t buf_size) | |
1639 | { | |
cb1977d3 RH |
1640 | tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame)); |
1641 | } | |
5bbd2cae RH |
1642 | |
1643 | void tb_set_jmp_target1(uintptr_t jmp_addr, uintptr_t addr) | |
1644 | { | |
1645 | uint32_t *ptr = (uint32_t *)jmp_addr; | |
c8fc56ce | 1646 | uintptr_t disp = addr - jmp_addr; |
5bbd2cae RH |
1647 | |
1648 | /* We can reach the entire address space for 32-bit. For 64-bit | |
1649 | the code_gen_buffer can't be larger than 2GB. */ | |
c8fc56ce | 1650 | assert(disp == (int32_t)disp); |
5bbd2cae | 1651 | |
c8fc56ce | 1652 | *ptr = CALL | (uint32_t)disp >> 2; |
5bbd2cae RH |
1653 | flush_icache_range(jmp_addr, jmp_addr + 4); |
1654 | } |