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8289b279 BS |
1 | /* |
2 | * Tiny Code Generator for QEMU | |
3 | * | |
4 | * Copyright (c) 2008 Fabrice Bellard | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
cb9c377f | 24 | #ifndef TCG_TARGET_SPARC |
8289b279 BS |
25 | #define TCG_TARGET_SPARC 1 |
26 | ||
78cd7b83 RH |
27 | #if UINTPTR_MAX == UINT32_MAX |
28 | # define TCG_TARGET_REG_BITS 32 | |
29 | #elif UINTPTR_MAX == UINT64_MAX | |
30 | # define TCG_TARGET_REG_BITS 64 | |
31 | #else | |
32 | # error Unknown pointer size for tcg target | |
33 | #endif | |
34 | ||
8289b279 BS |
35 | #define TCG_TARGET_WORDS_BIGENDIAN |
36 | ||
37 | #define TCG_TARGET_NB_REGS 32 | |
38 | ||
771142c2 | 39 | typedef enum { |
8289b279 BS |
40 | TCG_REG_G0 = 0, |
41 | TCG_REG_G1, | |
42 | TCG_REG_G2, | |
43 | TCG_REG_G3, | |
44 | TCG_REG_G4, | |
45 | TCG_REG_G5, | |
46 | TCG_REG_G6, | |
47 | TCG_REG_G7, | |
48 | TCG_REG_O0, | |
49 | TCG_REG_O1, | |
50 | TCG_REG_O2, | |
51 | TCG_REG_O3, | |
52 | TCG_REG_O4, | |
53 | TCG_REG_O5, | |
54 | TCG_REG_O6, | |
55 | TCG_REG_O7, | |
56 | TCG_REG_L0, | |
57 | TCG_REG_L1, | |
58 | TCG_REG_L2, | |
59 | TCG_REG_L3, | |
60 | TCG_REG_L4, | |
61 | TCG_REG_L5, | |
62 | TCG_REG_L6, | |
63 | TCG_REG_L7, | |
64 | TCG_REG_I0, | |
65 | TCG_REG_I1, | |
66 | TCG_REG_I2, | |
67 | TCG_REG_I3, | |
68 | TCG_REG_I4, | |
69 | TCG_REG_I5, | |
70 | TCG_REG_I6, | |
71 | TCG_REG_I7, | |
771142c2 | 72 | } TCGReg; |
8289b279 | 73 | |
89269f6c RH |
74 | #define TCG_CT_CONST_S11 0x100 |
75 | #define TCG_CT_CONST_S13 0x200 | |
76 | #define TCG_CT_CONST_ZERO 0x400 | |
8289b279 BS |
77 | |
78 | /* used for function call generation */ | |
4c3204cb | 79 | #define TCG_REG_CALL_STACK TCG_REG_O6 |
9b9c37c3 RH |
80 | |
81 | #if TCG_TARGET_REG_BITS == 64 | |
4c3204cb RH |
82 | #define TCG_TARGET_STACK_BIAS 2047 |
83 | #define TCG_TARGET_STACK_ALIGN 16 | |
84 | #define TCG_TARGET_CALL_STACK_OFFSET (128 + 6*8 + TCG_TARGET_STACK_BIAS) | |
b3db8758 | 85 | #else |
4c3204cb RH |
86 | #define TCG_TARGET_STACK_BIAS 0 |
87 | #define TCG_TARGET_STACK_ALIGN 8 | |
88 | #define TCG_TARGET_CALL_STACK_OFFSET (64 + 4 + 6*4) | |
b3db8758 BS |
89 | #endif |
90 | ||
9b9c37c3 | 91 | #if TCG_TARGET_REG_BITS == 64 |
2bece2c8 RH |
92 | #define TCG_TARGET_EXTEND_ARGS 1 |
93 | #endif | |
94 | ||
8289b279 | 95 | /* optional instructions */ |
25c4d9cc | 96 | #define TCG_TARGET_HAS_div_i32 1 |
ca675f46 | 97 | #define TCG_TARGET_HAS_rem_i32 1 |
25c4d9cc RH |
98 | #define TCG_TARGET_HAS_rot_i32 0 |
99 | #define TCG_TARGET_HAS_ext8s_i32 0 | |
100 | #define TCG_TARGET_HAS_ext16s_i32 0 | |
101 | #define TCG_TARGET_HAS_ext8u_i32 0 | |
102 | #define TCG_TARGET_HAS_ext16u_i32 0 | |
103 | #define TCG_TARGET_HAS_bswap16_i32 0 | |
104 | #define TCG_TARGET_HAS_bswap32_i32 0 | |
105 | #define TCG_TARGET_HAS_neg_i32 1 | |
106 | #define TCG_TARGET_HAS_not_i32 1 | |
107 | #define TCG_TARGET_HAS_andc_i32 1 | |
108 | #define TCG_TARGET_HAS_orc_i32 1 | |
109 | #define TCG_TARGET_HAS_eqv_i32 0 | |
110 | #define TCG_TARGET_HAS_nand_i32 0 | |
111 | #define TCG_TARGET_HAS_nor_i32 0 | |
112 | #define TCG_TARGET_HAS_deposit_i32 0 | |
ded37f0d | 113 | #define TCG_TARGET_HAS_movcond_i32 1 |
803d805b RH |
114 | #define TCG_TARGET_HAS_add2_i32 1 |
115 | #define TCG_TARGET_HAS_sub2_i32 1 | |
116 | #define TCG_TARGET_HAS_mulu2_i32 1 | |
4d3203fd | 117 | #define TCG_TARGET_HAS_muls2_i32 0 |
03271524 RH |
118 | #define TCG_TARGET_HAS_muluh_i32 0 |
119 | #define TCG_TARGET_HAS_mulsh_i32 0 | |
4b5a85c1 | 120 | |
cc6dfecf | 121 | #if TCG_TARGET_REG_BITS == 64 |
25c4d9cc | 122 | #define TCG_TARGET_HAS_div_i64 1 |
ca675f46 | 123 | #define TCG_TARGET_HAS_rem_i64 1 |
25c4d9cc RH |
124 | #define TCG_TARGET_HAS_rot_i64 0 |
125 | #define TCG_TARGET_HAS_ext8s_i64 0 | |
126 | #define TCG_TARGET_HAS_ext16s_i64 0 | |
127 | #define TCG_TARGET_HAS_ext32s_i64 1 | |
128 | #define TCG_TARGET_HAS_ext8u_i64 0 | |
129 | #define TCG_TARGET_HAS_ext16u_i64 0 | |
130 | #define TCG_TARGET_HAS_ext32u_i64 1 | |
131 | #define TCG_TARGET_HAS_bswap16_i64 0 | |
132 | #define TCG_TARGET_HAS_bswap32_i64 0 | |
133 | #define TCG_TARGET_HAS_bswap64_i64 0 | |
134 | #define TCG_TARGET_HAS_neg_i64 1 | |
135 | #define TCG_TARGET_HAS_not_i64 1 | |
136 | #define TCG_TARGET_HAS_andc_i64 1 | |
137 | #define TCG_TARGET_HAS_orc_i64 1 | |
138 | #define TCG_TARGET_HAS_eqv_i64 0 | |
139 | #define TCG_TARGET_HAS_nand_i64 0 | |
140 | #define TCG_TARGET_HAS_nor_i64 0 | |
141 | #define TCG_TARGET_HAS_deposit_i64 0 | |
ded37f0d | 142 | #define TCG_TARGET_HAS_movcond_i64 1 |
d7156f7c RH |
143 | #define TCG_TARGET_HAS_add2_i64 0 |
144 | #define TCG_TARGET_HAS_sub2_i64 0 | |
145 | #define TCG_TARGET_HAS_mulu2_i64 0 | |
4d3203fd | 146 | #define TCG_TARGET_HAS_muls2_i64 0 |
03271524 RH |
147 | #define TCG_TARGET_HAS_muluh_i64 0 |
148 | #define TCG_TARGET_HAS_mulsh_i64 0 | |
cc6dfecf RH |
149 | #endif |
150 | ||
f713d6ad RH |
151 | #define TCG_TARGET_HAS_new_ldst 0 |
152 | ||
0c554161 | 153 | #define TCG_AREG0 TCG_REG_I0 |
8289b279 | 154 | |
b93949ef | 155 | static inline void flush_icache_range(uintptr_t start, uintptr_t stop) |
8289b279 | 156 | { |
b93949ef | 157 | uintptr_t p; |
387e4176 | 158 | for (p = start & -8; p < ((stop + 7) & -8); p += 8) { |
8289b279 | 159 | __asm__ __volatile__("flush\t%0" : : "r" (p)); |
b93949ef | 160 | } |
8289b279 | 161 | } |
cb9c377f PB |
162 | |
163 | #endif |