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8289b279 BS |
1 | /* |
2 | * Tiny Code Generator for QEMU | |
3 | * | |
4 | * Copyright (c) 2008 Fabrice Bellard | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
24 | ||
3a5f6805 RH |
25 | /* We only support generating code for 64-bit mode. */ |
26 | #ifndef __arch64__ | |
27 | #error "unsupported code generation mode" | |
28 | #endif | |
29 | ||
29086503 | 30 | #include "../tcg-ldst.c.inc" |
139c1837 | 31 | #include "../tcg-pool.c.inc" |
e9823b4c | 32 | |
8d8fdbae | 33 | #ifdef CONFIG_DEBUG_TCG |
8289b279 BS |
34 | static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = { |
35 | "%g0", | |
36 | "%g1", | |
37 | "%g2", | |
38 | "%g3", | |
39 | "%g4", | |
40 | "%g5", | |
41 | "%g6", | |
42 | "%g7", | |
43 | "%o0", | |
44 | "%o1", | |
45 | "%o2", | |
46 | "%o3", | |
47 | "%o4", | |
48 | "%o5", | |
49 | "%o6", | |
50 | "%o7", | |
51 | "%l0", | |
52 | "%l1", | |
53 | "%l2", | |
54 | "%l3", | |
55 | "%l4", | |
56 | "%l5", | |
57 | "%l6", | |
58 | "%l7", | |
59 | "%i0", | |
60 | "%i1", | |
61 | "%i2", | |
62 | "%i3", | |
63 | "%i4", | |
64 | "%i5", | |
65 | "%i6", | |
66 | "%i7", | |
67 | }; | |
d4a9eb1f | 68 | #endif |
8289b279 | 69 | |
77f268e8 RH |
70 | #define TCG_CT_CONST_S11 0x100 |
71 | #define TCG_CT_CONST_S13 0x200 | |
72 | #define TCG_CT_CONST_ZERO 0x400 | |
73 | ||
29086503 | 74 | #define ALL_GENERAL_REGS MAKE_64BIT_MASK(0, 32) |
34b1a49c | 75 | |
33982b89 | 76 | /* Define some temporary registers. T3 is used for constant generation. */ |
375816f8 | 77 | #define TCG_REG_T1 TCG_REG_G1 |
33982b89 RH |
78 | #define TCG_REG_T2 TCG_REG_G2 |
79 | #define TCG_REG_T3 TCG_REG_O7 | |
375816f8 | 80 | |
4cbea598 | 81 | #ifndef CONFIG_SOFTMMU |
375816f8 | 82 | # define TCG_GUEST_BASE_REG TCG_REG_I5 |
c6f7e4fb | 83 | #endif |
e141ab52 | 84 | |
ab20bdc1 | 85 | #define TCG_REG_TB TCG_REG_I1 |
ab20bdc1 | 86 | |
0954d0d9 | 87 | static const int tcg_target_reg_alloc_order[] = { |
8289b279 BS |
88 | TCG_REG_L0, |
89 | TCG_REG_L1, | |
90 | TCG_REG_L2, | |
91 | TCG_REG_L3, | |
92 | TCG_REG_L4, | |
93 | TCG_REG_L5, | |
94 | TCG_REG_L6, | |
95 | TCG_REG_L7, | |
26adfb75 | 96 | |
8289b279 BS |
97 | TCG_REG_I0, |
98 | TCG_REG_I1, | |
99 | TCG_REG_I2, | |
100 | TCG_REG_I3, | |
101 | TCG_REG_I4, | |
375816f8 | 102 | TCG_REG_I5, |
26adfb75 | 103 | |
26adfb75 RH |
104 | TCG_REG_G3, |
105 | TCG_REG_G4, | |
106 | TCG_REG_G5, | |
107 | ||
108 | TCG_REG_O0, | |
109 | TCG_REG_O1, | |
110 | TCG_REG_O2, | |
111 | TCG_REG_O3, | |
112 | TCG_REG_O4, | |
113 | TCG_REG_O5, | |
8289b279 BS |
114 | }; |
115 | ||
116 | static const int tcg_target_call_iarg_regs[6] = { | |
117 | TCG_REG_O0, | |
118 | TCG_REG_O1, | |
119 | TCG_REG_O2, | |
120 | TCG_REG_O3, | |
121 | TCG_REG_O4, | |
122 | TCG_REG_O5, | |
123 | }; | |
124 | ||
5e3d0c19 RH |
125 | static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot) |
126 | { | |
127 | tcg_debug_assert(kind == TCG_CALL_RET_NORMAL); | |
128 | tcg_debug_assert(slot >= 0 && slot <= 3); | |
129 | return TCG_REG_O0 + slot; | |
130 | } | |
8289b279 | 131 | |
8289b279 BS |
132 | #define INSN_OP(x) ((x) << 30) |
133 | #define INSN_OP2(x) ((x) << 22) | |
134 | #define INSN_OP3(x) ((x) << 19) | |
135 | #define INSN_OPF(x) ((x) << 5) | |
136 | #define INSN_RD(x) ((x) << 25) | |
137 | #define INSN_RS1(x) ((x) << 14) | |
138 | #define INSN_RS2(x) (x) | |
8384dd67 | 139 | #define INSN_ASI(x) ((x) << 5) |
8289b279 | 140 | |
203342d8 | 141 | #define INSN_IMM10(x) ((1 << 13) | ((x) & 0x3ff)) |
dbfe80e1 | 142 | #define INSN_IMM11(x) ((1 << 13) | ((x) & 0x7ff)) |
8289b279 | 143 | #define INSN_IMM13(x) ((1 << 13) | ((x) & 0x1fff)) |
ab1339b9 | 144 | #define INSN_OFF16(x) ((((x) >> 2) & 0x3fff) | ((((x) >> 16) & 3) << 20)) |
1da92db2 | 145 | #define INSN_OFF19(x) (((x) >> 2) & 0x07ffff) |
a115f3ea | 146 | #define INSN_COND(x) ((x) << 25) |
8289b279 | 147 | |
cf7c2ca5 BS |
148 | #define COND_N 0x0 |
149 | #define COND_E 0x1 | |
150 | #define COND_LE 0x2 | |
151 | #define COND_L 0x3 | |
152 | #define COND_LEU 0x4 | |
153 | #define COND_CS 0x5 | |
154 | #define COND_NEG 0x6 | |
155 | #define COND_VS 0x7 | |
b3db8758 | 156 | #define COND_A 0x8 |
cf7c2ca5 BS |
157 | #define COND_NE 0x9 |
158 | #define COND_G 0xa | |
159 | #define COND_GE 0xb | |
160 | #define COND_GU 0xc | |
161 | #define COND_CC 0xd | |
162 | #define COND_POS 0xe | |
163 | #define COND_VC 0xf | |
a115f3ea | 164 | #define BA (INSN_OP(0) | INSN_COND(COND_A) | INSN_OP2(0x2)) |
8289b279 | 165 | |
ab1339b9 RH |
166 | #define RCOND_Z 1 |
167 | #define RCOND_LEZ 2 | |
168 | #define RCOND_LZ 3 | |
169 | #define RCOND_NZ 5 | |
170 | #define RCOND_GZ 6 | |
171 | #define RCOND_GEZ 7 | |
172 | ||
dbfe80e1 RH |
173 | #define MOVCC_ICC (1 << 18) |
174 | #define MOVCC_XCC (1 << 18 | 1 << 12) | |
175 | ||
a115f3ea RH |
176 | #define BPCC_ICC 0 |
177 | #define BPCC_XCC (2 << 20) | |
178 | #define BPCC_PT (1 << 19) | |
179 | #define BPCC_PN 0 | |
180 | #define BPCC_A (1 << 29) | |
181 | ||
ab1339b9 RH |
182 | #define BPR_PT BPCC_PT |
183 | ||
8289b279 | 184 | #define ARITH_ADD (INSN_OP(2) | INSN_OP3(0x00)) |
7a3766f3 | 185 | #define ARITH_ADDCC (INSN_OP(2) | INSN_OP3(0x10)) |
8289b279 | 186 | #define ARITH_AND (INSN_OP(2) | INSN_OP3(0x01)) |
321dbde3 | 187 | #define ARITH_ANDCC (INSN_OP(2) | INSN_OP3(0x11)) |
dc69960d | 188 | #define ARITH_ANDN (INSN_OP(2) | INSN_OP3(0x05)) |
8289b279 | 189 | #define ARITH_OR (INSN_OP(2) | INSN_OP3(0x02)) |
9a7f3228 | 190 | #define ARITH_ORCC (INSN_OP(2) | INSN_OP3(0x12)) |
be6551b1 | 191 | #define ARITH_ORN (INSN_OP(2) | INSN_OP3(0x06)) |
8289b279 | 192 | #define ARITH_XOR (INSN_OP(2) | INSN_OP3(0x03)) |
f5ef6aac BS |
193 | #define ARITH_SUB (INSN_OP(2) | INSN_OP3(0x04)) |
194 | #define ARITH_SUBCC (INSN_OP(2) | INSN_OP3(0x14)) | |
c470b663 RH |
195 | #define ARITH_ADDC (INSN_OP(2) | INSN_OP3(0x08)) |
196 | #define ARITH_SUBC (INSN_OP(2) | INSN_OP3(0x0c)) | |
8289b279 | 197 | #define ARITH_UMUL (INSN_OP(2) | INSN_OP3(0x0a)) |
f4c16661 | 198 | #define ARITH_SMUL (INSN_OP(2) | INSN_OP3(0x0b)) |
8289b279 BS |
199 | #define ARITH_UDIV (INSN_OP(2) | INSN_OP3(0x0e)) |
200 | #define ARITH_SDIV (INSN_OP(2) | INSN_OP3(0x0f)) | |
201 | #define ARITH_MULX (INSN_OP(2) | INSN_OP3(0x09)) | |
202 | #define ARITH_UDIVX (INSN_OP(2) | INSN_OP3(0x0d)) | |
203 | #define ARITH_SDIVX (INSN_OP(2) | INSN_OP3(0x2d)) | |
dbfe80e1 | 204 | #define ARITH_MOVCC (INSN_OP(2) | INSN_OP3(0x2c)) |
203342d8 | 205 | #define ARITH_MOVR (INSN_OP(2) | INSN_OP3(0x2f)) |
8289b279 | 206 | |
90379ca8 | 207 | #define ARITH_ADDXC (INSN_OP(2) | INSN_OP3(0x36) | INSN_OPF(0x11)) |
de8301e5 | 208 | #define ARITH_UMULXHI (INSN_OP(2) | INSN_OP3(0x36) | INSN_OPF(0x16)) |
90379ca8 | 209 | |
8289b279 BS |
210 | #define SHIFT_SLL (INSN_OP(2) | INSN_OP3(0x25)) |
211 | #define SHIFT_SRL (INSN_OP(2) | INSN_OP3(0x26)) | |
212 | #define SHIFT_SRA (INSN_OP(2) | INSN_OP3(0x27)) | |
213 | ||
214 | #define SHIFT_SLLX (INSN_OP(2) | INSN_OP3(0x25) | (1 << 12)) | |
215 | #define SHIFT_SRLX (INSN_OP(2) | INSN_OP3(0x26) | (1 << 12)) | |
216 | #define SHIFT_SRAX (INSN_OP(2) | INSN_OP3(0x27) | (1 << 12)) | |
217 | ||
7a3766f3 | 218 | #define RDY (INSN_OP(2) | INSN_OP3(0x28) | INSN_RS1(0)) |
583d1215 | 219 | #define WRY (INSN_OP(2) | INSN_OP3(0x30) | INSN_RD(0)) |
8289b279 | 220 | #define JMPL (INSN_OP(2) | INSN_OP3(0x38)) |
8b66eefe | 221 | #define RETURN (INSN_OP(2) | INSN_OP3(0x39)) |
8289b279 BS |
222 | #define SAVE (INSN_OP(2) | INSN_OP3(0x3c)) |
223 | #define RESTORE (INSN_OP(2) | INSN_OP3(0x3d)) | |
224 | #define SETHI (INSN_OP(0) | INSN_OP2(0x4)) | |
225 | #define CALL INSN_OP(1) | |
226 | #define LDUB (INSN_OP(3) | INSN_OP3(0x01)) | |
227 | #define LDSB (INSN_OP(3) | INSN_OP3(0x09)) | |
228 | #define LDUH (INSN_OP(3) | INSN_OP3(0x02)) | |
229 | #define LDSH (INSN_OP(3) | INSN_OP3(0x0a)) | |
230 | #define LDUW (INSN_OP(3) | INSN_OP3(0x00)) | |
231 | #define LDSW (INSN_OP(3) | INSN_OP3(0x08)) | |
232 | #define LDX (INSN_OP(3) | INSN_OP3(0x0b)) | |
233 | #define STB (INSN_OP(3) | INSN_OP3(0x05)) | |
234 | #define STH (INSN_OP(3) | INSN_OP3(0x06)) | |
235 | #define STW (INSN_OP(3) | INSN_OP3(0x04)) | |
236 | #define STX (INSN_OP(3) | INSN_OP3(0x0e)) | |
8384dd67 BS |
237 | #define LDUBA (INSN_OP(3) | INSN_OP3(0x11)) |
238 | #define LDSBA (INSN_OP(3) | INSN_OP3(0x19)) | |
239 | #define LDUHA (INSN_OP(3) | INSN_OP3(0x12)) | |
240 | #define LDSHA (INSN_OP(3) | INSN_OP3(0x1a)) | |
241 | #define LDUWA (INSN_OP(3) | INSN_OP3(0x10)) | |
242 | #define LDSWA (INSN_OP(3) | INSN_OP3(0x18)) | |
243 | #define LDXA (INSN_OP(3) | INSN_OP3(0x1b)) | |
244 | #define STBA (INSN_OP(3) | INSN_OP3(0x15)) | |
245 | #define STHA (INSN_OP(3) | INSN_OP3(0x16)) | |
246 | #define STWA (INSN_OP(3) | INSN_OP3(0x14)) | |
247 | #define STXA (INSN_OP(3) | INSN_OP3(0x1e)) | |
248 | ||
f8f03b37 PK |
249 | #define MEMBAR (INSN_OP(2) | INSN_OP3(0x28) | INSN_RS1(15) | (1 << 13)) |
250 | ||
ab20bdc1 RH |
251 | #define NOP (SETHI | INSN_RD(TCG_REG_G0) | 0) |
252 | ||
8384dd67 BS |
253 | #ifndef ASI_PRIMARY_LITTLE |
254 | #define ASI_PRIMARY_LITTLE 0x88 | |
255 | #endif | |
8289b279 | 256 | |
a0ce341a RH |
257 | #define LDUH_LE (LDUHA | INSN_ASI(ASI_PRIMARY_LITTLE)) |
258 | #define LDSH_LE (LDSHA | INSN_ASI(ASI_PRIMARY_LITTLE)) | |
259 | #define LDUW_LE (LDUWA | INSN_ASI(ASI_PRIMARY_LITTLE)) | |
260 | #define LDSW_LE (LDSWA | INSN_ASI(ASI_PRIMARY_LITTLE)) | |
261 | #define LDX_LE (LDXA | INSN_ASI(ASI_PRIMARY_LITTLE)) | |
262 | ||
263 | #define STH_LE (STHA | INSN_ASI(ASI_PRIMARY_LITTLE)) | |
264 | #define STW_LE (STWA | INSN_ASI(ASI_PRIMARY_LITTLE)) | |
265 | #define STX_LE (STXA | INSN_ASI(ASI_PRIMARY_LITTLE)) | |
266 | ||
90379ca8 RH |
267 | #ifndef use_vis3_instructions |
268 | bool use_vis3_instructions; | |
269 | #endif | |
270 | ||
897fd616 | 271 | static bool check_fit_i64(int64_t val, unsigned int bits) |
a115f3ea | 272 | { |
425532d7 | 273 | return val == sextract64(val, 0, bits); |
a115f3ea RH |
274 | } |
275 | ||
897fd616 | 276 | static bool check_fit_i32(int32_t val, unsigned int bits) |
a115f3ea | 277 | { |
425532d7 | 278 | return val == sextract32(val, 0, bits); |
a115f3ea RH |
279 | } |
280 | ||
425532d7 | 281 | #define check_fit_tl check_fit_i64 |
3a5f6805 | 282 | #define check_fit_ptr check_fit_i64 |
425532d7 | 283 | |
0d8b6191 | 284 | static bool patch_reloc(tcg_insn_unit *src_rw, int type, |
2ba7fae2 | 285 | intptr_t value, intptr_t addend) |
a115f3ea | 286 | { |
0d8b6191 RH |
287 | const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw); |
288 | uint32_t insn = *src_rw; | |
e9823b4c | 289 | intptr_t pcrel; |
abce5964 | 290 | |
e9823b4c | 291 | value += addend; |
0d8b6191 | 292 | pcrel = tcg_ptr_byte_diff((tcg_insn_unit *)value, src_rx); |
abce5964 | 293 | |
a115f3ea | 294 | switch (type) { |
ab1339b9 | 295 | case R_SPARC_WDISP16: |
6a6bfa3c RH |
296 | if (!check_fit_ptr(pcrel >> 2, 16)) { |
297 | return false; | |
298 | } | |
ab1339b9 | 299 | insn &= ~INSN_OFF16(-1); |
e9823b4c | 300 | insn |= INSN_OFF16(pcrel); |
ab1339b9 | 301 | break; |
a115f3ea | 302 | case R_SPARC_WDISP19: |
6a6bfa3c RH |
303 | if (!check_fit_ptr(pcrel >> 2, 19)) { |
304 | return false; | |
305 | } | |
a115f3ea | 306 | insn &= ~INSN_OFF19(-1); |
e9823b4c RH |
307 | insn |= INSN_OFF19(pcrel); |
308 | break; | |
c834b8d8 RH |
309 | case R_SPARC_13: |
310 | if (!check_fit_ptr(value, 13)) { | |
311 | return false; | |
312 | } | |
313 | insn &= ~INSN_IMM13(-1); | |
314 | insn |= INSN_IMM13(value); | |
315 | break; | |
a115f3ea | 316 | default: |
e9823b4c | 317 | g_assert_not_reached(); |
a115f3ea | 318 | } |
e9823b4c | 319 | |
0d8b6191 | 320 | *src_rw = insn; |
6ac17786 | 321 | return true; |
a115f3ea RH |
322 | } |
323 | ||
a115f3ea | 324 | /* test if a constant matches the constraint */ |
ebe92db2 | 325 | static bool tcg_target_const_match(int64_t val, TCGType type, int ct, int vece) |
a115f3ea | 326 | { |
a115f3ea RH |
327 | if (ct & TCG_CT_CONST) { |
328 | return 1; | |
4b304cfa RH |
329 | } |
330 | ||
331 | if (type == TCG_TYPE_I32) { | |
332 | val = (int32_t)val; | |
333 | } | |
334 | ||
335 | if ((ct & TCG_CT_CONST_ZERO) && val == 0) { | |
a115f3ea RH |
336 | return 1; |
337 | } else if ((ct & TCG_CT_CONST_S11) && check_fit_tl(val, 11)) { | |
338 | return 1; | |
339 | } else if ((ct & TCG_CT_CONST_S13) && check_fit_tl(val, 13)) { | |
340 | return 1; | |
341 | } else { | |
342 | return 0; | |
343 | } | |
344 | } | |
345 | ||
220b2da7 RH |
346 | static void tcg_out_nop(TCGContext *s) |
347 | { | |
348 | tcg_out32(s, NOP); | |
349 | } | |
350 | ||
897fd616 RH |
351 | static void tcg_out_arith(TCGContext *s, TCGReg rd, TCGReg rs1, |
352 | TCGReg rs2, int op) | |
26cc915c | 353 | { |
35e2da15 | 354 | tcg_out32(s, op | INSN_RD(rd) | INSN_RS1(rs1) | INSN_RS2(rs2)); |
26cc915c BS |
355 | } |
356 | ||
897fd616 RH |
357 | static void tcg_out_arithi(TCGContext *s, TCGReg rd, TCGReg rs1, |
358 | int32_t offset, int op) | |
26cc915c | 359 | { |
35e2da15 | 360 | tcg_out32(s, op | INSN_RD(rd) | INSN_RS1(rs1) | INSN_IMM13(offset)); |
26cc915c BS |
361 | } |
362 | ||
35e2da15 RH |
363 | static void tcg_out_arithc(TCGContext *s, TCGReg rd, TCGReg rs1, |
364 | int32_t val2, int val2const, int op) | |
ba225198 RH |
365 | { |
366 | tcg_out32(s, op | INSN_RD(rd) | INSN_RS1(rs1) | |
367 | | (val2const ? INSN_IMM13(val2) : INSN_RS2(val2))); | |
368 | } | |
369 | ||
897fd616 | 370 | static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg) |
8289b279 | 371 | { |
dda73c78 RH |
372 | if (ret != arg) { |
373 | tcg_out_arith(s, ret, arg, TCG_REG_G0, ARITH_OR); | |
374 | } | |
78113e83 | 375 | return true; |
26cc915c BS |
376 | } |
377 | ||
220b2da7 RH |
378 | static void tcg_out_mov_delay(TCGContext *s, TCGReg ret, TCGReg arg) |
379 | { | |
380 | if (ret != arg) { | |
381 | tcg_out_arith(s, ret, arg, TCG_REG_G0, ARITH_OR); | |
382 | } else { | |
383 | tcg_out_nop(s); | |
384 | } | |
385 | } | |
386 | ||
897fd616 | 387 | static void tcg_out_sethi(TCGContext *s, TCGReg ret, uint32_t arg) |
26cc915c BS |
388 | { |
389 | tcg_out32(s, SETHI | INSN_RD(ret) | ((arg & 0xfffffc00) >> 10)); | |
8289b279 BS |
390 | } |
391 | ||
8b14f862 RH |
392 | /* A 13-bit constant sign-extended to 64 bits. */ |
393 | static void tcg_out_movi_s13(TCGContext *s, TCGReg ret, int32_t arg) | |
b101234a BS |
394 | { |
395 | tcg_out_arithi(s, ret, TCG_REG_G0, arg, ARITH_OR); | |
396 | } | |
397 | ||
1a42d9d4 RH |
398 | /* A 32-bit constant sign-extended to 64 bits. */ |
399 | static void tcg_out_movi_s32(TCGContext *s, TCGReg ret, int32_t arg) | |
400 | { | |
401 | tcg_out_sethi(s, ret, ~arg); | |
402 | tcg_out_arithi(s, ret, ret, (arg & 0x3ff) | -0x400, ARITH_XOR); | |
403 | } | |
404 | ||
2cb3f794 RH |
405 | /* A 32-bit constant zero-extended to 64 bits. */ |
406 | static void tcg_out_movi_u32(TCGContext *s, TCGReg ret, uint32_t arg) | |
c71929c3 | 407 | { |
ca0681c9 RH |
408 | tcg_out_sethi(s, ret, arg); |
409 | if (arg & 0x3ff) { | |
410 | tcg_out_arithi(s, ret, ret, arg & 0x3ff, ARITH_OR); | |
c71929c3 RH |
411 | } |
412 | } | |
413 | ||
ab20bdc1 | 414 | static void tcg_out_movi_int(TCGContext *s, TCGType type, TCGReg ret, |
92840d06 RH |
415 | tcg_target_long arg, bool in_prologue, |
416 | TCGReg scratch) | |
8289b279 | 417 | { |
425532d7 | 418 | tcg_target_long hi, lo = (int32_t)arg; |
ab20bdc1 | 419 | tcg_target_long test, lsb; |
a9c7d27b RH |
420 | |
421 | /* A 13-bit constant sign-extended to 64-bits. */ | |
422 | if (check_fit_tl(arg, 13)) { | |
8b14f862 | 423 | tcg_out_movi_s13(s, ret, arg); |
a9c7d27b | 424 | return; |
8289b279 | 425 | } |
8289b279 | 426 | |
ca0681c9 RH |
427 | /* A 32-bit constant, or 32-bit zero-extended to 64-bits. */ |
428 | if (type == TCG_TYPE_I32 || arg == (uint32_t)arg) { | |
2cb3f794 | 429 | tcg_out_movi_u32(s, ret, arg); |
ca0681c9 RH |
430 | return; |
431 | } | |
432 | ||
f6823cbe | 433 | /* A 13-bit constant relative to the TB. */ |
1e42b4f8 | 434 | if (!in_prologue) { |
47c2206b | 435 | test = tcg_tbrel_diff(s, (void *)arg); |
f6823cbe RH |
436 | if (check_fit_ptr(test, 13)) { |
437 | tcg_out_arithi(s, ret, TCG_REG_TB, test, ARITH_ADD); | |
438 | return; | |
439 | } | |
440 | } | |
441 | ||
a9c7d27b | 442 | /* A 32-bit constant sign-extended to 64-bits. */ |
425532d7 | 443 | if (arg == lo) { |
1a42d9d4 | 444 | tcg_out_movi_s32(s, ret, arg); |
a9c7d27b RH |
445 | return; |
446 | } | |
447 | ||
684db2a0 | 448 | /* A 32-bit constant, shifted. */ |
ab20bdc1 RH |
449 | lsb = ctz64(arg); |
450 | test = (tcg_target_long)arg >> lsb; | |
684db2a0 | 451 | if (lsb > 10 && test == extract64(test, 0, 21)) { |
ab20bdc1 RH |
452 | tcg_out_sethi(s, ret, test << 10); |
453 | tcg_out_arithi(s, ret, ret, lsb - 10, SHIFT_SLLX); | |
454 | return; | |
684db2a0 RH |
455 | } else if (test == (uint32_t)test || test == (int32_t)test) { |
456 | tcg_out_movi_int(s, TCG_TYPE_I64, ret, test, in_prologue, scratch); | |
457 | tcg_out_arithi(s, ret, ret, lsb, SHIFT_SLLX); | |
458 | return; | |
ab20bdc1 RH |
459 | } |
460 | ||
c834b8d8 | 461 | /* Use the constant pool, if possible. */ |
1e42b4f8 | 462 | if (!in_prologue) { |
c834b8d8 RH |
463 | new_pool_label(s, arg, R_SPARC_13, s->code_ptr, |
464 | tcg_tbrel_diff(s, NULL)); | |
465 | tcg_out32(s, LDX | INSN_RD(ret) | INSN_RS1(TCG_REG_TB)); | |
466 | return; | |
467 | } | |
468 | ||
a9c7d27b | 469 | /* A 64-bit constant decomposed into 2 32-bit pieces. */ |
425532d7 | 470 | if (check_fit_i32(lo, 13)) { |
34b1a49c | 471 | hi = (arg - lo) >> 32; |
2cb3f794 | 472 | tcg_out_movi_u32(s, ret, hi); |
a9c7d27b RH |
473 | tcg_out_arithi(s, ret, ret, 32, SHIFT_SLLX); |
474 | tcg_out_arithi(s, ret, ret, lo, ARITH_ADD); | |
43172207 | 475 | } else { |
34b1a49c | 476 | hi = arg >> 32; |
2cb3f794 RH |
477 | tcg_out_movi_u32(s, ret, hi); |
478 | tcg_out_movi_u32(s, scratch, lo); | |
375816f8 | 479 | tcg_out_arithi(s, ret, ret, 32, SHIFT_SLLX); |
92840d06 | 480 | tcg_out_arith(s, ret, ret, scratch, ARITH_OR); |
6f41b777 | 481 | } |
b101234a BS |
482 | } |
483 | ||
897fd616 RH |
484 | static void tcg_out_movi(TCGContext *s, TCGType type, |
485 | TCGReg ret, tcg_target_long arg) | |
ab20bdc1 | 486 | { |
33982b89 RH |
487 | tcg_debug_assert(ret != TCG_REG_T3); |
488 | tcg_out_movi_int(s, type, ret, arg, false, TCG_REG_T3); | |
ab20bdc1 RH |
489 | } |
490 | ||
678155b2 RH |
491 | static void tcg_out_ext8s(TCGContext *s, TCGType type, TCGReg rd, TCGReg rs) |
492 | { | |
493 | g_assert_not_reached(); | |
494 | } | |
495 | ||
753e42ea RH |
496 | static void tcg_out_ext16s(TCGContext *s, TCGType type, TCGReg rd, TCGReg rs) |
497 | { | |
498 | g_assert_not_reached(); | |
499 | } | |
500 | ||
d0e66c89 RH |
501 | static void tcg_out_ext8u(TCGContext *s, TCGReg rd, TCGReg rs) |
502 | { | |
503 | tcg_out_arithi(s, rd, rs, 0xff, ARITH_AND); | |
504 | } | |
505 | ||
379afdff RH |
506 | static void tcg_out_ext16u(TCGContext *s, TCGReg rd, TCGReg rs) |
507 | { | |
508 | tcg_out_arithi(s, rd, rs, 16, SHIFT_SLL); | |
509 | tcg_out_arithi(s, rd, rd, 16, SHIFT_SRL); | |
510 | } | |
511 | ||
52bf3398 RH |
512 | static void tcg_out_ext32s(TCGContext *s, TCGReg rd, TCGReg rs) |
513 | { | |
514 | tcg_out_arithi(s, rd, rs, 0, SHIFT_SRA); | |
515 | } | |
516 | ||
9ecf5f61 RH |
517 | static void tcg_out_ext32u(TCGContext *s, TCGReg rd, TCGReg rs) |
518 | { | |
519 | tcg_out_arithi(s, rd, rs, 0, SHIFT_SRL); | |
520 | } | |
521 | ||
9c6aa274 RH |
522 | static void tcg_out_exts_i32_i64(TCGContext *s, TCGReg rd, TCGReg rs) |
523 | { | |
524 | tcg_out_ext32s(s, rd, rs); | |
525 | } | |
526 | ||
b9bfe000 RH |
527 | static void tcg_out_extu_i32_i64(TCGContext *s, TCGReg rd, TCGReg rs) |
528 | { | |
529 | tcg_out_ext32u(s, rd, rs); | |
530 | } | |
531 | ||
767c2503 RH |
532 | static bool tcg_out_xchg(TCGContext *s, TCGType type, TCGReg r1, TCGReg r2) |
533 | { | |
534 | return false; | |
535 | } | |
536 | ||
6a6d772e RH |
537 | static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs, |
538 | tcg_target_long imm) | |
539 | { | |
540 | /* This function is only used for passing structs by reference. */ | |
541 | g_assert_not_reached(); | |
542 | } | |
543 | ||
897fd616 RH |
544 | static void tcg_out_ldst_rr(TCGContext *s, TCGReg data, TCGReg a1, |
545 | TCGReg a2, int op) | |
8289b279 | 546 | { |
a0ce341a | 547 | tcg_out32(s, op | INSN_RD(data) | INSN_RS1(a1) | INSN_RS2(a2)); |
8289b279 BS |
548 | } |
549 | ||
35e2da15 RH |
550 | static void tcg_out_ldst(TCGContext *s, TCGReg ret, TCGReg addr, |
551 | intptr_t offset, int op) | |
8289b279 | 552 | { |
425532d7 | 553 | if (check_fit_ptr(offset, 13)) { |
8289b279 BS |
554 | tcg_out32(s, op | INSN_RD(ret) | INSN_RS1(addr) | |
555 | INSN_IMM13(offset)); | |
a0ce341a | 556 | } else { |
375816f8 RH |
557 | tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_T1, offset); |
558 | tcg_out_ldst_rr(s, ret, addr, TCG_REG_T1, op); | |
cf7c2ca5 | 559 | } |
8289b279 BS |
560 | } |
561 | ||
897fd616 RH |
562 | static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg ret, |
563 | TCGReg arg1, intptr_t arg2) | |
8289b279 | 564 | { |
a0ce341a | 565 | tcg_out_ldst(s, ret, arg1, arg2, (type == TCG_TYPE_I32 ? LDUW : LDX)); |
8289b279 BS |
566 | } |
567 | ||
897fd616 RH |
568 | static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, |
569 | TCGReg arg1, intptr_t arg2) | |
8289b279 | 570 | { |
a0ce341a RH |
571 | tcg_out_ldst(s, arg, arg1, arg2, (type == TCG_TYPE_I32 ? STW : STX)); |
572 | } | |
573 | ||
897fd616 RH |
574 | static bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val, |
575 | TCGReg base, intptr_t ofs) | |
59d7c14e RH |
576 | { |
577 | if (val == 0) { | |
578 | tcg_out_st(s, type, TCG_REG_G0, base, ofs); | |
579 | return true; | |
580 | } | |
581 | return false; | |
582 | } | |
583 | ||
897fd616 | 584 | static void tcg_out_sety(TCGContext *s, TCGReg rs) |
8289b279 | 585 | { |
583d1215 | 586 | tcg_out32(s, WRY | INSN_RS1(TCG_REG_G0) | INSN_RS2(rs)); |
8289b279 BS |
587 | } |
588 | ||
35e2da15 RH |
589 | static void tcg_out_div32(TCGContext *s, TCGReg rd, TCGReg rs1, |
590 | int32_t val2, int val2const, int uns) | |
583d1215 RH |
591 | { |
592 | /* Load Y with the sign/zero extension of RS1 to 64-bits. */ | |
593 | if (uns) { | |
594 | tcg_out_sety(s, TCG_REG_G0); | |
595 | } else { | |
375816f8 RH |
596 | tcg_out_arithi(s, TCG_REG_T1, rs1, 31, SHIFT_SRA); |
597 | tcg_out_sety(s, TCG_REG_T1); | |
583d1215 RH |
598 | } |
599 | ||
600 | tcg_out_arithc(s, rd, rs1, val2, val2const, | |
601 | uns ? ARITH_UDIV : ARITH_SDIV); | |
602 | } | |
603 | ||
0aed257f | 604 | static const uint8_t tcg_cond_to_bcond[] = { |
cf7c2ca5 BS |
605 | [TCG_COND_EQ] = COND_E, |
606 | [TCG_COND_NE] = COND_NE, | |
607 | [TCG_COND_LT] = COND_L, | |
608 | [TCG_COND_GE] = COND_GE, | |
609 | [TCG_COND_LE] = COND_LE, | |
610 | [TCG_COND_GT] = COND_G, | |
611 | [TCG_COND_LTU] = COND_CS, | |
612 | [TCG_COND_GEU] = COND_CC, | |
613 | [TCG_COND_LEU] = COND_LEU, | |
614 | [TCG_COND_GTU] = COND_GU, | |
615 | }; | |
616 | ||
ab1339b9 RH |
617 | static const uint8_t tcg_cond_to_rcond[] = { |
618 | [TCG_COND_EQ] = RCOND_Z, | |
619 | [TCG_COND_NE] = RCOND_NZ, | |
620 | [TCG_COND_LT] = RCOND_LZ, | |
621 | [TCG_COND_GT] = RCOND_GZ, | |
622 | [TCG_COND_LE] = RCOND_LEZ, | |
623 | [TCG_COND_GE] = RCOND_GEZ | |
624 | }; | |
625 | ||
a115f3ea RH |
626 | static void tcg_out_bpcc0(TCGContext *s, int scond, int flags, int off19) |
627 | { | |
628 | tcg_out32(s, INSN_OP(0) | INSN_OP2(1) | INSN_COND(scond) | flags | off19); | |
629 | } | |
630 | ||
bec16311 | 631 | static void tcg_out_bpcc(TCGContext *s, int scond, int flags, TCGLabel *l) |
a115f3ea | 632 | { |
791645f0 | 633 | int off19 = 0; |
a115f3ea RH |
634 | |
635 | if (l->has_value) { | |
abce5964 | 636 | off19 = INSN_OFF19(tcg_pcrel_diff(s, l->u.value_ptr)); |
a115f3ea | 637 | } else { |
bec16311 | 638 | tcg_out_reloc(s, s->code_ptr, R_SPARC_WDISP19, l, 0); |
a115f3ea RH |
639 | } |
640 | tcg_out_bpcc0(s, scond, flags, off19); | |
641 | } | |
642 | ||
35e2da15 | 643 | static void tcg_out_cmp(TCGContext *s, TCGReg c1, int32_t c2, int c2const) |
56f4927e | 644 | { |
ba225198 | 645 | tcg_out_arithc(s, TCG_REG_G0, c1, c2, c2const, ARITH_SUBCC); |
56f4927e RH |
646 | } |
647 | ||
35e2da15 | 648 | static void tcg_out_brcond_i32(TCGContext *s, TCGCond cond, TCGReg arg1, |
bec16311 | 649 | int32_t arg2, int const_arg2, TCGLabel *l) |
cf7c2ca5 | 650 | { |
56f4927e | 651 | tcg_out_cmp(s, arg1, arg2, const_arg2); |
bec16311 | 652 | tcg_out_bpcc(s, tcg_cond_to_bcond[cond], BPCC_ICC | BPCC_PT, l); |
cf7c2ca5 BS |
653 | tcg_out_nop(s); |
654 | } | |
655 | ||
35e2da15 RH |
656 | static void tcg_out_movcc(TCGContext *s, TCGCond cond, int cc, TCGReg ret, |
657 | int32_t v1, int v1const) | |
ded37f0d RH |
658 | { |
659 | tcg_out32(s, ARITH_MOVCC | cc | INSN_RD(ret) | |
660 | | INSN_RS1(tcg_cond_to_bcond[cond]) | |
661 | | (v1const ? INSN_IMM11(v1) : INSN_RS2(v1))); | |
662 | } | |
663 | ||
35e2da15 RH |
664 | static void tcg_out_movcond_i32(TCGContext *s, TCGCond cond, TCGReg ret, |
665 | TCGReg c1, int32_t c2, int c2const, | |
666 | int32_t v1, int v1const) | |
ded37f0d RH |
667 | { |
668 | tcg_out_cmp(s, c1, c2, c2const); | |
669 | tcg_out_movcc(s, cond, MOVCC_ICC, ret, v1, v1const); | |
670 | } | |
671 | ||
35e2da15 | 672 | static void tcg_out_brcond_i64(TCGContext *s, TCGCond cond, TCGReg arg1, |
bec16311 | 673 | int32_t arg2, int const_arg2, TCGLabel *l) |
1da92db2 | 674 | { |
ab1339b9 RH |
675 | /* For 64-bit signed comparisons vs zero, we can avoid the compare. */ |
676 | if (arg2 == 0 && !is_unsigned_cond(cond)) { | |
791645f0 | 677 | int off16 = 0; |
ab1339b9 RH |
678 | |
679 | if (l->has_value) { | |
abce5964 | 680 | off16 = INSN_OFF16(tcg_pcrel_diff(s, l->u.value_ptr)); |
ab1339b9 | 681 | } else { |
bec16311 | 682 | tcg_out_reloc(s, s->code_ptr, R_SPARC_WDISP16, l, 0); |
ab1339b9 RH |
683 | } |
684 | tcg_out32(s, INSN_OP(0) | INSN_OP2(3) | BPR_PT | INSN_RS1(arg1) | |
685 | | INSN_COND(tcg_cond_to_rcond[cond]) | off16); | |
686 | } else { | |
687 | tcg_out_cmp(s, arg1, arg2, const_arg2); | |
bec16311 | 688 | tcg_out_bpcc(s, tcg_cond_to_bcond[cond], BPCC_XCC | BPCC_PT, l); |
ab1339b9 | 689 | } |
1da92db2 BS |
690 | tcg_out_nop(s); |
691 | } | |
ded37f0d | 692 | |
35e2da15 RH |
693 | static void tcg_out_movr(TCGContext *s, TCGCond cond, TCGReg ret, TCGReg c1, |
694 | int32_t v1, int v1const) | |
203342d8 RH |
695 | { |
696 | tcg_out32(s, ARITH_MOVR | INSN_RD(ret) | INSN_RS1(c1) | |
697 | | (tcg_cond_to_rcond[cond] << 10) | |
698 | | (v1const ? INSN_IMM10(v1) : INSN_RS2(v1))); | |
699 | } | |
700 | ||
35e2da15 RH |
701 | static void tcg_out_movcond_i64(TCGContext *s, TCGCond cond, TCGReg ret, |
702 | TCGReg c1, int32_t c2, int c2const, | |
703 | int32_t v1, int v1const) | |
ded37f0d | 704 | { |
203342d8 RH |
705 | /* For 64-bit signed comparisons vs zero, we can avoid the compare. |
706 | Note that the immediate range is one bit smaller, so we must check | |
707 | for that as well. */ | |
708 | if (c2 == 0 && !is_unsigned_cond(cond) | |
35e2da15 | 709 | && (!v1const || check_fit_i32(v1, 10))) { |
203342d8 RH |
710 | tcg_out_movr(s, cond, ret, c1, v1, v1const); |
711 | } else { | |
712 | tcg_out_cmp(s, c1, c2, c2const); | |
713 | tcg_out_movcc(s, cond, MOVCC_XCC, ret, v1, v1const); | |
714 | } | |
ded37f0d | 715 | } |
1da92db2 | 716 | |
35e2da15 | 717 | static void tcg_out_setcond_i32(TCGContext *s, TCGCond cond, TCGReg ret, |
a0fdd7c9 | 718 | TCGReg c1, int32_t c2, int c2const, bool neg) |
dbfe80e1 | 719 | { |
c470b663 | 720 | /* For 32-bit comparisons, we can play games with ADDC/SUBC. */ |
dbfe80e1 | 721 | switch (cond) { |
7d458a75 RH |
722 | case TCG_COND_LTU: |
723 | case TCG_COND_GEU: | |
724 | /* The result of the comparison is in the carry bit. */ | |
725 | break; | |
726 | ||
dbfe80e1 RH |
727 | case TCG_COND_EQ: |
728 | case TCG_COND_NE: | |
7d458a75 | 729 | /* For equality, we can transform to inequality vs zero. */ |
dbfe80e1 | 730 | if (c2 != 0) { |
321b6c05 RH |
731 | tcg_out_arithc(s, TCG_REG_T1, c1, c2, c2const, ARITH_XOR); |
732 | c2 = TCG_REG_T1; | |
733 | } else { | |
734 | c2 = c1; | |
dbfe80e1 | 735 | } |
321b6c05 | 736 | c1 = TCG_REG_G0, c2const = 0; |
7d458a75 | 737 | cond = (cond == TCG_COND_EQ ? TCG_COND_GEU : TCG_COND_LTU); |
dbfe80e1 RH |
738 | break; |
739 | ||
740 | case TCG_COND_GTU: | |
dbfe80e1 | 741 | case TCG_COND_LEU: |
7d458a75 RH |
742 | /* If we don't need to load a constant into a register, we can |
743 | swap the operands on GTU/LEU. There's no benefit to loading | |
744 | the constant into a temporary register. */ | |
745 | if (!c2const || c2 == 0) { | |
35e2da15 | 746 | TCGReg t = c1; |
7d458a75 RH |
747 | c1 = c2; |
748 | c2 = t; | |
749 | c2const = 0; | |
750 | cond = tcg_swap_cond(cond); | |
751 | break; | |
752 | } | |
753 | /* FALLTHRU */ | |
dbfe80e1 RH |
754 | |
755 | default: | |
756 | tcg_out_cmp(s, c1, c2, c2const); | |
8b14f862 | 757 | tcg_out_movi_s13(s, ret, 0); |
a0fdd7c9 | 758 | tcg_out_movcc(s, cond, MOVCC_ICC, ret, neg ? -1 : 1, 1); |
dbfe80e1 RH |
759 | return; |
760 | } | |
761 | ||
762 | tcg_out_cmp(s, c1, c2, c2const); | |
763 | if (cond == TCG_COND_LTU) { | |
a0fdd7c9 RH |
764 | if (neg) { |
765 | /* 0 - 0 - C = -C = (C ? -1 : 0) */ | |
766 | tcg_out_arithi(s, ret, TCG_REG_G0, 0, ARITH_SUBC); | |
767 | } else { | |
768 | /* 0 + 0 + C = C = (C ? 1 : 0) */ | |
769 | tcg_out_arithi(s, ret, TCG_REG_G0, 0, ARITH_ADDC); | |
770 | } | |
dbfe80e1 | 771 | } else { |
a0fdd7c9 RH |
772 | if (neg) { |
773 | /* 0 + -1 + C = C - 1 = (C ? 0 : -1) */ | |
774 | tcg_out_arithi(s, ret, TCG_REG_G0, -1, ARITH_ADDC); | |
775 | } else { | |
776 | /* 0 - -1 - C = 1 - C = (C ? 0 : 1) */ | |
777 | tcg_out_arithi(s, ret, TCG_REG_G0, -1, ARITH_SUBC); | |
778 | } | |
dbfe80e1 RH |
779 | } |
780 | } | |
781 | ||
35e2da15 | 782 | static void tcg_out_setcond_i64(TCGContext *s, TCGCond cond, TCGReg ret, |
a0fdd7c9 | 783 | TCGReg c1, int32_t c2, int c2const, bool neg) |
dbfe80e1 | 784 | { |
a0fdd7c9 | 785 | if (use_vis3_instructions && !neg) { |
9d6a7a85 RH |
786 | switch (cond) { |
787 | case TCG_COND_NE: | |
788 | if (c2 != 0) { | |
789 | break; | |
790 | } | |
791 | c2 = c1, c2const = 0, c1 = TCG_REG_G0; | |
792 | /* FALLTHRU */ | |
793 | case TCG_COND_LTU: | |
794 | tcg_out_cmp(s, c1, c2, c2const); | |
795 | tcg_out_arith(s, ret, TCG_REG_G0, TCG_REG_G0, ARITH_ADDXC); | |
796 | return; | |
797 | default: | |
798 | break; | |
799 | } | |
800 | } | |
801 | ||
203342d8 RH |
802 | /* For 64-bit signed comparisons vs zero, we can avoid the compare |
803 | if the input does not overlap the output. */ | |
804 | if (c2 == 0 && !is_unsigned_cond(cond) && c1 != ret) { | |
8b14f862 | 805 | tcg_out_movi_s13(s, ret, 0); |
a0fdd7c9 | 806 | tcg_out_movr(s, cond, ret, c1, neg ? -1 : 1, 1); |
203342d8 RH |
807 | } else { |
808 | tcg_out_cmp(s, c1, c2, c2const); | |
8b14f862 | 809 | tcg_out_movi_s13(s, ret, 0); |
a0fdd7c9 | 810 | tcg_out_movcc(s, cond, MOVCC_XCC, ret, neg ? -1 : 1, 1); |
203342d8 | 811 | } |
dbfe80e1 | 812 | } |
4ec28e25 | 813 | |
609ac1e1 RH |
814 | static void tcg_out_addsub2_i32(TCGContext *s, TCGReg rl, TCGReg rh, |
815 | TCGReg al, TCGReg ah, int32_t bl, int blconst, | |
816 | int32_t bh, int bhconst, int opl, int oph) | |
4ec28e25 | 817 | { |
35e2da15 | 818 | TCGReg tmp = TCG_REG_T1; |
4ec28e25 RH |
819 | |
820 | /* Note that the low parts are fully consumed before tmp is set. */ | |
821 | if (rl != ah && (bhconst || rl != bh)) { | |
822 | tmp = rl; | |
823 | } | |
824 | ||
825 | tcg_out_arithc(s, tmp, al, bl, blconst, opl); | |
826 | tcg_out_arithc(s, rh, ah, bh, bhconst, oph); | |
827 | tcg_out_mov(s, TCG_TYPE_I32, rl, tmp); | |
828 | } | |
dbfe80e1 | 829 | |
609ac1e1 RH |
830 | static void tcg_out_addsub2_i64(TCGContext *s, TCGReg rl, TCGReg rh, |
831 | TCGReg al, TCGReg ah, int32_t bl, int blconst, | |
832 | int32_t bh, int bhconst, bool is_sub) | |
833 | { | |
834 | TCGReg tmp = TCG_REG_T1; | |
835 | ||
836 | /* Note that the low parts are fully consumed before tmp is set. */ | |
837 | if (rl != ah && (bhconst || rl != bh)) { | |
838 | tmp = rl; | |
839 | } | |
840 | ||
841 | tcg_out_arithc(s, tmp, al, bl, blconst, is_sub ? ARITH_SUBCC : ARITH_ADDCC); | |
842 | ||
90379ca8 RH |
843 | if (use_vis3_instructions && !is_sub) { |
844 | /* Note that ADDXC doesn't accept immediates. */ | |
845 | if (bhconst && bh != 0) { | |
8b14f862 | 846 | tcg_out_movi_s13(s, TCG_REG_T2, bh); |
90379ca8 RH |
847 | bh = TCG_REG_T2; |
848 | } | |
849 | tcg_out_arith(s, rh, ah, bh, ARITH_ADDXC); | |
850 | } else if (bh == TCG_REG_G0) { | |
609ac1e1 RH |
851 | /* If we have a zero, we can perform the operation in two insns, |
852 | with the arithmetic first, and a conditional move into place. */ | |
853 | if (rh == ah) { | |
854 | tcg_out_arithi(s, TCG_REG_T2, ah, 1, | |
855 | is_sub ? ARITH_SUB : ARITH_ADD); | |
856 | tcg_out_movcc(s, TCG_COND_LTU, MOVCC_XCC, rh, TCG_REG_T2, 0); | |
857 | } else { | |
858 | tcg_out_arithi(s, rh, ah, 1, is_sub ? ARITH_SUB : ARITH_ADD); | |
859 | tcg_out_movcc(s, TCG_COND_GEU, MOVCC_XCC, rh, ah, 0); | |
860 | } | |
861 | } else { | |
414399b6 RH |
862 | /* |
863 | * Otherwise adjust BH as if there is carry into T2. | |
864 | * Note that constant BH is constrained to 11 bits for the MOVCC, | |
865 | * so the adjustment fits 12 bits. | |
866 | */ | |
609ac1e1 | 867 | if (bhconst) { |
8b14f862 | 868 | tcg_out_movi_s13(s, TCG_REG_T2, bh + (is_sub ? -1 : 1)); |
609ac1e1 RH |
869 | } else { |
870 | tcg_out_arithi(s, TCG_REG_T2, bh, 1, | |
871 | is_sub ? ARITH_SUB : ARITH_ADD); | |
872 | } | |
873 | /* ... smoosh T2 back to original BH if carry is clear ... */ | |
874 | tcg_out_movcc(s, TCG_COND_GEU, MOVCC_XCC, TCG_REG_T2, bh, bhconst); | |
875 | /* ... and finally perform the arithmetic with the new operand. */ | |
876 | tcg_out_arith(s, rh, ah, TCG_REG_T2, is_sub ? ARITH_SUB : ARITH_ADD); | |
877 | } | |
878 | ||
879 | tcg_out_mov(s, TCG_TYPE_I64, rl, tmp); | |
880 | } | |
881 | ||
e01d60f2 RH |
882 | static void tcg_out_jmpl_const(TCGContext *s, const tcg_insn_unit *dest, |
883 | bool in_prologue, bool tail_call) | |
884 | { | |
885 | uintptr_t desti = (uintptr_t)dest; | |
886 | ||
e01d60f2 | 887 | tcg_out_movi_int(s, TCG_TYPE_PTR, TCG_REG_T1, |
33982b89 | 888 | desti & ~0xfff, in_prologue, TCG_REG_T2); |
e01d60f2 RH |
889 | tcg_out_arithi(s, tail_call ? TCG_REG_G0 : TCG_REG_O7, |
890 | TCG_REG_T1, desti & 0xfff, JMPL); | |
891 | } | |
892 | ||
2be7d76b | 893 | static void tcg_out_call_nodelay(TCGContext *s, const tcg_insn_unit *dest, |
ab20bdc1 | 894 | bool in_prologue) |
aad2f06a | 895 | { |
abce5964 | 896 | ptrdiff_t disp = tcg_pcrel_diff(s, dest); |
aad2f06a RH |
897 | |
898 | if (disp == (int32_t)disp) { | |
899 | tcg_out32(s, CALL | (uint32_t)disp >> 2); | |
900 | } else { | |
e01d60f2 | 901 | tcg_out_jmpl_const(s, dest, in_prologue, false); |
aad2f06a RH |
902 | } |
903 | } | |
904 | ||
cee44b03 RH |
905 | static void tcg_out_call(TCGContext *s, const tcg_insn_unit *dest, |
906 | const TCGHelperInfo *info) | |
4e9cf840 | 907 | { |
ab20bdc1 | 908 | tcg_out_call_nodelay(s, dest, false); |
4e9cf840 RH |
909 | tcg_out_nop(s); |
910 | } | |
911 | ||
f8f03b37 PK |
912 | static void tcg_out_mb(TCGContext *s, TCGArg a0) |
913 | { | |
914 | /* Note that the TCG memory order constants mirror the Sparc MEMBAR. */ | |
915 | tcg_out32(s, MEMBAR | (a0 & TCG_MO_ALL)); | |
916 | } | |
917 | ||
7d551702 | 918 | /* Generate global QEMU prologue and epilogue code */ |
e4d58b41 | 919 | static void tcg_target_qemu_prologue(TCGContext *s) |
b3db8758 | 920 | { |
4c3204cb RH |
921 | int tmp_buf_size, frame_size; |
922 | ||
9defd1bd RH |
923 | /* |
924 | * The TCG temp buffer is at the top of the frame, immediately | |
925 | * below the frame pointer. Use the logical (aligned) offset here; | |
926 | * the stack bias is applied in temp_allocate_frame(). | |
927 | */ | |
4c3204cb | 928 | tmp_buf_size = CPU_TEMP_BUF_NLONGS * (int)sizeof(long); |
9defd1bd | 929 | tcg_set_frame(s, TCG_REG_I6, -tmp_buf_size, tmp_buf_size); |
4c3204cb | 930 | |
9defd1bd RH |
931 | /* |
932 | * TCG_TARGET_CALL_STACK_OFFSET includes the stack bias, but is | |
933 | * otherwise the minimal frame usable by callees. | |
934 | */ | |
4c3204cb RH |
935 | frame_size = TCG_TARGET_CALL_STACK_OFFSET - TCG_TARGET_STACK_BIAS; |
936 | frame_size += TCG_STATIC_CALL_ARGS_SIZE + tmp_buf_size; | |
937 | frame_size += TCG_TARGET_STACK_ALIGN - 1; | |
938 | frame_size &= -TCG_TARGET_STACK_ALIGN; | |
b3db8758 | 939 | tcg_out32(s, SAVE | INSN_RD(TCG_REG_O6) | INSN_RS1(TCG_REG_O6) | |
4c3204cb | 940 | INSN_IMM13(-frame_size)); |
c6f7e4fb | 941 | |
4cbea598 | 942 | #ifndef CONFIG_SOFTMMU |
b76f21a7 | 943 | if (guest_base != 0) { |
92840d06 RH |
944 | tcg_out_movi_int(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, |
945 | guest_base, true, TCG_REG_T1); | |
c6f7e4fb RH |
946 | tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG); |
947 | } | |
948 | #endif | |
949 | ||
ab20bdc1 | 950 | /* We choose TCG_REG_TB such that no move is required. */ |
1e42b4f8 RH |
951 | QEMU_BUILD_BUG_ON(TCG_REG_TB != TCG_REG_I1); |
952 | tcg_regset_set_reg(s->reserved_regs, TCG_REG_TB); | |
ab20bdc1 | 953 | |
aad2f06a | 954 | tcg_out_arithi(s, TCG_REG_G0, TCG_REG_I1, 0, JMPL); |
0c554161 RH |
955 | /* delay slot */ |
956 | tcg_out_nop(s); | |
4c3204cb | 957 | |
38f81dc5 | 958 | /* Epilogue for goto_ptr. */ |
c8bc1168 | 959 | tcg_code_gen_epilogue = tcg_splitwx_to_rx(s->code_ptr); |
38f81dc5 RH |
960 | tcg_out_arithi(s, TCG_REG_G0, TCG_REG_I7, 8, RETURN); |
961 | /* delay slot */ | |
8b14f862 | 962 | tcg_out_movi_s13(s, TCG_REG_O0, 0); |
b3db8758 BS |
963 | } |
964 | ||
9358fbbf RH |
965 | static void tcg_out_tb_start(TCGContext *s) |
966 | { | |
967 | /* nothing to do */ | |
968 | } | |
969 | ||
e9823b4c RH |
970 | static void tcg_out_nop_fill(tcg_insn_unit *p, int count) |
971 | { | |
972 | int i; | |
973 | for (i = 0; i < count; ++i) { | |
974 | p[i] = NOP; | |
975 | } | |
976 | } | |
977 | ||
29086503 RH |
978 | static const TCGLdstHelperParam ldst_helper_param = { |
979 | .ntmp = 1, .tmp = { TCG_REG_T1 } | |
980 | }; | |
a0ce341a | 981 | |
29086503 | 982 | static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) |
a0ce341a | 983 | { |
29086503 RH |
984 | MemOp opc = get_memop(lb->oi); |
985 | MemOp sgn; | |
17ff9f78 | 986 | |
29086503 RH |
987 | if (!patch_reloc(lb->label_ptr[0], R_SPARC_WDISP19, |
988 | (intptr_t)tcg_splitwx_to_rx(s->code_ptr), 0)) { | |
989 | return false; | |
990 | } | |
a0ce341a | 991 | |
29086503 RH |
992 | /* Use inline tcg_out_ext32s; otherwise let the helper sign-extend. */ |
993 | sgn = (opc & MO_SIZE) < MO_32 ? MO_SIGN : 0; | |
17ff9f78 | 994 | |
29086503 RH |
995 | tcg_out_ld_helper_args(s, lb, &ldst_helper_param); |
996 | tcg_out_call(s, qemu_ld_helpers[opc & (MO_SIZE | sgn)], NULL); | |
997 | tcg_out_ld_helper_ret(s, lb, sgn, &ldst_helper_param); | |
17ff9f78 | 998 | |
29086503 RH |
999 | tcg_out_bpcc0(s, COND_A, BPCC_A | BPCC_PT, 0); |
1000 | return patch_reloc(s->code_ptr - 1, R_SPARC_WDISP19, | |
1001 | (intptr_t)lb->raddr, 0); | |
1002 | } | |
a0ce341a | 1003 | |
29086503 RH |
1004 | static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) |
1005 | { | |
1006 | MemOp opc = get_memop(lb->oi); | |
a0ce341a | 1007 | |
29086503 RH |
1008 | if (!patch_reloc(lb->label_ptr[0], R_SPARC_WDISP19, |
1009 | (intptr_t)tcg_splitwx_to_rx(s->code_ptr), 0)) { | |
1010 | return false; | |
a0ce341a | 1011 | } |
9d0efc88 | 1012 | |
29086503 RH |
1013 | tcg_out_st_helper_args(s, lb, &ldst_helper_param); |
1014 | tcg_out_call(s, qemu_st_helpers[opc & MO_SIZE], NULL); | |
eef0d9e7 | 1015 | |
29086503 RH |
1016 | tcg_out_bpcc0(s, COND_A, BPCC_A | BPCC_PT, 0); |
1017 | return patch_reloc(s->code_ptr - 1, R_SPARC_WDISP19, | |
1018 | (intptr_t)lb->raddr, 0); | |
1019 | } | |
eef0d9e7 | 1020 | |
29086503 RH |
1021 | typedef struct { |
1022 | TCGReg base; | |
1023 | TCGReg index; | |
9ca63431 | 1024 | TCGAtomAlign aa; |
29086503 | 1025 | } HostAddress; |
bffe1431 | 1026 | |
7b880107 RH |
1027 | bool tcg_target_has_memory_bswap(MemOp memop) |
1028 | { | |
1029 | return true; | |
1030 | } | |
1031 | ||
d0a9bb5e RH |
1032 | /* We expect to use a 13-bit negative offset from ENV. */ |
1033 | #define MIN_TLB_MASK_TABLE_OFS -(1 << 12) | |
1034 | ||
29086503 | 1035 | /* |
7893e42d PMD |
1036 | * For system-mode, perform the TLB load and compare. |
1037 | * For user-mode, perform any required alignment tests. | |
29086503 RH |
1038 | * In both cases, return a TCGLabelQemuLdst structure if the slow path |
1039 | * is required and fill in @h with the host address for the fast path. | |
1040 | */ | |
1041 | static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h, | |
1042 | TCGReg addr_reg, MemOpIdx oi, | |
1043 | bool is_ld) | |
f5ef6aac | 1044 | { |
40bca78d | 1045 | TCGType addr_type = s->addr_type; |
29086503 RH |
1046 | TCGLabelQemuLdst *ldst = NULL; |
1047 | MemOp opc = get_memop(oi); | |
9ca63431 | 1048 | MemOp s_bits = opc & MO_SIZE; |
29086503 | 1049 | unsigned a_mask; |
321dbde3 | 1050 | |
29086503 | 1051 | /* We don't support unaligned accesses. */ |
9ca63431 RH |
1052 | h->aa = atom_and_align_for_opc(s, opc, MO_ATOM_IFALIGN, false); |
1053 | h->aa.align = MAX(h->aa.align, s_bits); | |
1054 | a_mask = (1u << h->aa.align) - 1; | |
f5ef6aac | 1055 | |
29086503 RH |
1056 | #ifdef CONFIG_SOFTMMU |
1057 | int mem_index = get_mmuidx(oi); | |
d0a9bb5e | 1058 | int fast_off = tlb_mask_table_ofs(s, mem_index); |
29086503 RH |
1059 | int mask_off = fast_off + offsetof(CPUTLBDescFast, mask); |
1060 | int table_off = fast_off + offsetof(CPUTLBDescFast, table); | |
1061 | int cmp_off = is_ld ? offsetof(CPUTLBEntry, addr_read) | |
1062 | : offsetof(CPUTLBEntry, addr_write); | |
1063 | int add_off = offsetof(CPUTLBEntry, addend); | |
1064 | int compare_mask; | |
1065 | int cc; | |
a0ce341a | 1066 | |
29086503 | 1067 | /* Load tlb_mask[mmu_idx] and tlb_table[mmu_idx]. */ |
29086503 RH |
1068 | tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_T2, TCG_AREG0, mask_off); |
1069 | tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_T3, TCG_AREG0, table_off); | |
a0ce341a | 1070 | |
29086503 RH |
1071 | /* Extract the page index, shifted into place for tlb index. */ |
1072 | tcg_out_arithi(s, TCG_REG_T1, addr_reg, | |
aece72b7 | 1073 | s->page_bits - CPU_TLB_ENTRY_BITS, SHIFT_SRL); |
29086503 | 1074 | tcg_out_arith(s, TCG_REG_T1, TCG_REG_T1, TCG_REG_T2, ARITH_AND); |
53c37487 | 1075 | |
29086503 RH |
1076 | /* Add the tlb_table pointer, creating the CPUTLBEntry address into R2. */ |
1077 | tcg_out_arith(s, TCG_REG_T1, TCG_REG_T1, TCG_REG_T3, ARITH_ADD); | |
f5ef6aac | 1078 | |
238f4380 RH |
1079 | /* |
1080 | * Load the tlb comparator and the addend. | |
1081 | * Always load the entire 64-bit comparator for simplicity. | |
1082 | * We will ignore the high bits via BPCC_ICC below. | |
1083 | */ | |
1084 | tcg_out_ld(s, TCG_TYPE_I64, TCG_REG_T2, TCG_REG_T1, cmp_off); | |
29086503 RH |
1085 | tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_T1, TCG_REG_T1, add_off); |
1086 | h->base = TCG_REG_T1; | |
f5ef6aac | 1087 | |
29086503 | 1088 | /* Mask out the page offset, except for the required alignment. */ |
aece72b7 | 1089 | compare_mask = s->page_mask | a_mask; |
29086503 RH |
1090 | if (check_fit_tl(compare_mask, 13)) { |
1091 | tcg_out_arithi(s, TCG_REG_T3, addr_reg, compare_mask, ARITH_AND); | |
7ea5d725 | 1092 | } else { |
29086503 RH |
1093 | tcg_out_movi_s32(s, TCG_REG_T3, compare_mask); |
1094 | tcg_out_arith(s, TCG_REG_T3, addr_reg, TCG_REG_T3, ARITH_AND); | |
7ea5d725 | 1095 | } |
29086503 | 1096 | tcg_out_cmp(s, TCG_REG_T2, TCG_REG_T3, 0); |
3a5f6805 | 1097 | |
29086503 RH |
1098 | ldst = new_ldst_label(s); |
1099 | ldst->is_ld = is_ld; | |
1100 | ldst->oi = oi; | |
1101 | ldst->addrlo_reg = addr_reg; | |
1102 | ldst->label_ptr[0] = s->code_ptr; | |
f5ef6aac | 1103 | |
29086503 | 1104 | /* bne,pn %[xi]cc, label0 */ |
40bca78d | 1105 | cc = addr_type == TCG_TYPE_I32 ? BPCC_ICC : BPCC_XCC; |
29086503 | 1106 | tcg_out_bpcc0(s, COND_NE, BPCC_PN | cc, 0); |
90cbed46 | 1107 | #else |
9ca63431 RH |
1108 | /* |
1109 | * If the size equals the required alignment, we can skip the test | |
1110 | * and allow host SIGBUS to deliver SIGBUS to the guest. | |
1111 | * Otherwise, test for at least natural alignment and defer | |
1112 | * everything else to the helper functions. | |
1113 | */ | |
1114 | if (s_bits != get_alignment_bits(opc)) { | |
29086503 RH |
1115 | tcg_debug_assert(check_fit_tl(a_mask, 13)); |
1116 | tcg_out_arithi(s, TCG_REG_G0, addr_reg, a_mask, ARITH_ANDCC); | |
321dbde3 | 1117 | |
29086503 RH |
1118 | ldst = new_ldst_label(s); |
1119 | ldst->is_ld = is_ld; | |
1120 | ldst->oi = oi; | |
1121 | ldst->addrlo_reg = addr_reg; | |
1122 | ldst->label_ptr[0] = s->code_ptr; | |
321dbde3 | 1123 | |
29086503 RH |
1124 | /* bne,pn %icc, label0 */ |
1125 | tcg_out_bpcc0(s, COND_NE, BPCC_PN | BPCC_ICC, 0); | |
321dbde3 | 1126 | } |
29086503 RH |
1127 | h->base = guest_base ? TCG_GUEST_BASE_REG : TCG_REG_G0; |
1128 | #endif | |
321dbde3 | 1129 | |
29086503 | 1130 | /* If the guest address must be zero-extended, do in the delay slot. */ |
40bca78d | 1131 | if (addr_type == TCG_TYPE_I32) { |
29086503 RH |
1132 | tcg_out_ext32u(s, TCG_REG_T2, addr_reg); |
1133 | h->index = TCG_REG_T2; | |
321dbde3 | 1134 | } else { |
29086503 RH |
1135 | if (ldst) { |
1136 | tcg_out_nop(s); | |
321dbde3 | 1137 | } |
29086503 | 1138 | h->index = addr_reg; |
321dbde3 | 1139 | } |
29086503 RH |
1140 | return ldst; |
1141 | } | |
321dbde3 | 1142 | |
29086503 RH |
1143 | static void tcg_out_qemu_ld(TCGContext *s, TCGReg data, TCGReg addr, |
1144 | MemOpIdx oi, TCGType data_type) | |
1145 | { | |
1146 | static const int ld_opc[(MO_SSIZE | MO_BSWAP) + 1] = { | |
1147 | [MO_UB] = LDUB, | |
1148 | [MO_SB] = LDSB, | |
1149 | [MO_UB | MO_LE] = LDUB, | |
1150 | [MO_SB | MO_LE] = LDSB, | |
1151 | ||
1152 | [MO_BEUW] = LDUH, | |
1153 | [MO_BESW] = LDSH, | |
1154 | [MO_BEUL] = LDUW, | |
1155 | [MO_BESL] = LDSW, | |
1156 | [MO_BEUQ] = LDX, | |
1157 | [MO_BESQ] = LDX, | |
1158 | ||
1159 | [MO_LEUW] = LDUH_LE, | |
1160 | [MO_LESW] = LDSH_LE, | |
1161 | [MO_LEUL] = LDUW_LE, | |
1162 | [MO_LESL] = LDSW_LE, | |
1163 | [MO_LEUQ] = LDX_LE, | |
1164 | [MO_LESQ] = LDX_LE, | |
1165 | }; | |
1166 | ||
1167 | TCGLabelQemuLdst *ldst; | |
1168 | HostAddress h; | |
1169 | ||
1170 | ldst = prepare_host_addr(s, &h, addr, oi, true); | |
1171 | ||
1172 | tcg_out_ldst_rr(s, data, h.base, h.index, | |
1173 | ld_opc[get_memop(oi) & (MO_BSWAP | MO_SSIZE)]); | |
1174 | ||
1175 | if (ldst) { | |
1176 | ldst->type = data_type; | |
1177 | ldst->datalo_reg = data; | |
1178 | ldst->raddr = tcg_splitwx_to_rx(s->code_ptr); | |
1179 | } | |
f5ef6aac BS |
1180 | } |
1181 | ||
34b1a49c | 1182 | static void tcg_out_qemu_st(TCGContext *s, TCGReg data, TCGReg addr, |
b3dfd5fc | 1183 | MemOpIdx oi, TCGType data_type) |
f5ef6aac | 1184 | { |
29086503 RH |
1185 | static const int st_opc[(MO_SIZE | MO_BSWAP) + 1] = { |
1186 | [MO_UB] = STB, | |
321dbde3 | 1187 | |
29086503 RH |
1188 | [MO_BEUW] = STH, |
1189 | [MO_BEUL] = STW, | |
1190 | [MO_BEUQ] = STX, | |
a0ce341a | 1191 | |
29086503 RH |
1192 | [MO_LEUW] = STH_LE, |
1193 | [MO_LEUL] = STW_LE, | |
1194 | [MO_LEUQ] = STX_LE, | |
1195 | }; | |
a0ce341a | 1196 | |
29086503 RH |
1197 | TCGLabelQemuLdst *ldst; |
1198 | HostAddress h; | |
53c37487 | 1199 | |
29086503 | 1200 | ldst = prepare_host_addr(s, &h, addr, oi, false); |
f5ef6aac | 1201 | |
29086503 RH |
1202 | tcg_out_ldst_rr(s, data, h.base, h.index, |
1203 | st_opc[get_memop(oi) & (MO_BSWAP | MO_SIZE)]); | |
321dbde3 | 1204 | |
29086503 RH |
1205 | if (ldst) { |
1206 | ldst->type = data_type; | |
1207 | ldst->datalo_reg = data; | |
1208 | ldst->raddr = tcg_splitwx_to_rx(s->code_ptr); | |
321dbde3 | 1209 | } |
f5ef6aac BS |
1210 | } |
1211 | ||
b55a8d9d RH |
1212 | static void tcg_out_exit_tb(TCGContext *s, uintptr_t a0) |
1213 | { | |
1214 | if (check_fit_ptr(a0, 13)) { | |
1215 | tcg_out_arithi(s, TCG_REG_G0, TCG_REG_I7, 8, RETURN); | |
8b14f862 | 1216 | tcg_out_movi_s13(s, TCG_REG_O0, a0); |
b55a8d9d | 1217 | return; |
1e42b4f8 | 1218 | } else { |
b55a8d9d RH |
1219 | intptr_t tb_diff = tcg_tbrel_diff(s, (void *)a0); |
1220 | if (check_fit_ptr(tb_diff, 13)) { | |
1221 | tcg_out_arithi(s, TCG_REG_G0, TCG_REG_I7, 8, RETURN); | |
1222 | /* Note that TCG_REG_TB has been unwound to O1. */ | |
1223 | tcg_out_arithi(s, TCG_REG_O0, TCG_REG_O1, tb_diff, ARITH_ADD); | |
1224 | return; | |
1225 | } | |
1226 | } | |
1227 | tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_I0, a0 & ~0x3ff); | |
1228 | tcg_out_arithi(s, TCG_REG_G0, TCG_REG_I7, 8, RETURN); | |
1229 | tcg_out_arithi(s, TCG_REG_O0, TCG_REG_O0, a0 & 0x3ff, ARITH_OR); | |
1230 | } | |
1231 | ||
cf7d6b8e RH |
1232 | static void tcg_out_goto_tb(TCGContext *s, int which) |
1233 | { | |
a228ae3e | 1234 | ptrdiff_t off = tcg_tbrel_diff(s, (void *)get_jmp_target_addr(s, which)); |
1e42b4f8 | 1235 | |
1ffbe5d6 | 1236 | /* Load link and indirect branch. */ |
1e42b4f8 | 1237 | set_jmp_insn_offset(s, which); |
a228ae3e | 1238 | tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TB, TCG_REG_TB, off); |
1ffbe5d6 RH |
1239 | tcg_out_arithi(s, TCG_REG_G0, TCG_REG_TB, 0, JMPL); |
1240 | /* delay slot */ | |
1241 | tcg_out_nop(s); | |
cf7d6b8e RH |
1242 | set_jmp_reset_offset(s, which); |
1243 | ||
1244 | /* | |
1245 | * For the unlinked path of goto_tb, we need to reset TCG_REG_TB | |
1246 | * to the beginning of this TB. | |
1247 | */ | |
a228ae3e RH |
1248 | off = -tcg_current_code_size(s); |
1249 | if (check_fit_i32(off, 13)) { | |
1250 | tcg_out_arithi(s, TCG_REG_TB, TCG_REG_TB, off, ARITH_ADD); | |
1e42b4f8 | 1251 | } else { |
a228ae3e | 1252 | tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_T1, off); |
1e42b4f8 | 1253 | tcg_out_arith(s, TCG_REG_TB, TCG_REG_TB, TCG_REG_T1, ARITH_ADD); |
cf7d6b8e RH |
1254 | } |
1255 | } | |
1256 | ||
a228ae3e RH |
1257 | void tb_target_set_jmp_target(const TranslationBlock *tb, int n, |
1258 | uintptr_t jmp_rx, uintptr_t jmp_rw) | |
1259 | { | |
a228ae3e RH |
1260 | } |
1261 | ||
b357f902 RH |
1262 | static void tcg_out_op(TCGContext *s, TCGOpcode opc, |
1263 | const TCGArg args[TCG_MAX_OP_ARGS], | |
1264 | const int const_args[TCG_MAX_OP_ARGS]) | |
8289b279 | 1265 | { |
b357f902 RH |
1266 | TCGArg a0, a1, a2; |
1267 | int c, c2; | |
1268 | ||
1269 | /* Hoist the loads of the most common arguments. */ | |
1270 | a0 = args[0]; | |
1271 | a1 = args[1]; | |
1272 | a2 = args[2]; | |
1273 | c2 = const_args[2]; | |
8289b279 BS |
1274 | |
1275 | switch (opc) { | |
38f81dc5 RH |
1276 | case INDEX_op_goto_ptr: |
1277 | tcg_out_arithi(s, TCG_REG_G0, a0, 0, JMPL); | |
1e42b4f8 | 1278 | tcg_out_mov_delay(s, TCG_REG_TB, a0); |
38f81dc5 | 1279 | break; |
8289b279 | 1280 | case INDEX_op_br: |
bec16311 | 1281 | tcg_out_bpcc(s, COND_A, BPCC_PT, arg_label(a0)); |
f5ef6aac | 1282 | tcg_out_nop(s); |
8289b279 | 1283 | break; |
8289b279 | 1284 | |
8289b279 | 1285 | #define OP_32_64(x) \ |
ba225198 RH |
1286 | glue(glue(case INDEX_op_, x), _i32): \ |
1287 | glue(glue(case INDEX_op_, x), _i64) | |
34b1a49c | 1288 | |
ba225198 | 1289 | OP_32_64(ld8u): |
b357f902 | 1290 | tcg_out_ldst(s, a0, a1, a2, LDUB); |
8289b279 | 1291 | break; |
ba225198 | 1292 | OP_32_64(ld8s): |
b357f902 | 1293 | tcg_out_ldst(s, a0, a1, a2, LDSB); |
8289b279 | 1294 | break; |
ba225198 | 1295 | OP_32_64(ld16u): |
b357f902 | 1296 | tcg_out_ldst(s, a0, a1, a2, LDUH); |
8289b279 | 1297 | break; |
ba225198 | 1298 | OP_32_64(ld16s): |
b357f902 | 1299 | tcg_out_ldst(s, a0, a1, a2, LDSH); |
8289b279 BS |
1300 | break; |
1301 | case INDEX_op_ld_i32: | |
53cd9273 | 1302 | case INDEX_op_ld32u_i64: |
b357f902 | 1303 | tcg_out_ldst(s, a0, a1, a2, LDUW); |
8289b279 | 1304 | break; |
ba225198 | 1305 | OP_32_64(st8): |
b357f902 | 1306 | tcg_out_ldst(s, a0, a1, a2, STB); |
8289b279 | 1307 | break; |
ba225198 | 1308 | OP_32_64(st16): |
b357f902 | 1309 | tcg_out_ldst(s, a0, a1, a2, STH); |
8289b279 BS |
1310 | break; |
1311 | case INDEX_op_st_i32: | |
53cd9273 | 1312 | case INDEX_op_st32_i64: |
b357f902 | 1313 | tcg_out_ldst(s, a0, a1, a2, STW); |
8289b279 | 1314 | break; |
ba225198 | 1315 | OP_32_64(add): |
53cd9273 | 1316 | c = ARITH_ADD; |
ba225198 RH |
1317 | goto gen_arith; |
1318 | OP_32_64(sub): | |
8289b279 | 1319 | c = ARITH_SUB; |
ba225198 RH |
1320 | goto gen_arith; |
1321 | OP_32_64(and): | |
8289b279 | 1322 | c = ARITH_AND; |
ba225198 | 1323 | goto gen_arith; |
dc69960d RH |
1324 | OP_32_64(andc): |
1325 | c = ARITH_ANDN; | |
1326 | goto gen_arith; | |
ba225198 | 1327 | OP_32_64(or): |
8289b279 | 1328 | c = ARITH_OR; |
ba225198 | 1329 | goto gen_arith; |
18c8f7a3 RH |
1330 | OP_32_64(orc): |
1331 | c = ARITH_ORN; | |
1332 | goto gen_arith; | |
ba225198 | 1333 | OP_32_64(xor): |
8289b279 | 1334 | c = ARITH_XOR; |
ba225198 | 1335 | goto gen_arith; |
8289b279 BS |
1336 | case INDEX_op_shl_i32: |
1337 | c = SHIFT_SLL; | |
1fd95946 RH |
1338 | do_shift32: |
1339 | /* Limit immediate shift count lest we create an illegal insn. */ | |
b357f902 | 1340 | tcg_out_arithc(s, a0, a1, a2 & 31, c2, c); |
1fd95946 | 1341 | break; |
8289b279 BS |
1342 | case INDEX_op_shr_i32: |
1343 | c = SHIFT_SRL; | |
1fd95946 | 1344 | goto do_shift32; |
8289b279 BS |
1345 | case INDEX_op_sar_i32: |
1346 | c = SHIFT_SRA; | |
1fd95946 | 1347 | goto do_shift32; |
8289b279 BS |
1348 | case INDEX_op_mul_i32: |
1349 | c = ARITH_UMUL; | |
ba225198 | 1350 | goto gen_arith; |
583d1215 | 1351 | |
4b5a85c1 RH |
1352 | OP_32_64(neg): |
1353 | c = ARITH_SUB; | |
1354 | goto gen_arith1; | |
be6551b1 RH |
1355 | OP_32_64(not): |
1356 | c = ARITH_ORN; | |
1357 | goto gen_arith1; | |
4b5a85c1 | 1358 | |
583d1215 | 1359 | case INDEX_op_div_i32: |
b357f902 | 1360 | tcg_out_div32(s, a0, a1, a2, c2, 0); |
583d1215 RH |
1361 | break; |
1362 | case INDEX_op_divu_i32: | |
b357f902 | 1363 | tcg_out_div32(s, a0, a1, a2, c2, 1); |
583d1215 RH |
1364 | break; |
1365 | ||
8289b279 | 1366 | case INDEX_op_brcond_i32: |
bec16311 | 1367 | tcg_out_brcond_i32(s, a2, a0, a1, const_args[1], arg_label(args[3])); |
8289b279 | 1368 | break; |
dbfe80e1 | 1369 | case INDEX_op_setcond_i32: |
a0fdd7c9 RH |
1370 | tcg_out_setcond_i32(s, args[3], a0, a1, a2, c2, false); |
1371 | break; | |
1372 | case INDEX_op_negsetcond_i32: | |
1373 | tcg_out_setcond_i32(s, args[3], a0, a1, a2, c2, true); | |
dbfe80e1 | 1374 | break; |
ded37f0d | 1375 | case INDEX_op_movcond_i32: |
b357f902 | 1376 | tcg_out_movcond_i32(s, args[5], a0, a1, a2, c2, args[3], const_args[3]); |
ded37f0d | 1377 | break; |
dbfe80e1 | 1378 | |
7a3766f3 | 1379 | case INDEX_op_add2_i32: |
609ac1e1 RH |
1380 | tcg_out_addsub2_i32(s, args[0], args[1], args[2], args[3], |
1381 | args[4], const_args[4], args[5], const_args[5], | |
c470b663 | 1382 | ARITH_ADDCC, ARITH_ADDC); |
7a3766f3 RH |
1383 | break; |
1384 | case INDEX_op_sub2_i32: | |
609ac1e1 RH |
1385 | tcg_out_addsub2_i32(s, args[0], args[1], args[2], args[3], |
1386 | args[4], const_args[4], args[5], const_args[5], | |
c470b663 | 1387 | ARITH_SUBCC, ARITH_SUBC); |
7a3766f3 RH |
1388 | break; |
1389 | case INDEX_op_mulu2_i32: | |
f4c16661 RH |
1390 | c = ARITH_UMUL; |
1391 | goto do_mul2; | |
1392 | case INDEX_op_muls2_i32: | |
1393 | c = ARITH_SMUL; | |
1394 | do_mul2: | |
3a5f6805 | 1395 | /* The 32-bit multiply insns produce a full 64-bit result. */ |
b357f902 | 1396 | tcg_out_arithc(s, a0, a2, args[3], const_args[3], c); |
3a5f6805 | 1397 | tcg_out_arithi(s, a1, a0, 32, SHIFT_SRLX); |
7a3766f3 | 1398 | break; |
8289b279 | 1399 | |
fecccfcc RH |
1400 | case INDEX_op_qemu_ld_a32_i32: |
1401 | case INDEX_op_qemu_ld_a64_i32: | |
e2adae3f | 1402 | tcg_out_qemu_ld(s, a0, a1, a2, TCG_TYPE_I32); |
8289b279 | 1403 | break; |
fecccfcc RH |
1404 | case INDEX_op_qemu_ld_a32_i64: |
1405 | case INDEX_op_qemu_ld_a64_i64: | |
e2adae3f | 1406 | tcg_out_qemu_ld(s, a0, a1, a2, TCG_TYPE_I64); |
8289b279 | 1407 | break; |
fecccfcc RH |
1408 | case INDEX_op_qemu_st_a32_i32: |
1409 | case INDEX_op_qemu_st_a64_i32: | |
b3dfd5fc RH |
1410 | tcg_out_qemu_st(s, a0, a1, a2, TCG_TYPE_I32); |
1411 | break; | |
fecccfcc RH |
1412 | case INDEX_op_qemu_st_a32_i64: |
1413 | case INDEX_op_qemu_st_a64_i64: | |
b3dfd5fc | 1414 | tcg_out_qemu_st(s, a0, a1, a2, TCG_TYPE_I64); |
a0ce341a | 1415 | break; |
8289b279 | 1416 | |
53cd9273 | 1417 | case INDEX_op_ld32s_i64: |
b357f902 | 1418 | tcg_out_ldst(s, a0, a1, a2, LDSW); |
53cd9273 | 1419 | break; |
8289b279 | 1420 | case INDEX_op_ld_i64: |
b357f902 | 1421 | tcg_out_ldst(s, a0, a1, a2, LDX); |
8289b279 BS |
1422 | break; |
1423 | case INDEX_op_st_i64: | |
b357f902 | 1424 | tcg_out_ldst(s, a0, a1, a2, STX); |
8289b279 BS |
1425 | break; |
1426 | case INDEX_op_shl_i64: | |
1427 | c = SHIFT_SLLX; | |
1fd95946 RH |
1428 | do_shift64: |
1429 | /* Limit immediate shift count lest we create an illegal insn. */ | |
b357f902 | 1430 | tcg_out_arithc(s, a0, a1, a2 & 63, c2, c); |
1fd95946 | 1431 | break; |
8289b279 BS |
1432 | case INDEX_op_shr_i64: |
1433 | c = SHIFT_SRLX; | |
1fd95946 | 1434 | goto do_shift64; |
8289b279 BS |
1435 | case INDEX_op_sar_i64: |
1436 | c = SHIFT_SRAX; | |
1fd95946 | 1437 | goto do_shift64; |
8289b279 BS |
1438 | case INDEX_op_mul_i64: |
1439 | c = ARITH_MULX; | |
ba225198 | 1440 | goto gen_arith; |
583d1215 | 1441 | case INDEX_op_div_i64: |
53cd9273 | 1442 | c = ARITH_SDIVX; |
ba225198 | 1443 | goto gen_arith; |
583d1215 | 1444 | case INDEX_op_divu_i64: |
8289b279 | 1445 | c = ARITH_UDIVX; |
ba225198 | 1446 | goto gen_arith; |
8289b279 BS |
1447 | |
1448 | case INDEX_op_brcond_i64: | |
bec16311 | 1449 | tcg_out_brcond_i64(s, a2, a0, a1, const_args[1], arg_label(args[3])); |
8289b279 | 1450 | break; |
dbfe80e1 | 1451 | case INDEX_op_setcond_i64: |
a0fdd7c9 RH |
1452 | tcg_out_setcond_i64(s, args[3], a0, a1, a2, c2, false); |
1453 | break; | |
1454 | case INDEX_op_negsetcond_i64: | |
1455 | tcg_out_setcond_i64(s, args[3], a0, a1, a2, c2, true); | |
dbfe80e1 | 1456 | break; |
ded37f0d | 1457 | case INDEX_op_movcond_i64: |
b357f902 | 1458 | tcg_out_movcond_i64(s, args[5], a0, a1, a2, c2, args[3], const_args[3]); |
ded37f0d | 1459 | break; |
609ac1e1 RH |
1460 | case INDEX_op_add2_i64: |
1461 | tcg_out_addsub2_i64(s, args[0], args[1], args[2], args[3], args[4], | |
1462 | const_args[4], args[5], const_args[5], false); | |
1463 | break; | |
1464 | case INDEX_op_sub2_i64: | |
1465 | tcg_out_addsub2_i64(s, args[0], args[1], args[2], args[3], args[4], | |
1466 | const_args[4], args[5], const_args[5], true); | |
1467 | break; | |
de8301e5 RH |
1468 | case INDEX_op_muluh_i64: |
1469 | tcg_out_arith(s, args[0], args[1], args[2], ARITH_UMULXHI); | |
1470 | break; | |
34b1a49c | 1471 | |
ba225198 | 1472 | gen_arith: |
b357f902 | 1473 | tcg_out_arithc(s, a0, a1, a2, c2, c); |
53cd9273 BS |
1474 | break; |
1475 | ||
4b5a85c1 | 1476 | gen_arith1: |
b357f902 | 1477 | tcg_out_arithc(s, a0, TCG_REG_G0, a1, const_args[1], c); |
4b5a85c1 RH |
1478 | break; |
1479 | ||
f8f03b37 PK |
1480 | case INDEX_op_mb: |
1481 | tcg_out_mb(s, a0); | |
1482 | break; | |
1483 | ||
96d0ee7f | 1484 | case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ |
98b90bab | 1485 | case INDEX_op_mov_i64: |
96d0ee7f | 1486 | case INDEX_op_call: /* Always emitted via tcg_out_call. */ |
b55a8d9d | 1487 | case INDEX_op_exit_tb: /* Always emitted via tcg_out_exit_tb. */ |
cf7d6b8e | 1488 | case INDEX_op_goto_tb: /* Always emitted via tcg_out_goto_tb. */ |
678155b2 RH |
1489 | case INDEX_op_ext8s_i32: /* Always emitted via tcg_reg_alloc_op. */ |
1490 | case INDEX_op_ext8s_i64: | |
d0e66c89 RH |
1491 | case INDEX_op_ext8u_i32: |
1492 | case INDEX_op_ext8u_i64: | |
753e42ea RH |
1493 | case INDEX_op_ext16s_i32: |
1494 | case INDEX_op_ext16s_i64: | |
379afdff RH |
1495 | case INDEX_op_ext16u_i32: |
1496 | case INDEX_op_ext16u_i64: | |
52bf3398 | 1497 | case INDEX_op_ext32s_i64: |
9ecf5f61 | 1498 | case INDEX_op_ext32u_i64: |
9c6aa274 | 1499 | case INDEX_op_ext_i32_i64: |
b9bfe000 | 1500 | case INDEX_op_extu_i32_i64: |
8289b279 | 1501 | default: |
732e89f4 | 1502 | g_assert_not_reached(); |
8289b279 BS |
1503 | } |
1504 | } | |
1505 | ||
0d11dc7c | 1506 | static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) |
f69d277e | 1507 | { |
9be44a16 RH |
1508 | switch (op) { |
1509 | case INDEX_op_goto_ptr: | |
0d11dc7c | 1510 | return C_O0_I1(r); |
f69d277e | 1511 | |
9be44a16 | 1512 | case INDEX_op_ld8u_i32: |
a59a2931 | 1513 | case INDEX_op_ld8u_i64: |
9be44a16 | 1514 | case INDEX_op_ld8s_i32: |
a59a2931 | 1515 | case INDEX_op_ld8s_i64: |
9be44a16 | 1516 | case INDEX_op_ld16u_i32: |
a59a2931 | 1517 | case INDEX_op_ld16u_i64: |
9be44a16 | 1518 | case INDEX_op_ld16s_i32: |
a59a2931 | 1519 | case INDEX_op_ld16s_i64: |
9be44a16 | 1520 | case INDEX_op_ld_i32: |
a59a2931 RH |
1521 | case INDEX_op_ld32u_i64: |
1522 | case INDEX_op_ld32s_i64: | |
1523 | case INDEX_op_ld_i64: | |
9be44a16 | 1524 | case INDEX_op_neg_i32: |
a59a2931 | 1525 | case INDEX_op_neg_i64: |
9be44a16 | 1526 | case INDEX_op_not_i32: |
a59a2931 RH |
1527 | case INDEX_op_not_i64: |
1528 | case INDEX_op_ext32s_i64: | |
1529 | case INDEX_op_ext32u_i64: | |
1530 | case INDEX_op_ext_i32_i64: | |
1531 | case INDEX_op_extu_i32_i64: | |
fecccfcc RH |
1532 | case INDEX_op_qemu_ld_a32_i32: |
1533 | case INDEX_op_qemu_ld_a64_i32: | |
1534 | case INDEX_op_qemu_ld_a32_i64: | |
1535 | case INDEX_op_qemu_ld_a64_i64: | |
0d11dc7c | 1536 | return C_O1_I1(r, r); |
9be44a16 RH |
1537 | |
1538 | case INDEX_op_st8_i32: | |
a59a2931 | 1539 | case INDEX_op_st8_i64: |
9be44a16 | 1540 | case INDEX_op_st16_i32: |
a59a2931 | 1541 | case INDEX_op_st16_i64: |
9be44a16 | 1542 | case INDEX_op_st_i32: |
a59a2931 RH |
1543 | case INDEX_op_st32_i64: |
1544 | case INDEX_op_st_i64: | |
fecccfcc RH |
1545 | case INDEX_op_qemu_st_a32_i32: |
1546 | case INDEX_op_qemu_st_a64_i32: | |
1547 | case INDEX_op_qemu_st_a32_i64: | |
1548 | case INDEX_op_qemu_st_a64_i64: | |
0d11dc7c | 1549 | return C_O0_I2(rZ, r); |
9be44a16 RH |
1550 | |
1551 | case INDEX_op_add_i32: | |
a59a2931 | 1552 | case INDEX_op_add_i64: |
9be44a16 | 1553 | case INDEX_op_mul_i32: |
a59a2931 | 1554 | case INDEX_op_mul_i64: |
9be44a16 | 1555 | case INDEX_op_div_i32: |
a59a2931 | 1556 | case INDEX_op_div_i64: |
9be44a16 | 1557 | case INDEX_op_divu_i32: |
a59a2931 | 1558 | case INDEX_op_divu_i64: |
9be44a16 | 1559 | case INDEX_op_sub_i32: |
a59a2931 | 1560 | case INDEX_op_sub_i64: |
9be44a16 | 1561 | case INDEX_op_and_i32: |
a59a2931 | 1562 | case INDEX_op_and_i64: |
9be44a16 | 1563 | case INDEX_op_andc_i32: |
a59a2931 | 1564 | case INDEX_op_andc_i64: |
9be44a16 | 1565 | case INDEX_op_or_i32: |
a59a2931 | 1566 | case INDEX_op_or_i64: |
9be44a16 | 1567 | case INDEX_op_orc_i32: |
a59a2931 | 1568 | case INDEX_op_orc_i64: |
9be44a16 | 1569 | case INDEX_op_xor_i32: |
a59a2931 | 1570 | case INDEX_op_xor_i64: |
9be44a16 | 1571 | case INDEX_op_shl_i32: |
a59a2931 | 1572 | case INDEX_op_shl_i64: |
9be44a16 | 1573 | case INDEX_op_shr_i32: |
a59a2931 | 1574 | case INDEX_op_shr_i64: |
9be44a16 | 1575 | case INDEX_op_sar_i32: |
a59a2931 | 1576 | case INDEX_op_sar_i64: |
9be44a16 | 1577 | case INDEX_op_setcond_i32: |
a59a2931 | 1578 | case INDEX_op_setcond_i64: |
a0fdd7c9 RH |
1579 | case INDEX_op_negsetcond_i32: |
1580 | case INDEX_op_negsetcond_i64: | |
0d11dc7c | 1581 | return C_O1_I2(r, rZ, rJ); |
9be44a16 RH |
1582 | |
1583 | case INDEX_op_brcond_i32: | |
a59a2931 | 1584 | case INDEX_op_brcond_i64: |
0d11dc7c | 1585 | return C_O0_I2(rZ, rJ); |
9be44a16 | 1586 | case INDEX_op_movcond_i32: |
a59a2931 | 1587 | case INDEX_op_movcond_i64: |
0d11dc7c | 1588 | return C_O1_I4(r, rZ, rJ, rI, 0); |
9be44a16 | 1589 | case INDEX_op_add2_i32: |
a59a2931 | 1590 | case INDEX_op_add2_i64: |
9be44a16 | 1591 | case INDEX_op_sub2_i32: |
a59a2931 | 1592 | case INDEX_op_sub2_i64: |
0d11dc7c | 1593 | return C_O2_I4(r, r, rZ, rZ, rJ, rJ); |
9be44a16 RH |
1594 | case INDEX_op_mulu2_i32: |
1595 | case INDEX_op_muls2_i32: | |
0d11dc7c | 1596 | return C_O2_I2(r, r, rZ, rJ); |
9be44a16 | 1597 | case INDEX_op_muluh_i64: |
a59a2931 | 1598 | return C_O1_I2(r, r, r); |
9be44a16 | 1599 | |
9be44a16 | 1600 | default: |
0d11dc7c | 1601 | g_assert_not_reached(); |
f69d277e | 1602 | } |
f69d277e RH |
1603 | } |
1604 | ||
e4d58b41 | 1605 | static void tcg_target_init(TCGContext *s) |
8289b279 | 1606 | { |
a4761232 PMD |
1607 | /* |
1608 | * Only probe for the platform and capabilities if we haven't already | |
1609 | * determined maximum values at compile time. | |
1610 | */ | |
90379ca8 RH |
1611 | #ifndef use_vis3_instructions |
1612 | { | |
1613 | unsigned long hwcap = qemu_getauxval(AT_HWCAP); | |
1614 | use_vis3_instructions = (hwcap & HWCAP_SPARC_VIS3) != 0; | |
1615 | } | |
1616 | #endif | |
1617 | ||
77f268e8 | 1618 | tcg_target_available_regs[TCG_TYPE_I32] = ALL_GENERAL_REGS; |
a59a2931 | 1619 | tcg_target_available_regs[TCG_TYPE_I64] = ALL_GENERAL_REGS; |
f46934df RH |
1620 | |
1621 | tcg_target_call_clobber_regs = 0; | |
1622 | tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_G1); | |
1623 | tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_G2); | |
1624 | tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_G3); | |
1625 | tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_G4); | |
1626 | tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_G5); | |
1627 | tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_G6); | |
1628 | tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_G7); | |
1629 | tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_O0); | |
1630 | tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_O1); | |
1631 | tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_O2); | |
1632 | tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_O3); | |
1633 | tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_O4); | |
1634 | tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_O5); | |
1635 | tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_O6); | |
1636 | tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_O7); | |
8289b279 | 1637 | |
ccb1bb66 | 1638 | s->reserved_regs = 0; |
375816f8 RH |
1639 | tcg_regset_set_reg(s->reserved_regs, TCG_REG_G0); /* zero */ |
1640 | tcg_regset_set_reg(s->reserved_regs, TCG_REG_G6); /* reserved for os */ | |
1641 | tcg_regset_set_reg(s->reserved_regs, TCG_REG_G7); /* thread pointer */ | |
1642 | tcg_regset_set_reg(s->reserved_regs, TCG_REG_I6); /* frame pointer */ | |
1643 | tcg_regset_set_reg(s->reserved_regs, TCG_REG_I7); /* return address */ | |
1644 | tcg_regset_set_reg(s->reserved_regs, TCG_REG_O6); /* stack pointer */ | |
1645 | tcg_regset_set_reg(s->reserved_regs, TCG_REG_T1); /* for internal use */ | |
1646 | tcg_regset_set_reg(s->reserved_regs, TCG_REG_T2); /* for internal use */ | |
33982b89 | 1647 | tcg_regset_set_reg(s->reserved_regs, TCG_REG_T3); /* for internal use */ |
8289b279 | 1648 | } |
cb1977d3 | 1649 | |
3a5f6805 | 1650 | #define ELF_HOST_MACHINE EM_SPARCV9 |
cb1977d3 | 1651 | |
cb1977d3 | 1652 | typedef struct { |
ae18b28d | 1653 | DebugFrameHeader h; |
3a5f6805 | 1654 | uint8_t fde_def_cfa[4]; |
497a22eb RH |
1655 | uint8_t fde_win_save; |
1656 | uint8_t fde_ret_save[3]; | |
cb1977d3 RH |
1657 | } DebugFrame; |
1658 | ||
ae18b28d RH |
1659 | static const DebugFrame debug_frame = { |
1660 | .h.cie.len = sizeof(DebugFrameCIE)-4, /* length after .len member */ | |
1661 | .h.cie.id = -1, | |
1662 | .h.cie.version = 1, | |
1663 | .h.cie.code_align = 1, | |
1664 | .h.cie.data_align = -sizeof(void *) & 0x7f, | |
1665 | .h.cie.return_column = 15, /* o7 */ | |
cb1977d3 | 1666 | |
497a22eb | 1667 | /* Total FDE size does not include the "len" member. */ |
ae18b28d | 1668 | .h.fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, h.fde.cie_offset), |
497a22eb RH |
1669 | |
1670 | .fde_def_cfa = { | |
cb1977d3 RH |
1671 | 12, 30, /* DW_CFA_def_cfa i6, 2047 */ |
1672 | (2047 & 0x7f) | 0x80, (2047 >> 7) | |
cb1977d3 | 1673 | }, |
497a22eb RH |
1674 | .fde_win_save = 0x2d, /* DW_CFA_GNU_window_save */ |
1675 | .fde_ret_save = { 9, 15, 31 }, /* DW_CFA_register o7, i7 */ | |
cb1977d3 RH |
1676 | }; |
1677 | ||
755bf9e5 | 1678 | void tcg_register_jit(const void *buf, size_t buf_size) |
cb1977d3 | 1679 | { |
cb1977d3 RH |
1680 | tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame)); |
1681 | } |