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Commit | Line | Data |
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c896fe29 FB |
1 | /* |
2 | * Tiny Code Generator for QEMU | |
3 | * | |
4 | * Copyright (c) 2008 Fabrice Bellard | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
24 | #include "tcg.h" | |
25 | ||
c896fe29 FB |
26 | int gen_new_label(void); |
27 | ||
212c328d RH |
28 | static inline void tcg_gen_op0(TCGOpcode opc) |
29 | { | |
30 | *gen_opc_ptr++ = opc; | |
31 | } | |
32 | ||
a9751609 | 33 | static inline void tcg_gen_op1_i32(TCGOpcode opc, TCGv_i32 arg1) |
c896fe29 FB |
34 | { |
35 | *gen_opc_ptr++ = opc; | |
a7812ae4 PB |
36 | *gen_opparam_ptr++ = GET_TCGV_I32(arg1); |
37 | } | |
38 | ||
a9751609 | 39 | static inline void tcg_gen_op1_i64(TCGOpcode opc, TCGv_i64 arg1) |
a7812ae4 PB |
40 | { |
41 | *gen_opc_ptr++ = opc; | |
42 | *gen_opparam_ptr++ = GET_TCGV_I64(arg1); | |
c896fe29 FB |
43 | } |
44 | ||
a9751609 | 45 | static inline void tcg_gen_op1i(TCGOpcode opc, TCGArg arg1) |
c896fe29 FB |
46 | { |
47 | *gen_opc_ptr++ = opc; | |
48 | *gen_opparam_ptr++ = arg1; | |
c896fe29 FB |
49 | } |
50 | ||
a9751609 | 51 | static inline void tcg_gen_op2_i32(TCGOpcode opc, TCGv_i32 arg1, TCGv_i32 arg2) |
a7812ae4 PB |
52 | { |
53 | *gen_opc_ptr++ = opc; | |
54 | *gen_opparam_ptr++ = GET_TCGV_I32(arg1); | |
55 | *gen_opparam_ptr++ = GET_TCGV_I32(arg2); | |
56 | } | |
57 | ||
a9751609 | 58 | static inline void tcg_gen_op2_i64(TCGOpcode opc, TCGv_i64 arg1, TCGv_i64 arg2) |
a7812ae4 PB |
59 | { |
60 | *gen_opc_ptr++ = opc; | |
61 | *gen_opparam_ptr++ = GET_TCGV_I64(arg1); | |
62 | *gen_opparam_ptr++ = GET_TCGV_I64(arg2); | |
63 | } | |
64 | ||
a9751609 | 65 | static inline void tcg_gen_op2i_i32(TCGOpcode opc, TCGv_i32 arg1, TCGArg arg2) |
c896fe29 FB |
66 | { |
67 | *gen_opc_ptr++ = opc; | |
a7812ae4 PB |
68 | *gen_opparam_ptr++ = GET_TCGV_I32(arg1); |
69 | *gen_opparam_ptr++ = arg2; | |
c896fe29 FB |
70 | } |
71 | ||
a9751609 | 72 | static inline void tcg_gen_op2i_i64(TCGOpcode opc, TCGv_i64 arg1, TCGArg arg2) |
c896fe29 FB |
73 | { |
74 | *gen_opc_ptr++ = opc; | |
a7812ae4 | 75 | *gen_opparam_ptr++ = GET_TCGV_I64(arg1); |
c896fe29 | 76 | *gen_opparam_ptr++ = arg2; |
ac56dd48 PB |
77 | } |
78 | ||
a9751609 | 79 | static inline void tcg_gen_op2ii(TCGOpcode opc, TCGArg arg1, TCGArg arg2) |
bcb0126f PB |
80 | { |
81 | *gen_opc_ptr++ = opc; | |
82 | *gen_opparam_ptr++ = arg1; | |
83 | *gen_opparam_ptr++ = arg2; | |
84 | } | |
85 | ||
a9751609 | 86 | static inline void tcg_gen_op3_i32(TCGOpcode opc, TCGv_i32 arg1, TCGv_i32 arg2, |
a7812ae4 PB |
87 | TCGv_i32 arg3) |
88 | { | |
89 | *gen_opc_ptr++ = opc; | |
90 | *gen_opparam_ptr++ = GET_TCGV_I32(arg1); | |
91 | *gen_opparam_ptr++ = GET_TCGV_I32(arg2); | |
92 | *gen_opparam_ptr++ = GET_TCGV_I32(arg3); | |
93 | } | |
94 | ||
a9751609 | 95 | static inline void tcg_gen_op3_i64(TCGOpcode opc, TCGv_i64 arg1, TCGv_i64 arg2, |
a7812ae4 PB |
96 | TCGv_i64 arg3) |
97 | { | |
98 | *gen_opc_ptr++ = opc; | |
99 | *gen_opparam_ptr++ = GET_TCGV_I64(arg1); | |
100 | *gen_opparam_ptr++ = GET_TCGV_I64(arg2); | |
101 | *gen_opparam_ptr++ = GET_TCGV_I64(arg3); | |
102 | } | |
103 | ||
a9751609 RH |
104 | static inline void tcg_gen_op3i_i32(TCGOpcode opc, TCGv_i32 arg1, |
105 | TCGv_i32 arg2, TCGArg arg3) | |
ac56dd48 PB |
106 | { |
107 | *gen_opc_ptr++ = opc; | |
a7812ae4 PB |
108 | *gen_opparam_ptr++ = GET_TCGV_I32(arg1); |
109 | *gen_opparam_ptr++ = GET_TCGV_I32(arg2); | |
110 | *gen_opparam_ptr++ = arg3; | |
ac56dd48 PB |
111 | } |
112 | ||
a9751609 RH |
113 | static inline void tcg_gen_op3i_i64(TCGOpcode opc, TCGv_i64 arg1, |
114 | TCGv_i64 arg2, TCGArg arg3) | |
ac56dd48 PB |
115 | { |
116 | *gen_opc_ptr++ = opc; | |
a7812ae4 PB |
117 | *gen_opparam_ptr++ = GET_TCGV_I64(arg1); |
118 | *gen_opparam_ptr++ = GET_TCGV_I64(arg2); | |
c896fe29 | 119 | *gen_opparam_ptr++ = arg3; |
ac56dd48 PB |
120 | } |
121 | ||
a9751609 RH |
122 | static inline void tcg_gen_ldst_op_i32(TCGOpcode opc, TCGv_i32 val, |
123 | TCGv_ptr base, TCGArg offset) | |
a7812ae4 PB |
124 | { |
125 | *gen_opc_ptr++ = opc; | |
126 | *gen_opparam_ptr++ = GET_TCGV_I32(val); | |
127 | *gen_opparam_ptr++ = GET_TCGV_PTR(base); | |
128 | *gen_opparam_ptr++ = offset; | |
129 | } | |
130 | ||
a9751609 RH |
131 | static inline void tcg_gen_ldst_op_i64(TCGOpcode opc, TCGv_i64 val, |
132 | TCGv_ptr base, TCGArg offset) | |
a7812ae4 PB |
133 | { |
134 | *gen_opc_ptr++ = opc; | |
a810a2de | 135 | *gen_opparam_ptr++ = GET_TCGV_I64(val); |
a7812ae4 PB |
136 | *gen_opparam_ptr++ = GET_TCGV_PTR(base); |
137 | *gen_opparam_ptr++ = offset; | |
138 | } | |
139 | ||
a9751609 RH |
140 | static inline void tcg_gen_qemu_ldst_op_i64_i32(TCGOpcode opc, TCGv_i64 val, |
141 | TCGv_i32 addr, TCGArg mem_index) | |
a7812ae4 PB |
142 | { |
143 | *gen_opc_ptr++ = opc; | |
144 | *gen_opparam_ptr++ = GET_TCGV_I64(val); | |
145 | *gen_opparam_ptr++ = GET_TCGV_I32(addr); | |
146 | *gen_opparam_ptr++ = mem_index; | |
147 | } | |
148 | ||
a9751609 RH |
149 | static inline void tcg_gen_qemu_ldst_op_i64_i64(TCGOpcode opc, TCGv_i64 val, |
150 | TCGv_i64 addr, TCGArg mem_index) | |
a7812ae4 PB |
151 | { |
152 | *gen_opc_ptr++ = opc; | |
153 | *gen_opparam_ptr++ = GET_TCGV_I64(val); | |
154 | *gen_opparam_ptr++ = GET_TCGV_I64(addr); | |
155 | *gen_opparam_ptr++ = mem_index; | |
156 | } | |
157 | ||
a9751609 | 158 | static inline void tcg_gen_op4_i32(TCGOpcode opc, TCGv_i32 arg1, TCGv_i32 arg2, |
a7812ae4 PB |
159 | TCGv_i32 arg3, TCGv_i32 arg4) |
160 | { | |
161 | *gen_opc_ptr++ = opc; | |
162 | *gen_opparam_ptr++ = GET_TCGV_I32(arg1); | |
163 | *gen_opparam_ptr++ = GET_TCGV_I32(arg2); | |
164 | *gen_opparam_ptr++ = GET_TCGV_I32(arg3); | |
165 | *gen_opparam_ptr++ = GET_TCGV_I32(arg4); | |
166 | } | |
167 | ||
a9751609 | 168 | static inline void tcg_gen_op4_i64(TCGOpcode opc, TCGv_i64 arg1, TCGv_i64 arg2, |
a810a2de | 169 | TCGv_i64 arg3, TCGv_i64 arg4) |
a7812ae4 PB |
170 | { |
171 | *gen_opc_ptr++ = opc; | |
172 | *gen_opparam_ptr++ = GET_TCGV_I64(arg1); | |
173 | *gen_opparam_ptr++ = GET_TCGV_I64(arg2); | |
174 | *gen_opparam_ptr++ = GET_TCGV_I64(arg3); | |
175 | *gen_opparam_ptr++ = GET_TCGV_I64(arg4); | |
176 | } | |
177 | ||
a9751609 | 178 | static inline void tcg_gen_op4i_i32(TCGOpcode opc, TCGv_i32 arg1, TCGv_i32 arg2, |
a7812ae4 PB |
179 | TCGv_i32 arg3, TCGArg arg4) |
180 | { | |
181 | *gen_opc_ptr++ = opc; | |
182 | *gen_opparam_ptr++ = GET_TCGV_I32(arg1); | |
183 | *gen_opparam_ptr++ = GET_TCGV_I32(arg2); | |
184 | *gen_opparam_ptr++ = GET_TCGV_I32(arg3); | |
185 | *gen_opparam_ptr++ = arg4; | |
186 | } | |
187 | ||
a9751609 | 188 | static inline void tcg_gen_op4i_i64(TCGOpcode opc, TCGv_i64 arg1, TCGv_i64 arg2, |
a7812ae4 | 189 | TCGv_i64 arg3, TCGArg arg4) |
ac56dd48 PB |
190 | { |
191 | *gen_opc_ptr++ = opc; | |
a7812ae4 PB |
192 | *gen_opparam_ptr++ = GET_TCGV_I64(arg1); |
193 | *gen_opparam_ptr++ = GET_TCGV_I64(arg2); | |
194 | *gen_opparam_ptr++ = GET_TCGV_I64(arg3); | |
195 | *gen_opparam_ptr++ = arg4; | |
ac56dd48 PB |
196 | } |
197 | ||
a9751609 | 198 | static inline void tcg_gen_op4ii_i32(TCGOpcode opc, TCGv_i32 arg1, TCGv_i32 arg2, |
a7812ae4 | 199 | TCGArg arg3, TCGArg arg4) |
ac56dd48 PB |
200 | { |
201 | *gen_opc_ptr++ = opc; | |
a7812ae4 PB |
202 | *gen_opparam_ptr++ = GET_TCGV_I32(arg1); |
203 | *gen_opparam_ptr++ = GET_TCGV_I32(arg2); | |
204 | *gen_opparam_ptr++ = arg3; | |
c896fe29 FB |
205 | *gen_opparam_ptr++ = arg4; |
206 | } | |
207 | ||
a9751609 | 208 | static inline void tcg_gen_op4ii_i64(TCGOpcode opc, TCGv_i64 arg1, TCGv_i64 arg2, |
a7812ae4 | 209 | TCGArg arg3, TCGArg arg4) |
c896fe29 FB |
210 | { |
211 | *gen_opc_ptr++ = opc; | |
a7812ae4 PB |
212 | *gen_opparam_ptr++ = GET_TCGV_I64(arg1); |
213 | *gen_opparam_ptr++ = GET_TCGV_I64(arg2); | |
c896fe29 FB |
214 | *gen_opparam_ptr++ = arg3; |
215 | *gen_opparam_ptr++ = arg4; | |
ac56dd48 PB |
216 | } |
217 | ||
a9751609 | 218 | static inline void tcg_gen_op5_i32(TCGOpcode opc, TCGv_i32 arg1, TCGv_i32 arg2, |
a7812ae4 PB |
219 | TCGv_i32 arg3, TCGv_i32 arg4, TCGv_i32 arg5) |
220 | { | |
221 | *gen_opc_ptr++ = opc; | |
222 | *gen_opparam_ptr++ = GET_TCGV_I32(arg1); | |
223 | *gen_opparam_ptr++ = GET_TCGV_I32(arg2); | |
224 | *gen_opparam_ptr++ = GET_TCGV_I32(arg3); | |
225 | *gen_opparam_ptr++ = GET_TCGV_I32(arg4); | |
226 | *gen_opparam_ptr++ = GET_TCGV_I32(arg5); | |
227 | } | |
228 | ||
a9751609 | 229 | static inline void tcg_gen_op5_i64(TCGOpcode opc, TCGv_i64 arg1, TCGv_i64 arg2, |
a7812ae4 PB |
230 | TCGv_i64 arg3, TCGv_i64 arg4, TCGv_i64 arg5) |
231 | { | |
232 | *gen_opc_ptr++ = opc; | |
233 | *gen_opparam_ptr++ = GET_TCGV_I64(arg1); | |
234 | *gen_opparam_ptr++ = GET_TCGV_I64(arg2); | |
235 | *gen_opparam_ptr++ = GET_TCGV_I64(arg3); | |
236 | *gen_opparam_ptr++ = GET_TCGV_I64(arg4); | |
237 | *gen_opparam_ptr++ = GET_TCGV_I64(arg5); | |
238 | } | |
239 | ||
a9751609 | 240 | static inline void tcg_gen_op5i_i32(TCGOpcode opc, TCGv_i32 arg1, TCGv_i32 arg2, |
a7812ae4 | 241 | TCGv_i32 arg3, TCGv_i32 arg4, TCGArg arg5) |
ac56dd48 PB |
242 | { |
243 | *gen_opc_ptr++ = opc; | |
a7812ae4 PB |
244 | *gen_opparam_ptr++ = GET_TCGV_I32(arg1); |
245 | *gen_opparam_ptr++ = GET_TCGV_I32(arg2); | |
246 | *gen_opparam_ptr++ = GET_TCGV_I32(arg3); | |
247 | *gen_opparam_ptr++ = GET_TCGV_I32(arg4); | |
248 | *gen_opparam_ptr++ = arg5; | |
ac56dd48 PB |
249 | } |
250 | ||
a9751609 | 251 | static inline void tcg_gen_op5i_i64(TCGOpcode opc, TCGv_i64 arg1, TCGv_i64 arg2, |
a7812ae4 | 252 | TCGv_i64 arg3, TCGv_i64 arg4, TCGArg arg5) |
ac56dd48 PB |
253 | { |
254 | *gen_opc_ptr++ = opc; | |
a7812ae4 PB |
255 | *gen_opparam_ptr++ = GET_TCGV_I64(arg1); |
256 | *gen_opparam_ptr++ = GET_TCGV_I64(arg2); | |
257 | *gen_opparam_ptr++ = GET_TCGV_I64(arg3); | |
258 | *gen_opparam_ptr++ = GET_TCGV_I64(arg4); | |
c896fe29 FB |
259 | *gen_opparam_ptr++ = arg5; |
260 | } | |
261 | ||
b7767f0f RH |
262 | static inline void tcg_gen_op5ii_i32(TCGOpcode opc, TCGv_i32 arg1, |
263 | TCGv_i32 arg2, TCGv_i32 arg3, | |
264 | TCGArg arg4, TCGArg arg5) | |
265 | { | |
266 | *gen_opc_ptr++ = opc; | |
267 | *gen_opparam_ptr++ = GET_TCGV_I32(arg1); | |
268 | *gen_opparam_ptr++ = GET_TCGV_I32(arg2); | |
269 | *gen_opparam_ptr++ = GET_TCGV_I32(arg3); | |
270 | *gen_opparam_ptr++ = arg4; | |
271 | *gen_opparam_ptr++ = arg5; | |
272 | } | |
273 | ||
274 | static inline void tcg_gen_op5ii_i64(TCGOpcode opc, TCGv_i64 arg1, | |
275 | TCGv_i64 arg2, TCGv_i64 arg3, | |
276 | TCGArg arg4, TCGArg arg5) | |
277 | { | |
278 | *gen_opc_ptr++ = opc; | |
279 | *gen_opparam_ptr++ = GET_TCGV_I64(arg1); | |
280 | *gen_opparam_ptr++ = GET_TCGV_I64(arg2); | |
281 | *gen_opparam_ptr++ = GET_TCGV_I64(arg3); | |
282 | *gen_opparam_ptr++ = arg4; | |
283 | *gen_opparam_ptr++ = arg5; | |
284 | } | |
285 | ||
a9751609 | 286 | static inline void tcg_gen_op6_i32(TCGOpcode opc, TCGv_i32 arg1, TCGv_i32 arg2, |
a7812ae4 PB |
287 | TCGv_i32 arg3, TCGv_i32 arg4, TCGv_i32 arg5, |
288 | TCGv_i32 arg6) | |
289 | { | |
290 | *gen_opc_ptr++ = opc; | |
291 | *gen_opparam_ptr++ = GET_TCGV_I32(arg1); | |
292 | *gen_opparam_ptr++ = GET_TCGV_I32(arg2); | |
293 | *gen_opparam_ptr++ = GET_TCGV_I32(arg3); | |
294 | *gen_opparam_ptr++ = GET_TCGV_I32(arg4); | |
295 | *gen_opparam_ptr++ = GET_TCGV_I32(arg5); | |
296 | *gen_opparam_ptr++ = GET_TCGV_I32(arg6); | |
297 | } | |
298 | ||
a9751609 | 299 | static inline void tcg_gen_op6_i64(TCGOpcode opc, TCGv_i64 arg1, TCGv_i64 arg2, |
a7812ae4 PB |
300 | TCGv_i64 arg3, TCGv_i64 arg4, TCGv_i64 arg5, |
301 | TCGv_i64 arg6) | |
c896fe29 FB |
302 | { |
303 | *gen_opc_ptr++ = opc; | |
a7812ae4 PB |
304 | *gen_opparam_ptr++ = GET_TCGV_I64(arg1); |
305 | *gen_opparam_ptr++ = GET_TCGV_I64(arg2); | |
306 | *gen_opparam_ptr++ = GET_TCGV_I64(arg3); | |
307 | *gen_opparam_ptr++ = GET_TCGV_I64(arg4); | |
308 | *gen_opparam_ptr++ = GET_TCGV_I64(arg5); | |
309 | *gen_opparam_ptr++ = GET_TCGV_I64(arg6); | |
ac56dd48 PB |
310 | } |
311 | ||
a9751609 | 312 | static inline void tcg_gen_op6i_i32(TCGOpcode opc, TCGv_i32 arg1, TCGv_i32 arg2, |
be210acb RH |
313 | TCGv_i32 arg3, TCGv_i32 arg4, |
314 | TCGv_i32 arg5, TCGArg arg6) | |
315 | { | |
316 | *gen_opc_ptr++ = opc; | |
317 | *gen_opparam_ptr++ = GET_TCGV_I32(arg1); | |
318 | *gen_opparam_ptr++ = GET_TCGV_I32(arg2); | |
319 | *gen_opparam_ptr++ = GET_TCGV_I32(arg3); | |
320 | *gen_opparam_ptr++ = GET_TCGV_I32(arg4); | |
321 | *gen_opparam_ptr++ = GET_TCGV_I32(arg5); | |
322 | *gen_opparam_ptr++ = arg6; | |
323 | } | |
324 | ||
a9751609 | 325 | static inline void tcg_gen_op6i_i64(TCGOpcode opc, TCGv_i64 arg1, TCGv_i64 arg2, |
be210acb RH |
326 | TCGv_i64 arg3, TCGv_i64 arg4, |
327 | TCGv_i64 arg5, TCGArg arg6) | |
328 | { | |
329 | *gen_opc_ptr++ = opc; | |
330 | *gen_opparam_ptr++ = GET_TCGV_I64(arg1); | |
331 | *gen_opparam_ptr++ = GET_TCGV_I64(arg2); | |
332 | *gen_opparam_ptr++ = GET_TCGV_I64(arg3); | |
333 | *gen_opparam_ptr++ = GET_TCGV_I64(arg4); | |
334 | *gen_opparam_ptr++ = GET_TCGV_I64(arg5); | |
335 | *gen_opparam_ptr++ = arg6; | |
336 | } | |
337 | ||
a9751609 RH |
338 | static inline void tcg_gen_op6ii_i32(TCGOpcode opc, TCGv_i32 arg1, |
339 | TCGv_i32 arg2, TCGv_i32 arg3, | |
340 | TCGv_i32 arg4, TCGArg arg5, TCGArg arg6) | |
ac56dd48 PB |
341 | { |
342 | *gen_opc_ptr++ = opc; | |
a7812ae4 PB |
343 | *gen_opparam_ptr++ = GET_TCGV_I32(arg1); |
344 | *gen_opparam_ptr++ = GET_TCGV_I32(arg2); | |
345 | *gen_opparam_ptr++ = GET_TCGV_I32(arg3); | |
346 | *gen_opparam_ptr++ = GET_TCGV_I32(arg4); | |
347 | *gen_opparam_ptr++ = arg5; | |
348 | *gen_opparam_ptr++ = arg6; | |
349 | } | |
350 | ||
a9751609 RH |
351 | static inline void tcg_gen_op6ii_i64(TCGOpcode opc, TCGv_i64 arg1, |
352 | TCGv_i64 arg2, TCGv_i64 arg3, | |
353 | TCGv_i64 arg4, TCGArg arg5, TCGArg arg6) | |
a7812ae4 PB |
354 | { |
355 | *gen_opc_ptr++ = opc; | |
356 | *gen_opparam_ptr++ = GET_TCGV_I64(arg1); | |
357 | *gen_opparam_ptr++ = GET_TCGV_I64(arg2); | |
358 | *gen_opparam_ptr++ = GET_TCGV_I64(arg3); | |
359 | *gen_opparam_ptr++ = GET_TCGV_I64(arg4); | |
c896fe29 FB |
360 | *gen_opparam_ptr++ = arg5; |
361 | *gen_opparam_ptr++ = arg6; | |
362 | } | |
363 | ||
364 | static inline void gen_set_label(int n) | |
365 | { | |
ac56dd48 | 366 | tcg_gen_op1i(INDEX_op_set_label, n); |
c896fe29 FB |
367 | } |
368 | ||
fb50d413 BS |
369 | static inline void tcg_gen_br(int label) |
370 | { | |
371 | tcg_gen_op1i(INDEX_op_br, label); | |
372 | } | |
373 | ||
a7812ae4 | 374 | static inline void tcg_gen_mov_i32(TCGv_i32 ret, TCGv_i32 arg) |
c896fe29 | 375 | { |
fe75bcf7 | 376 | if (!TCGV_EQUAL_I32(ret, arg)) |
a7812ae4 | 377 | tcg_gen_op2_i32(INDEX_op_mov_i32, ret, arg); |
c896fe29 FB |
378 | } |
379 | ||
a7812ae4 | 380 | static inline void tcg_gen_movi_i32(TCGv_i32 ret, int32_t arg) |
c896fe29 | 381 | { |
a7812ae4 | 382 | tcg_gen_op2i_i32(INDEX_op_movi_i32, ret, arg); |
c896fe29 FB |
383 | } |
384 | ||
2bece2c8 RH |
385 | /* A version of dh_sizemask from def-helper.h that doesn't rely on |
386 | preprocessor magic. */ | |
387 | static inline int tcg_gen_sizemask(int n, int is_64bit, int is_signed) | |
388 | { | |
389 | return (is_64bit << n*2) | (is_signed << (n*2 + 1)); | |
390 | } | |
391 | ||
c896fe29 | 392 | /* helper calls */ |
a7812ae4 PB |
393 | static inline void tcg_gen_helperN(void *func, int flags, int sizemask, |
394 | TCGArg ret, int nargs, TCGArg *args) | |
395 | { | |
396 | TCGv_ptr fn; | |
73f5e313 | 397 | fn = tcg_const_ptr(func); |
a7812ae4 PB |
398 | tcg_gen_callN(&tcg_ctx, fn, flags, sizemask, ret, |
399 | nargs, args); | |
400 | tcg_temp_free_ptr(fn); | |
401 | } | |
c896fe29 | 402 | |
dbfff4de AJ |
403 | /* Note: Both tcg_gen_helper32() and tcg_gen_helper64() are currently |
404 | reserved for helpers in tcg-runtime.c. These helpers are all const | |
405 | and pure, hence the call to tcg_gen_callN() with TCG_CALL_CONST | | |
406 | TCG_CALL_PURE. This may need to be adjusted if these functions | |
407 | start to be used with other helpers. */ | |
2bece2c8 | 408 | static inline void tcg_gen_helper32(void *func, int sizemask, TCGv_i32 ret, |
31d66551 AJ |
409 | TCGv_i32 a, TCGv_i32 b) |
410 | { | |
411 | TCGv_ptr fn; | |
412 | TCGArg args[2]; | |
73f5e313 | 413 | fn = tcg_const_ptr(func); |
31d66551 AJ |
414 | args[0] = GET_TCGV_I32(a); |
415 | args[1] = GET_TCGV_I32(b); | |
2bece2c8 RH |
416 | tcg_gen_callN(&tcg_ctx, fn, TCG_CALL_CONST | TCG_CALL_PURE, sizemask, |
417 | GET_TCGV_I32(ret), 2, args); | |
31d66551 AJ |
418 | tcg_temp_free_ptr(fn); |
419 | } | |
420 | ||
2bece2c8 | 421 | static inline void tcg_gen_helper64(void *func, int sizemask, TCGv_i64 ret, |
a7812ae4 | 422 | TCGv_i64 a, TCGv_i64 b) |
c896fe29 | 423 | { |
a7812ae4 PB |
424 | TCGv_ptr fn; |
425 | TCGArg args[2]; | |
73f5e313 | 426 | fn = tcg_const_ptr(func); |
a7812ae4 PB |
427 | args[0] = GET_TCGV_I64(a); |
428 | args[1] = GET_TCGV_I64(b); | |
2bece2c8 RH |
429 | tcg_gen_callN(&tcg_ctx, fn, TCG_CALL_CONST | TCG_CALL_PURE, sizemask, |
430 | GET_TCGV_I64(ret), 2, args); | |
a7812ae4 | 431 | tcg_temp_free_ptr(fn); |
f8422f52 BS |
432 | } |
433 | ||
c896fe29 FB |
434 | /* 32 bit ops */ |
435 | ||
a7812ae4 | 436 | static inline void tcg_gen_ld8u_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset) |
c896fe29 | 437 | { |
a7812ae4 | 438 | tcg_gen_ldst_op_i32(INDEX_op_ld8u_i32, ret, arg2, offset); |
c896fe29 FB |
439 | } |
440 | ||
a7812ae4 | 441 | static inline void tcg_gen_ld8s_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset) |
c896fe29 | 442 | { |
a7812ae4 | 443 | tcg_gen_ldst_op_i32(INDEX_op_ld8s_i32, ret, arg2, offset); |
c896fe29 FB |
444 | } |
445 | ||
a7812ae4 | 446 | static inline void tcg_gen_ld16u_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset) |
c896fe29 | 447 | { |
a7812ae4 | 448 | tcg_gen_ldst_op_i32(INDEX_op_ld16u_i32, ret, arg2, offset); |
c896fe29 FB |
449 | } |
450 | ||
a7812ae4 | 451 | static inline void tcg_gen_ld16s_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset) |
c896fe29 | 452 | { |
a7812ae4 | 453 | tcg_gen_ldst_op_i32(INDEX_op_ld16s_i32, ret, arg2, offset); |
c896fe29 FB |
454 | } |
455 | ||
a7812ae4 | 456 | static inline void tcg_gen_ld_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset) |
c896fe29 | 457 | { |
a7812ae4 | 458 | tcg_gen_ldst_op_i32(INDEX_op_ld_i32, ret, arg2, offset); |
c896fe29 FB |
459 | } |
460 | ||
a7812ae4 | 461 | static inline void tcg_gen_st8_i32(TCGv_i32 arg1, TCGv_ptr arg2, tcg_target_long offset) |
c896fe29 | 462 | { |
a7812ae4 | 463 | tcg_gen_ldst_op_i32(INDEX_op_st8_i32, arg1, arg2, offset); |
c896fe29 FB |
464 | } |
465 | ||
a7812ae4 | 466 | static inline void tcg_gen_st16_i32(TCGv_i32 arg1, TCGv_ptr arg2, tcg_target_long offset) |
c896fe29 | 467 | { |
a7812ae4 | 468 | tcg_gen_ldst_op_i32(INDEX_op_st16_i32, arg1, arg2, offset); |
c896fe29 FB |
469 | } |
470 | ||
a7812ae4 | 471 | static inline void tcg_gen_st_i32(TCGv_i32 arg1, TCGv_ptr arg2, tcg_target_long offset) |
c896fe29 | 472 | { |
a7812ae4 | 473 | tcg_gen_ldst_op_i32(INDEX_op_st_i32, arg1, arg2, offset); |
c896fe29 FB |
474 | } |
475 | ||
a7812ae4 | 476 | static inline void tcg_gen_add_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
c896fe29 | 477 | { |
a7812ae4 | 478 | tcg_gen_op3_i32(INDEX_op_add_i32, ret, arg1, arg2); |
c896fe29 FB |
479 | } |
480 | ||
a7812ae4 | 481 | static inline void tcg_gen_addi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) |
c896fe29 | 482 | { |
7089442c BS |
483 | /* some cases can be optimized here */ |
484 | if (arg2 == 0) { | |
485 | tcg_gen_mov_i32(ret, arg1); | |
486 | } else { | |
a7812ae4 | 487 | TCGv_i32 t0 = tcg_const_i32(arg2); |
e8996ee0 | 488 | tcg_gen_add_i32(ret, arg1, t0); |
a7812ae4 | 489 | tcg_temp_free_i32(t0); |
7089442c | 490 | } |
c896fe29 FB |
491 | } |
492 | ||
a7812ae4 | 493 | static inline void tcg_gen_sub_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
c896fe29 | 494 | { |
a7812ae4 | 495 | tcg_gen_op3_i32(INDEX_op_sub_i32, ret, arg1, arg2); |
c896fe29 FB |
496 | } |
497 | ||
a7812ae4 | 498 | static inline void tcg_gen_subfi_i32(TCGv_i32 ret, int32_t arg1, TCGv_i32 arg2) |
0045734a | 499 | { |
a7812ae4 | 500 | TCGv_i32 t0 = tcg_const_i32(arg1); |
0045734a | 501 | tcg_gen_sub_i32(ret, t0, arg2); |
a7812ae4 | 502 | tcg_temp_free_i32(t0); |
0045734a AJ |
503 | } |
504 | ||
a7812ae4 | 505 | static inline void tcg_gen_subi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) |
c896fe29 | 506 | { |
7089442c BS |
507 | /* some cases can be optimized here */ |
508 | if (arg2 == 0) { | |
509 | tcg_gen_mov_i32(ret, arg1); | |
510 | } else { | |
a7812ae4 | 511 | TCGv_i32 t0 = tcg_const_i32(arg2); |
e8996ee0 | 512 | tcg_gen_sub_i32(ret, arg1, t0); |
a7812ae4 | 513 | tcg_temp_free_i32(t0); |
7089442c | 514 | } |
c896fe29 FB |
515 | } |
516 | ||
a7812ae4 | 517 | static inline void tcg_gen_and_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
c896fe29 | 518 | { |
7fc81051 AJ |
519 | if (TCGV_EQUAL_I32(arg1, arg2)) { |
520 | tcg_gen_mov_i32(ret, arg1); | |
521 | } else { | |
522 | tcg_gen_op3_i32(INDEX_op_and_i32, ret, arg1, arg2); | |
523 | } | |
c896fe29 FB |
524 | } |
525 | ||
42ce3e20 | 526 | static inline void tcg_gen_andi_i32(TCGv_i32 ret, TCGv_i32 arg1, uint32_t arg2) |
c896fe29 | 527 | { |
42ce3e20 RH |
528 | TCGv_i32 t0; |
529 | /* Some cases can be optimized here. */ | |
530 | switch (arg2) { | |
531 | case 0: | |
c896fe29 | 532 | tcg_gen_movi_i32(ret, 0); |
42ce3e20 RH |
533 | return; |
534 | case 0xffffffffu: | |
c896fe29 | 535 | tcg_gen_mov_i32(ret, arg1); |
42ce3e20 RH |
536 | return; |
537 | case 0xffu: | |
538 | /* Don't recurse with tcg_gen_ext8u_i32. */ | |
539 | if (TCG_TARGET_HAS_ext8u_i32) { | |
540 | tcg_gen_op2_i32(INDEX_op_ext8u_i32, ret, arg1); | |
541 | return; | |
542 | } | |
543 | break; | |
544 | case 0xffffu: | |
545 | if (TCG_TARGET_HAS_ext16u_i32) { | |
546 | tcg_gen_op2_i32(INDEX_op_ext16u_i32, ret, arg1); | |
547 | return; | |
548 | } | |
549 | break; | |
c896fe29 | 550 | } |
42ce3e20 RH |
551 | t0 = tcg_const_i32(arg2); |
552 | tcg_gen_and_i32(ret, arg1, t0); | |
553 | tcg_temp_free_i32(t0); | |
c896fe29 FB |
554 | } |
555 | ||
a7812ae4 | 556 | static inline void tcg_gen_or_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
c896fe29 | 557 | { |
7fc81051 AJ |
558 | if (TCGV_EQUAL_I32(arg1, arg2)) { |
559 | tcg_gen_mov_i32(ret, arg1); | |
560 | } else { | |
561 | tcg_gen_op3_i32(INDEX_op_or_i32, ret, arg1, arg2); | |
562 | } | |
c896fe29 FB |
563 | } |
564 | ||
a7812ae4 | 565 | static inline void tcg_gen_ori_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) |
c896fe29 | 566 | { |
d81ada7f RH |
567 | /* Some cases can be optimized here. */ |
568 | if (arg2 == -1) { | |
569 | tcg_gen_movi_i32(ret, -1); | |
c896fe29 FB |
570 | } else if (arg2 == 0) { |
571 | tcg_gen_mov_i32(ret, arg1); | |
572 | } else { | |
a7812ae4 | 573 | TCGv_i32 t0 = tcg_const_i32(arg2); |
e8996ee0 | 574 | tcg_gen_or_i32(ret, arg1, t0); |
a7812ae4 | 575 | tcg_temp_free_i32(t0); |
c896fe29 FB |
576 | } |
577 | } | |
578 | ||
a7812ae4 | 579 | static inline void tcg_gen_xor_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
c896fe29 | 580 | { |
7fc81051 AJ |
581 | if (TCGV_EQUAL_I32(arg1, arg2)) { |
582 | tcg_gen_movi_i32(ret, 0); | |
583 | } else { | |
584 | tcg_gen_op3_i32(INDEX_op_xor_i32, ret, arg1, arg2); | |
585 | } | |
c896fe29 FB |
586 | } |
587 | ||
a7812ae4 | 588 | static inline void tcg_gen_xori_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) |
c896fe29 | 589 | { |
6f3bb33e | 590 | /* Some cases can be optimized here. */ |
c896fe29 FB |
591 | if (arg2 == 0) { |
592 | tcg_gen_mov_i32(ret, arg1); | |
6f3bb33e RH |
593 | } else if (arg2 == -1 && TCG_TARGET_HAS_not_i32) { |
594 | /* Don't recurse with tcg_gen_not_i32. */ | |
595 | tcg_gen_op2_i32(INDEX_op_not_i32, ret, arg1); | |
c896fe29 | 596 | } else { |
a7812ae4 | 597 | TCGv_i32 t0 = tcg_const_i32(arg2); |
e8996ee0 | 598 | tcg_gen_xor_i32(ret, arg1, t0); |
a7812ae4 | 599 | tcg_temp_free_i32(t0); |
c896fe29 FB |
600 | } |
601 | } | |
602 | ||
a7812ae4 | 603 | static inline void tcg_gen_shl_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
c896fe29 | 604 | { |
a7812ae4 | 605 | tcg_gen_op3_i32(INDEX_op_shl_i32, ret, arg1, arg2); |
c896fe29 FB |
606 | } |
607 | ||
a7812ae4 | 608 | static inline void tcg_gen_shli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) |
c896fe29 | 609 | { |
34151a20 FB |
610 | if (arg2 == 0) { |
611 | tcg_gen_mov_i32(ret, arg1); | |
612 | } else { | |
a7812ae4 | 613 | TCGv_i32 t0 = tcg_const_i32(arg2); |
e8996ee0 | 614 | tcg_gen_shl_i32(ret, arg1, t0); |
a7812ae4 | 615 | tcg_temp_free_i32(t0); |
34151a20 | 616 | } |
c896fe29 FB |
617 | } |
618 | ||
a7812ae4 | 619 | static inline void tcg_gen_shr_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
c896fe29 | 620 | { |
a7812ae4 | 621 | tcg_gen_op3_i32(INDEX_op_shr_i32, ret, arg1, arg2); |
c896fe29 FB |
622 | } |
623 | ||
a7812ae4 | 624 | static inline void tcg_gen_shri_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) |
c896fe29 | 625 | { |
34151a20 FB |
626 | if (arg2 == 0) { |
627 | tcg_gen_mov_i32(ret, arg1); | |
628 | } else { | |
a7812ae4 | 629 | TCGv_i32 t0 = tcg_const_i32(arg2); |
e8996ee0 | 630 | tcg_gen_shr_i32(ret, arg1, t0); |
a7812ae4 | 631 | tcg_temp_free_i32(t0); |
34151a20 | 632 | } |
c896fe29 FB |
633 | } |
634 | ||
a7812ae4 | 635 | static inline void tcg_gen_sar_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
c896fe29 | 636 | { |
a7812ae4 | 637 | tcg_gen_op3_i32(INDEX_op_sar_i32, ret, arg1, arg2); |
c896fe29 FB |
638 | } |
639 | ||
a7812ae4 | 640 | static inline void tcg_gen_sari_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) |
c896fe29 | 641 | { |
34151a20 FB |
642 | if (arg2 == 0) { |
643 | tcg_gen_mov_i32(ret, arg1); | |
644 | } else { | |
a7812ae4 | 645 | TCGv_i32 t0 = tcg_const_i32(arg2); |
e8996ee0 | 646 | tcg_gen_sar_i32(ret, arg1, t0); |
a7812ae4 | 647 | tcg_temp_free_i32(t0); |
34151a20 | 648 | } |
c896fe29 FB |
649 | } |
650 | ||
8a56e840 RH |
651 | static inline void tcg_gen_brcond_i32(TCGCond cond, TCGv_i32 arg1, |
652 | TCGv_i32 arg2, int label_index) | |
c896fe29 | 653 | { |
0aed257f RH |
654 | if (cond == TCG_COND_ALWAYS) { |
655 | tcg_gen_br(label_index); | |
656 | } else if (cond != TCG_COND_NEVER) { | |
657 | tcg_gen_op4ii_i32(INDEX_op_brcond_i32, arg1, arg2, cond, label_index); | |
658 | } | |
c896fe29 FB |
659 | } |
660 | ||
8a56e840 RH |
661 | static inline void tcg_gen_brcondi_i32(TCGCond cond, TCGv_i32 arg1, |
662 | int32_t arg2, int label_index) | |
cb63669a | 663 | { |
0aed257f RH |
664 | if (cond == TCG_COND_ALWAYS) { |
665 | tcg_gen_br(label_index); | |
666 | } else if (cond != TCG_COND_NEVER) { | |
667 | TCGv_i32 t0 = tcg_const_i32(arg2); | |
668 | tcg_gen_brcond_i32(cond, arg1, t0, label_index); | |
669 | tcg_temp_free_i32(t0); | |
670 | } | |
cb63669a PB |
671 | } |
672 | ||
8a56e840 | 673 | static inline void tcg_gen_setcond_i32(TCGCond cond, TCGv_i32 ret, |
5105c556 AJ |
674 | TCGv_i32 arg1, TCGv_i32 arg2) |
675 | { | |
0aed257f RH |
676 | if (cond == TCG_COND_ALWAYS) { |
677 | tcg_gen_movi_i32(ret, 1); | |
678 | } else if (cond == TCG_COND_NEVER) { | |
679 | tcg_gen_movi_i32(ret, 0); | |
680 | } else { | |
681 | tcg_gen_op4i_i32(INDEX_op_setcond_i32, ret, arg1, arg2, cond); | |
682 | } | |
5105c556 AJ |
683 | } |
684 | ||
8a56e840 RH |
685 | static inline void tcg_gen_setcondi_i32(TCGCond cond, TCGv_i32 ret, |
686 | TCGv_i32 arg1, int32_t arg2) | |
5105c556 | 687 | { |
0aed257f RH |
688 | if (cond == TCG_COND_ALWAYS) { |
689 | tcg_gen_movi_i32(ret, 1); | |
690 | } else if (cond == TCG_COND_NEVER) { | |
691 | tcg_gen_movi_i32(ret, 0); | |
692 | } else { | |
693 | TCGv_i32 t0 = tcg_const_i32(arg2); | |
694 | tcg_gen_setcond_i32(cond, ret, arg1, t0); | |
695 | tcg_temp_free_i32(t0); | |
696 | } | |
5105c556 AJ |
697 | } |
698 | ||
a7812ae4 | 699 | static inline void tcg_gen_mul_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
c896fe29 | 700 | { |
a7812ae4 | 701 | tcg_gen_op3_i32(INDEX_op_mul_i32, ret, arg1, arg2); |
c896fe29 FB |
702 | } |
703 | ||
a7812ae4 | 704 | static inline void tcg_gen_muli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) |
f730fd27 | 705 | { |
a7812ae4 | 706 | TCGv_i32 t0 = tcg_const_i32(arg2); |
e8996ee0 | 707 | tcg_gen_mul_i32(ret, arg1, t0); |
a7812ae4 | 708 | tcg_temp_free_i32(t0); |
f730fd27 TS |
709 | } |
710 | ||
a7812ae4 | 711 | static inline void tcg_gen_div_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
c896fe29 | 712 | { |
25c4d9cc RH |
713 | if (TCG_TARGET_HAS_div_i32) { |
714 | tcg_gen_op3_i32(INDEX_op_div_i32, ret, arg1, arg2); | |
715 | } else if (TCG_TARGET_HAS_div2_i32) { | |
716 | TCGv_i32 t0 = tcg_temp_new_i32(); | |
717 | tcg_gen_sari_i32(t0, arg1, 31); | |
718 | tcg_gen_op5_i32(INDEX_op_div2_i32, ret, t0, arg1, t0, arg2); | |
719 | tcg_temp_free_i32(t0); | |
720 | } else { | |
721 | int sizemask = 0; | |
722 | /* Return value and both arguments are 32-bit and signed. */ | |
723 | sizemask |= tcg_gen_sizemask(0, 0, 1); | |
724 | sizemask |= tcg_gen_sizemask(1, 0, 1); | |
725 | sizemask |= tcg_gen_sizemask(2, 0, 1); | |
726 | tcg_gen_helper32(tcg_helper_div_i32, sizemask, ret, arg1, arg2); | |
727 | } | |
31d66551 AJ |
728 | } |
729 | ||
730 | static inline void tcg_gen_rem_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) | |
731 | { | |
25c4d9cc RH |
732 | if (TCG_TARGET_HAS_div_i32) { |
733 | tcg_gen_op3_i32(INDEX_op_rem_i32, ret, arg1, arg2); | |
734 | } else if (TCG_TARGET_HAS_div2_i32) { | |
735 | TCGv_i32 t0 = tcg_temp_new_i32(); | |
736 | tcg_gen_sari_i32(t0, arg1, 31); | |
737 | tcg_gen_op5_i32(INDEX_op_div2_i32, t0, ret, arg1, t0, arg2); | |
738 | tcg_temp_free_i32(t0); | |
739 | } else { | |
740 | int sizemask = 0; | |
741 | /* Return value and both arguments are 32-bit and signed. */ | |
742 | sizemask |= tcg_gen_sizemask(0, 0, 1); | |
743 | sizemask |= tcg_gen_sizemask(1, 0, 1); | |
744 | sizemask |= tcg_gen_sizemask(2, 0, 1); | |
745 | tcg_gen_helper32(tcg_helper_rem_i32, sizemask, ret, arg1, arg2); | |
746 | } | |
31d66551 AJ |
747 | } |
748 | ||
749 | static inline void tcg_gen_divu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) | |
750 | { | |
25c4d9cc RH |
751 | if (TCG_TARGET_HAS_div_i32) { |
752 | tcg_gen_op3_i32(INDEX_op_divu_i32, ret, arg1, arg2); | |
753 | } else if (TCG_TARGET_HAS_div2_i32) { | |
754 | TCGv_i32 t0 = tcg_temp_new_i32(); | |
755 | tcg_gen_movi_i32(t0, 0); | |
756 | tcg_gen_op5_i32(INDEX_op_divu2_i32, ret, t0, arg1, t0, arg2); | |
757 | tcg_temp_free_i32(t0); | |
758 | } else { | |
759 | int sizemask = 0; | |
760 | /* Return value and both arguments are 32-bit and unsigned. */ | |
761 | sizemask |= tcg_gen_sizemask(0, 0, 0); | |
762 | sizemask |= tcg_gen_sizemask(1, 0, 0); | |
763 | sizemask |= tcg_gen_sizemask(2, 0, 0); | |
764 | tcg_gen_helper32(tcg_helper_divu_i32, sizemask, ret, arg1, arg2); | |
765 | } | |
31d66551 AJ |
766 | } |
767 | ||
768 | static inline void tcg_gen_remu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) | |
769 | { | |
25c4d9cc RH |
770 | if (TCG_TARGET_HAS_div_i32) { |
771 | tcg_gen_op3_i32(INDEX_op_remu_i32, ret, arg1, arg2); | |
772 | } else if (TCG_TARGET_HAS_div2_i32) { | |
773 | TCGv_i32 t0 = tcg_temp_new_i32(); | |
774 | tcg_gen_movi_i32(t0, 0); | |
775 | tcg_gen_op5_i32(INDEX_op_divu2_i32, t0, ret, arg1, t0, arg2); | |
776 | tcg_temp_free_i32(t0); | |
777 | } else { | |
778 | int sizemask = 0; | |
779 | /* Return value and both arguments are 32-bit and unsigned. */ | |
780 | sizemask |= tcg_gen_sizemask(0, 0, 0); | |
781 | sizemask |= tcg_gen_sizemask(1, 0, 0); | |
782 | sizemask |= tcg_gen_sizemask(2, 0, 0); | |
783 | tcg_gen_helper32(tcg_helper_remu_i32, sizemask, ret, arg1, arg2); | |
784 | } | |
31d66551 | 785 | } |
c896fe29 FB |
786 | |
787 | #if TCG_TARGET_REG_BITS == 32 | |
788 | ||
a7812ae4 | 789 | static inline void tcg_gen_mov_i64(TCGv_i64 ret, TCGv_i64 arg) |
c896fe29 | 790 | { |
fe75bcf7 | 791 | if (!TCGV_EQUAL_I64(ret, arg)) { |
a7812ae4 | 792 | tcg_gen_mov_i32(TCGV_LOW(ret), TCGV_LOW(arg)); |
4d07272d BS |
793 | tcg_gen_mov_i32(TCGV_HIGH(ret), TCGV_HIGH(arg)); |
794 | } | |
c896fe29 FB |
795 | } |
796 | ||
a7812ae4 | 797 | static inline void tcg_gen_movi_i64(TCGv_i64 ret, int64_t arg) |
c896fe29 | 798 | { |
a7812ae4 | 799 | tcg_gen_movi_i32(TCGV_LOW(ret), arg); |
ac56dd48 | 800 | tcg_gen_movi_i32(TCGV_HIGH(ret), arg >> 32); |
c896fe29 FB |
801 | } |
802 | ||
a7812ae4 PB |
803 | static inline void tcg_gen_ld8u_i64(TCGv_i64 ret, TCGv_ptr arg2, |
804 | tcg_target_long offset) | |
c896fe29 | 805 | { |
a7812ae4 | 806 | tcg_gen_ld8u_i32(TCGV_LOW(ret), arg2, offset); |
ac56dd48 | 807 | tcg_gen_movi_i32(TCGV_HIGH(ret), 0); |
c896fe29 FB |
808 | } |
809 | ||
a7812ae4 PB |
810 | static inline void tcg_gen_ld8s_i64(TCGv_i64 ret, TCGv_ptr arg2, |
811 | tcg_target_long offset) | |
c896fe29 | 812 | { |
a7812ae4 PB |
813 | tcg_gen_ld8s_i32(TCGV_LOW(ret), arg2, offset); |
814 | tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_HIGH(ret), 31); | |
c896fe29 FB |
815 | } |
816 | ||
a7812ae4 PB |
817 | static inline void tcg_gen_ld16u_i64(TCGv_i64 ret, TCGv_ptr arg2, |
818 | tcg_target_long offset) | |
c896fe29 | 819 | { |
a747723b | 820 | tcg_gen_ld16u_i32(TCGV_LOW(ret), arg2, offset); |
ac56dd48 | 821 | tcg_gen_movi_i32(TCGV_HIGH(ret), 0); |
c896fe29 FB |
822 | } |
823 | ||
a7812ae4 PB |
824 | static inline void tcg_gen_ld16s_i64(TCGv_i64 ret, TCGv_ptr arg2, |
825 | tcg_target_long offset) | |
c896fe29 | 826 | { |
a7812ae4 PB |
827 | tcg_gen_ld16s_i32(TCGV_LOW(ret), arg2, offset); |
828 | tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31); | |
c896fe29 FB |
829 | } |
830 | ||
a7812ae4 PB |
831 | static inline void tcg_gen_ld32u_i64(TCGv_i64 ret, TCGv_ptr arg2, |
832 | tcg_target_long offset) | |
c896fe29 | 833 | { |
a7812ae4 | 834 | tcg_gen_ld_i32(TCGV_LOW(ret), arg2, offset); |
ac56dd48 | 835 | tcg_gen_movi_i32(TCGV_HIGH(ret), 0); |
c896fe29 FB |
836 | } |
837 | ||
a7812ae4 PB |
838 | static inline void tcg_gen_ld32s_i64(TCGv_i64 ret, TCGv_ptr arg2, |
839 | tcg_target_long offset) | |
c896fe29 | 840 | { |
a7812ae4 PB |
841 | tcg_gen_ld_i32(TCGV_LOW(ret), arg2, offset); |
842 | tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31); | |
c896fe29 FB |
843 | } |
844 | ||
a7812ae4 PB |
845 | static inline void tcg_gen_ld_i64(TCGv_i64 ret, TCGv_ptr arg2, |
846 | tcg_target_long offset) | |
c896fe29 FB |
847 | { |
848 | /* since arg2 and ret have different types, they cannot be the | |
849 | same temporary */ | |
850 | #ifdef TCG_TARGET_WORDS_BIGENDIAN | |
ac56dd48 | 851 | tcg_gen_ld_i32(TCGV_HIGH(ret), arg2, offset); |
a7812ae4 | 852 | tcg_gen_ld_i32(TCGV_LOW(ret), arg2, offset + 4); |
c896fe29 | 853 | #else |
a7812ae4 | 854 | tcg_gen_ld_i32(TCGV_LOW(ret), arg2, offset); |
ac56dd48 | 855 | tcg_gen_ld_i32(TCGV_HIGH(ret), arg2, offset + 4); |
c896fe29 FB |
856 | #endif |
857 | } | |
858 | ||
a7812ae4 PB |
859 | static inline void tcg_gen_st8_i64(TCGv_i64 arg1, TCGv_ptr arg2, |
860 | tcg_target_long offset) | |
c896fe29 | 861 | { |
a7812ae4 | 862 | tcg_gen_st8_i32(TCGV_LOW(arg1), arg2, offset); |
c896fe29 FB |
863 | } |
864 | ||
a7812ae4 PB |
865 | static inline void tcg_gen_st16_i64(TCGv_i64 arg1, TCGv_ptr arg2, |
866 | tcg_target_long offset) | |
c896fe29 | 867 | { |
a7812ae4 | 868 | tcg_gen_st16_i32(TCGV_LOW(arg1), arg2, offset); |
c896fe29 FB |
869 | } |
870 | ||
a7812ae4 PB |
871 | static inline void tcg_gen_st32_i64(TCGv_i64 arg1, TCGv_ptr arg2, |
872 | tcg_target_long offset) | |
c896fe29 | 873 | { |
a7812ae4 | 874 | tcg_gen_st_i32(TCGV_LOW(arg1), arg2, offset); |
c896fe29 FB |
875 | } |
876 | ||
a7812ae4 PB |
877 | static inline void tcg_gen_st_i64(TCGv_i64 arg1, TCGv_ptr arg2, |
878 | tcg_target_long offset) | |
c896fe29 FB |
879 | { |
880 | #ifdef TCG_TARGET_WORDS_BIGENDIAN | |
ac56dd48 | 881 | tcg_gen_st_i32(TCGV_HIGH(arg1), arg2, offset); |
a7812ae4 | 882 | tcg_gen_st_i32(TCGV_LOW(arg1), arg2, offset + 4); |
c896fe29 | 883 | #else |
a7812ae4 | 884 | tcg_gen_st_i32(TCGV_LOW(arg1), arg2, offset); |
ac56dd48 | 885 | tcg_gen_st_i32(TCGV_HIGH(arg1), arg2, offset + 4); |
c896fe29 FB |
886 | #endif |
887 | } | |
888 | ||
a7812ae4 | 889 | static inline void tcg_gen_add_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
c896fe29 | 890 | { |
a7812ae4 PB |
891 | tcg_gen_op6_i32(INDEX_op_add2_i32, TCGV_LOW(ret), TCGV_HIGH(ret), |
892 | TCGV_LOW(arg1), TCGV_HIGH(arg1), TCGV_LOW(arg2), | |
893 | TCGV_HIGH(arg2)); | |
212c328d RH |
894 | /* Allow the optimizer room to replace add2 with two moves. */ |
895 | tcg_gen_op0(INDEX_op_nop); | |
c896fe29 FB |
896 | } |
897 | ||
a7812ae4 | 898 | static inline void tcg_gen_sub_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
c896fe29 | 899 | { |
a7812ae4 PB |
900 | tcg_gen_op6_i32(INDEX_op_sub2_i32, TCGV_LOW(ret), TCGV_HIGH(ret), |
901 | TCGV_LOW(arg1), TCGV_HIGH(arg1), TCGV_LOW(arg2), | |
902 | TCGV_HIGH(arg2)); | |
212c328d RH |
903 | /* Allow the optimizer room to replace sub2 with two moves. */ |
904 | tcg_gen_op0(INDEX_op_nop); | |
c896fe29 FB |
905 | } |
906 | ||
a7812ae4 | 907 | static inline void tcg_gen_and_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
c896fe29 | 908 | { |
a7812ae4 | 909 | tcg_gen_and_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2)); |
ac56dd48 | 910 | tcg_gen_and_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2)); |
c896fe29 FB |
911 | } |
912 | ||
a7812ae4 | 913 | static inline void tcg_gen_andi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
c896fe29 | 914 | { |
e5105083 AJ |
915 | tcg_gen_andi_i32(TCGV_LOW(ret), TCGV_LOW(arg1), arg2); |
916 | tcg_gen_andi_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), arg2 >> 32); | |
c896fe29 FB |
917 | } |
918 | ||
a7812ae4 | 919 | static inline void tcg_gen_or_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
c896fe29 | 920 | { |
e5105083 AJ |
921 | tcg_gen_or_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2)); |
922 | tcg_gen_or_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2)); | |
c896fe29 FB |
923 | } |
924 | ||
a7812ae4 | 925 | static inline void tcg_gen_ori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
c896fe29 | 926 | { |
a7812ae4 | 927 | tcg_gen_ori_i32(TCGV_LOW(ret), TCGV_LOW(arg1), arg2); |
ac56dd48 | 928 | tcg_gen_ori_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), arg2 >> 32); |
c896fe29 FB |
929 | } |
930 | ||
a7812ae4 | 931 | static inline void tcg_gen_xor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
c896fe29 | 932 | { |
e5105083 AJ |
933 | tcg_gen_xor_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2)); |
934 | tcg_gen_xor_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2)); | |
c896fe29 FB |
935 | } |
936 | ||
a7812ae4 | 937 | static inline void tcg_gen_xori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
c896fe29 | 938 | { |
a7812ae4 | 939 | tcg_gen_xori_i32(TCGV_LOW(ret), TCGV_LOW(arg1), arg2); |
ac56dd48 | 940 | tcg_gen_xori_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), arg2 >> 32); |
c896fe29 FB |
941 | } |
942 | ||
943 | /* XXX: use generic code when basic block handling is OK or CPU | |
944 | specific code (x86) */ | |
a7812ae4 | 945 | static inline void tcg_gen_shl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
c896fe29 | 946 | { |
2bece2c8 RH |
947 | int sizemask = 0; |
948 | /* Return value and both arguments are 64-bit and signed. */ | |
949 | sizemask |= tcg_gen_sizemask(0, 1, 1); | |
950 | sizemask |= tcg_gen_sizemask(1, 1, 1); | |
951 | sizemask |= tcg_gen_sizemask(2, 1, 1); | |
952 | ||
953 | tcg_gen_helper64(tcg_helper_shl_i64, sizemask, ret, arg1, arg2); | |
c896fe29 FB |
954 | } |
955 | ||
a7812ae4 | 956 | static inline void tcg_gen_shli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
c896fe29 FB |
957 | { |
958 | tcg_gen_shifti_i64(ret, arg1, arg2, 0, 0); | |
959 | } | |
960 | ||
a7812ae4 | 961 | static inline void tcg_gen_shr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
c896fe29 | 962 | { |
2bece2c8 RH |
963 | int sizemask = 0; |
964 | /* Return value and both arguments are 64-bit and signed. */ | |
965 | sizemask |= tcg_gen_sizemask(0, 1, 1); | |
966 | sizemask |= tcg_gen_sizemask(1, 1, 1); | |
967 | sizemask |= tcg_gen_sizemask(2, 1, 1); | |
968 | ||
969 | tcg_gen_helper64(tcg_helper_shr_i64, sizemask, ret, arg1, arg2); | |
c896fe29 FB |
970 | } |
971 | ||
a7812ae4 | 972 | static inline void tcg_gen_shri_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
c896fe29 FB |
973 | { |
974 | tcg_gen_shifti_i64(ret, arg1, arg2, 1, 0); | |
975 | } | |
976 | ||
a7812ae4 | 977 | static inline void tcg_gen_sar_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
c896fe29 | 978 | { |
2bece2c8 RH |
979 | int sizemask = 0; |
980 | /* Return value and both arguments are 64-bit and signed. */ | |
981 | sizemask |= tcg_gen_sizemask(0, 1, 1); | |
982 | sizemask |= tcg_gen_sizemask(1, 1, 1); | |
983 | sizemask |= tcg_gen_sizemask(2, 1, 1); | |
984 | ||
985 | tcg_gen_helper64(tcg_helper_sar_i64, sizemask, ret, arg1, arg2); | |
c896fe29 FB |
986 | } |
987 | ||
a7812ae4 | 988 | static inline void tcg_gen_sari_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
c896fe29 FB |
989 | { |
990 | tcg_gen_shifti_i64(ret, arg1, arg2, 1, 1); | |
991 | } | |
992 | ||
8a56e840 RH |
993 | static inline void tcg_gen_brcond_i64(TCGCond cond, TCGv_i64 arg1, |
994 | TCGv_i64 arg2, int label_index) | |
c896fe29 | 995 | { |
0aed257f RH |
996 | if (cond == TCG_COND_ALWAYS) { |
997 | tcg_gen_br(label_index); | |
998 | } else if (cond != TCG_COND_NEVER) { | |
999 | tcg_gen_op6ii_i32(INDEX_op_brcond2_i32, | |
1000 | TCGV_LOW(arg1), TCGV_HIGH(arg1), TCGV_LOW(arg2), | |
1001 | TCGV_HIGH(arg2), cond, label_index); | |
1002 | } | |
c896fe29 FB |
1003 | } |
1004 | ||
8a56e840 | 1005 | static inline void tcg_gen_setcond_i64(TCGCond cond, TCGv_i64 ret, |
5105c556 AJ |
1006 | TCGv_i64 arg1, TCGv_i64 arg2) |
1007 | { | |
0aed257f RH |
1008 | if (cond == TCG_COND_ALWAYS) { |
1009 | tcg_gen_movi_i32(TCGV_LOW(ret), 1); | |
1010 | } else if (cond == TCG_COND_NEVER) { | |
1011 | tcg_gen_movi_i32(TCGV_LOW(ret), 0); | |
1012 | } else { | |
1013 | tcg_gen_op6i_i32(INDEX_op_setcond2_i32, TCGV_LOW(ret), | |
1014 | TCGV_LOW(arg1), TCGV_HIGH(arg1), | |
1015 | TCGV_LOW(arg2), TCGV_HIGH(arg2), cond); | |
1016 | } | |
5105c556 AJ |
1017 | tcg_gen_movi_i32(TCGV_HIGH(ret), 0); |
1018 | } | |
1019 | ||
a7812ae4 | 1020 | static inline void tcg_gen_mul_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
c896fe29 | 1021 | { |
a7812ae4 PB |
1022 | TCGv_i64 t0; |
1023 | TCGv_i32 t1; | |
c896fe29 | 1024 | |
a7812ae4 PB |
1025 | t0 = tcg_temp_new_i64(); |
1026 | t1 = tcg_temp_new_i32(); | |
1027 | ||
1028 | tcg_gen_op4_i32(INDEX_op_mulu2_i32, TCGV_LOW(t0), TCGV_HIGH(t0), | |
1029 | TCGV_LOW(arg1), TCGV_LOW(arg2)); | |
1030 | ||
1031 | tcg_gen_mul_i32(t1, TCGV_LOW(arg1), TCGV_HIGH(arg2)); | |
ac56dd48 | 1032 | tcg_gen_add_i32(TCGV_HIGH(t0), TCGV_HIGH(t0), t1); |
a7812ae4 | 1033 | tcg_gen_mul_i32(t1, TCGV_HIGH(arg1), TCGV_LOW(arg2)); |
ac56dd48 | 1034 | tcg_gen_add_i32(TCGV_HIGH(t0), TCGV_HIGH(t0), t1); |
a7812ae4 | 1035 | |
c896fe29 | 1036 | tcg_gen_mov_i64(ret, t0); |
a7812ae4 PB |
1037 | tcg_temp_free_i64(t0); |
1038 | tcg_temp_free_i32(t1); | |
c896fe29 FB |
1039 | } |
1040 | ||
a7812ae4 | 1041 | static inline void tcg_gen_div_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
c896fe29 | 1042 | { |
2bece2c8 RH |
1043 | int sizemask = 0; |
1044 | /* Return value and both arguments are 64-bit and signed. */ | |
1045 | sizemask |= tcg_gen_sizemask(0, 1, 1); | |
1046 | sizemask |= tcg_gen_sizemask(1, 1, 1); | |
1047 | sizemask |= tcg_gen_sizemask(2, 1, 1); | |
1048 | ||
1049 | tcg_gen_helper64(tcg_helper_div_i64, sizemask, ret, arg1, arg2); | |
c896fe29 FB |
1050 | } |
1051 | ||
a7812ae4 | 1052 | static inline void tcg_gen_rem_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
c896fe29 | 1053 | { |
2bece2c8 RH |
1054 | int sizemask = 0; |
1055 | /* Return value and both arguments are 64-bit and signed. */ | |
1056 | sizemask |= tcg_gen_sizemask(0, 1, 1); | |
1057 | sizemask |= tcg_gen_sizemask(1, 1, 1); | |
1058 | sizemask |= tcg_gen_sizemask(2, 1, 1); | |
1059 | ||
1060 | tcg_gen_helper64(tcg_helper_rem_i64, sizemask, ret, arg1, arg2); | |
c896fe29 FB |
1061 | } |
1062 | ||
a7812ae4 | 1063 | static inline void tcg_gen_divu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
c896fe29 | 1064 | { |
2bece2c8 RH |
1065 | int sizemask = 0; |
1066 | /* Return value and both arguments are 64-bit and unsigned. */ | |
1067 | sizemask |= tcg_gen_sizemask(0, 1, 0); | |
1068 | sizemask |= tcg_gen_sizemask(1, 1, 0); | |
1069 | sizemask |= tcg_gen_sizemask(2, 1, 0); | |
1070 | ||
1071 | tcg_gen_helper64(tcg_helper_divu_i64, sizemask, ret, arg1, arg2); | |
c896fe29 FB |
1072 | } |
1073 | ||
a7812ae4 | 1074 | static inline void tcg_gen_remu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
c896fe29 | 1075 | { |
2bece2c8 RH |
1076 | int sizemask = 0; |
1077 | /* Return value and both arguments are 64-bit and unsigned. */ | |
1078 | sizemask |= tcg_gen_sizemask(0, 1, 0); | |
1079 | sizemask |= tcg_gen_sizemask(1, 1, 0); | |
1080 | sizemask |= tcg_gen_sizemask(2, 1, 0); | |
1081 | ||
1082 | tcg_gen_helper64(tcg_helper_remu_i64, sizemask, ret, arg1, arg2); | |
c896fe29 FB |
1083 | } |
1084 | ||
1085 | #else | |
1086 | ||
a7812ae4 | 1087 | static inline void tcg_gen_mov_i64(TCGv_i64 ret, TCGv_i64 arg) |
c896fe29 | 1088 | { |
fe75bcf7 | 1089 | if (!TCGV_EQUAL_I64(ret, arg)) |
a7812ae4 | 1090 | tcg_gen_op2_i64(INDEX_op_mov_i64, ret, arg); |
c896fe29 FB |
1091 | } |
1092 | ||
a7812ae4 | 1093 | static inline void tcg_gen_movi_i64(TCGv_i64 ret, int64_t arg) |
c896fe29 | 1094 | { |
a7812ae4 | 1095 | tcg_gen_op2i_i64(INDEX_op_movi_i64, ret, arg); |
c896fe29 FB |
1096 | } |
1097 | ||
6bd4b08a | 1098 | static inline void tcg_gen_ld8u_i64(TCGv_i64 ret, TCGv_ptr arg2, |
ac56dd48 | 1099 | tcg_target_long offset) |
c896fe29 | 1100 | { |
a7812ae4 | 1101 | tcg_gen_ldst_op_i64(INDEX_op_ld8u_i64, ret, arg2, offset); |
c896fe29 FB |
1102 | } |
1103 | ||
6bd4b08a | 1104 | static inline void tcg_gen_ld8s_i64(TCGv_i64 ret, TCGv_ptr arg2, |
ac56dd48 | 1105 | tcg_target_long offset) |
c896fe29 | 1106 | { |
a7812ae4 | 1107 | tcg_gen_ldst_op_i64(INDEX_op_ld8s_i64, ret, arg2, offset); |
c896fe29 FB |
1108 | } |
1109 | ||
6bd4b08a | 1110 | static inline void tcg_gen_ld16u_i64(TCGv_i64 ret, TCGv_ptr arg2, |
ac56dd48 | 1111 | tcg_target_long offset) |
c896fe29 | 1112 | { |
a7812ae4 | 1113 | tcg_gen_ldst_op_i64(INDEX_op_ld16u_i64, ret, arg2, offset); |
c896fe29 FB |
1114 | } |
1115 | ||
6bd4b08a | 1116 | static inline void tcg_gen_ld16s_i64(TCGv_i64 ret, TCGv_ptr arg2, |
ac56dd48 | 1117 | tcg_target_long offset) |
c896fe29 | 1118 | { |
a7812ae4 | 1119 | tcg_gen_ldst_op_i64(INDEX_op_ld16s_i64, ret, arg2, offset); |
c896fe29 FB |
1120 | } |
1121 | ||
6bd4b08a | 1122 | static inline void tcg_gen_ld32u_i64(TCGv_i64 ret, TCGv_ptr arg2, |
ac56dd48 | 1123 | tcg_target_long offset) |
c896fe29 | 1124 | { |
a7812ae4 | 1125 | tcg_gen_ldst_op_i64(INDEX_op_ld32u_i64, ret, arg2, offset); |
c896fe29 FB |
1126 | } |
1127 | ||
6bd4b08a | 1128 | static inline void tcg_gen_ld32s_i64(TCGv_i64 ret, TCGv_ptr arg2, |
ac56dd48 | 1129 | tcg_target_long offset) |
c896fe29 | 1130 | { |
a7812ae4 | 1131 | tcg_gen_ldst_op_i64(INDEX_op_ld32s_i64, ret, arg2, offset); |
c896fe29 FB |
1132 | } |
1133 | ||
6bd4b08a | 1134 | static inline void tcg_gen_ld_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset) |
c896fe29 | 1135 | { |
a7812ae4 | 1136 | tcg_gen_ldst_op_i64(INDEX_op_ld_i64, ret, arg2, offset); |
c896fe29 FB |
1137 | } |
1138 | ||
6bd4b08a | 1139 | static inline void tcg_gen_st8_i64(TCGv_i64 arg1, TCGv_ptr arg2, |
ac56dd48 | 1140 | tcg_target_long offset) |
c896fe29 | 1141 | { |
a7812ae4 | 1142 | tcg_gen_ldst_op_i64(INDEX_op_st8_i64, arg1, arg2, offset); |
c896fe29 FB |
1143 | } |
1144 | ||
6bd4b08a | 1145 | static inline void tcg_gen_st16_i64(TCGv_i64 arg1, TCGv_ptr arg2, |
ac56dd48 | 1146 | tcg_target_long offset) |
c896fe29 | 1147 | { |
a7812ae4 | 1148 | tcg_gen_ldst_op_i64(INDEX_op_st16_i64, arg1, arg2, offset); |
c896fe29 FB |
1149 | } |
1150 | ||
6bd4b08a | 1151 | static inline void tcg_gen_st32_i64(TCGv_i64 arg1, TCGv_ptr arg2, |
ac56dd48 | 1152 | tcg_target_long offset) |
c896fe29 | 1153 | { |
a7812ae4 | 1154 | tcg_gen_ldst_op_i64(INDEX_op_st32_i64, arg1, arg2, offset); |
c896fe29 FB |
1155 | } |
1156 | ||
6bd4b08a | 1157 | static inline void tcg_gen_st_i64(TCGv_i64 arg1, TCGv_ptr arg2, tcg_target_long offset) |
c896fe29 | 1158 | { |
a7812ae4 | 1159 | tcg_gen_ldst_op_i64(INDEX_op_st_i64, arg1, arg2, offset); |
c896fe29 FB |
1160 | } |
1161 | ||
a7812ae4 | 1162 | static inline void tcg_gen_add_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
c896fe29 | 1163 | { |
a7812ae4 | 1164 | tcg_gen_op3_i64(INDEX_op_add_i64, ret, arg1, arg2); |
c896fe29 FB |
1165 | } |
1166 | ||
a7812ae4 | 1167 | static inline void tcg_gen_sub_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
c896fe29 | 1168 | { |
a7812ae4 | 1169 | tcg_gen_op3_i64(INDEX_op_sub_i64, ret, arg1, arg2); |
c896fe29 FB |
1170 | } |
1171 | ||
a7812ae4 | 1172 | static inline void tcg_gen_and_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
c896fe29 | 1173 | { |
7fc81051 AJ |
1174 | if (TCGV_EQUAL_I64(arg1, arg2)) { |
1175 | tcg_gen_mov_i64(ret, arg1); | |
1176 | } else { | |
1177 | tcg_gen_op3_i64(INDEX_op_and_i64, ret, arg1, arg2); | |
1178 | } | |
c896fe29 FB |
1179 | } |
1180 | ||
42ce3e20 | 1181 | static inline void tcg_gen_andi_i64(TCGv_i64 ret, TCGv_i64 arg1, uint64_t arg2) |
c896fe29 | 1182 | { |
42ce3e20 RH |
1183 | TCGv_i64 t0; |
1184 | /* Some cases can be optimized here. */ | |
1185 | switch (arg2) { | |
1186 | case 0: | |
1187 | tcg_gen_movi_i64(ret, 0); | |
1188 | return; | |
1189 | case 0xffffffffffffffffull: | |
1190 | tcg_gen_mov_i64(ret, arg1); | |
1191 | return; | |
1192 | case 0xffull: | |
1193 | /* Don't recurse with tcg_gen_ext8u_i32. */ | |
1194 | if (TCG_TARGET_HAS_ext8u_i64) { | |
1195 | tcg_gen_op2_i64(INDEX_op_ext8u_i64, ret, arg1); | |
1196 | return; | |
1197 | } | |
1198 | break; | |
1199 | case 0xffffu: | |
1200 | if (TCG_TARGET_HAS_ext16u_i64) { | |
1201 | tcg_gen_op2_i64(INDEX_op_ext16u_i64, ret, arg1); | |
1202 | return; | |
1203 | } | |
1204 | break; | |
1205 | case 0xffffffffull: | |
1206 | if (TCG_TARGET_HAS_ext32u_i64) { | |
1207 | tcg_gen_op2_i64(INDEX_op_ext32u_i64, ret, arg1); | |
1208 | return; | |
1209 | } | |
1210 | break; | |
1211 | } | |
1212 | t0 = tcg_const_i64(arg2); | |
e8996ee0 | 1213 | tcg_gen_and_i64(ret, arg1, t0); |
a7812ae4 | 1214 | tcg_temp_free_i64(t0); |
c896fe29 FB |
1215 | } |
1216 | ||
a7812ae4 | 1217 | static inline void tcg_gen_or_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
c896fe29 | 1218 | { |
7fc81051 AJ |
1219 | if (TCGV_EQUAL_I64(arg1, arg2)) { |
1220 | tcg_gen_mov_i64(ret, arg1); | |
1221 | } else { | |
1222 | tcg_gen_op3_i64(INDEX_op_or_i64, ret, arg1, arg2); | |
1223 | } | |
c896fe29 FB |
1224 | } |
1225 | ||
a7812ae4 | 1226 | static inline void tcg_gen_ori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
c896fe29 | 1227 | { |
d81ada7f RH |
1228 | /* Some cases can be optimized here. */ |
1229 | if (arg2 == -1) { | |
1230 | tcg_gen_movi_i64(ret, -1); | |
1231 | } else if (arg2 == 0) { | |
1232 | tcg_gen_mov_i64(ret, arg1); | |
1233 | } else { | |
1234 | TCGv_i64 t0 = tcg_const_i64(arg2); | |
1235 | tcg_gen_or_i64(ret, arg1, t0); | |
1236 | tcg_temp_free_i64(t0); | |
1237 | } | |
c896fe29 FB |
1238 | } |
1239 | ||
a7812ae4 | 1240 | static inline void tcg_gen_xor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
c896fe29 | 1241 | { |
7fc81051 AJ |
1242 | if (TCGV_EQUAL_I64(arg1, arg2)) { |
1243 | tcg_gen_movi_i64(ret, 0); | |
1244 | } else { | |
1245 | tcg_gen_op3_i64(INDEX_op_xor_i64, ret, arg1, arg2); | |
1246 | } | |
c896fe29 FB |
1247 | } |
1248 | ||
a7812ae4 | 1249 | static inline void tcg_gen_xori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
c896fe29 | 1250 | { |
6f3bb33e RH |
1251 | /* Some cases can be optimized here. */ |
1252 | if (arg2 == 0) { | |
1253 | tcg_gen_mov_i64(ret, arg1); | |
1254 | } else if (arg2 == -1 && TCG_TARGET_HAS_not_i64) { | |
1255 | /* Don't recurse with tcg_gen_not_i64. */ | |
1256 | tcg_gen_op2_i64(INDEX_op_not_i64, ret, arg1); | |
1257 | } else { | |
1258 | TCGv_i64 t0 = tcg_const_i64(arg2); | |
1259 | tcg_gen_xor_i64(ret, arg1, t0); | |
1260 | tcg_temp_free_i64(t0); | |
1261 | } | |
c896fe29 FB |
1262 | } |
1263 | ||
a7812ae4 | 1264 | static inline void tcg_gen_shl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
c896fe29 | 1265 | { |
a7812ae4 | 1266 | tcg_gen_op3_i64(INDEX_op_shl_i64, ret, arg1, arg2); |
c896fe29 FB |
1267 | } |
1268 | ||
a7812ae4 | 1269 | static inline void tcg_gen_shli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
c896fe29 | 1270 | { |
34151a20 FB |
1271 | if (arg2 == 0) { |
1272 | tcg_gen_mov_i64(ret, arg1); | |
1273 | } else { | |
a7812ae4 | 1274 | TCGv_i64 t0 = tcg_const_i64(arg2); |
e8996ee0 | 1275 | tcg_gen_shl_i64(ret, arg1, t0); |
a7812ae4 | 1276 | tcg_temp_free_i64(t0); |
34151a20 | 1277 | } |
c896fe29 FB |
1278 | } |
1279 | ||
a7812ae4 | 1280 | static inline void tcg_gen_shr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
c896fe29 | 1281 | { |
a7812ae4 | 1282 | tcg_gen_op3_i64(INDEX_op_shr_i64, ret, arg1, arg2); |
c896fe29 FB |
1283 | } |
1284 | ||
a7812ae4 | 1285 | static inline void tcg_gen_shri_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
c896fe29 | 1286 | { |
34151a20 FB |
1287 | if (arg2 == 0) { |
1288 | tcg_gen_mov_i64(ret, arg1); | |
1289 | } else { | |
a7812ae4 | 1290 | TCGv_i64 t0 = tcg_const_i64(arg2); |
e8996ee0 | 1291 | tcg_gen_shr_i64(ret, arg1, t0); |
a7812ae4 | 1292 | tcg_temp_free_i64(t0); |
34151a20 | 1293 | } |
c896fe29 FB |
1294 | } |
1295 | ||
a7812ae4 | 1296 | static inline void tcg_gen_sar_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
c896fe29 | 1297 | { |
a7812ae4 | 1298 | tcg_gen_op3_i64(INDEX_op_sar_i64, ret, arg1, arg2); |
c896fe29 FB |
1299 | } |
1300 | ||
a7812ae4 | 1301 | static inline void tcg_gen_sari_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
c896fe29 | 1302 | { |
34151a20 FB |
1303 | if (arg2 == 0) { |
1304 | tcg_gen_mov_i64(ret, arg1); | |
1305 | } else { | |
a7812ae4 | 1306 | TCGv_i64 t0 = tcg_const_i64(arg2); |
e8996ee0 | 1307 | tcg_gen_sar_i64(ret, arg1, t0); |
a7812ae4 | 1308 | tcg_temp_free_i64(t0); |
34151a20 | 1309 | } |
c896fe29 FB |
1310 | } |
1311 | ||
8a56e840 RH |
1312 | static inline void tcg_gen_brcond_i64(TCGCond cond, TCGv_i64 arg1, |
1313 | TCGv_i64 arg2, int label_index) | |
c896fe29 | 1314 | { |
0aed257f RH |
1315 | if (cond == TCG_COND_ALWAYS) { |
1316 | tcg_gen_br(label_index); | |
1317 | } else if (cond != TCG_COND_NEVER) { | |
1318 | tcg_gen_op4ii_i64(INDEX_op_brcond_i64, arg1, arg2, cond, label_index); | |
1319 | } | |
c896fe29 FB |
1320 | } |
1321 | ||
8a56e840 | 1322 | static inline void tcg_gen_setcond_i64(TCGCond cond, TCGv_i64 ret, |
5105c556 AJ |
1323 | TCGv_i64 arg1, TCGv_i64 arg2) |
1324 | { | |
0aed257f RH |
1325 | if (cond == TCG_COND_ALWAYS) { |
1326 | tcg_gen_movi_i64(ret, 1); | |
1327 | } else if (cond == TCG_COND_NEVER) { | |
1328 | tcg_gen_movi_i64(ret, 0); | |
1329 | } else { | |
1330 | tcg_gen_op4i_i64(INDEX_op_setcond_i64, ret, arg1, arg2, cond); | |
1331 | } | |
5105c556 AJ |
1332 | } |
1333 | ||
a7812ae4 | 1334 | static inline void tcg_gen_mul_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
c896fe29 | 1335 | { |
a7812ae4 | 1336 | tcg_gen_op3_i64(INDEX_op_mul_i64, ret, arg1, arg2); |
c896fe29 FB |
1337 | } |
1338 | ||
31d66551 AJ |
1339 | static inline void tcg_gen_div_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
1340 | { | |
25c4d9cc RH |
1341 | if (TCG_TARGET_HAS_div_i64) { |
1342 | tcg_gen_op3_i64(INDEX_op_div_i64, ret, arg1, arg2); | |
1343 | } else if (TCG_TARGET_HAS_div2_i64) { | |
1344 | TCGv_i64 t0 = tcg_temp_new_i64(); | |
1345 | tcg_gen_sari_i64(t0, arg1, 63); | |
1346 | tcg_gen_op5_i64(INDEX_op_div2_i64, ret, t0, arg1, t0, arg2); | |
1347 | tcg_temp_free_i64(t0); | |
1348 | } else { | |
1349 | int sizemask = 0; | |
1350 | /* Return value and both arguments are 64-bit and signed. */ | |
1351 | sizemask |= tcg_gen_sizemask(0, 1, 1); | |
1352 | sizemask |= tcg_gen_sizemask(1, 1, 1); | |
1353 | sizemask |= tcg_gen_sizemask(2, 1, 1); | |
1354 | tcg_gen_helper64(tcg_helper_div_i64, sizemask, ret, arg1, arg2); | |
1355 | } | |
31d66551 AJ |
1356 | } |
1357 | ||
1358 | static inline void tcg_gen_rem_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) | |
1359 | { | |
25c4d9cc RH |
1360 | if (TCG_TARGET_HAS_div_i64) { |
1361 | tcg_gen_op3_i64(INDEX_op_rem_i64, ret, arg1, arg2); | |
1362 | } else if (TCG_TARGET_HAS_div2_i64) { | |
1363 | TCGv_i64 t0 = tcg_temp_new_i64(); | |
1364 | tcg_gen_sari_i64(t0, arg1, 63); | |
1365 | tcg_gen_op5_i64(INDEX_op_div2_i64, t0, ret, arg1, t0, arg2); | |
1366 | tcg_temp_free_i64(t0); | |
1367 | } else { | |
1368 | int sizemask = 0; | |
1369 | /* Return value and both arguments are 64-bit and signed. */ | |
1370 | sizemask |= tcg_gen_sizemask(0, 1, 1); | |
1371 | sizemask |= tcg_gen_sizemask(1, 1, 1); | |
1372 | sizemask |= tcg_gen_sizemask(2, 1, 1); | |
1373 | tcg_gen_helper64(tcg_helper_rem_i64, sizemask, ret, arg1, arg2); | |
1374 | } | |
31d66551 AJ |
1375 | } |
1376 | ||
1377 | static inline void tcg_gen_divu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) | |
1378 | { | |
25c4d9cc RH |
1379 | if (TCG_TARGET_HAS_div_i64) { |
1380 | tcg_gen_op3_i64(INDEX_op_divu_i64, ret, arg1, arg2); | |
1381 | } else if (TCG_TARGET_HAS_div2_i64) { | |
1382 | TCGv_i64 t0 = tcg_temp_new_i64(); | |
1383 | tcg_gen_movi_i64(t0, 0); | |
1384 | tcg_gen_op5_i64(INDEX_op_divu2_i64, ret, t0, arg1, t0, arg2); | |
1385 | tcg_temp_free_i64(t0); | |
1386 | } else { | |
1387 | int sizemask = 0; | |
1388 | /* Return value and both arguments are 64-bit and unsigned. */ | |
1389 | sizemask |= tcg_gen_sizemask(0, 1, 0); | |
1390 | sizemask |= tcg_gen_sizemask(1, 1, 0); | |
1391 | sizemask |= tcg_gen_sizemask(2, 1, 0); | |
1392 | tcg_gen_helper64(tcg_helper_divu_i64, sizemask, ret, arg1, arg2); | |
1393 | } | |
31d66551 AJ |
1394 | } |
1395 | ||
1396 | static inline void tcg_gen_remu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) | |
1397 | { | |
25c4d9cc RH |
1398 | if (TCG_TARGET_HAS_div_i64) { |
1399 | tcg_gen_op3_i64(INDEX_op_remu_i64, ret, arg1, arg2); | |
1400 | } else if (TCG_TARGET_HAS_div2_i64) { | |
1401 | TCGv_i64 t0 = tcg_temp_new_i64(); | |
1402 | tcg_gen_movi_i64(t0, 0); | |
1403 | tcg_gen_op5_i64(INDEX_op_divu2_i64, t0, ret, arg1, t0, arg2); | |
1404 | tcg_temp_free_i64(t0); | |
1405 | } else { | |
1406 | int sizemask = 0; | |
1407 | /* Return value and both arguments are 64-bit and unsigned. */ | |
1408 | sizemask |= tcg_gen_sizemask(0, 1, 0); | |
1409 | sizemask |= tcg_gen_sizemask(1, 1, 0); | |
1410 | sizemask |= tcg_gen_sizemask(2, 1, 0); | |
1411 | tcg_gen_helper64(tcg_helper_remu_i64, sizemask, ret, arg1, arg2); | |
1412 | } | |
31d66551 | 1413 | } |
25c4d9cc | 1414 | #endif /* TCG_TARGET_REG_BITS == 32 */ |
c896fe29 | 1415 | |
a7812ae4 | 1416 | static inline void tcg_gen_addi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
6359706f AJ |
1417 | { |
1418 | /* some cases can be optimized here */ | |
1419 | if (arg2 == 0) { | |
1420 | tcg_gen_mov_i64(ret, arg1); | |
1421 | } else { | |
a7812ae4 | 1422 | TCGv_i64 t0 = tcg_const_i64(arg2); |
6359706f | 1423 | tcg_gen_add_i64(ret, arg1, t0); |
a7812ae4 | 1424 | tcg_temp_free_i64(t0); |
6359706f AJ |
1425 | } |
1426 | } | |
1427 | ||
a7812ae4 | 1428 | static inline void tcg_gen_subfi_i64(TCGv_i64 ret, int64_t arg1, TCGv_i64 arg2) |
0045734a | 1429 | { |
a7812ae4 | 1430 | TCGv_i64 t0 = tcg_const_i64(arg1); |
0045734a | 1431 | tcg_gen_sub_i64(ret, t0, arg2); |
a7812ae4 | 1432 | tcg_temp_free_i64(t0); |
0045734a AJ |
1433 | } |
1434 | ||
a7812ae4 | 1435 | static inline void tcg_gen_subi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
6359706f AJ |
1436 | { |
1437 | /* some cases can be optimized here */ | |
1438 | if (arg2 == 0) { | |
1439 | tcg_gen_mov_i64(ret, arg1); | |
1440 | } else { | |
a7812ae4 | 1441 | TCGv_i64 t0 = tcg_const_i64(arg2); |
6359706f | 1442 | tcg_gen_sub_i64(ret, arg1, t0); |
a7812ae4 | 1443 | tcg_temp_free_i64(t0); |
6359706f AJ |
1444 | } |
1445 | } | |
8a56e840 RH |
1446 | static inline void tcg_gen_brcondi_i64(TCGCond cond, TCGv_i64 arg1, |
1447 | int64_t arg2, int label_index) | |
f02bb954 | 1448 | { |
0aed257f RH |
1449 | if (cond == TCG_COND_ALWAYS) { |
1450 | tcg_gen_br(label_index); | |
1451 | } else if (cond != TCG_COND_NEVER) { | |
1452 | TCGv_i64 t0 = tcg_const_i64(arg2); | |
1453 | tcg_gen_brcond_i64(cond, arg1, t0, label_index); | |
1454 | tcg_temp_free_i64(t0); | |
1455 | } | |
f02bb954 AJ |
1456 | } |
1457 | ||
8a56e840 RH |
1458 | static inline void tcg_gen_setcondi_i64(TCGCond cond, TCGv_i64 ret, |
1459 | TCGv_i64 arg1, int64_t arg2) | |
5105c556 AJ |
1460 | { |
1461 | TCGv_i64 t0 = tcg_const_i64(arg2); | |
1462 | tcg_gen_setcond_i64(cond, ret, arg1, t0); | |
1463 | tcg_temp_free_i64(t0); | |
1464 | } | |
1465 | ||
a7812ae4 | 1466 | static inline void tcg_gen_muli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
f02bb954 | 1467 | { |
a7812ae4 | 1468 | TCGv_i64 t0 = tcg_const_i64(arg2); |
f02bb954 | 1469 | tcg_gen_mul_i64(ret, arg1, t0); |
a7812ae4 | 1470 | tcg_temp_free_i64(t0); |
f02bb954 AJ |
1471 | } |
1472 | ||
6359706f | 1473 | |
c896fe29 FB |
1474 | /***************************************/ |
1475 | /* optional operations */ | |
1476 | ||
a7812ae4 | 1477 | static inline void tcg_gen_ext8s_i32(TCGv_i32 ret, TCGv_i32 arg) |
c896fe29 | 1478 | { |
25c4d9cc RH |
1479 | if (TCG_TARGET_HAS_ext8s_i32) { |
1480 | tcg_gen_op2_i32(INDEX_op_ext8s_i32, ret, arg); | |
1481 | } else { | |
1482 | tcg_gen_shli_i32(ret, arg, 24); | |
1483 | tcg_gen_sari_i32(ret, ret, 24); | |
1484 | } | |
c896fe29 FB |
1485 | } |
1486 | ||
a7812ae4 | 1487 | static inline void tcg_gen_ext16s_i32(TCGv_i32 ret, TCGv_i32 arg) |
c896fe29 | 1488 | { |
25c4d9cc RH |
1489 | if (TCG_TARGET_HAS_ext16s_i32) { |
1490 | tcg_gen_op2_i32(INDEX_op_ext16s_i32, ret, arg); | |
1491 | } else { | |
1492 | tcg_gen_shli_i32(ret, arg, 16); | |
1493 | tcg_gen_sari_i32(ret, ret, 16); | |
1494 | } | |
c896fe29 FB |
1495 | } |
1496 | ||
a7812ae4 | 1497 | static inline void tcg_gen_ext8u_i32(TCGv_i32 ret, TCGv_i32 arg) |
86831435 | 1498 | { |
25c4d9cc RH |
1499 | if (TCG_TARGET_HAS_ext8u_i32) { |
1500 | tcg_gen_op2_i32(INDEX_op_ext8u_i32, ret, arg); | |
1501 | } else { | |
1502 | tcg_gen_andi_i32(ret, arg, 0xffu); | |
1503 | } | |
86831435 PB |
1504 | } |
1505 | ||
a7812ae4 | 1506 | static inline void tcg_gen_ext16u_i32(TCGv_i32 ret, TCGv_i32 arg) |
86831435 | 1507 | { |
25c4d9cc RH |
1508 | if (TCG_TARGET_HAS_ext16u_i32) { |
1509 | tcg_gen_op2_i32(INDEX_op_ext16u_i32, ret, arg); | |
1510 | } else { | |
1511 | tcg_gen_andi_i32(ret, arg, 0xffffu); | |
1512 | } | |
86831435 PB |
1513 | } |
1514 | ||
c896fe29 | 1515 | /* Note: we assume the two high bytes are set to zero */ |
a7812ae4 | 1516 | static inline void tcg_gen_bswap16_i32(TCGv_i32 ret, TCGv_i32 arg) |
c896fe29 | 1517 | { |
25c4d9cc RH |
1518 | if (TCG_TARGET_HAS_bswap16_i32) { |
1519 | tcg_gen_op2_i32(INDEX_op_bswap16_i32, ret, arg); | |
1520 | } else { | |
1521 | TCGv_i32 t0 = tcg_temp_new_i32(); | |
c896fe29 | 1522 | |
25c4d9cc RH |
1523 | tcg_gen_ext8u_i32(t0, arg); |
1524 | tcg_gen_shli_i32(t0, t0, 8); | |
1525 | tcg_gen_shri_i32(ret, arg, 8); | |
1526 | tcg_gen_or_i32(ret, ret, t0); | |
1527 | tcg_temp_free_i32(t0); | |
1528 | } | |
c896fe29 FB |
1529 | } |
1530 | ||
66896cb8 | 1531 | static inline void tcg_gen_bswap32_i32(TCGv_i32 ret, TCGv_i32 arg) |
c896fe29 | 1532 | { |
25c4d9cc RH |
1533 | if (TCG_TARGET_HAS_bswap32_i32) { |
1534 | tcg_gen_op2_i32(INDEX_op_bswap32_i32, ret, arg); | |
1535 | } else { | |
1536 | TCGv_i32 t0, t1; | |
1537 | t0 = tcg_temp_new_i32(); | |
1538 | t1 = tcg_temp_new_i32(); | |
c896fe29 | 1539 | |
25c4d9cc | 1540 | tcg_gen_shli_i32(t0, arg, 24); |
c896fe29 | 1541 | |
25c4d9cc RH |
1542 | tcg_gen_andi_i32(t1, arg, 0x0000ff00); |
1543 | tcg_gen_shli_i32(t1, t1, 8); | |
1544 | tcg_gen_or_i32(t0, t0, t1); | |
c896fe29 | 1545 | |
25c4d9cc RH |
1546 | tcg_gen_shri_i32(t1, arg, 8); |
1547 | tcg_gen_andi_i32(t1, t1, 0x0000ff00); | |
1548 | tcg_gen_or_i32(t0, t0, t1); | |
c896fe29 | 1549 | |
25c4d9cc RH |
1550 | tcg_gen_shri_i32(t1, arg, 24); |
1551 | tcg_gen_or_i32(ret, t0, t1); | |
1552 | tcg_temp_free_i32(t0); | |
1553 | tcg_temp_free_i32(t1); | |
1554 | } | |
c896fe29 FB |
1555 | } |
1556 | ||
1557 | #if TCG_TARGET_REG_BITS == 32 | |
a7812ae4 | 1558 | static inline void tcg_gen_ext8s_i64(TCGv_i64 ret, TCGv_i64 arg) |
c896fe29 | 1559 | { |
a7812ae4 PB |
1560 | tcg_gen_ext8s_i32(TCGV_LOW(ret), TCGV_LOW(arg)); |
1561 | tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31); | |
c896fe29 FB |
1562 | } |
1563 | ||
a7812ae4 | 1564 | static inline void tcg_gen_ext16s_i64(TCGv_i64 ret, TCGv_i64 arg) |
c896fe29 | 1565 | { |
a7812ae4 PB |
1566 | tcg_gen_ext16s_i32(TCGV_LOW(ret), TCGV_LOW(arg)); |
1567 | tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31); | |
c896fe29 FB |
1568 | } |
1569 | ||
a7812ae4 | 1570 | static inline void tcg_gen_ext32s_i64(TCGv_i64 ret, TCGv_i64 arg) |
c896fe29 | 1571 | { |
a7812ae4 PB |
1572 | tcg_gen_mov_i32(TCGV_LOW(ret), TCGV_LOW(arg)); |
1573 | tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31); | |
c896fe29 FB |
1574 | } |
1575 | ||
a7812ae4 | 1576 | static inline void tcg_gen_ext8u_i64(TCGv_i64 ret, TCGv_i64 arg) |
86831435 | 1577 | { |
a7812ae4 | 1578 | tcg_gen_ext8u_i32(TCGV_LOW(ret), TCGV_LOW(arg)); |
86831435 PB |
1579 | tcg_gen_movi_i32(TCGV_HIGH(ret), 0); |
1580 | } | |
1581 | ||
a7812ae4 | 1582 | static inline void tcg_gen_ext16u_i64(TCGv_i64 ret, TCGv_i64 arg) |
86831435 | 1583 | { |
a7812ae4 | 1584 | tcg_gen_ext16u_i32(TCGV_LOW(ret), TCGV_LOW(arg)); |
86831435 PB |
1585 | tcg_gen_movi_i32(TCGV_HIGH(ret), 0); |
1586 | } | |
1587 | ||
a7812ae4 | 1588 | static inline void tcg_gen_ext32u_i64(TCGv_i64 ret, TCGv_i64 arg) |
86831435 | 1589 | { |
a7812ae4 | 1590 | tcg_gen_mov_i32(TCGV_LOW(ret), TCGV_LOW(arg)); |
86831435 PB |
1591 | tcg_gen_movi_i32(TCGV_HIGH(ret), 0); |
1592 | } | |
1593 | ||
a7812ae4 | 1594 | static inline void tcg_gen_trunc_i64_i32(TCGv_i32 ret, TCGv_i64 arg) |
c896fe29 | 1595 | { |
a7812ae4 | 1596 | tcg_gen_mov_i32(ret, TCGV_LOW(arg)); |
c896fe29 FB |
1597 | } |
1598 | ||
a7812ae4 | 1599 | static inline void tcg_gen_extu_i32_i64(TCGv_i64 ret, TCGv_i32 arg) |
c896fe29 | 1600 | { |
a7812ae4 | 1601 | tcg_gen_mov_i32(TCGV_LOW(ret), arg); |
ac56dd48 | 1602 | tcg_gen_movi_i32(TCGV_HIGH(ret), 0); |
c896fe29 FB |
1603 | } |
1604 | ||
a7812ae4 | 1605 | static inline void tcg_gen_ext_i32_i64(TCGv_i64 ret, TCGv_i32 arg) |
c896fe29 | 1606 | { |
a7812ae4 PB |
1607 | tcg_gen_mov_i32(TCGV_LOW(ret), arg); |
1608 | tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31); | |
c896fe29 FB |
1609 | } |
1610 | ||
9a5c57fd AJ |
1611 | /* Note: we assume the six high bytes are set to zero */ |
1612 | static inline void tcg_gen_bswap16_i64(TCGv_i64 ret, TCGv_i64 arg) | |
1613 | { | |
1614 | tcg_gen_mov_i32(TCGV_HIGH(ret), TCGV_HIGH(arg)); | |
1615 | tcg_gen_bswap16_i32(TCGV_LOW(ret), TCGV_LOW(arg)); | |
1616 | } | |
1617 | ||
1618 | /* Note: we assume the four high bytes are set to zero */ | |
1619 | static inline void tcg_gen_bswap32_i64(TCGv_i64 ret, TCGv_i64 arg) | |
1620 | { | |
1621 | tcg_gen_mov_i32(TCGV_HIGH(ret), TCGV_HIGH(arg)); | |
1622 | tcg_gen_bswap32_i32(TCGV_LOW(ret), TCGV_LOW(arg)); | |
1623 | } | |
1624 | ||
66896cb8 | 1625 | static inline void tcg_gen_bswap64_i64(TCGv_i64 ret, TCGv_i64 arg) |
c896fe29 | 1626 | { |
a7812ae4 PB |
1627 | TCGv_i32 t0, t1; |
1628 | t0 = tcg_temp_new_i32(); | |
1629 | t1 = tcg_temp_new_i32(); | |
c896fe29 | 1630 | |
66896cb8 AJ |
1631 | tcg_gen_bswap32_i32(t0, TCGV_LOW(arg)); |
1632 | tcg_gen_bswap32_i32(t1, TCGV_HIGH(arg)); | |
a7812ae4 | 1633 | tcg_gen_mov_i32(TCGV_LOW(ret), t1); |
ac56dd48 | 1634 | tcg_gen_mov_i32(TCGV_HIGH(ret), t0); |
a7812ae4 PB |
1635 | tcg_temp_free_i32(t0); |
1636 | tcg_temp_free_i32(t1); | |
c896fe29 FB |
1637 | } |
1638 | #else | |
1639 | ||
a7812ae4 | 1640 | static inline void tcg_gen_ext8s_i64(TCGv_i64 ret, TCGv_i64 arg) |
c896fe29 | 1641 | { |
25c4d9cc RH |
1642 | if (TCG_TARGET_HAS_ext8s_i64) { |
1643 | tcg_gen_op2_i64(INDEX_op_ext8s_i64, ret, arg); | |
1644 | } else { | |
1645 | tcg_gen_shli_i64(ret, arg, 56); | |
1646 | tcg_gen_sari_i64(ret, ret, 56); | |
1647 | } | |
c896fe29 FB |
1648 | } |
1649 | ||
a7812ae4 | 1650 | static inline void tcg_gen_ext16s_i64(TCGv_i64 ret, TCGv_i64 arg) |
c896fe29 | 1651 | { |
25c4d9cc RH |
1652 | if (TCG_TARGET_HAS_ext16s_i64) { |
1653 | tcg_gen_op2_i64(INDEX_op_ext16s_i64, ret, arg); | |
1654 | } else { | |
1655 | tcg_gen_shli_i64(ret, arg, 48); | |
1656 | tcg_gen_sari_i64(ret, ret, 48); | |
1657 | } | |
c896fe29 FB |
1658 | } |
1659 | ||
a7812ae4 | 1660 | static inline void tcg_gen_ext32s_i64(TCGv_i64 ret, TCGv_i64 arg) |
c896fe29 | 1661 | { |
25c4d9cc RH |
1662 | if (TCG_TARGET_HAS_ext32s_i64) { |
1663 | tcg_gen_op2_i64(INDEX_op_ext32s_i64, ret, arg); | |
1664 | } else { | |
1665 | tcg_gen_shli_i64(ret, arg, 32); | |
1666 | tcg_gen_sari_i64(ret, ret, 32); | |
1667 | } | |
c896fe29 FB |
1668 | } |
1669 | ||
a7812ae4 | 1670 | static inline void tcg_gen_ext8u_i64(TCGv_i64 ret, TCGv_i64 arg) |
86831435 | 1671 | { |
25c4d9cc RH |
1672 | if (TCG_TARGET_HAS_ext8u_i64) { |
1673 | tcg_gen_op2_i64(INDEX_op_ext8u_i64, ret, arg); | |
1674 | } else { | |
1675 | tcg_gen_andi_i64(ret, arg, 0xffu); | |
1676 | } | |
86831435 PB |
1677 | } |
1678 | ||
a7812ae4 | 1679 | static inline void tcg_gen_ext16u_i64(TCGv_i64 ret, TCGv_i64 arg) |
86831435 | 1680 | { |
25c4d9cc RH |
1681 | if (TCG_TARGET_HAS_ext16u_i64) { |
1682 | tcg_gen_op2_i64(INDEX_op_ext16u_i64, ret, arg); | |
1683 | } else { | |
1684 | tcg_gen_andi_i64(ret, arg, 0xffffu); | |
1685 | } | |
86831435 PB |
1686 | } |
1687 | ||
a7812ae4 | 1688 | static inline void tcg_gen_ext32u_i64(TCGv_i64 ret, TCGv_i64 arg) |
86831435 | 1689 | { |
25c4d9cc RH |
1690 | if (TCG_TARGET_HAS_ext32u_i64) { |
1691 | tcg_gen_op2_i64(INDEX_op_ext32u_i64, ret, arg); | |
1692 | } else { | |
1693 | tcg_gen_andi_i64(ret, arg, 0xffffffffu); | |
1694 | } | |
86831435 PB |
1695 | } |
1696 | ||
c896fe29 | 1697 | /* Note: we assume the target supports move between 32 and 64 bit |
ac56dd48 | 1698 | registers. This will probably break MIPS64 targets. */ |
a7812ae4 | 1699 | static inline void tcg_gen_trunc_i64_i32(TCGv_i32 ret, TCGv_i64 arg) |
c896fe29 | 1700 | { |
a7812ae4 | 1701 | tcg_gen_mov_i32(ret, MAKE_TCGV_I32(GET_TCGV_I64(arg))); |
c896fe29 FB |
1702 | } |
1703 | ||
1704 | /* Note: we assume the target supports move between 32 and 64 bit | |
1705 | registers */ | |
a7812ae4 | 1706 | static inline void tcg_gen_extu_i32_i64(TCGv_i64 ret, TCGv_i32 arg) |
c896fe29 | 1707 | { |
cfc86988 | 1708 | tcg_gen_ext32u_i64(ret, MAKE_TCGV_I64(GET_TCGV_I32(arg))); |
c896fe29 FB |
1709 | } |
1710 | ||
1711 | /* Note: we assume the target supports move between 32 and 64 bit | |
1712 | registers */ | |
a7812ae4 | 1713 | static inline void tcg_gen_ext_i32_i64(TCGv_i64 ret, TCGv_i32 arg) |
c896fe29 | 1714 | { |
a7812ae4 | 1715 | tcg_gen_ext32s_i64(ret, MAKE_TCGV_I64(GET_TCGV_I32(arg))); |
c896fe29 FB |
1716 | } |
1717 | ||
9a5c57fd AJ |
1718 | /* Note: we assume the six high bytes are set to zero */ |
1719 | static inline void tcg_gen_bswap16_i64(TCGv_i64 ret, TCGv_i64 arg) | |
1720 | { | |
25c4d9cc RH |
1721 | if (TCG_TARGET_HAS_bswap16_i64) { |
1722 | tcg_gen_op2_i64(INDEX_op_bswap16_i64, ret, arg); | |
1723 | } else { | |
1724 | TCGv_i64 t0 = tcg_temp_new_i64(); | |
9a5c57fd | 1725 | |
25c4d9cc RH |
1726 | tcg_gen_ext8u_i64(t0, arg); |
1727 | tcg_gen_shli_i64(t0, t0, 8); | |
1728 | tcg_gen_shri_i64(ret, arg, 8); | |
1729 | tcg_gen_or_i64(ret, ret, t0); | |
1730 | tcg_temp_free_i64(t0); | |
1731 | } | |
9a5c57fd AJ |
1732 | } |
1733 | ||
1734 | /* Note: we assume the four high bytes are set to zero */ | |
1735 | static inline void tcg_gen_bswap32_i64(TCGv_i64 ret, TCGv_i64 arg) | |
1736 | { | |
25c4d9cc RH |
1737 | if (TCG_TARGET_HAS_bswap32_i64) { |
1738 | tcg_gen_op2_i64(INDEX_op_bswap32_i64, ret, arg); | |
1739 | } else { | |
1740 | TCGv_i64 t0, t1; | |
1741 | t0 = tcg_temp_new_i64(); | |
1742 | t1 = tcg_temp_new_i64(); | |
9a5c57fd | 1743 | |
25c4d9cc RH |
1744 | tcg_gen_shli_i64(t0, arg, 24); |
1745 | tcg_gen_ext32u_i64(t0, t0); | |
9a5c57fd | 1746 | |
25c4d9cc RH |
1747 | tcg_gen_andi_i64(t1, arg, 0x0000ff00); |
1748 | tcg_gen_shli_i64(t1, t1, 8); | |
1749 | tcg_gen_or_i64(t0, t0, t1); | |
9a5c57fd | 1750 | |
25c4d9cc RH |
1751 | tcg_gen_shri_i64(t1, arg, 8); |
1752 | tcg_gen_andi_i64(t1, t1, 0x0000ff00); | |
1753 | tcg_gen_or_i64(t0, t0, t1); | |
9a5c57fd | 1754 | |
25c4d9cc RH |
1755 | tcg_gen_shri_i64(t1, arg, 24); |
1756 | tcg_gen_or_i64(ret, t0, t1); | |
1757 | tcg_temp_free_i64(t0); | |
1758 | tcg_temp_free_i64(t1); | |
1759 | } | |
9a5c57fd AJ |
1760 | } |
1761 | ||
66896cb8 | 1762 | static inline void tcg_gen_bswap64_i64(TCGv_i64 ret, TCGv_i64 arg) |
c896fe29 | 1763 | { |
25c4d9cc RH |
1764 | if (TCG_TARGET_HAS_bswap64_i64) { |
1765 | tcg_gen_op2_i64(INDEX_op_bswap64_i64, ret, arg); | |
1766 | } else { | |
1767 | TCGv_i64 t0 = tcg_temp_new_i64(); | |
1768 | TCGv_i64 t1 = tcg_temp_new_i64(); | |
c896fe29 | 1769 | |
25c4d9cc | 1770 | tcg_gen_shli_i64(t0, arg, 56); |
c896fe29 | 1771 | |
25c4d9cc RH |
1772 | tcg_gen_andi_i64(t1, arg, 0x0000ff00); |
1773 | tcg_gen_shli_i64(t1, t1, 40); | |
1774 | tcg_gen_or_i64(t0, t0, t1); | |
c896fe29 | 1775 | |
25c4d9cc RH |
1776 | tcg_gen_andi_i64(t1, arg, 0x00ff0000); |
1777 | tcg_gen_shli_i64(t1, t1, 24); | |
1778 | tcg_gen_or_i64(t0, t0, t1); | |
c896fe29 | 1779 | |
25c4d9cc RH |
1780 | tcg_gen_andi_i64(t1, arg, 0xff000000); |
1781 | tcg_gen_shli_i64(t1, t1, 8); | |
1782 | tcg_gen_or_i64(t0, t0, t1); | |
c896fe29 | 1783 | |
25c4d9cc RH |
1784 | tcg_gen_shri_i64(t1, arg, 8); |
1785 | tcg_gen_andi_i64(t1, t1, 0xff000000); | |
1786 | tcg_gen_or_i64(t0, t0, t1); | |
c896fe29 | 1787 | |
25c4d9cc RH |
1788 | tcg_gen_shri_i64(t1, arg, 24); |
1789 | tcg_gen_andi_i64(t1, t1, 0x00ff0000); | |
1790 | tcg_gen_or_i64(t0, t0, t1); | |
c896fe29 | 1791 | |
25c4d9cc RH |
1792 | tcg_gen_shri_i64(t1, arg, 40); |
1793 | tcg_gen_andi_i64(t1, t1, 0x0000ff00); | |
1794 | tcg_gen_or_i64(t0, t0, t1); | |
c896fe29 | 1795 | |
25c4d9cc RH |
1796 | tcg_gen_shri_i64(t1, arg, 56); |
1797 | tcg_gen_or_i64(ret, t0, t1); | |
1798 | tcg_temp_free_i64(t0); | |
1799 | tcg_temp_free_i64(t1); | |
1800 | } | |
c896fe29 FB |
1801 | } |
1802 | ||
1803 | #endif | |
1804 | ||
a7812ae4 | 1805 | static inline void tcg_gen_neg_i32(TCGv_i32 ret, TCGv_i32 arg) |
390efc54 | 1806 | { |
25c4d9cc RH |
1807 | if (TCG_TARGET_HAS_neg_i32) { |
1808 | tcg_gen_op2_i32(INDEX_op_neg_i32, ret, arg); | |
1809 | } else { | |
1810 | TCGv_i32 t0 = tcg_const_i32(0); | |
1811 | tcg_gen_sub_i32(ret, t0, arg); | |
1812 | tcg_temp_free_i32(t0); | |
1813 | } | |
390efc54 PB |
1814 | } |
1815 | ||
a7812ae4 | 1816 | static inline void tcg_gen_neg_i64(TCGv_i64 ret, TCGv_i64 arg) |
390efc54 | 1817 | { |
25c4d9cc RH |
1818 | if (TCG_TARGET_HAS_neg_i64) { |
1819 | tcg_gen_op2_i64(INDEX_op_neg_i64, ret, arg); | |
1820 | } else { | |
1821 | TCGv_i64 t0 = tcg_const_i64(0); | |
1822 | tcg_gen_sub_i64(ret, t0, arg); | |
1823 | tcg_temp_free_i64(t0); | |
1824 | } | |
390efc54 PB |
1825 | } |
1826 | ||
a7812ae4 | 1827 | static inline void tcg_gen_not_i32(TCGv_i32 ret, TCGv_i32 arg) |
0b6ce4cf | 1828 | { |
25c4d9cc RH |
1829 | if (TCG_TARGET_HAS_not_i32) { |
1830 | tcg_gen_op2_i32(INDEX_op_not_i32, ret, arg); | |
1831 | } else { | |
1832 | tcg_gen_xori_i32(ret, arg, -1); | |
1833 | } | |
0b6ce4cf FB |
1834 | } |
1835 | ||
a7812ae4 | 1836 | static inline void tcg_gen_not_i64(TCGv_i64 ret, TCGv_i64 arg) |
0b6ce4cf | 1837 | { |
25c4d9cc RH |
1838 | #if TCG_TARGET_REG_BITS == 64 |
1839 | if (TCG_TARGET_HAS_not_i64) { | |
1840 | tcg_gen_op2_i64(INDEX_op_not_i64, ret, arg); | |
1841 | } else { | |
1842 | tcg_gen_xori_i64(ret, arg, -1); | |
1843 | } | |
1844 | #else | |
a10f9f4f RH |
1845 | tcg_gen_not_i32(TCGV_LOW(ret), TCGV_LOW(arg)); |
1846 | tcg_gen_not_i32(TCGV_HIGH(ret), TCGV_HIGH(arg)); | |
d2604285 | 1847 | #endif |
0b6ce4cf | 1848 | } |
5ff9d6a4 | 1849 | |
a7812ae4 | 1850 | static inline void tcg_gen_discard_i32(TCGv_i32 arg) |
5ff9d6a4 | 1851 | { |
a7812ae4 | 1852 | tcg_gen_op1_i32(INDEX_op_discard, arg); |
5ff9d6a4 FB |
1853 | } |
1854 | ||
a7812ae4 | 1855 | static inline void tcg_gen_discard_i64(TCGv_i64 arg) |
5ff9d6a4 | 1856 | { |
25c4d9cc | 1857 | #if TCG_TARGET_REG_BITS == 32 |
a7812ae4 | 1858 | tcg_gen_discard_i32(TCGV_LOW(arg)); |
5ff9d6a4 | 1859 | tcg_gen_discard_i32(TCGV_HIGH(arg)); |
5ff9d6a4 | 1860 | #else |
a7812ae4 | 1861 | tcg_gen_op1_i64(INDEX_op_discard, arg); |
5ff9d6a4 | 1862 | #endif |
25c4d9cc | 1863 | } |
5ff9d6a4 | 1864 | |
a7812ae4 | 1865 | static inline void tcg_gen_andc_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
f24cb33e | 1866 | { |
25c4d9cc RH |
1867 | if (TCG_TARGET_HAS_andc_i32) { |
1868 | tcg_gen_op3_i32(INDEX_op_andc_i32, ret, arg1, arg2); | |
1869 | } else { | |
1870 | TCGv_i32 t0 = tcg_temp_new_i32(); | |
1871 | tcg_gen_not_i32(t0, arg2); | |
1872 | tcg_gen_and_i32(ret, arg1, t0); | |
1873 | tcg_temp_free_i32(t0); | |
1874 | } | |
f24cb33e AJ |
1875 | } |
1876 | ||
a7812ae4 | 1877 | static inline void tcg_gen_andc_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
f24cb33e | 1878 | { |
25c4d9cc RH |
1879 | #if TCG_TARGET_REG_BITS == 64 |
1880 | if (TCG_TARGET_HAS_andc_i64) { | |
1881 | tcg_gen_op3_i64(INDEX_op_andc_i64, ret, arg1, arg2); | |
1882 | } else { | |
1883 | TCGv_i64 t0 = tcg_temp_new_i64(); | |
1884 | tcg_gen_not_i64(t0, arg2); | |
1885 | tcg_gen_and_i64(ret, arg1, t0); | |
1886 | tcg_temp_free_i64(t0); | |
1887 | } | |
1888 | #else | |
241cbed4 RH |
1889 | tcg_gen_andc_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2)); |
1890 | tcg_gen_andc_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2)); | |
241cbed4 | 1891 | #endif |
f24cb33e AJ |
1892 | } |
1893 | ||
a7812ae4 | 1894 | static inline void tcg_gen_eqv_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
f24cb33e | 1895 | { |
25c4d9cc RH |
1896 | if (TCG_TARGET_HAS_eqv_i32) { |
1897 | tcg_gen_op3_i32(INDEX_op_eqv_i32, ret, arg1, arg2); | |
1898 | } else { | |
1899 | tcg_gen_xor_i32(ret, arg1, arg2); | |
1900 | tcg_gen_not_i32(ret, ret); | |
1901 | } | |
f24cb33e AJ |
1902 | } |
1903 | ||
a7812ae4 | 1904 | static inline void tcg_gen_eqv_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
f24cb33e | 1905 | { |
25c4d9cc RH |
1906 | #if TCG_TARGET_REG_BITS == 64 |
1907 | if (TCG_TARGET_HAS_eqv_i64) { | |
1908 | tcg_gen_op3_i64(INDEX_op_eqv_i64, ret, arg1, arg2); | |
1909 | } else { | |
1910 | tcg_gen_xor_i64(ret, arg1, arg2); | |
1911 | tcg_gen_not_i64(ret, ret); | |
1912 | } | |
1913 | #else | |
8d625cf1 RH |
1914 | tcg_gen_eqv_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2)); |
1915 | tcg_gen_eqv_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2)); | |
8d625cf1 | 1916 | #endif |
f24cb33e AJ |
1917 | } |
1918 | ||
a7812ae4 | 1919 | static inline void tcg_gen_nand_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
f24cb33e | 1920 | { |
25c4d9cc RH |
1921 | if (TCG_TARGET_HAS_nand_i32) { |
1922 | tcg_gen_op3_i32(INDEX_op_nand_i32, ret, arg1, arg2); | |
1923 | } else { | |
1924 | tcg_gen_and_i32(ret, arg1, arg2); | |
1925 | tcg_gen_not_i32(ret, ret); | |
1926 | } | |
f24cb33e AJ |
1927 | } |
1928 | ||
a7812ae4 | 1929 | static inline void tcg_gen_nand_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
f24cb33e | 1930 | { |
25c4d9cc RH |
1931 | #if TCG_TARGET_REG_BITS == 64 |
1932 | if (TCG_TARGET_HAS_nand_i64) { | |
1933 | tcg_gen_op3_i64(INDEX_op_nand_i64, ret, arg1, arg2); | |
1934 | } else { | |
1935 | tcg_gen_and_i64(ret, arg1, arg2); | |
1936 | tcg_gen_not_i64(ret, ret); | |
1937 | } | |
1938 | #else | |
9940a96b RH |
1939 | tcg_gen_nand_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2)); |
1940 | tcg_gen_nand_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2)); | |
9940a96b | 1941 | #endif |
f24cb33e AJ |
1942 | } |
1943 | ||
a7812ae4 | 1944 | static inline void tcg_gen_nor_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
f24cb33e | 1945 | { |
25c4d9cc RH |
1946 | if (TCG_TARGET_HAS_nor_i32) { |
1947 | tcg_gen_op3_i32(INDEX_op_nor_i32, ret, arg1, arg2); | |
1948 | } else { | |
1949 | tcg_gen_or_i32(ret, arg1, arg2); | |
1950 | tcg_gen_not_i32(ret, ret); | |
1951 | } | |
f24cb33e AJ |
1952 | } |
1953 | ||
a7812ae4 | 1954 | static inline void tcg_gen_nor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
f24cb33e | 1955 | { |
25c4d9cc RH |
1956 | #if TCG_TARGET_REG_BITS == 64 |
1957 | if (TCG_TARGET_HAS_nor_i64) { | |
1958 | tcg_gen_op3_i64(INDEX_op_nor_i64, ret, arg1, arg2); | |
1959 | } else { | |
1960 | tcg_gen_or_i64(ret, arg1, arg2); | |
1961 | tcg_gen_not_i64(ret, ret); | |
1962 | } | |
1963 | #else | |
32d98fbd RH |
1964 | tcg_gen_nor_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2)); |
1965 | tcg_gen_nor_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2)); | |
32d98fbd | 1966 | #endif |
f24cb33e AJ |
1967 | } |
1968 | ||
a7812ae4 | 1969 | static inline void tcg_gen_orc_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
f24cb33e | 1970 | { |
25c4d9cc RH |
1971 | if (TCG_TARGET_HAS_orc_i32) { |
1972 | tcg_gen_op3_i32(INDEX_op_orc_i32, ret, arg1, arg2); | |
1973 | } else { | |
1974 | TCGv_i32 t0 = tcg_temp_new_i32(); | |
1975 | tcg_gen_not_i32(t0, arg2); | |
1976 | tcg_gen_or_i32(ret, arg1, t0); | |
1977 | tcg_temp_free_i32(t0); | |
1978 | } | |
f24cb33e AJ |
1979 | } |
1980 | ||
a7812ae4 | 1981 | static inline void tcg_gen_orc_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
f24cb33e | 1982 | { |
25c4d9cc RH |
1983 | #if TCG_TARGET_REG_BITS == 64 |
1984 | if (TCG_TARGET_HAS_orc_i64) { | |
1985 | tcg_gen_op3_i64(INDEX_op_orc_i64, ret, arg1, arg2); | |
1986 | } else { | |
1987 | TCGv_i64 t0 = tcg_temp_new_i64(); | |
1988 | tcg_gen_not_i64(t0, arg2); | |
1989 | tcg_gen_or_i64(ret, arg1, t0); | |
1990 | tcg_temp_free_i64(t0); | |
1991 | } | |
1992 | #else | |
791d1262 RH |
1993 | tcg_gen_orc_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2)); |
1994 | tcg_gen_orc_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2)); | |
791d1262 | 1995 | #endif |
f24cb33e AJ |
1996 | } |
1997 | ||
a7812ae4 | 1998 | static inline void tcg_gen_rotl_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
15824571 | 1999 | { |
25c4d9cc RH |
2000 | if (TCG_TARGET_HAS_rot_i32) { |
2001 | tcg_gen_op3_i32(INDEX_op_rotl_i32, ret, arg1, arg2); | |
2002 | } else { | |
2003 | TCGv_i32 t0, t1; | |
15824571 | 2004 | |
25c4d9cc RH |
2005 | t0 = tcg_temp_new_i32(); |
2006 | t1 = tcg_temp_new_i32(); | |
2007 | tcg_gen_shl_i32(t0, arg1, arg2); | |
2008 | tcg_gen_subfi_i32(t1, 32, arg2); | |
2009 | tcg_gen_shr_i32(t1, arg1, t1); | |
2010 | tcg_gen_or_i32(ret, t0, t1); | |
2011 | tcg_temp_free_i32(t0); | |
2012 | tcg_temp_free_i32(t1); | |
2013 | } | |
15824571 AJ |
2014 | } |
2015 | ||
a7812ae4 | 2016 | static inline void tcg_gen_rotl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
15824571 | 2017 | { |
25c4d9cc RH |
2018 | if (TCG_TARGET_HAS_rot_i64) { |
2019 | tcg_gen_op3_i64(INDEX_op_rotl_i64, ret, arg1, arg2); | |
2020 | } else { | |
2021 | TCGv_i64 t0, t1; | |
2022 | t0 = tcg_temp_new_i64(); | |
2023 | t1 = tcg_temp_new_i64(); | |
2024 | tcg_gen_shl_i64(t0, arg1, arg2); | |
2025 | tcg_gen_subfi_i64(t1, 64, arg2); | |
2026 | tcg_gen_shr_i64(t1, arg1, t1); | |
2027 | tcg_gen_or_i64(ret, t0, t1); | |
2028 | tcg_temp_free_i64(t0); | |
2029 | tcg_temp_free_i64(t1); | |
2030 | } | |
15824571 AJ |
2031 | } |
2032 | ||
a7812ae4 | 2033 | static inline void tcg_gen_rotli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) |
15824571 AJ |
2034 | { |
2035 | /* some cases can be optimized here */ | |
2036 | if (arg2 == 0) { | |
2037 | tcg_gen_mov_i32(ret, arg1); | |
25c4d9cc | 2038 | } else if (TCG_TARGET_HAS_rot_i32) { |
d42f183c AJ |
2039 | TCGv_i32 t0 = tcg_const_i32(arg2); |
2040 | tcg_gen_rotl_i32(ret, arg1, t0); | |
2041 | tcg_temp_free_i32(t0); | |
25c4d9cc | 2042 | } else { |
a7812ae4 PB |
2043 | TCGv_i32 t0, t1; |
2044 | t0 = tcg_temp_new_i32(); | |
2045 | t1 = tcg_temp_new_i32(); | |
15824571 AJ |
2046 | tcg_gen_shli_i32(t0, arg1, arg2); |
2047 | tcg_gen_shri_i32(t1, arg1, 32 - arg2); | |
2048 | tcg_gen_or_i32(ret, t0, t1); | |
a7812ae4 PB |
2049 | tcg_temp_free_i32(t0); |
2050 | tcg_temp_free_i32(t1); | |
15824571 AJ |
2051 | } |
2052 | } | |
2053 | ||
a7812ae4 | 2054 | static inline void tcg_gen_rotli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
15824571 AJ |
2055 | { |
2056 | /* some cases can be optimized here */ | |
2057 | if (arg2 == 0) { | |
2058 | tcg_gen_mov_i64(ret, arg1); | |
25c4d9cc | 2059 | } else if (TCG_TARGET_HAS_rot_i64) { |
d42f183c AJ |
2060 | TCGv_i64 t0 = tcg_const_i64(arg2); |
2061 | tcg_gen_rotl_i64(ret, arg1, t0); | |
2062 | tcg_temp_free_i64(t0); | |
25c4d9cc | 2063 | } else { |
a7812ae4 PB |
2064 | TCGv_i64 t0, t1; |
2065 | t0 = tcg_temp_new_i64(); | |
2066 | t1 = tcg_temp_new_i64(); | |
15824571 AJ |
2067 | tcg_gen_shli_i64(t0, arg1, arg2); |
2068 | tcg_gen_shri_i64(t1, arg1, 64 - arg2); | |
2069 | tcg_gen_or_i64(ret, t0, t1); | |
a7812ae4 PB |
2070 | tcg_temp_free_i64(t0); |
2071 | tcg_temp_free_i64(t1); | |
15824571 AJ |
2072 | } |
2073 | } | |
2074 | ||
a7812ae4 | 2075 | static inline void tcg_gen_rotr_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
15824571 | 2076 | { |
25c4d9cc RH |
2077 | if (TCG_TARGET_HAS_rot_i32) { |
2078 | tcg_gen_op3_i32(INDEX_op_rotr_i32, ret, arg1, arg2); | |
2079 | } else { | |
2080 | TCGv_i32 t0, t1; | |
15824571 | 2081 | |
25c4d9cc RH |
2082 | t0 = tcg_temp_new_i32(); |
2083 | t1 = tcg_temp_new_i32(); | |
2084 | tcg_gen_shr_i32(t0, arg1, arg2); | |
2085 | tcg_gen_subfi_i32(t1, 32, arg2); | |
2086 | tcg_gen_shl_i32(t1, arg1, t1); | |
2087 | tcg_gen_or_i32(ret, t0, t1); | |
2088 | tcg_temp_free_i32(t0); | |
2089 | tcg_temp_free_i32(t1); | |
2090 | } | |
15824571 AJ |
2091 | } |
2092 | ||
a7812ae4 | 2093 | static inline void tcg_gen_rotr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
15824571 | 2094 | { |
25c4d9cc RH |
2095 | if (TCG_TARGET_HAS_rot_i64) { |
2096 | tcg_gen_op3_i64(INDEX_op_rotr_i64, ret, arg1, arg2); | |
2097 | } else { | |
2098 | TCGv_i64 t0, t1; | |
2099 | t0 = tcg_temp_new_i64(); | |
2100 | t1 = tcg_temp_new_i64(); | |
2101 | tcg_gen_shr_i64(t0, arg1, arg2); | |
2102 | tcg_gen_subfi_i64(t1, 64, arg2); | |
2103 | tcg_gen_shl_i64(t1, arg1, t1); | |
2104 | tcg_gen_or_i64(ret, t0, t1); | |
2105 | tcg_temp_free_i64(t0); | |
2106 | tcg_temp_free_i64(t1); | |
2107 | } | |
15824571 AJ |
2108 | } |
2109 | ||
a7812ae4 | 2110 | static inline void tcg_gen_rotri_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) |
15824571 AJ |
2111 | { |
2112 | /* some cases can be optimized here */ | |
2113 | if (arg2 == 0) { | |
2114 | tcg_gen_mov_i32(ret, arg1); | |
2115 | } else { | |
2116 | tcg_gen_rotli_i32(ret, arg1, 32 - arg2); | |
2117 | } | |
2118 | } | |
2119 | ||
a7812ae4 | 2120 | static inline void tcg_gen_rotri_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
15824571 AJ |
2121 | { |
2122 | /* some cases can be optimized here */ | |
2123 | if (arg2 == 0) { | |
de3526b2 | 2124 | tcg_gen_mov_i64(ret, arg1); |
15824571 AJ |
2125 | } else { |
2126 | tcg_gen_rotli_i64(ret, arg1, 64 - arg2); | |
2127 | } | |
2128 | } | |
2129 | ||
b7767f0f | 2130 | static inline void tcg_gen_deposit_i32(TCGv_i32 ret, TCGv_i32 arg1, |
0756e71c RH |
2131 | TCGv_i32 arg2, unsigned int ofs, |
2132 | unsigned int len) | |
b7767f0f | 2133 | { |
df072774 RH |
2134 | uint32_t mask; |
2135 | TCGv_i32 t1; | |
2136 | ||
717e7036 RH |
2137 | tcg_debug_assert(ofs < 32); |
2138 | tcg_debug_assert(len <= 32); | |
2139 | tcg_debug_assert(ofs + len <= 32); | |
2140 | ||
df072774 RH |
2141 | if (ofs == 0 && len == 32) { |
2142 | tcg_gen_mov_i32(ret, arg2); | |
2143 | return; | |
2144 | } | |
a4773324 | 2145 | if (TCG_TARGET_HAS_deposit_i32 && TCG_TARGET_deposit_i32_valid(ofs, len)) { |
25c4d9cc | 2146 | tcg_gen_op5ii_i32(INDEX_op_deposit_i32, ret, arg1, arg2, ofs, len); |
df072774 RH |
2147 | return; |
2148 | } | |
2149 | ||
2150 | mask = (1u << len) - 1; | |
2151 | t1 = tcg_temp_new_i32(); | |
b7767f0f | 2152 | |
df072774 | 2153 | if (ofs + len < 32) { |
25c4d9cc RH |
2154 | tcg_gen_andi_i32(t1, arg2, mask); |
2155 | tcg_gen_shli_i32(t1, t1, ofs); | |
df072774 RH |
2156 | } else { |
2157 | tcg_gen_shli_i32(t1, arg2, ofs); | |
25c4d9cc | 2158 | } |
df072774 RH |
2159 | tcg_gen_andi_i32(ret, arg1, ~(mask << ofs)); |
2160 | tcg_gen_or_i32(ret, ret, t1); | |
2161 | ||
2162 | tcg_temp_free_i32(t1); | |
b7767f0f RH |
2163 | } |
2164 | ||
2165 | static inline void tcg_gen_deposit_i64(TCGv_i64 ret, TCGv_i64 arg1, | |
0756e71c RH |
2166 | TCGv_i64 arg2, unsigned int ofs, |
2167 | unsigned int len) | |
b7767f0f | 2168 | { |
df072774 RH |
2169 | uint64_t mask; |
2170 | TCGv_i64 t1; | |
2171 | ||
717e7036 RH |
2172 | tcg_debug_assert(ofs < 64); |
2173 | tcg_debug_assert(len <= 64); | |
2174 | tcg_debug_assert(ofs + len <= 64); | |
2175 | ||
df072774 RH |
2176 | if (ofs == 0 && len == 64) { |
2177 | tcg_gen_mov_i64(ret, arg2); | |
2178 | return; | |
2179 | } | |
a4773324 | 2180 | if (TCG_TARGET_HAS_deposit_i64 && TCG_TARGET_deposit_i64_valid(ofs, len)) { |
25c4d9cc | 2181 | tcg_gen_op5ii_i64(INDEX_op_deposit_i64, ret, arg1, arg2, ofs, len); |
df072774 RH |
2182 | return; |
2183 | } | |
b7767f0f | 2184 | |
df072774 RH |
2185 | #if TCG_TARGET_REG_BITS == 32 |
2186 | if (ofs >= 32) { | |
2f98c9db | 2187 | tcg_gen_mov_i32(TCGV_LOW(ret), TCGV_LOW(arg1)); |
df072774 RH |
2188 | tcg_gen_deposit_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), |
2189 | TCGV_LOW(arg2), ofs - 32, len); | |
2190 | return; | |
2191 | } | |
2192 | if (ofs + len <= 32) { | |
2193 | tcg_gen_deposit_i32(TCGV_LOW(ret), TCGV_LOW(arg1), | |
2194 | TCGV_LOW(arg2), ofs, len); | |
2f98c9db | 2195 | tcg_gen_mov_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1)); |
df072774 RH |
2196 | return; |
2197 | } | |
2198 | #endif | |
2199 | ||
2200 | mask = (1ull << len) - 1; | |
2201 | t1 = tcg_temp_new_i64(); | |
2202 | ||
2203 | if (ofs + len < 64) { | |
25c4d9cc RH |
2204 | tcg_gen_andi_i64(t1, arg2, mask); |
2205 | tcg_gen_shli_i64(t1, t1, ofs); | |
df072774 RH |
2206 | } else { |
2207 | tcg_gen_shli_i64(t1, arg2, ofs); | |
25c4d9cc | 2208 | } |
df072774 RH |
2209 | tcg_gen_andi_i64(ret, arg1, ~(mask << ofs)); |
2210 | tcg_gen_or_i64(ret, ret, t1); | |
2211 | ||
2212 | tcg_temp_free_i64(t1); | |
b7767f0f RH |
2213 | } |
2214 | ||
77276f65 RH |
2215 | static inline void tcg_gen_concat_i32_i64(TCGv_i64 dest, TCGv_i32 low, |
2216 | TCGv_i32 high) | |
2217 | { | |
2218 | #if TCG_TARGET_REG_BITS == 32 | |
2219 | tcg_gen_mov_i32(TCGV_LOW(dest), low); | |
2220 | tcg_gen_mov_i32(TCGV_HIGH(dest), high); | |
2221 | #else | |
2222 | TCGv_i64 tmp = tcg_temp_new_i64(); | |
2223 | /* These extensions are only needed for type correctness. | |
2224 | We may be able to do better given target specific information. */ | |
2225 | tcg_gen_extu_i32_i64(tmp, high); | |
2226 | tcg_gen_extu_i32_i64(dest, low); | |
2227 | /* If deposit is available, use it. Otherwise use the extra | |
2228 | knowledge that we have of the zero-extensions above. */ | |
2229 | if (TCG_TARGET_HAS_deposit_i64 && TCG_TARGET_deposit_i64_valid(32, 32)) { | |
2230 | tcg_gen_deposit_i64(dest, dest, tmp, 32, 32); | |
2231 | } else { | |
2232 | tcg_gen_shli_i64(tmp, tmp, 32); | |
2233 | tcg_gen_or_i64(dest, dest, tmp); | |
2234 | } | |
2235 | tcg_temp_free_i64(tmp); | |
2236 | #endif | |
2237 | } | |
2238 | ||
2239 | static inline void tcg_gen_concat32_i64(TCGv_i64 dest, TCGv_i64 low, | |
2240 | TCGv_i64 high) | |
2241 | { | |
2242 | tcg_gen_deposit_i64(dest, low, high, 32, 32); | |
2243 | } | |
2244 | ||
ffc5ea09 RH |
2245 | static inline void tcg_gen_movcond_i32(TCGCond cond, TCGv_i32 ret, |
2246 | TCGv_i32 c1, TCGv_i32 c2, | |
2247 | TCGv_i32 v1, TCGv_i32 v2) | |
2248 | { | |
2249 | if (TCG_TARGET_HAS_movcond_i32) { | |
2250 | tcg_gen_op6i_i32(INDEX_op_movcond_i32, ret, c1, c2, v1, v2, cond); | |
2251 | } else { | |
2252 | TCGv_i32 t0 = tcg_temp_new_i32(); | |
2253 | TCGv_i32 t1 = tcg_temp_new_i32(); | |
2254 | tcg_gen_setcond_i32(cond, t0, c1, c2); | |
2255 | tcg_gen_neg_i32(t0, t0); | |
2256 | tcg_gen_and_i32(t1, v1, t0); | |
2257 | tcg_gen_andc_i32(ret, v2, t0); | |
2258 | tcg_gen_or_i32(ret, ret, t1); | |
2259 | tcg_temp_free_i32(t0); | |
2260 | tcg_temp_free_i32(t1); | |
2261 | } | |
2262 | } | |
2263 | ||
2264 | static inline void tcg_gen_movcond_i64(TCGCond cond, TCGv_i64 ret, | |
2265 | TCGv_i64 c1, TCGv_i64 c2, | |
2266 | TCGv_i64 v1, TCGv_i64 v2) | |
2267 | { | |
a463133e RH |
2268 | #if TCG_TARGET_REG_BITS == 32 |
2269 | TCGv_i32 t0 = tcg_temp_new_i32(); | |
2270 | TCGv_i32 t1 = tcg_temp_new_i32(); | |
2271 | tcg_gen_op6i_i32(INDEX_op_setcond2_i32, t0, | |
2272 | TCGV_LOW(c1), TCGV_HIGH(c1), | |
2273 | TCGV_LOW(c2), TCGV_HIGH(c2), cond); | |
a463133e | 2274 | |
a80a6b63 RH |
2275 | if (TCG_TARGET_HAS_movcond_i32) { |
2276 | tcg_gen_movi_i32(t1, 0); | |
2277 | tcg_gen_movcond_i32(TCG_COND_NE, TCGV_LOW(ret), t0, t1, | |
2278 | TCGV_LOW(v1), TCGV_LOW(v2)); | |
2279 | tcg_gen_movcond_i32(TCG_COND_NE, TCGV_HIGH(ret), t0, t1, | |
2280 | TCGV_HIGH(v1), TCGV_HIGH(v2)); | |
2281 | } else { | |
2282 | tcg_gen_neg_i32(t0, t0); | |
a463133e | 2283 | |
a80a6b63 RH |
2284 | tcg_gen_and_i32(t1, TCGV_LOW(v1), t0); |
2285 | tcg_gen_andc_i32(TCGV_LOW(ret), TCGV_LOW(v2), t0); | |
2286 | tcg_gen_or_i32(TCGV_LOW(ret), TCGV_LOW(ret), t1); | |
a463133e | 2287 | |
a80a6b63 RH |
2288 | tcg_gen_and_i32(t1, TCGV_HIGH(v1), t0); |
2289 | tcg_gen_andc_i32(TCGV_HIGH(ret), TCGV_HIGH(v2), t0); | |
2290 | tcg_gen_or_i32(TCGV_HIGH(ret), TCGV_HIGH(ret), t1); | |
2291 | } | |
a463133e RH |
2292 | tcg_temp_free_i32(t0); |
2293 | tcg_temp_free_i32(t1); | |
2294 | #else | |
ffc5ea09 RH |
2295 | if (TCG_TARGET_HAS_movcond_i64) { |
2296 | tcg_gen_op6i_i64(INDEX_op_movcond_i64, ret, c1, c2, v1, v2, cond); | |
2297 | } else { | |
2298 | TCGv_i64 t0 = tcg_temp_new_i64(); | |
2299 | TCGv_i64 t1 = tcg_temp_new_i64(); | |
2300 | tcg_gen_setcond_i64(cond, t0, c1, c2); | |
2301 | tcg_gen_neg_i64(t0, t0); | |
2302 | tcg_gen_and_i64(t1, v1, t0); | |
2303 | tcg_gen_andc_i64(ret, v2, t0); | |
2304 | tcg_gen_or_i64(ret, ret, t1); | |
2305 | tcg_temp_free_i64(t0); | |
2306 | tcg_temp_free_i64(t1); | |
2307 | } | |
a463133e | 2308 | #endif |
ffc5ea09 RH |
2309 | } |
2310 | ||
c896fe29 FB |
2311 | /***************************************/ |
2312 | /* QEMU specific operations. Their type depend on the QEMU CPU | |
2313 | type. */ | |
2314 | #ifndef TARGET_LONG_BITS | |
2315 | #error must include QEMU headers | |
2316 | #endif | |
2317 | ||
a7812ae4 PB |
2318 | #if TARGET_LONG_BITS == 32 |
2319 | #define TCGv TCGv_i32 | |
2320 | #define tcg_temp_new() tcg_temp_new_i32() | |
2321 | #define tcg_global_reg_new tcg_global_reg_new_i32 | |
2322 | #define tcg_global_mem_new tcg_global_mem_new_i32 | |
df9247b2 | 2323 | #define tcg_temp_local_new() tcg_temp_local_new_i32() |
a7812ae4 PB |
2324 | #define tcg_temp_free tcg_temp_free_i32 |
2325 | #define tcg_gen_qemu_ldst_op tcg_gen_op3i_i32 | |
2326 | #define tcg_gen_qemu_ldst_op_i64 tcg_gen_qemu_ldst_op_i64_i32 | |
2327 | #define TCGV_UNUSED(x) TCGV_UNUSED_I32(x) | |
fe75bcf7 | 2328 | #define TCGV_EQUAL(a, b) TCGV_EQUAL_I32(a, b) |
a7812ae4 PB |
2329 | #else |
2330 | #define TCGv TCGv_i64 | |
2331 | #define tcg_temp_new() tcg_temp_new_i64() | |
2332 | #define tcg_global_reg_new tcg_global_reg_new_i64 | |
2333 | #define tcg_global_mem_new tcg_global_mem_new_i64 | |
df9247b2 | 2334 | #define tcg_temp_local_new() tcg_temp_local_new_i64() |
a7812ae4 PB |
2335 | #define tcg_temp_free tcg_temp_free_i64 |
2336 | #define tcg_gen_qemu_ldst_op tcg_gen_op3i_i64 | |
2337 | #define tcg_gen_qemu_ldst_op_i64 tcg_gen_qemu_ldst_op_i64_i64 | |
2338 | #define TCGV_UNUSED(x) TCGV_UNUSED_I64(x) | |
fe75bcf7 | 2339 | #define TCGV_EQUAL(a, b) TCGV_EQUAL_I64(a, b) |
a7812ae4 PB |
2340 | #endif |
2341 | ||
7e4597d7 FB |
2342 | /* debug info: write the PC of the corresponding QEMU CPU instruction */ |
2343 | static inline void tcg_gen_debug_insn_start(uint64_t pc) | |
2344 | { | |
2345 | /* XXX: must really use a 32 bit size for TCGArg in all cases */ | |
2346 | #if TARGET_LONG_BITS > TCG_TARGET_REG_BITS | |
bcb0126f PB |
2347 | tcg_gen_op2ii(INDEX_op_debug_insn_start, |
2348 | (uint32_t)(pc), (uint32_t)(pc >> 32)); | |
7e4597d7 FB |
2349 | #else |
2350 | tcg_gen_op1i(INDEX_op_debug_insn_start, pc); | |
2351 | #endif | |
2352 | } | |
2353 | ||
c896fe29 FB |
2354 | static inline void tcg_gen_exit_tb(tcg_target_long val) |
2355 | { | |
ac56dd48 | 2356 | tcg_gen_op1i(INDEX_op_exit_tb, val); |
c896fe29 FB |
2357 | } |
2358 | ||
0a209d4b RH |
2359 | static inline void tcg_gen_goto_tb(unsigned idx) |
2360 | { | |
2361 | /* We only support two chained exits. */ | |
2362 | tcg_debug_assert(idx <= 1); | |
2363 | #ifdef CONFIG_DEBUG_TCG | |
2364 | /* Verify that we havn't seen this numbered exit before. */ | |
2365 | tcg_debug_assert((tcg_ctx.goto_tb_issue_mask & (1 << idx)) == 0); | |
2366 | tcg_ctx.goto_tb_issue_mask |= 1 << idx; | |
2367 | #endif | |
ac56dd48 | 2368 | tcg_gen_op1i(INDEX_op_goto_tb, idx); |
c896fe29 FB |
2369 | } |
2370 | ||
2371 | #if TCG_TARGET_REG_BITS == 32 | |
ac56dd48 | 2372 | static inline void tcg_gen_qemu_ld8u(TCGv ret, TCGv addr, int mem_index) |
c896fe29 FB |
2373 | { |
2374 | #if TARGET_LONG_BITS == 32 | |
a7812ae4 | 2375 | tcg_gen_op3i_i32(INDEX_op_qemu_ld8u, ret, addr, mem_index); |
c896fe29 | 2376 | #else |
a7812ae4 PB |
2377 | tcg_gen_op4i_i32(INDEX_op_qemu_ld8u, TCGV_LOW(ret), TCGV_LOW(addr), |
2378 | TCGV_HIGH(addr), mem_index); | |
ac56dd48 | 2379 | tcg_gen_movi_i32(TCGV_HIGH(ret), 0); |
c896fe29 FB |
2380 | #endif |
2381 | } | |
2382 | ||
ac56dd48 | 2383 | static inline void tcg_gen_qemu_ld8s(TCGv ret, TCGv addr, int mem_index) |
c896fe29 FB |
2384 | { |
2385 | #if TARGET_LONG_BITS == 32 | |
a7812ae4 | 2386 | tcg_gen_op3i_i32(INDEX_op_qemu_ld8s, ret, addr, mem_index); |
c896fe29 | 2387 | #else |
a7812ae4 PB |
2388 | tcg_gen_op4i_i32(INDEX_op_qemu_ld8s, TCGV_LOW(ret), TCGV_LOW(addr), |
2389 | TCGV_HIGH(addr), mem_index); | |
2390 | tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31); | |
c896fe29 FB |
2391 | #endif |
2392 | } | |
2393 | ||
ac56dd48 | 2394 | static inline void tcg_gen_qemu_ld16u(TCGv ret, TCGv addr, int mem_index) |
c896fe29 FB |
2395 | { |
2396 | #if TARGET_LONG_BITS == 32 | |
a7812ae4 | 2397 | tcg_gen_op3i_i32(INDEX_op_qemu_ld16u, ret, addr, mem_index); |
c896fe29 | 2398 | #else |
a7812ae4 PB |
2399 | tcg_gen_op4i_i32(INDEX_op_qemu_ld16u, TCGV_LOW(ret), TCGV_LOW(addr), |
2400 | TCGV_HIGH(addr), mem_index); | |
ac56dd48 | 2401 | tcg_gen_movi_i32(TCGV_HIGH(ret), 0); |
c896fe29 FB |
2402 | #endif |
2403 | } | |
2404 | ||
ac56dd48 | 2405 | static inline void tcg_gen_qemu_ld16s(TCGv ret, TCGv addr, int mem_index) |
c896fe29 FB |
2406 | { |
2407 | #if TARGET_LONG_BITS == 32 | |
a7812ae4 | 2408 | tcg_gen_op3i_i32(INDEX_op_qemu_ld16s, ret, addr, mem_index); |
c896fe29 | 2409 | #else |
a7812ae4 PB |
2410 | tcg_gen_op4i_i32(INDEX_op_qemu_ld16s, TCGV_LOW(ret), TCGV_LOW(addr), |
2411 | TCGV_HIGH(addr), mem_index); | |
2412 | tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31); | |
c896fe29 FB |
2413 | #endif |
2414 | } | |
2415 | ||
ac56dd48 | 2416 | static inline void tcg_gen_qemu_ld32u(TCGv ret, TCGv addr, int mem_index) |
c896fe29 FB |
2417 | { |
2418 | #if TARGET_LONG_BITS == 32 | |
86feb1c8 | 2419 | tcg_gen_op3i_i32(INDEX_op_qemu_ld32, ret, addr, mem_index); |
c896fe29 | 2420 | #else |
86feb1c8 | 2421 | tcg_gen_op4i_i32(INDEX_op_qemu_ld32, TCGV_LOW(ret), TCGV_LOW(addr), |
a7812ae4 | 2422 | TCGV_HIGH(addr), mem_index); |
ac56dd48 | 2423 | tcg_gen_movi_i32(TCGV_HIGH(ret), 0); |
c896fe29 FB |
2424 | #endif |
2425 | } | |
2426 | ||
ac56dd48 | 2427 | static inline void tcg_gen_qemu_ld32s(TCGv ret, TCGv addr, int mem_index) |
c896fe29 FB |
2428 | { |
2429 | #if TARGET_LONG_BITS == 32 | |
86feb1c8 | 2430 | tcg_gen_op3i_i32(INDEX_op_qemu_ld32, ret, addr, mem_index); |
c896fe29 | 2431 | #else |
86feb1c8 | 2432 | tcg_gen_op4i_i32(INDEX_op_qemu_ld32, TCGV_LOW(ret), TCGV_LOW(addr), |
a7812ae4 PB |
2433 | TCGV_HIGH(addr), mem_index); |
2434 | tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31); | |
c896fe29 FB |
2435 | #endif |
2436 | } | |
2437 | ||
a7812ae4 | 2438 | static inline void tcg_gen_qemu_ld64(TCGv_i64 ret, TCGv addr, int mem_index) |
c896fe29 FB |
2439 | { |
2440 | #if TARGET_LONG_BITS == 32 | |
a7812ae4 | 2441 | tcg_gen_op4i_i32(INDEX_op_qemu_ld64, TCGV_LOW(ret), TCGV_HIGH(ret), addr, mem_index); |
c896fe29 | 2442 | #else |
a7812ae4 PB |
2443 | tcg_gen_op5i_i32(INDEX_op_qemu_ld64, TCGV_LOW(ret), TCGV_HIGH(ret), |
2444 | TCGV_LOW(addr), TCGV_HIGH(addr), mem_index); | |
c896fe29 FB |
2445 | #endif |
2446 | } | |
2447 | ||
ac56dd48 | 2448 | static inline void tcg_gen_qemu_st8(TCGv arg, TCGv addr, int mem_index) |
c896fe29 FB |
2449 | { |
2450 | #if TARGET_LONG_BITS == 32 | |
a7812ae4 | 2451 | tcg_gen_op3i_i32(INDEX_op_qemu_st8, arg, addr, mem_index); |
c896fe29 | 2452 | #else |
a7812ae4 PB |
2453 | tcg_gen_op4i_i32(INDEX_op_qemu_st8, TCGV_LOW(arg), TCGV_LOW(addr), |
2454 | TCGV_HIGH(addr), mem_index); | |
c896fe29 FB |
2455 | #endif |
2456 | } | |
2457 | ||
ac56dd48 | 2458 | static inline void tcg_gen_qemu_st16(TCGv arg, TCGv addr, int mem_index) |
c896fe29 FB |
2459 | { |
2460 | #if TARGET_LONG_BITS == 32 | |
a7812ae4 | 2461 | tcg_gen_op3i_i32(INDEX_op_qemu_st16, arg, addr, mem_index); |
c896fe29 | 2462 | #else |
a7812ae4 PB |
2463 | tcg_gen_op4i_i32(INDEX_op_qemu_st16, TCGV_LOW(arg), TCGV_LOW(addr), |
2464 | TCGV_HIGH(addr), mem_index); | |
c896fe29 FB |
2465 | #endif |
2466 | } | |
2467 | ||
ac56dd48 | 2468 | static inline void tcg_gen_qemu_st32(TCGv arg, TCGv addr, int mem_index) |
c896fe29 FB |
2469 | { |
2470 | #if TARGET_LONG_BITS == 32 | |
a7812ae4 | 2471 | tcg_gen_op3i_i32(INDEX_op_qemu_st32, arg, addr, mem_index); |
c896fe29 | 2472 | #else |
a7812ae4 PB |
2473 | tcg_gen_op4i_i32(INDEX_op_qemu_st32, TCGV_LOW(arg), TCGV_LOW(addr), |
2474 | TCGV_HIGH(addr), mem_index); | |
c896fe29 FB |
2475 | #endif |
2476 | } | |
2477 | ||
a7812ae4 | 2478 | static inline void tcg_gen_qemu_st64(TCGv_i64 arg, TCGv addr, int mem_index) |
c896fe29 FB |
2479 | { |
2480 | #if TARGET_LONG_BITS == 32 | |
a7812ae4 PB |
2481 | tcg_gen_op4i_i32(INDEX_op_qemu_st64, TCGV_LOW(arg), TCGV_HIGH(arg), addr, |
2482 | mem_index); | |
c896fe29 | 2483 | #else |
a7812ae4 PB |
2484 | tcg_gen_op5i_i32(INDEX_op_qemu_st64, TCGV_LOW(arg), TCGV_HIGH(arg), |
2485 | TCGV_LOW(addr), TCGV_HIGH(addr), mem_index); | |
c896fe29 FB |
2486 | #endif |
2487 | } | |
2488 | ||
ebecf363 PM |
2489 | #define tcg_gen_ld_ptr(R, A, O) tcg_gen_ld_i32(TCGV_PTR_TO_NAT(R), (A), (O)) |
2490 | #define tcg_gen_discard_ptr(A) tcg_gen_discard_i32(TCGV_PTR_TO_NAT(A)) | |
f8422f52 | 2491 | |
c896fe29 FB |
2492 | #else /* TCG_TARGET_REG_BITS == 32 */ |
2493 | ||
ac56dd48 | 2494 | static inline void tcg_gen_qemu_ld8u(TCGv ret, TCGv addr, int mem_index) |
c896fe29 | 2495 | { |
a7812ae4 | 2496 | tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld8u, ret, addr, mem_index); |
c896fe29 FB |
2497 | } |
2498 | ||
ac56dd48 | 2499 | static inline void tcg_gen_qemu_ld8s(TCGv ret, TCGv addr, int mem_index) |
c896fe29 | 2500 | { |
a7812ae4 | 2501 | tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld8s, ret, addr, mem_index); |
c896fe29 FB |
2502 | } |
2503 | ||
ac56dd48 | 2504 | static inline void tcg_gen_qemu_ld16u(TCGv ret, TCGv addr, int mem_index) |
c896fe29 | 2505 | { |
a7812ae4 | 2506 | tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld16u, ret, addr, mem_index); |
c896fe29 FB |
2507 | } |
2508 | ||
ac56dd48 | 2509 | static inline void tcg_gen_qemu_ld16s(TCGv ret, TCGv addr, int mem_index) |
c896fe29 | 2510 | { |
a7812ae4 | 2511 | tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld16s, ret, addr, mem_index); |
c896fe29 FB |
2512 | } |
2513 | ||
ac56dd48 | 2514 | static inline void tcg_gen_qemu_ld32u(TCGv ret, TCGv addr, int mem_index) |
c896fe29 | 2515 | { |
3e1dbadd RH |
2516 | #if TARGET_LONG_BITS == 32 |
2517 | tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld32, ret, addr, mem_index); | |
2518 | #else | |
a7812ae4 | 2519 | tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld32u, ret, addr, mem_index); |
3e1dbadd | 2520 | #endif |
c896fe29 FB |
2521 | } |
2522 | ||
ac56dd48 | 2523 | static inline void tcg_gen_qemu_ld32s(TCGv ret, TCGv addr, int mem_index) |
c896fe29 | 2524 | { |
3e1dbadd RH |
2525 | #if TARGET_LONG_BITS == 32 |
2526 | tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld32, ret, addr, mem_index); | |
2527 | #else | |
a7812ae4 | 2528 | tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld32s, ret, addr, mem_index); |
3e1dbadd | 2529 | #endif |
c896fe29 FB |
2530 | } |
2531 | ||
a7812ae4 | 2532 | static inline void tcg_gen_qemu_ld64(TCGv_i64 ret, TCGv addr, int mem_index) |
c896fe29 | 2533 | { |
a7812ae4 | 2534 | tcg_gen_qemu_ldst_op_i64(INDEX_op_qemu_ld64, ret, addr, mem_index); |
c896fe29 FB |
2535 | } |
2536 | ||
ac56dd48 | 2537 | static inline void tcg_gen_qemu_st8(TCGv arg, TCGv addr, int mem_index) |
c896fe29 | 2538 | { |
a7812ae4 | 2539 | tcg_gen_qemu_ldst_op(INDEX_op_qemu_st8, arg, addr, mem_index); |
c896fe29 FB |
2540 | } |
2541 | ||
ac56dd48 | 2542 | static inline void tcg_gen_qemu_st16(TCGv arg, TCGv addr, int mem_index) |
c896fe29 | 2543 | { |
a7812ae4 | 2544 | tcg_gen_qemu_ldst_op(INDEX_op_qemu_st16, arg, addr, mem_index); |
c896fe29 FB |
2545 | } |
2546 | ||
ac56dd48 | 2547 | static inline void tcg_gen_qemu_st32(TCGv arg, TCGv addr, int mem_index) |
c896fe29 | 2548 | { |
a7812ae4 | 2549 | tcg_gen_qemu_ldst_op(INDEX_op_qemu_st32, arg, addr, mem_index); |
c896fe29 FB |
2550 | } |
2551 | ||
a7812ae4 | 2552 | static inline void tcg_gen_qemu_st64(TCGv_i64 arg, TCGv addr, int mem_index) |
c896fe29 | 2553 | { |
a7812ae4 | 2554 | tcg_gen_qemu_ldst_op_i64(INDEX_op_qemu_st64, arg, addr, mem_index); |
c896fe29 FB |
2555 | } |
2556 | ||
ebecf363 PM |
2557 | #define tcg_gen_ld_ptr(R, A, O) tcg_gen_ld_i64(TCGV_PTR_TO_NAT(R), (A), (O)) |
2558 | #define tcg_gen_discard_ptr(A) tcg_gen_discard_i64(TCGV_PTR_TO_NAT(A)) | |
f8422f52 | 2559 | |
c896fe29 | 2560 | #endif /* TCG_TARGET_REG_BITS != 32 */ |
f8422f52 BS |
2561 | |
2562 | #if TARGET_LONG_BITS == 64 | |
f8422f52 BS |
2563 | #define tcg_gen_movi_tl tcg_gen_movi_i64 |
2564 | #define tcg_gen_mov_tl tcg_gen_mov_i64 | |
2565 | #define tcg_gen_ld8u_tl tcg_gen_ld8u_i64 | |
2566 | #define tcg_gen_ld8s_tl tcg_gen_ld8s_i64 | |
2567 | #define tcg_gen_ld16u_tl tcg_gen_ld16u_i64 | |
2568 | #define tcg_gen_ld16s_tl tcg_gen_ld16s_i64 | |
2569 | #define tcg_gen_ld32u_tl tcg_gen_ld32u_i64 | |
2570 | #define tcg_gen_ld32s_tl tcg_gen_ld32s_i64 | |
2571 | #define tcg_gen_ld_tl tcg_gen_ld_i64 | |
2572 | #define tcg_gen_st8_tl tcg_gen_st8_i64 | |
2573 | #define tcg_gen_st16_tl tcg_gen_st16_i64 | |
2574 | #define tcg_gen_st32_tl tcg_gen_st32_i64 | |
2575 | #define tcg_gen_st_tl tcg_gen_st_i64 | |
2576 | #define tcg_gen_add_tl tcg_gen_add_i64 | |
2577 | #define tcg_gen_addi_tl tcg_gen_addi_i64 | |
2578 | #define tcg_gen_sub_tl tcg_gen_sub_i64 | |
390efc54 | 2579 | #define tcg_gen_neg_tl tcg_gen_neg_i64 |
10460c8a | 2580 | #define tcg_gen_subfi_tl tcg_gen_subfi_i64 |
f8422f52 BS |
2581 | #define tcg_gen_subi_tl tcg_gen_subi_i64 |
2582 | #define tcg_gen_and_tl tcg_gen_and_i64 | |
2583 | #define tcg_gen_andi_tl tcg_gen_andi_i64 | |
2584 | #define tcg_gen_or_tl tcg_gen_or_i64 | |
2585 | #define tcg_gen_ori_tl tcg_gen_ori_i64 | |
2586 | #define tcg_gen_xor_tl tcg_gen_xor_i64 | |
2587 | #define tcg_gen_xori_tl tcg_gen_xori_i64 | |
0b6ce4cf | 2588 | #define tcg_gen_not_tl tcg_gen_not_i64 |
f8422f52 BS |
2589 | #define tcg_gen_shl_tl tcg_gen_shl_i64 |
2590 | #define tcg_gen_shli_tl tcg_gen_shli_i64 | |
2591 | #define tcg_gen_shr_tl tcg_gen_shr_i64 | |
2592 | #define tcg_gen_shri_tl tcg_gen_shri_i64 | |
2593 | #define tcg_gen_sar_tl tcg_gen_sar_i64 | |
2594 | #define tcg_gen_sari_tl tcg_gen_sari_i64 | |
0cf767d6 | 2595 | #define tcg_gen_brcond_tl tcg_gen_brcond_i64 |
cb63669a | 2596 | #define tcg_gen_brcondi_tl tcg_gen_brcondi_i64 |
be210acb | 2597 | #define tcg_gen_setcond_tl tcg_gen_setcond_i64 |
add1e7ea | 2598 | #define tcg_gen_setcondi_tl tcg_gen_setcondi_i64 |
f730fd27 TS |
2599 | #define tcg_gen_mul_tl tcg_gen_mul_i64 |
2600 | #define tcg_gen_muli_tl tcg_gen_muli_i64 | |
ab36421e AJ |
2601 | #define tcg_gen_div_tl tcg_gen_div_i64 |
2602 | #define tcg_gen_rem_tl tcg_gen_rem_i64 | |
864951af AJ |
2603 | #define tcg_gen_divu_tl tcg_gen_divu_i64 |
2604 | #define tcg_gen_remu_tl tcg_gen_remu_i64 | |
a768e4b2 | 2605 | #define tcg_gen_discard_tl tcg_gen_discard_i64 |
e429073d BS |
2606 | #define tcg_gen_trunc_tl_i32 tcg_gen_trunc_i64_i32 |
2607 | #define tcg_gen_trunc_i64_tl tcg_gen_mov_i64 | |
2608 | #define tcg_gen_extu_i32_tl tcg_gen_extu_i32_i64 | |
2609 | #define tcg_gen_ext_i32_tl tcg_gen_ext_i32_i64 | |
2610 | #define tcg_gen_extu_tl_i64 tcg_gen_mov_i64 | |
2611 | #define tcg_gen_ext_tl_i64 tcg_gen_mov_i64 | |
0b6ce4cf FB |
2612 | #define tcg_gen_ext8u_tl tcg_gen_ext8u_i64 |
2613 | #define tcg_gen_ext8s_tl tcg_gen_ext8s_i64 | |
2614 | #define tcg_gen_ext16u_tl tcg_gen_ext16u_i64 | |
2615 | #define tcg_gen_ext16s_tl tcg_gen_ext16s_i64 | |
2616 | #define tcg_gen_ext32u_tl tcg_gen_ext32u_i64 | |
2617 | #define tcg_gen_ext32s_tl tcg_gen_ext32s_i64 | |
911d79ba AJ |
2618 | #define tcg_gen_bswap16_tl tcg_gen_bswap16_i64 |
2619 | #define tcg_gen_bswap32_tl tcg_gen_bswap32_i64 | |
2620 | #define tcg_gen_bswap64_tl tcg_gen_bswap64_i64 | |
945ca823 | 2621 | #define tcg_gen_concat_tl_i64 tcg_gen_concat32_i64 |
f24cb33e AJ |
2622 | #define tcg_gen_andc_tl tcg_gen_andc_i64 |
2623 | #define tcg_gen_eqv_tl tcg_gen_eqv_i64 | |
2624 | #define tcg_gen_nand_tl tcg_gen_nand_i64 | |
2625 | #define tcg_gen_nor_tl tcg_gen_nor_i64 | |
2626 | #define tcg_gen_orc_tl tcg_gen_orc_i64 | |
15824571 AJ |
2627 | #define tcg_gen_rotl_tl tcg_gen_rotl_i64 |
2628 | #define tcg_gen_rotli_tl tcg_gen_rotli_i64 | |
2629 | #define tcg_gen_rotr_tl tcg_gen_rotr_i64 | |
2630 | #define tcg_gen_rotri_tl tcg_gen_rotri_i64 | |
b7767f0f | 2631 | #define tcg_gen_deposit_tl tcg_gen_deposit_i64 |
a98824ac | 2632 | #define tcg_const_tl tcg_const_i64 |
bdffd4a9 | 2633 | #define tcg_const_local_tl tcg_const_local_i64 |
ffc5ea09 | 2634 | #define tcg_gen_movcond_tl tcg_gen_movcond_i64 |
f8422f52 | 2635 | #else |
f8422f52 BS |
2636 | #define tcg_gen_movi_tl tcg_gen_movi_i32 |
2637 | #define tcg_gen_mov_tl tcg_gen_mov_i32 | |
2638 | #define tcg_gen_ld8u_tl tcg_gen_ld8u_i32 | |
2639 | #define tcg_gen_ld8s_tl tcg_gen_ld8s_i32 | |
2640 | #define tcg_gen_ld16u_tl tcg_gen_ld16u_i32 | |
2641 | #define tcg_gen_ld16s_tl tcg_gen_ld16s_i32 | |
2642 | #define tcg_gen_ld32u_tl tcg_gen_ld_i32 | |
2643 | #define tcg_gen_ld32s_tl tcg_gen_ld_i32 | |
2644 | #define tcg_gen_ld_tl tcg_gen_ld_i32 | |
2645 | #define tcg_gen_st8_tl tcg_gen_st8_i32 | |
2646 | #define tcg_gen_st16_tl tcg_gen_st16_i32 | |
2647 | #define tcg_gen_st32_tl tcg_gen_st_i32 | |
2648 | #define tcg_gen_st_tl tcg_gen_st_i32 | |
2649 | #define tcg_gen_add_tl tcg_gen_add_i32 | |
2650 | #define tcg_gen_addi_tl tcg_gen_addi_i32 | |
2651 | #define tcg_gen_sub_tl tcg_gen_sub_i32 | |
390efc54 | 2652 | #define tcg_gen_neg_tl tcg_gen_neg_i32 |
0045734a | 2653 | #define tcg_gen_subfi_tl tcg_gen_subfi_i32 |
f8422f52 BS |
2654 | #define tcg_gen_subi_tl tcg_gen_subi_i32 |
2655 | #define tcg_gen_and_tl tcg_gen_and_i32 | |
2656 | #define tcg_gen_andi_tl tcg_gen_andi_i32 | |
2657 | #define tcg_gen_or_tl tcg_gen_or_i32 | |
2658 | #define tcg_gen_ori_tl tcg_gen_ori_i32 | |
2659 | #define tcg_gen_xor_tl tcg_gen_xor_i32 | |
2660 | #define tcg_gen_xori_tl tcg_gen_xori_i32 | |
0b6ce4cf | 2661 | #define tcg_gen_not_tl tcg_gen_not_i32 |
f8422f52 BS |
2662 | #define tcg_gen_shl_tl tcg_gen_shl_i32 |
2663 | #define tcg_gen_shli_tl tcg_gen_shli_i32 | |
2664 | #define tcg_gen_shr_tl tcg_gen_shr_i32 | |
2665 | #define tcg_gen_shri_tl tcg_gen_shri_i32 | |
2666 | #define tcg_gen_sar_tl tcg_gen_sar_i32 | |
2667 | #define tcg_gen_sari_tl tcg_gen_sari_i32 | |
0cf767d6 | 2668 | #define tcg_gen_brcond_tl tcg_gen_brcond_i32 |
cb63669a | 2669 | #define tcg_gen_brcondi_tl tcg_gen_brcondi_i32 |
be210acb | 2670 | #define tcg_gen_setcond_tl tcg_gen_setcond_i32 |
add1e7ea | 2671 | #define tcg_gen_setcondi_tl tcg_gen_setcondi_i32 |
f730fd27 TS |
2672 | #define tcg_gen_mul_tl tcg_gen_mul_i32 |
2673 | #define tcg_gen_muli_tl tcg_gen_muli_i32 | |
ab36421e AJ |
2674 | #define tcg_gen_div_tl tcg_gen_div_i32 |
2675 | #define tcg_gen_rem_tl tcg_gen_rem_i32 | |
864951af AJ |
2676 | #define tcg_gen_divu_tl tcg_gen_divu_i32 |
2677 | #define tcg_gen_remu_tl tcg_gen_remu_i32 | |
a768e4b2 | 2678 | #define tcg_gen_discard_tl tcg_gen_discard_i32 |
e429073d BS |
2679 | #define tcg_gen_trunc_tl_i32 tcg_gen_mov_i32 |
2680 | #define tcg_gen_trunc_i64_tl tcg_gen_trunc_i64_i32 | |
2681 | #define tcg_gen_extu_i32_tl tcg_gen_mov_i32 | |
2682 | #define tcg_gen_ext_i32_tl tcg_gen_mov_i32 | |
2683 | #define tcg_gen_extu_tl_i64 tcg_gen_extu_i32_i64 | |
2684 | #define tcg_gen_ext_tl_i64 tcg_gen_ext_i32_i64 | |
0b6ce4cf FB |
2685 | #define tcg_gen_ext8u_tl tcg_gen_ext8u_i32 |
2686 | #define tcg_gen_ext8s_tl tcg_gen_ext8s_i32 | |
2687 | #define tcg_gen_ext16u_tl tcg_gen_ext16u_i32 | |
2688 | #define tcg_gen_ext16s_tl tcg_gen_ext16s_i32 | |
2689 | #define tcg_gen_ext32u_tl tcg_gen_mov_i32 | |
2690 | #define tcg_gen_ext32s_tl tcg_gen_mov_i32 | |
911d79ba AJ |
2691 | #define tcg_gen_bswap16_tl tcg_gen_bswap16_i32 |
2692 | #define tcg_gen_bswap32_tl tcg_gen_bswap32_i32 | |
945ca823 | 2693 | #define tcg_gen_concat_tl_i64 tcg_gen_concat_i32_i64 |
f24cb33e AJ |
2694 | #define tcg_gen_andc_tl tcg_gen_andc_i32 |
2695 | #define tcg_gen_eqv_tl tcg_gen_eqv_i32 | |
2696 | #define tcg_gen_nand_tl tcg_gen_nand_i32 | |
2697 | #define tcg_gen_nor_tl tcg_gen_nor_i32 | |
2698 | #define tcg_gen_orc_tl tcg_gen_orc_i32 | |
15824571 AJ |
2699 | #define tcg_gen_rotl_tl tcg_gen_rotl_i32 |
2700 | #define tcg_gen_rotli_tl tcg_gen_rotli_i32 | |
2701 | #define tcg_gen_rotr_tl tcg_gen_rotr_i32 | |
2702 | #define tcg_gen_rotri_tl tcg_gen_rotri_i32 | |
b7767f0f | 2703 | #define tcg_gen_deposit_tl tcg_gen_deposit_i32 |
a98824ac | 2704 | #define tcg_const_tl tcg_const_i32 |
bdffd4a9 | 2705 | #define tcg_const_local_tl tcg_const_local_i32 |
ffc5ea09 | 2706 | #define tcg_gen_movcond_tl tcg_gen_movcond_i32 |
f8422f52 | 2707 | #endif |
6ddbc6e4 PB |
2708 | |
2709 | #if TCG_TARGET_REG_BITS == 32 | |
ebecf363 PM |
2710 | #define tcg_gen_add_ptr(R, A, B) tcg_gen_add_i32(TCGV_PTR_TO_NAT(R), \ |
2711 | TCGV_PTR_TO_NAT(A), \ | |
2712 | TCGV_PTR_TO_NAT(B)) | |
2713 | #define tcg_gen_addi_ptr(R, A, B) tcg_gen_addi_i32(TCGV_PTR_TO_NAT(R), \ | |
2714 | TCGV_PTR_TO_NAT(A), (B)) | |
2715 | #define tcg_gen_ext_i32_ptr(R, A) tcg_gen_mov_i32(TCGV_PTR_TO_NAT(R), (A)) | |
6ddbc6e4 | 2716 | #else /* TCG_TARGET_REG_BITS == 32 */ |
ebecf363 PM |
2717 | #define tcg_gen_add_ptr(R, A, B) tcg_gen_add_i64(TCGV_PTR_TO_NAT(R), \ |
2718 | TCGV_PTR_TO_NAT(A), \ | |
2719 | TCGV_PTR_TO_NAT(B)) | |
2720 | #define tcg_gen_addi_ptr(R, A, B) tcg_gen_addi_i64(TCGV_PTR_TO_NAT(R), \ | |
2721 | TCGV_PTR_TO_NAT(A), (B)) | |
2722 | #define tcg_gen_ext_i32_ptr(R, A) tcg_gen_ext_i32_i64(TCGV_PTR_TO_NAT(R), (A)) | |
6ddbc6e4 | 2723 | #endif /* TCG_TARGET_REG_BITS != 32 */ |