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c896fe29 FB |
1 | /* |
2 | * Tiny Code Generator for QEMU | |
3 | * | |
4 | * Copyright (c) 2008 Fabrice Bellard | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
24 | #include "tcg.h" | |
25 | ||
c896fe29 FB |
26 | int gen_new_label(void); |
27 | ||
a9751609 | 28 | static inline void tcg_gen_op1_i32(TCGOpcode opc, TCGv_i32 arg1) |
c896fe29 FB |
29 | { |
30 | *gen_opc_ptr++ = opc; | |
a7812ae4 PB |
31 | *gen_opparam_ptr++ = GET_TCGV_I32(arg1); |
32 | } | |
33 | ||
a9751609 | 34 | static inline void tcg_gen_op1_i64(TCGOpcode opc, TCGv_i64 arg1) |
a7812ae4 PB |
35 | { |
36 | *gen_opc_ptr++ = opc; | |
37 | *gen_opparam_ptr++ = GET_TCGV_I64(arg1); | |
c896fe29 FB |
38 | } |
39 | ||
a9751609 | 40 | static inline void tcg_gen_op1i(TCGOpcode opc, TCGArg arg1) |
c896fe29 FB |
41 | { |
42 | *gen_opc_ptr++ = opc; | |
43 | *gen_opparam_ptr++ = arg1; | |
c896fe29 FB |
44 | } |
45 | ||
a9751609 | 46 | static inline void tcg_gen_op2_i32(TCGOpcode opc, TCGv_i32 arg1, TCGv_i32 arg2) |
a7812ae4 PB |
47 | { |
48 | *gen_opc_ptr++ = opc; | |
49 | *gen_opparam_ptr++ = GET_TCGV_I32(arg1); | |
50 | *gen_opparam_ptr++ = GET_TCGV_I32(arg2); | |
51 | } | |
52 | ||
a9751609 | 53 | static inline void tcg_gen_op2_i64(TCGOpcode opc, TCGv_i64 arg1, TCGv_i64 arg2) |
a7812ae4 PB |
54 | { |
55 | *gen_opc_ptr++ = opc; | |
56 | *gen_opparam_ptr++ = GET_TCGV_I64(arg1); | |
57 | *gen_opparam_ptr++ = GET_TCGV_I64(arg2); | |
58 | } | |
59 | ||
a9751609 | 60 | static inline void tcg_gen_op2i_i32(TCGOpcode opc, TCGv_i32 arg1, TCGArg arg2) |
c896fe29 FB |
61 | { |
62 | *gen_opc_ptr++ = opc; | |
a7812ae4 PB |
63 | *gen_opparam_ptr++ = GET_TCGV_I32(arg1); |
64 | *gen_opparam_ptr++ = arg2; | |
c896fe29 FB |
65 | } |
66 | ||
a9751609 | 67 | static inline void tcg_gen_op2i_i64(TCGOpcode opc, TCGv_i64 arg1, TCGArg arg2) |
c896fe29 FB |
68 | { |
69 | *gen_opc_ptr++ = opc; | |
a7812ae4 | 70 | *gen_opparam_ptr++ = GET_TCGV_I64(arg1); |
c896fe29 | 71 | *gen_opparam_ptr++ = arg2; |
ac56dd48 PB |
72 | } |
73 | ||
a9751609 | 74 | static inline void tcg_gen_op2ii(TCGOpcode opc, TCGArg arg1, TCGArg arg2) |
bcb0126f PB |
75 | { |
76 | *gen_opc_ptr++ = opc; | |
77 | *gen_opparam_ptr++ = arg1; | |
78 | *gen_opparam_ptr++ = arg2; | |
79 | } | |
80 | ||
a9751609 | 81 | static inline void tcg_gen_op3_i32(TCGOpcode opc, TCGv_i32 arg1, TCGv_i32 arg2, |
a7812ae4 PB |
82 | TCGv_i32 arg3) |
83 | { | |
84 | *gen_opc_ptr++ = opc; | |
85 | *gen_opparam_ptr++ = GET_TCGV_I32(arg1); | |
86 | *gen_opparam_ptr++ = GET_TCGV_I32(arg2); | |
87 | *gen_opparam_ptr++ = GET_TCGV_I32(arg3); | |
88 | } | |
89 | ||
a9751609 | 90 | static inline void tcg_gen_op3_i64(TCGOpcode opc, TCGv_i64 arg1, TCGv_i64 arg2, |
a7812ae4 PB |
91 | TCGv_i64 arg3) |
92 | { | |
93 | *gen_opc_ptr++ = opc; | |
94 | *gen_opparam_ptr++ = GET_TCGV_I64(arg1); | |
95 | *gen_opparam_ptr++ = GET_TCGV_I64(arg2); | |
96 | *gen_opparam_ptr++ = GET_TCGV_I64(arg3); | |
97 | } | |
98 | ||
a9751609 RH |
99 | static inline void tcg_gen_op3i_i32(TCGOpcode opc, TCGv_i32 arg1, |
100 | TCGv_i32 arg2, TCGArg arg3) | |
ac56dd48 PB |
101 | { |
102 | *gen_opc_ptr++ = opc; | |
a7812ae4 PB |
103 | *gen_opparam_ptr++ = GET_TCGV_I32(arg1); |
104 | *gen_opparam_ptr++ = GET_TCGV_I32(arg2); | |
105 | *gen_opparam_ptr++ = arg3; | |
ac56dd48 PB |
106 | } |
107 | ||
a9751609 RH |
108 | static inline void tcg_gen_op3i_i64(TCGOpcode opc, TCGv_i64 arg1, |
109 | TCGv_i64 arg2, TCGArg arg3) | |
ac56dd48 PB |
110 | { |
111 | *gen_opc_ptr++ = opc; | |
a7812ae4 PB |
112 | *gen_opparam_ptr++ = GET_TCGV_I64(arg1); |
113 | *gen_opparam_ptr++ = GET_TCGV_I64(arg2); | |
c896fe29 | 114 | *gen_opparam_ptr++ = arg3; |
ac56dd48 PB |
115 | } |
116 | ||
a9751609 RH |
117 | static inline void tcg_gen_ldst_op_i32(TCGOpcode opc, TCGv_i32 val, |
118 | TCGv_ptr base, TCGArg offset) | |
a7812ae4 PB |
119 | { |
120 | *gen_opc_ptr++ = opc; | |
121 | *gen_opparam_ptr++ = GET_TCGV_I32(val); | |
122 | *gen_opparam_ptr++ = GET_TCGV_PTR(base); | |
123 | *gen_opparam_ptr++ = offset; | |
124 | } | |
125 | ||
a9751609 RH |
126 | static inline void tcg_gen_ldst_op_i64(TCGOpcode opc, TCGv_i64 val, |
127 | TCGv_ptr base, TCGArg offset) | |
a7812ae4 PB |
128 | { |
129 | *gen_opc_ptr++ = opc; | |
a810a2de | 130 | *gen_opparam_ptr++ = GET_TCGV_I64(val); |
a7812ae4 PB |
131 | *gen_opparam_ptr++ = GET_TCGV_PTR(base); |
132 | *gen_opparam_ptr++ = offset; | |
133 | } | |
134 | ||
a9751609 RH |
135 | static inline void tcg_gen_qemu_ldst_op_i64_i32(TCGOpcode opc, TCGv_i64 val, |
136 | TCGv_i32 addr, TCGArg mem_index) | |
a7812ae4 PB |
137 | { |
138 | *gen_opc_ptr++ = opc; | |
139 | *gen_opparam_ptr++ = GET_TCGV_I64(val); | |
140 | *gen_opparam_ptr++ = GET_TCGV_I32(addr); | |
141 | *gen_opparam_ptr++ = mem_index; | |
142 | } | |
143 | ||
a9751609 RH |
144 | static inline void tcg_gen_qemu_ldst_op_i64_i64(TCGOpcode opc, TCGv_i64 val, |
145 | TCGv_i64 addr, TCGArg mem_index) | |
a7812ae4 PB |
146 | { |
147 | *gen_opc_ptr++ = opc; | |
148 | *gen_opparam_ptr++ = GET_TCGV_I64(val); | |
149 | *gen_opparam_ptr++ = GET_TCGV_I64(addr); | |
150 | *gen_opparam_ptr++ = mem_index; | |
151 | } | |
152 | ||
a9751609 | 153 | static inline void tcg_gen_op4_i32(TCGOpcode opc, TCGv_i32 arg1, TCGv_i32 arg2, |
a7812ae4 PB |
154 | TCGv_i32 arg3, TCGv_i32 arg4) |
155 | { | |
156 | *gen_opc_ptr++ = opc; | |
157 | *gen_opparam_ptr++ = GET_TCGV_I32(arg1); | |
158 | *gen_opparam_ptr++ = GET_TCGV_I32(arg2); | |
159 | *gen_opparam_ptr++ = GET_TCGV_I32(arg3); | |
160 | *gen_opparam_ptr++ = GET_TCGV_I32(arg4); | |
161 | } | |
162 | ||
a9751609 | 163 | static inline void tcg_gen_op4_i64(TCGOpcode opc, TCGv_i64 arg1, TCGv_i64 arg2, |
a810a2de | 164 | TCGv_i64 arg3, TCGv_i64 arg4) |
a7812ae4 PB |
165 | { |
166 | *gen_opc_ptr++ = opc; | |
167 | *gen_opparam_ptr++ = GET_TCGV_I64(arg1); | |
168 | *gen_opparam_ptr++ = GET_TCGV_I64(arg2); | |
169 | *gen_opparam_ptr++ = GET_TCGV_I64(arg3); | |
170 | *gen_opparam_ptr++ = GET_TCGV_I64(arg4); | |
171 | } | |
172 | ||
a9751609 | 173 | static inline void tcg_gen_op4i_i32(TCGOpcode opc, TCGv_i32 arg1, TCGv_i32 arg2, |
a7812ae4 PB |
174 | TCGv_i32 arg3, TCGArg arg4) |
175 | { | |
176 | *gen_opc_ptr++ = opc; | |
177 | *gen_opparam_ptr++ = GET_TCGV_I32(arg1); | |
178 | *gen_opparam_ptr++ = GET_TCGV_I32(arg2); | |
179 | *gen_opparam_ptr++ = GET_TCGV_I32(arg3); | |
180 | *gen_opparam_ptr++ = arg4; | |
181 | } | |
182 | ||
a9751609 | 183 | static inline void tcg_gen_op4i_i64(TCGOpcode opc, TCGv_i64 arg1, TCGv_i64 arg2, |
a7812ae4 | 184 | TCGv_i64 arg3, TCGArg arg4) |
ac56dd48 PB |
185 | { |
186 | *gen_opc_ptr++ = opc; | |
a7812ae4 PB |
187 | *gen_opparam_ptr++ = GET_TCGV_I64(arg1); |
188 | *gen_opparam_ptr++ = GET_TCGV_I64(arg2); | |
189 | *gen_opparam_ptr++ = GET_TCGV_I64(arg3); | |
190 | *gen_opparam_ptr++ = arg4; | |
ac56dd48 PB |
191 | } |
192 | ||
a9751609 | 193 | static inline void tcg_gen_op4ii_i32(TCGOpcode opc, TCGv_i32 arg1, TCGv_i32 arg2, |
a7812ae4 | 194 | TCGArg arg3, TCGArg arg4) |
ac56dd48 PB |
195 | { |
196 | *gen_opc_ptr++ = opc; | |
a7812ae4 PB |
197 | *gen_opparam_ptr++ = GET_TCGV_I32(arg1); |
198 | *gen_opparam_ptr++ = GET_TCGV_I32(arg2); | |
199 | *gen_opparam_ptr++ = arg3; | |
c896fe29 FB |
200 | *gen_opparam_ptr++ = arg4; |
201 | } | |
202 | ||
a9751609 | 203 | static inline void tcg_gen_op4ii_i64(TCGOpcode opc, TCGv_i64 arg1, TCGv_i64 arg2, |
a7812ae4 | 204 | TCGArg arg3, TCGArg arg4) |
c896fe29 FB |
205 | { |
206 | *gen_opc_ptr++ = opc; | |
a7812ae4 PB |
207 | *gen_opparam_ptr++ = GET_TCGV_I64(arg1); |
208 | *gen_opparam_ptr++ = GET_TCGV_I64(arg2); | |
c896fe29 FB |
209 | *gen_opparam_ptr++ = arg3; |
210 | *gen_opparam_ptr++ = arg4; | |
ac56dd48 PB |
211 | } |
212 | ||
a9751609 | 213 | static inline void tcg_gen_op5_i32(TCGOpcode opc, TCGv_i32 arg1, TCGv_i32 arg2, |
a7812ae4 PB |
214 | TCGv_i32 arg3, TCGv_i32 arg4, TCGv_i32 arg5) |
215 | { | |
216 | *gen_opc_ptr++ = opc; | |
217 | *gen_opparam_ptr++ = GET_TCGV_I32(arg1); | |
218 | *gen_opparam_ptr++ = GET_TCGV_I32(arg2); | |
219 | *gen_opparam_ptr++ = GET_TCGV_I32(arg3); | |
220 | *gen_opparam_ptr++ = GET_TCGV_I32(arg4); | |
221 | *gen_opparam_ptr++ = GET_TCGV_I32(arg5); | |
222 | } | |
223 | ||
a9751609 | 224 | static inline void tcg_gen_op5_i64(TCGOpcode opc, TCGv_i64 arg1, TCGv_i64 arg2, |
a7812ae4 PB |
225 | TCGv_i64 arg3, TCGv_i64 arg4, TCGv_i64 arg5) |
226 | { | |
227 | *gen_opc_ptr++ = opc; | |
228 | *gen_opparam_ptr++ = GET_TCGV_I64(arg1); | |
229 | *gen_opparam_ptr++ = GET_TCGV_I64(arg2); | |
230 | *gen_opparam_ptr++ = GET_TCGV_I64(arg3); | |
231 | *gen_opparam_ptr++ = GET_TCGV_I64(arg4); | |
232 | *gen_opparam_ptr++ = GET_TCGV_I64(arg5); | |
233 | } | |
234 | ||
a9751609 | 235 | static inline void tcg_gen_op5i_i32(TCGOpcode opc, TCGv_i32 arg1, TCGv_i32 arg2, |
a7812ae4 | 236 | TCGv_i32 arg3, TCGv_i32 arg4, TCGArg arg5) |
ac56dd48 PB |
237 | { |
238 | *gen_opc_ptr++ = opc; | |
a7812ae4 PB |
239 | *gen_opparam_ptr++ = GET_TCGV_I32(arg1); |
240 | *gen_opparam_ptr++ = GET_TCGV_I32(arg2); | |
241 | *gen_opparam_ptr++ = GET_TCGV_I32(arg3); | |
242 | *gen_opparam_ptr++ = GET_TCGV_I32(arg4); | |
243 | *gen_opparam_ptr++ = arg5; | |
ac56dd48 PB |
244 | } |
245 | ||
a9751609 | 246 | static inline void tcg_gen_op5i_i64(TCGOpcode opc, TCGv_i64 arg1, TCGv_i64 arg2, |
a7812ae4 | 247 | TCGv_i64 arg3, TCGv_i64 arg4, TCGArg arg5) |
ac56dd48 PB |
248 | { |
249 | *gen_opc_ptr++ = opc; | |
a7812ae4 PB |
250 | *gen_opparam_ptr++ = GET_TCGV_I64(arg1); |
251 | *gen_opparam_ptr++ = GET_TCGV_I64(arg2); | |
252 | *gen_opparam_ptr++ = GET_TCGV_I64(arg3); | |
253 | *gen_opparam_ptr++ = GET_TCGV_I64(arg4); | |
c896fe29 FB |
254 | *gen_opparam_ptr++ = arg5; |
255 | } | |
256 | ||
a9751609 | 257 | static inline void tcg_gen_op6_i32(TCGOpcode opc, TCGv_i32 arg1, TCGv_i32 arg2, |
a7812ae4 PB |
258 | TCGv_i32 arg3, TCGv_i32 arg4, TCGv_i32 arg5, |
259 | TCGv_i32 arg6) | |
260 | { | |
261 | *gen_opc_ptr++ = opc; | |
262 | *gen_opparam_ptr++ = GET_TCGV_I32(arg1); | |
263 | *gen_opparam_ptr++ = GET_TCGV_I32(arg2); | |
264 | *gen_opparam_ptr++ = GET_TCGV_I32(arg3); | |
265 | *gen_opparam_ptr++ = GET_TCGV_I32(arg4); | |
266 | *gen_opparam_ptr++ = GET_TCGV_I32(arg5); | |
267 | *gen_opparam_ptr++ = GET_TCGV_I32(arg6); | |
268 | } | |
269 | ||
a9751609 | 270 | static inline void tcg_gen_op6_i64(TCGOpcode opc, TCGv_i64 arg1, TCGv_i64 arg2, |
a7812ae4 PB |
271 | TCGv_i64 arg3, TCGv_i64 arg4, TCGv_i64 arg5, |
272 | TCGv_i64 arg6) | |
c896fe29 FB |
273 | { |
274 | *gen_opc_ptr++ = opc; | |
a7812ae4 PB |
275 | *gen_opparam_ptr++ = GET_TCGV_I64(arg1); |
276 | *gen_opparam_ptr++ = GET_TCGV_I64(arg2); | |
277 | *gen_opparam_ptr++ = GET_TCGV_I64(arg3); | |
278 | *gen_opparam_ptr++ = GET_TCGV_I64(arg4); | |
279 | *gen_opparam_ptr++ = GET_TCGV_I64(arg5); | |
280 | *gen_opparam_ptr++ = GET_TCGV_I64(arg6); | |
ac56dd48 PB |
281 | } |
282 | ||
a9751609 | 283 | static inline void tcg_gen_op6i_i32(TCGOpcode opc, TCGv_i32 arg1, TCGv_i32 arg2, |
be210acb RH |
284 | TCGv_i32 arg3, TCGv_i32 arg4, |
285 | TCGv_i32 arg5, TCGArg arg6) | |
286 | { | |
287 | *gen_opc_ptr++ = opc; | |
288 | *gen_opparam_ptr++ = GET_TCGV_I32(arg1); | |
289 | *gen_opparam_ptr++ = GET_TCGV_I32(arg2); | |
290 | *gen_opparam_ptr++ = GET_TCGV_I32(arg3); | |
291 | *gen_opparam_ptr++ = GET_TCGV_I32(arg4); | |
292 | *gen_opparam_ptr++ = GET_TCGV_I32(arg5); | |
293 | *gen_opparam_ptr++ = arg6; | |
294 | } | |
295 | ||
a9751609 | 296 | static inline void tcg_gen_op6i_i64(TCGOpcode opc, TCGv_i64 arg1, TCGv_i64 arg2, |
be210acb RH |
297 | TCGv_i64 arg3, TCGv_i64 arg4, |
298 | TCGv_i64 arg5, TCGArg arg6) | |
299 | { | |
300 | *gen_opc_ptr++ = opc; | |
301 | *gen_opparam_ptr++ = GET_TCGV_I64(arg1); | |
302 | *gen_opparam_ptr++ = GET_TCGV_I64(arg2); | |
303 | *gen_opparam_ptr++ = GET_TCGV_I64(arg3); | |
304 | *gen_opparam_ptr++ = GET_TCGV_I64(arg4); | |
305 | *gen_opparam_ptr++ = GET_TCGV_I64(arg5); | |
306 | *gen_opparam_ptr++ = arg6; | |
307 | } | |
308 | ||
a9751609 RH |
309 | static inline void tcg_gen_op6ii_i32(TCGOpcode opc, TCGv_i32 arg1, |
310 | TCGv_i32 arg2, TCGv_i32 arg3, | |
311 | TCGv_i32 arg4, TCGArg arg5, TCGArg arg6) | |
ac56dd48 PB |
312 | { |
313 | *gen_opc_ptr++ = opc; | |
a7812ae4 PB |
314 | *gen_opparam_ptr++ = GET_TCGV_I32(arg1); |
315 | *gen_opparam_ptr++ = GET_TCGV_I32(arg2); | |
316 | *gen_opparam_ptr++ = GET_TCGV_I32(arg3); | |
317 | *gen_opparam_ptr++ = GET_TCGV_I32(arg4); | |
318 | *gen_opparam_ptr++ = arg5; | |
319 | *gen_opparam_ptr++ = arg6; | |
320 | } | |
321 | ||
a9751609 RH |
322 | static inline void tcg_gen_op6ii_i64(TCGOpcode opc, TCGv_i64 arg1, |
323 | TCGv_i64 arg2, TCGv_i64 arg3, | |
324 | TCGv_i64 arg4, TCGArg arg5, TCGArg arg6) | |
a7812ae4 PB |
325 | { |
326 | *gen_opc_ptr++ = opc; | |
327 | *gen_opparam_ptr++ = GET_TCGV_I64(arg1); | |
328 | *gen_opparam_ptr++ = GET_TCGV_I64(arg2); | |
329 | *gen_opparam_ptr++ = GET_TCGV_I64(arg3); | |
330 | *gen_opparam_ptr++ = GET_TCGV_I64(arg4); | |
c896fe29 FB |
331 | *gen_opparam_ptr++ = arg5; |
332 | *gen_opparam_ptr++ = arg6; | |
333 | } | |
334 | ||
335 | static inline void gen_set_label(int n) | |
336 | { | |
ac56dd48 | 337 | tcg_gen_op1i(INDEX_op_set_label, n); |
c896fe29 FB |
338 | } |
339 | ||
fb50d413 BS |
340 | static inline void tcg_gen_br(int label) |
341 | { | |
342 | tcg_gen_op1i(INDEX_op_br, label); | |
343 | } | |
344 | ||
a7812ae4 | 345 | static inline void tcg_gen_mov_i32(TCGv_i32 ret, TCGv_i32 arg) |
c896fe29 | 346 | { |
fe75bcf7 | 347 | if (!TCGV_EQUAL_I32(ret, arg)) |
a7812ae4 | 348 | tcg_gen_op2_i32(INDEX_op_mov_i32, ret, arg); |
c896fe29 FB |
349 | } |
350 | ||
a7812ae4 | 351 | static inline void tcg_gen_movi_i32(TCGv_i32 ret, int32_t arg) |
c896fe29 | 352 | { |
a7812ae4 | 353 | tcg_gen_op2i_i32(INDEX_op_movi_i32, ret, arg); |
c896fe29 FB |
354 | } |
355 | ||
2bece2c8 RH |
356 | /* A version of dh_sizemask from def-helper.h that doesn't rely on |
357 | preprocessor magic. */ | |
358 | static inline int tcg_gen_sizemask(int n, int is_64bit, int is_signed) | |
359 | { | |
360 | return (is_64bit << n*2) | (is_signed << (n*2 + 1)); | |
361 | } | |
362 | ||
c896fe29 | 363 | /* helper calls */ |
a7812ae4 PB |
364 | static inline void tcg_gen_helperN(void *func, int flags, int sizemask, |
365 | TCGArg ret, int nargs, TCGArg *args) | |
366 | { | |
367 | TCGv_ptr fn; | |
368 | fn = tcg_const_ptr((tcg_target_long)func); | |
369 | tcg_gen_callN(&tcg_ctx, fn, flags, sizemask, ret, | |
370 | nargs, args); | |
371 | tcg_temp_free_ptr(fn); | |
372 | } | |
c896fe29 | 373 | |
dbfff4de AJ |
374 | /* Note: Both tcg_gen_helper32() and tcg_gen_helper64() are currently |
375 | reserved for helpers in tcg-runtime.c. These helpers are all const | |
376 | and pure, hence the call to tcg_gen_callN() with TCG_CALL_CONST | | |
377 | TCG_CALL_PURE. This may need to be adjusted if these functions | |
378 | start to be used with other helpers. */ | |
2bece2c8 | 379 | static inline void tcg_gen_helper32(void *func, int sizemask, TCGv_i32 ret, |
31d66551 AJ |
380 | TCGv_i32 a, TCGv_i32 b) |
381 | { | |
382 | TCGv_ptr fn; | |
383 | TCGArg args[2]; | |
384 | fn = tcg_const_ptr((tcg_target_long)func); | |
385 | args[0] = GET_TCGV_I32(a); | |
386 | args[1] = GET_TCGV_I32(b); | |
2bece2c8 RH |
387 | tcg_gen_callN(&tcg_ctx, fn, TCG_CALL_CONST | TCG_CALL_PURE, sizemask, |
388 | GET_TCGV_I32(ret), 2, args); | |
31d66551 AJ |
389 | tcg_temp_free_ptr(fn); |
390 | } | |
391 | ||
2bece2c8 | 392 | static inline void tcg_gen_helper64(void *func, int sizemask, TCGv_i64 ret, |
a7812ae4 | 393 | TCGv_i64 a, TCGv_i64 b) |
c896fe29 | 394 | { |
a7812ae4 PB |
395 | TCGv_ptr fn; |
396 | TCGArg args[2]; | |
397 | fn = tcg_const_ptr((tcg_target_long)func); | |
398 | args[0] = GET_TCGV_I64(a); | |
399 | args[1] = GET_TCGV_I64(b); | |
2bece2c8 RH |
400 | tcg_gen_callN(&tcg_ctx, fn, TCG_CALL_CONST | TCG_CALL_PURE, sizemask, |
401 | GET_TCGV_I64(ret), 2, args); | |
a7812ae4 | 402 | tcg_temp_free_ptr(fn); |
f8422f52 BS |
403 | } |
404 | ||
c896fe29 FB |
405 | /* 32 bit ops */ |
406 | ||
a7812ae4 | 407 | static inline void tcg_gen_ld8u_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset) |
c896fe29 | 408 | { |
a7812ae4 | 409 | tcg_gen_ldst_op_i32(INDEX_op_ld8u_i32, ret, arg2, offset); |
c896fe29 FB |
410 | } |
411 | ||
a7812ae4 | 412 | static inline void tcg_gen_ld8s_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset) |
c896fe29 | 413 | { |
a7812ae4 | 414 | tcg_gen_ldst_op_i32(INDEX_op_ld8s_i32, ret, arg2, offset); |
c896fe29 FB |
415 | } |
416 | ||
a7812ae4 | 417 | static inline void tcg_gen_ld16u_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset) |
c896fe29 | 418 | { |
a7812ae4 | 419 | tcg_gen_ldst_op_i32(INDEX_op_ld16u_i32, ret, arg2, offset); |
c896fe29 FB |
420 | } |
421 | ||
a7812ae4 | 422 | static inline void tcg_gen_ld16s_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset) |
c896fe29 | 423 | { |
a7812ae4 | 424 | tcg_gen_ldst_op_i32(INDEX_op_ld16s_i32, ret, arg2, offset); |
c896fe29 FB |
425 | } |
426 | ||
a7812ae4 | 427 | static inline void tcg_gen_ld_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset) |
c896fe29 | 428 | { |
a7812ae4 | 429 | tcg_gen_ldst_op_i32(INDEX_op_ld_i32, ret, arg2, offset); |
c896fe29 FB |
430 | } |
431 | ||
a7812ae4 | 432 | static inline void tcg_gen_st8_i32(TCGv_i32 arg1, TCGv_ptr arg2, tcg_target_long offset) |
c896fe29 | 433 | { |
a7812ae4 | 434 | tcg_gen_ldst_op_i32(INDEX_op_st8_i32, arg1, arg2, offset); |
c896fe29 FB |
435 | } |
436 | ||
a7812ae4 | 437 | static inline void tcg_gen_st16_i32(TCGv_i32 arg1, TCGv_ptr arg2, tcg_target_long offset) |
c896fe29 | 438 | { |
a7812ae4 | 439 | tcg_gen_ldst_op_i32(INDEX_op_st16_i32, arg1, arg2, offset); |
c896fe29 FB |
440 | } |
441 | ||
a7812ae4 | 442 | static inline void tcg_gen_st_i32(TCGv_i32 arg1, TCGv_ptr arg2, tcg_target_long offset) |
c896fe29 | 443 | { |
a7812ae4 | 444 | tcg_gen_ldst_op_i32(INDEX_op_st_i32, arg1, arg2, offset); |
c896fe29 FB |
445 | } |
446 | ||
a7812ae4 | 447 | static inline void tcg_gen_add_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
c896fe29 | 448 | { |
a7812ae4 | 449 | tcg_gen_op3_i32(INDEX_op_add_i32, ret, arg1, arg2); |
c896fe29 FB |
450 | } |
451 | ||
a7812ae4 | 452 | static inline void tcg_gen_addi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) |
c896fe29 | 453 | { |
7089442c BS |
454 | /* some cases can be optimized here */ |
455 | if (arg2 == 0) { | |
456 | tcg_gen_mov_i32(ret, arg1); | |
457 | } else { | |
a7812ae4 | 458 | TCGv_i32 t0 = tcg_const_i32(arg2); |
e8996ee0 | 459 | tcg_gen_add_i32(ret, arg1, t0); |
a7812ae4 | 460 | tcg_temp_free_i32(t0); |
7089442c | 461 | } |
c896fe29 FB |
462 | } |
463 | ||
a7812ae4 | 464 | static inline void tcg_gen_sub_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
c896fe29 | 465 | { |
a7812ae4 | 466 | tcg_gen_op3_i32(INDEX_op_sub_i32, ret, arg1, arg2); |
c896fe29 FB |
467 | } |
468 | ||
a7812ae4 | 469 | static inline void tcg_gen_subfi_i32(TCGv_i32 ret, int32_t arg1, TCGv_i32 arg2) |
0045734a | 470 | { |
a7812ae4 | 471 | TCGv_i32 t0 = tcg_const_i32(arg1); |
0045734a | 472 | tcg_gen_sub_i32(ret, t0, arg2); |
a7812ae4 | 473 | tcg_temp_free_i32(t0); |
0045734a AJ |
474 | } |
475 | ||
a7812ae4 | 476 | static inline void tcg_gen_subi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) |
c896fe29 | 477 | { |
7089442c BS |
478 | /* some cases can be optimized here */ |
479 | if (arg2 == 0) { | |
480 | tcg_gen_mov_i32(ret, arg1); | |
481 | } else { | |
a7812ae4 | 482 | TCGv_i32 t0 = tcg_const_i32(arg2); |
e8996ee0 | 483 | tcg_gen_sub_i32(ret, arg1, t0); |
a7812ae4 | 484 | tcg_temp_free_i32(t0); |
7089442c | 485 | } |
c896fe29 FB |
486 | } |
487 | ||
a7812ae4 | 488 | static inline void tcg_gen_and_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
c896fe29 | 489 | { |
7fc81051 AJ |
490 | if (TCGV_EQUAL_I32(arg1, arg2)) { |
491 | tcg_gen_mov_i32(ret, arg1); | |
492 | } else { | |
493 | tcg_gen_op3_i32(INDEX_op_and_i32, ret, arg1, arg2); | |
494 | } | |
c896fe29 FB |
495 | } |
496 | ||
a7812ae4 | 497 | static inline void tcg_gen_andi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) |
c896fe29 FB |
498 | { |
499 | /* some cases can be optimized here */ | |
500 | if (arg2 == 0) { | |
501 | tcg_gen_movi_i32(ret, 0); | |
502 | } else if (arg2 == 0xffffffff) { | |
503 | tcg_gen_mov_i32(ret, arg1); | |
504 | } else { | |
a7812ae4 | 505 | TCGv_i32 t0 = tcg_const_i32(arg2); |
e8996ee0 | 506 | tcg_gen_and_i32(ret, arg1, t0); |
a7812ae4 | 507 | tcg_temp_free_i32(t0); |
c896fe29 FB |
508 | } |
509 | } | |
510 | ||
a7812ae4 | 511 | static inline void tcg_gen_or_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
c896fe29 | 512 | { |
7fc81051 AJ |
513 | if (TCGV_EQUAL_I32(arg1, arg2)) { |
514 | tcg_gen_mov_i32(ret, arg1); | |
515 | } else { | |
516 | tcg_gen_op3_i32(INDEX_op_or_i32, ret, arg1, arg2); | |
517 | } | |
c896fe29 FB |
518 | } |
519 | ||
a7812ae4 | 520 | static inline void tcg_gen_ori_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) |
c896fe29 FB |
521 | { |
522 | /* some cases can be optimized here */ | |
523 | if (arg2 == 0xffffffff) { | |
7089442c | 524 | tcg_gen_movi_i32(ret, 0xffffffff); |
c896fe29 FB |
525 | } else if (arg2 == 0) { |
526 | tcg_gen_mov_i32(ret, arg1); | |
527 | } else { | |
a7812ae4 | 528 | TCGv_i32 t0 = tcg_const_i32(arg2); |
e8996ee0 | 529 | tcg_gen_or_i32(ret, arg1, t0); |
a7812ae4 | 530 | tcg_temp_free_i32(t0); |
c896fe29 FB |
531 | } |
532 | } | |
533 | ||
a7812ae4 | 534 | static inline void tcg_gen_xor_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
c896fe29 | 535 | { |
7fc81051 AJ |
536 | if (TCGV_EQUAL_I32(arg1, arg2)) { |
537 | tcg_gen_movi_i32(ret, 0); | |
538 | } else { | |
539 | tcg_gen_op3_i32(INDEX_op_xor_i32, ret, arg1, arg2); | |
540 | } | |
c896fe29 FB |
541 | } |
542 | ||
a7812ae4 | 543 | static inline void tcg_gen_xori_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) |
c896fe29 FB |
544 | { |
545 | /* some cases can be optimized here */ | |
546 | if (arg2 == 0) { | |
547 | tcg_gen_mov_i32(ret, arg1); | |
548 | } else { | |
a7812ae4 | 549 | TCGv_i32 t0 = tcg_const_i32(arg2); |
e8996ee0 | 550 | tcg_gen_xor_i32(ret, arg1, t0); |
a7812ae4 | 551 | tcg_temp_free_i32(t0); |
c896fe29 FB |
552 | } |
553 | } | |
554 | ||
a7812ae4 | 555 | static inline void tcg_gen_shl_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
c896fe29 | 556 | { |
a7812ae4 | 557 | tcg_gen_op3_i32(INDEX_op_shl_i32, ret, arg1, arg2); |
c896fe29 FB |
558 | } |
559 | ||
a7812ae4 | 560 | static inline void tcg_gen_shli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) |
c896fe29 | 561 | { |
34151a20 FB |
562 | if (arg2 == 0) { |
563 | tcg_gen_mov_i32(ret, arg1); | |
564 | } else { | |
a7812ae4 | 565 | TCGv_i32 t0 = tcg_const_i32(arg2); |
e8996ee0 | 566 | tcg_gen_shl_i32(ret, arg1, t0); |
a7812ae4 | 567 | tcg_temp_free_i32(t0); |
34151a20 | 568 | } |
c896fe29 FB |
569 | } |
570 | ||
a7812ae4 | 571 | static inline void tcg_gen_shr_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
c896fe29 | 572 | { |
a7812ae4 | 573 | tcg_gen_op3_i32(INDEX_op_shr_i32, ret, arg1, arg2); |
c896fe29 FB |
574 | } |
575 | ||
a7812ae4 | 576 | static inline void tcg_gen_shri_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) |
c896fe29 | 577 | { |
34151a20 FB |
578 | if (arg2 == 0) { |
579 | tcg_gen_mov_i32(ret, arg1); | |
580 | } else { | |
a7812ae4 | 581 | TCGv_i32 t0 = tcg_const_i32(arg2); |
e8996ee0 | 582 | tcg_gen_shr_i32(ret, arg1, t0); |
a7812ae4 | 583 | tcg_temp_free_i32(t0); |
34151a20 | 584 | } |
c896fe29 FB |
585 | } |
586 | ||
a7812ae4 | 587 | static inline void tcg_gen_sar_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
c896fe29 | 588 | { |
a7812ae4 | 589 | tcg_gen_op3_i32(INDEX_op_sar_i32, ret, arg1, arg2); |
c896fe29 FB |
590 | } |
591 | ||
a7812ae4 | 592 | static inline void tcg_gen_sari_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) |
c896fe29 | 593 | { |
34151a20 FB |
594 | if (arg2 == 0) { |
595 | tcg_gen_mov_i32(ret, arg1); | |
596 | } else { | |
a7812ae4 | 597 | TCGv_i32 t0 = tcg_const_i32(arg2); |
e8996ee0 | 598 | tcg_gen_sar_i32(ret, arg1, t0); |
a7812ae4 | 599 | tcg_temp_free_i32(t0); |
34151a20 | 600 | } |
c896fe29 FB |
601 | } |
602 | ||
8a56e840 RH |
603 | static inline void tcg_gen_brcond_i32(TCGCond cond, TCGv_i32 arg1, |
604 | TCGv_i32 arg2, int label_index) | |
c896fe29 | 605 | { |
a7812ae4 | 606 | tcg_gen_op4ii_i32(INDEX_op_brcond_i32, arg1, arg2, cond, label_index); |
c896fe29 FB |
607 | } |
608 | ||
8a56e840 RH |
609 | static inline void tcg_gen_brcondi_i32(TCGCond cond, TCGv_i32 arg1, |
610 | int32_t arg2, int label_index) | |
cb63669a | 611 | { |
a7812ae4 | 612 | TCGv_i32 t0 = tcg_const_i32(arg2); |
cb63669a | 613 | tcg_gen_brcond_i32(cond, arg1, t0, label_index); |
a7812ae4 | 614 | tcg_temp_free_i32(t0); |
cb63669a PB |
615 | } |
616 | ||
8a56e840 | 617 | static inline void tcg_gen_setcond_i32(TCGCond cond, TCGv_i32 ret, |
5105c556 AJ |
618 | TCGv_i32 arg1, TCGv_i32 arg2) |
619 | { | |
620 | tcg_gen_op4i_i32(INDEX_op_setcond_i32, ret, arg1, arg2, cond); | |
621 | } | |
622 | ||
8a56e840 RH |
623 | static inline void tcg_gen_setcondi_i32(TCGCond cond, TCGv_i32 ret, |
624 | TCGv_i32 arg1, int32_t arg2) | |
5105c556 AJ |
625 | { |
626 | TCGv_i32 t0 = tcg_const_i32(arg2); | |
627 | tcg_gen_setcond_i32(cond, ret, arg1, t0); | |
628 | tcg_temp_free_i32(t0); | |
629 | } | |
630 | ||
a7812ae4 | 631 | static inline void tcg_gen_mul_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
c896fe29 | 632 | { |
a7812ae4 | 633 | tcg_gen_op3_i32(INDEX_op_mul_i32, ret, arg1, arg2); |
c896fe29 FB |
634 | } |
635 | ||
a7812ae4 | 636 | static inline void tcg_gen_muli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) |
f730fd27 | 637 | { |
a7812ae4 | 638 | TCGv_i32 t0 = tcg_const_i32(arg2); |
e8996ee0 | 639 | tcg_gen_mul_i32(ret, arg1, t0); |
a7812ae4 | 640 | tcg_temp_free_i32(t0); |
f730fd27 TS |
641 | } |
642 | ||
c896fe29 | 643 | #ifdef TCG_TARGET_HAS_div_i32 |
a7812ae4 | 644 | static inline void tcg_gen_div_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
c896fe29 | 645 | { |
a7812ae4 | 646 | tcg_gen_op3_i32(INDEX_op_div_i32, ret, arg1, arg2); |
c896fe29 FB |
647 | } |
648 | ||
a7812ae4 | 649 | static inline void tcg_gen_rem_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
c896fe29 | 650 | { |
a7812ae4 | 651 | tcg_gen_op3_i32(INDEX_op_rem_i32, ret, arg1, arg2); |
c896fe29 FB |
652 | } |
653 | ||
a7812ae4 | 654 | static inline void tcg_gen_divu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
c896fe29 | 655 | { |
a7812ae4 | 656 | tcg_gen_op3_i32(INDEX_op_divu_i32, ret, arg1, arg2); |
c896fe29 FB |
657 | } |
658 | ||
a7812ae4 | 659 | static inline void tcg_gen_remu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
c896fe29 | 660 | { |
a7812ae4 | 661 | tcg_gen_op3_i32(INDEX_op_remu_i32, ret, arg1, arg2); |
c896fe29 | 662 | } |
31d66551 | 663 | #elif defined(TCG_TARGET_HAS_div2_i32) |
a7812ae4 | 664 | static inline void tcg_gen_div_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
c896fe29 | 665 | { |
a7812ae4 PB |
666 | TCGv_i32 t0; |
667 | t0 = tcg_temp_new_i32(); | |
c896fe29 | 668 | tcg_gen_sari_i32(t0, arg1, 31); |
a7812ae4 PB |
669 | tcg_gen_op5_i32(INDEX_op_div2_i32, ret, t0, arg1, t0, arg2); |
670 | tcg_temp_free_i32(t0); | |
c896fe29 FB |
671 | } |
672 | ||
a7812ae4 | 673 | static inline void tcg_gen_rem_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
c896fe29 | 674 | { |
a7812ae4 PB |
675 | TCGv_i32 t0; |
676 | t0 = tcg_temp_new_i32(); | |
c896fe29 | 677 | tcg_gen_sari_i32(t0, arg1, 31); |
a7812ae4 PB |
678 | tcg_gen_op5_i32(INDEX_op_div2_i32, t0, ret, arg1, t0, arg2); |
679 | tcg_temp_free_i32(t0); | |
c896fe29 FB |
680 | } |
681 | ||
a7812ae4 | 682 | static inline void tcg_gen_divu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
c896fe29 | 683 | { |
a7812ae4 PB |
684 | TCGv_i32 t0; |
685 | t0 = tcg_temp_new_i32(); | |
c896fe29 | 686 | tcg_gen_movi_i32(t0, 0); |
a7812ae4 PB |
687 | tcg_gen_op5_i32(INDEX_op_divu2_i32, ret, t0, arg1, t0, arg2); |
688 | tcg_temp_free_i32(t0); | |
c896fe29 FB |
689 | } |
690 | ||
a7812ae4 | 691 | static inline void tcg_gen_remu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
c896fe29 | 692 | { |
a7812ae4 PB |
693 | TCGv_i32 t0; |
694 | t0 = tcg_temp_new_i32(); | |
c896fe29 | 695 | tcg_gen_movi_i32(t0, 0); |
a7812ae4 PB |
696 | tcg_gen_op5_i32(INDEX_op_divu2_i32, t0, ret, arg1, t0, arg2); |
697 | tcg_temp_free_i32(t0); | |
c896fe29 | 698 | } |
31d66551 AJ |
699 | #else |
700 | static inline void tcg_gen_div_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) | |
701 | { | |
2bece2c8 RH |
702 | int sizemask = 0; |
703 | /* Return value and both arguments are 32-bit and signed. */ | |
704 | sizemask |= tcg_gen_sizemask(0, 0, 1); | |
705 | sizemask |= tcg_gen_sizemask(1, 0, 1); | |
706 | sizemask |= tcg_gen_sizemask(2, 0, 1); | |
707 | ||
708 | tcg_gen_helper32(tcg_helper_div_i32, sizemask, ret, arg1, arg2); | |
31d66551 AJ |
709 | } |
710 | ||
711 | static inline void tcg_gen_rem_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) | |
712 | { | |
2bece2c8 RH |
713 | int sizemask = 0; |
714 | /* Return value and both arguments are 32-bit and signed. */ | |
715 | sizemask |= tcg_gen_sizemask(0, 0, 1); | |
716 | sizemask |= tcg_gen_sizemask(1, 0, 1); | |
717 | sizemask |= tcg_gen_sizemask(2, 0, 1); | |
718 | ||
719 | tcg_gen_helper32(tcg_helper_rem_i32, sizemask, ret, arg1, arg2); | |
31d66551 AJ |
720 | } |
721 | ||
722 | static inline void tcg_gen_divu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) | |
723 | { | |
2bece2c8 RH |
724 | int sizemask = 0; |
725 | /* Return value and both arguments are 32-bit and unsigned. */ | |
726 | sizemask |= tcg_gen_sizemask(0, 0, 0); | |
727 | sizemask |= tcg_gen_sizemask(1, 0, 0); | |
728 | sizemask |= tcg_gen_sizemask(2, 0, 0); | |
729 | ||
730 | tcg_gen_helper32(tcg_helper_divu_i32, ret, arg1, arg2, 0); | |
31d66551 AJ |
731 | } |
732 | ||
733 | static inline void tcg_gen_remu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) | |
734 | { | |
2bece2c8 RH |
735 | int sizemask = 0; |
736 | /* Return value and both arguments are 32-bit and unsigned. */ | |
737 | sizemask |= tcg_gen_sizemask(0, 0, 0); | |
738 | sizemask |= tcg_gen_sizemask(1, 0, 0); | |
739 | sizemask |= tcg_gen_sizemask(2, 0, 0); | |
740 | ||
741 | tcg_gen_helper32(tcg_helper_remu_i32, ret, arg1, arg2, 0); | |
31d66551 | 742 | } |
c896fe29 FB |
743 | #endif |
744 | ||
745 | #if TCG_TARGET_REG_BITS == 32 | |
746 | ||
a7812ae4 | 747 | static inline void tcg_gen_mov_i64(TCGv_i64 ret, TCGv_i64 arg) |
c896fe29 | 748 | { |
fe75bcf7 | 749 | if (!TCGV_EQUAL_I64(ret, arg)) { |
a7812ae4 | 750 | tcg_gen_mov_i32(TCGV_LOW(ret), TCGV_LOW(arg)); |
4d07272d BS |
751 | tcg_gen_mov_i32(TCGV_HIGH(ret), TCGV_HIGH(arg)); |
752 | } | |
c896fe29 FB |
753 | } |
754 | ||
a7812ae4 | 755 | static inline void tcg_gen_movi_i64(TCGv_i64 ret, int64_t arg) |
c896fe29 | 756 | { |
a7812ae4 | 757 | tcg_gen_movi_i32(TCGV_LOW(ret), arg); |
ac56dd48 | 758 | tcg_gen_movi_i32(TCGV_HIGH(ret), arg >> 32); |
c896fe29 FB |
759 | } |
760 | ||
a7812ae4 PB |
761 | static inline void tcg_gen_ld8u_i64(TCGv_i64 ret, TCGv_ptr arg2, |
762 | tcg_target_long offset) | |
c896fe29 | 763 | { |
a7812ae4 | 764 | tcg_gen_ld8u_i32(TCGV_LOW(ret), arg2, offset); |
ac56dd48 | 765 | tcg_gen_movi_i32(TCGV_HIGH(ret), 0); |
c896fe29 FB |
766 | } |
767 | ||
a7812ae4 PB |
768 | static inline void tcg_gen_ld8s_i64(TCGv_i64 ret, TCGv_ptr arg2, |
769 | tcg_target_long offset) | |
c896fe29 | 770 | { |
a7812ae4 PB |
771 | tcg_gen_ld8s_i32(TCGV_LOW(ret), arg2, offset); |
772 | tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_HIGH(ret), 31); | |
c896fe29 FB |
773 | } |
774 | ||
a7812ae4 PB |
775 | static inline void tcg_gen_ld16u_i64(TCGv_i64 ret, TCGv_ptr arg2, |
776 | tcg_target_long offset) | |
c896fe29 | 777 | { |
a747723b | 778 | tcg_gen_ld16u_i32(TCGV_LOW(ret), arg2, offset); |
ac56dd48 | 779 | tcg_gen_movi_i32(TCGV_HIGH(ret), 0); |
c896fe29 FB |
780 | } |
781 | ||
a7812ae4 PB |
782 | static inline void tcg_gen_ld16s_i64(TCGv_i64 ret, TCGv_ptr arg2, |
783 | tcg_target_long offset) | |
c896fe29 | 784 | { |
a7812ae4 PB |
785 | tcg_gen_ld16s_i32(TCGV_LOW(ret), arg2, offset); |
786 | tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31); | |
c896fe29 FB |
787 | } |
788 | ||
a7812ae4 PB |
789 | static inline void tcg_gen_ld32u_i64(TCGv_i64 ret, TCGv_ptr arg2, |
790 | tcg_target_long offset) | |
c896fe29 | 791 | { |
a7812ae4 | 792 | tcg_gen_ld_i32(TCGV_LOW(ret), arg2, offset); |
ac56dd48 | 793 | tcg_gen_movi_i32(TCGV_HIGH(ret), 0); |
c896fe29 FB |
794 | } |
795 | ||
a7812ae4 PB |
796 | static inline void tcg_gen_ld32s_i64(TCGv_i64 ret, TCGv_ptr arg2, |
797 | tcg_target_long offset) | |
c896fe29 | 798 | { |
a7812ae4 PB |
799 | tcg_gen_ld_i32(TCGV_LOW(ret), arg2, offset); |
800 | tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31); | |
c896fe29 FB |
801 | } |
802 | ||
a7812ae4 PB |
803 | static inline void tcg_gen_ld_i64(TCGv_i64 ret, TCGv_ptr arg2, |
804 | tcg_target_long offset) | |
c896fe29 FB |
805 | { |
806 | /* since arg2 and ret have different types, they cannot be the | |
807 | same temporary */ | |
808 | #ifdef TCG_TARGET_WORDS_BIGENDIAN | |
ac56dd48 | 809 | tcg_gen_ld_i32(TCGV_HIGH(ret), arg2, offset); |
a7812ae4 | 810 | tcg_gen_ld_i32(TCGV_LOW(ret), arg2, offset + 4); |
c896fe29 | 811 | #else |
a7812ae4 | 812 | tcg_gen_ld_i32(TCGV_LOW(ret), arg2, offset); |
ac56dd48 | 813 | tcg_gen_ld_i32(TCGV_HIGH(ret), arg2, offset + 4); |
c896fe29 FB |
814 | #endif |
815 | } | |
816 | ||
a7812ae4 PB |
817 | static inline void tcg_gen_st8_i64(TCGv_i64 arg1, TCGv_ptr arg2, |
818 | tcg_target_long offset) | |
c896fe29 | 819 | { |
a7812ae4 | 820 | tcg_gen_st8_i32(TCGV_LOW(arg1), arg2, offset); |
c896fe29 FB |
821 | } |
822 | ||
a7812ae4 PB |
823 | static inline void tcg_gen_st16_i64(TCGv_i64 arg1, TCGv_ptr arg2, |
824 | tcg_target_long offset) | |
c896fe29 | 825 | { |
a7812ae4 | 826 | tcg_gen_st16_i32(TCGV_LOW(arg1), arg2, offset); |
c896fe29 FB |
827 | } |
828 | ||
a7812ae4 PB |
829 | static inline void tcg_gen_st32_i64(TCGv_i64 arg1, TCGv_ptr arg2, |
830 | tcg_target_long offset) | |
c896fe29 | 831 | { |
a7812ae4 | 832 | tcg_gen_st_i32(TCGV_LOW(arg1), arg2, offset); |
c896fe29 FB |
833 | } |
834 | ||
a7812ae4 PB |
835 | static inline void tcg_gen_st_i64(TCGv_i64 arg1, TCGv_ptr arg2, |
836 | tcg_target_long offset) | |
c896fe29 FB |
837 | { |
838 | #ifdef TCG_TARGET_WORDS_BIGENDIAN | |
ac56dd48 | 839 | tcg_gen_st_i32(TCGV_HIGH(arg1), arg2, offset); |
a7812ae4 | 840 | tcg_gen_st_i32(TCGV_LOW(arg1), arg2, offset + 4); |
c896fe29 | 841 | #else |
a7812ae4 | 842 | tcg_gen_st_i32(TCGV_LOW(arg1), arg2, offset); |
ac56dd48 | 843 | tcg_gen_st_i32(TCGV_HIGH(arg1), arg2, offset + 4); |
c896fe29 FB |
844 | #endif |
845 | } | |
846 | ||
a7812ae4 | 847 | static inline void tcg_gen_add_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
c896fe29 | 848 | { |
a7812ae4 PB |
849 | tcg_gen_op6_i32(INDEX_op_add2_i32, TCGV_LOW(ret), TCGV_HIGH(ret), |
850 | TCGV_LOW(arg1), TCGV_HIGH(arg1), TCGV_LOW(arg2), | |
851 | TCGV_HIGH(arg2)); | |
c896fe29 FB |
852 | } |
853 | ||
a7812ae4 | 854 | static inline void tcg_gen_sub_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
c896fe29 | 855 | { |
a7812ae4 PB |
856 | tcg_gen_op6_i32(INDEX_op_sub2_i32, TCGV_LOW(ret), TCGV_HIGH(ret), |
857 | TCGV_LOW(arg1), TCGV_HIGH(arg1), TCGV_LOW(arg2), | |
858 | TCGV_HIGH(arg2)); | |
c896fe29 FB |
859 | } |
860 | ||
a7812ae4 | 861 | static inline void tcg_gen_and_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
c896fe29 | 862 | { |
a7812ae4 | 863 | tcg_gen_and_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2)); |
ac56dd48 | 864 | tcg_gen_and_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2)); |
c896fe29 FB |
865 | } |
866 | ||
a7812ae4 | 867 | static inline void tcg_gen_andi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
c896fe29 | 868 | { |
e5105083 AJ |
869 | tcg_gen_andi_i32(TCGV_LOW(ret), TCGV_LOW(arg1), arg2); |
870 | tcg_gen_andi_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), arg2 >> 32); | |
c896fe29 FB |
871 | } |
872 | ||
a7812ae4 | 873 | static inline void tcg_gen_or_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
c896fe29 | 874 | { |
e5105083 AJ |
875 | tcg_gen_or_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2)); |
876 | tcg_gen_or_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2)); | |
c896fe29 FB |
877 | } |
878 | ||
a7812ae4 | 879 | static inline void tcg_gen_ori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
c896fe29 | 880 | { |
a7812ae4 | 881 | tcg_gen_ori_i32(TCGV_LOW(ret), TCGV_LOW(arg1), arg2); |
ac56dd48 | 882 | tcg_gen_ori_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), arg2 >> 32); |
c896fe29 FB |
883 | } |
884 | ||
a7812ae4 | 885 | static inline void tcg_gen_xor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
c896fe29 | 886 | { |
e5105083 AJ |
887 | tcg_gen_xor_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2)); |
888 | tcg_gen_xor_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2)); | |
c896fe29 FB |
889 | } |
890 | ||
a7812ae4 | 891 | static inline void tcg_gen_xori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
c896fe29 | 892 | { |
a7812ae4 | 893 | tcg_gen_xori_i32(TCGV_LOW(ret), TCGV_LOW(arg1), arg2); |
ac56dd48 | 894 | tcg_gen_xori_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), arg2 >> 32); |
c896fe29 FB |
895 | } |
896 | ||
897 | /* XXX: use generic code when basic block handling is OK or CPU | |
898 | specific code (x86) */ | |
a7812ae4 | 899 | static inline void tcg_gen_shl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
c896fe29 | 900 | { |
2bece2c8 RH |
901 | int sizemask = 0; |
902 | /* Return value and both arguments are 64-bit and signed. */ | |
903 | sizemask |= tcg_gen_sizemask(0, 1, 1); | |
904 | sizemask |= tcg_gen_sizemask(1, 1, 1); | |
905 | sizemask |= tcg_gen_sizemask(2, 1, 1); | |
906 | ||
907 | tcg_gen_helper64(tcg_helper_shl_i64, sizemask, ret, arg1, arg2); | |
c896fe29 FB |
908 | } |
909 | ||
a7812ae4 | 910 | static inline void tcg_gen_shli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
c896fe29 FB |
911 | { |
912 | tcg_gen_shifti_i64(ret, arg1, arg2, 0, 0); | |
913 | } | |
914 | ||
a7812ae4 | 915 | static inline void tcg_gen_shr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
c896fe29 | 916 | { |
2bece2c8 RH |
917 | int sizemask = 0; |
918 | /* Return value and both arguments are 64-bit and signed. */ | |
919 | sizemask |= tcg_gen_sizemask(0, 1, 1); | |
920 | sizemask |= tcg_gen_sizemask(1, 1, 1); | |
921 | sizemask |= tcg_gen_sizemask(2, 1, 1); | |
922 | ||
923 | tcg_gen_helper64(tcg_helper_shr_i64, sizemask, ret, arg1, arg2); | |
c896fe29 FB |
924 | } |
925 | ||
a7812ae4 | 926 | static inline void tcg_gen_shri_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
c896fe29 FB |
927 | { |
928 | tcg_gen_shifti_i64(ret, arg1, arg2, 1, 0); | |
929 | } | |
930 | ||
a7812ae4 | 931 | static inline void tcg_gen_sar_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
c896fe29 | 932 | { |
2bece2c8 RH |
933 | int sizemask = 0; |
934 | /* Return value and both arguments are 64-bit and signed. */ | |
935 | sizemask |= tcg_gen_sizemask(0, 1, 1); | |
936 | sizemask |= tcg_gen_sizemask(1, 1, 1); | |
937 | sizemask |= tcg_gen_sizemask(2, 1, 1); | |
938 | ||
939 | tcg_gen_helper64(tcg_helper_sar_i64, sizemask, ret, arg1, arg2); | |
c896fe29 FB |
940 | } |
941 | ||
a7812ae4 | 942 | static inline void tcg_gen_sari_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
c896fe29 FB |
943 | { |
944 | tcg_gen_shifti_i64(ret, arg1, arg2, 1, 1); | |
945 | } | |
946 | ||
8a56e840 RH |
947 | static inline void tcg_gen_brcond_i64(TCGCond cond, TCGv_i64 arg1, |
948 | TCGv_i64 arg2, int label_index) | |
c896fe29 | 949 | { |
a7812ae4 PB |
950 | tcg_gen_op6ii_i32(INDEX_op_brcond2_i32, |
951 | TCGV_LOW(arg1), TCGV_HIGH(arg1), TCGV_LOW(arg2), | |
952 | TCGV_HIGH(arg2), cond, label_index); | |
c896fe29 FB |
953 | } |
954 | ||
8a56e840 | 955 | static inline void tcg_gen_setcond_i64(TCGCond cond, TCGv_i64 ret, |
5105c556 AJ |
956 | TCGv_i64 arg1, TCGv_i64 arg2) |
957 | { | |
958 | tcg_gen_op6i_i32(INDEX_op_setcond2_i32, TCGV_LOW(ret), | |
959 | TCGV_LOW(arg1), TCGV_HIGH(arg1), | |
960 | TCGV_LOW(arg2), TCGV_HIGH(arg2), cond); | |
961 | tcg_gen_movi_i32(TCGV_HIGH(ret), 0); | |
962 | } | |
963 | ||
a7812ae4 | 964 | static inline void tcg_gen_mul_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
c896fe29 | 965 | { |
a7812ae4 PB |
966 | TCGv_i64 t0; |
967 | TCGv_i32 t1; | |
c896fe29 | 968 | |
a7812ae4 PB |
969 | t0 = tcg_temp_new_i64(); |
970 | t1 = tcg_temp_new_i32(); | |
971 | ||
972 | tcg_gen_op4_i32(INDEX_op_mulu2_i32, TCGV_LOW(t0), TCGV_HIGH(t0), | |
973 | TCGV_LOW(arg1), TCGV_LOW(arg2)); | |
974 | ||
975 | tcg_gen_mul_i32(t1, TCGV_LOW(arg1), TCGV_HIGH(arg2)); | |
ac56dd48 | 976 | tcg_gen_add_i32(TCGV_HIGH(t0), TCGV_HIGH(t0), t1); |
a7812ae4 | 977 | tcg_gen_mul_i32(t1, TCGV_HIGH(arg1), TCGV_LOW(arg2)); |
ac56dd48 | 978 | tcg_gen_add_i32(TCGV_HIGH(t0), TCGV_HIGH(t0), t1); |
a7812ae4 | 979 | |
c896fe29 | 980 | tcg_gen_mov_i64(ret, t0); |
a7812ae4 PB |
981 | tcg_temp_free_i64(t0); |
982 | tcg_temp_free_i32(t1); | |
c896fe29 FB |
983 | } |
984 | ||
a7812ae4 | 985 | static inline void tcg_gen_div_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
c896fe29 | 986 | { |
2bece2c8 RH |
987 | int sizemask = 0; |
988 | /* Return value and both arguments are 64-bit and signed. */ | |
989 | sizemask |= tcg_gen_sizemask(0, 1, 1); | |
990 | sizemask |= tcg_gen_sizemask(1, 1, 1); | |
991 | sizemask |= tcg_gen_sizemask(2, 1, 1); | |
992 | ||
993 | tcg_gen_helper64(tcg_helper_div_i64, sizemask, ret, arg1, arg2); | |
c896fe29 FB |
994 | } |
995 | ||
a7812ae4 | 996 | static inline void tcg_gen_rem_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
c896fe29 | 997 | { |
2bece2c8 RH |
998 | int sizemask = 0; |
999 | /* Return value and both arguments are 64-bit and signed. */ | |
1000 | sizemask |= tcg_gen_sizemask(0, 1, 1); | |
1001 | sizemask |= tcg_gen_sizemask(1, 1, 1); | |
1002 | sizemask |= tcg_gen_sizemask(2, 1, 1); | |
1003 | ||
1004 | tcg_gen_helper64(tcg_helper_rem_i64, sizemask, ret, arg1, arg2); | |
c896fe29 FB |
1005 | } |
1006 | ||
a7812ae4 | 1007 | static inline void tcg_gen_divu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
c896fe29 | 1008 | { |
2bece2c8 RH |
1009 | int sizemask = 0; |
1010 | /* Return value and both arguments are 64-bit and unsigned. */ | |
1011 | sizemask |= tcg_gen_sizemask(0, 1, 0); | |
1012 | sizemask |= tcg_gen_sizemask(1, 1, 0); | |
1013 | sizemask |= tcg_gen_sizemask(2, 1, 0); | |
1014 | ||
1015 | tcg_gen_helper64(tcg_helper_divu_i64, sizemask, ret, arg1, arg2); | |
c896fe29 FB |
1016 | } |
1017 | ||
a7812ae4 | 1018 | static inline void tcg_gen_remu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
c896fe29 | 1019 | { |
2bece2c8 RH |
1020 | int sizemask = 0; |
1021 | /* Return value and both arguments are 64-bit and unsigned. */ | |
1022 | sizemask |= tcg_gen_sizemask(0, 1, 0); | |
1023 | sizemask |= tcg_gen_sizemask(1, 1, 0); | |
1024 | sizemask |= tcg_gen_sizemask(2, 1, 0); | |
1025 | ||
1026 | tcg_gen_helper64(tcg_helper_remu_i64, sizemask, ret, arg1, arg2); | |
c896fe29 FB |
1027 | } |
1028 | ||
1029 | #else | |
1030 | ||
a7812ae4 | 1031 | static inline void tcg_gen_mov_i64(TCGv_i64 ret, TCGv_i64 arg) |
c896fe29 | 1032 | { |
fe75bcf7 | 1033 | if (!TCGV_EQUAL_I64(ret, arg)) |
a7812ae4 | 1034 | tcg_gen_op2_i64(INDEX_op_mov_i64, ret, arg); |
c896fe29 FB |
1035 | } |
1036 | ||
a7812ae4 | 1037 | static inline void tcg_gen_movi_i64(TCGv_i64 ret, int64_t arg) |
c896fe29 | 1038 | { |
a7812ae4 | 1039 | tcg_gen_op2i_i64(INDEX_op_movi_i64, ret, arg); |
c896fe29 FB |
1040 | } |
1041 | ||
a7812ae4 | 1042 | static inline void tcg_gen_ld8u_i64(TCGv_i64 ret, TCGv_i64 arg2, |
ac56dd48 | 1043 | tcg_target_long offset) |
c896fe29 | 1044 | { |
a7812ae4 | 1045 | tcg_gen_ldst_op_i64(INDEX_op_ld8u_i64, ret, arg2, offset); |
c896fe29 FB |
1046 | } |
1047 | ||
a7812ae4 | 1048 | static inline void tcg_gen_ld8s_i64(TCGv_i64 ret, TCGv_i64 arg2, |
ac56dd48 | 1049 | tcg_target_long offset) |
c896fe29 | 1050 | { |
a7812ae4 | 1051 | tcg_gen_ldst_op_i64(INDEX_op_ld8s_i64, ret, arg2, offset); |
c896fe29 FB |
1052 | } |
1053 | ||
a7812ae4 | 1054 | static inline void tcg_gen_ld16u_i64(TCGv_i64 ret, TCGv_i64 arg2, |
ac56dd48 | 1055 | tcg_target_long offset) |
c896fe29 | 1056 | { |
a7812ae4 | 1057 | tcg_gen_ldst_op_i64(INDEX_op_ld16u_i64, ret, arg2, offset); |
c896fe29 FB |
1058 | } |
1059 | ||
a7812ae4 | 1060 | static inline void tcg_gen_ld16s_i64(TCGv_i64 ret, TCGv_i64 arg2, |
ac56dd48 | 1061 | tcg_target_long offset) |
c896fe29 | 1062 | { |
a7812ae4 | 1063 | tcg_gen_ldst_op_i64(INDEX_op_ld16s_i64, ret, arg2, offset); |
c896fe29 FB |
1064 | } |
1065 | ||
a7812ae4 | 1066 | static inline void tcg_gen_ld32u_i64(TCGv_i64 ret, TCGv_i64 arg2, |
ac56dd48 | 1067 | tcg_target_long offset) |
c896fe29 | 1068 | { |
a7812ae4 | 1069 | tcg_gen_ldst_op_i64(INDEX_op_ld32u_i64, ret, arg2, offset); |
c896fe29 FB |
1070 | } |
1071 | ||
a7812ae4 | 1072 | static inline void tcg_gen_ld32s_i64(TCGv_i64 ret, TCGv_i64 arg2, |
ac56dd48 | 1073 | tcg_target_long offset) |
c896fe29 | 1074 | { |
a7812ae4 | 1075 | tcg_gen_ldst_op_i64(INDEX_op_ld32s_i64, ret, arg2, offset); |
c896fe29 FB |
1076 | } |
1077 | ||
a7812ae4 | 1078 | static inline void tcg_gen_ld_i64(TCGv_i64 ret, TCGv_i64 arg2, tcg_target_long offset) |
c896fe29 | 1079 | { |
a7812ae4 | 1080 | tcg_gen_ldst_op_i64(INDEX_op_ld_i64, ret, arg2, offset); |
c896fe29 FB |
1081 | } |
1082 | ||
a7812ae4 | 1083 | static inline void tcg_gen_st8_i64(TCGv_i64 arg1, TCGv_i64 arg2, |
ac56dd48 | 1084 | tcg_target_long offset) |
c896fe29 | 1085 | { |
a7812ae4 | 1086 | tcg_gen_ldst_op_i64(INDEX_op_st8_i64, arg1, arg2, offset); |
c896fe29 FB |
1087 | } |
1088 | ||
a7812ae4 | 1089 | static inline void tcg_gen_st16_i64(TCGv_i64 arg1, TCGv_i64 arg2, |
ac56dd48 | 1090 | tcg_target_long offset) |
c896fe29 | 1091 | { |
a7812ae4 | 1092 | tcg_gen_ldst_op_i64(INDEX_op_st16_i64, arg1, arg2, offset); |
c896fe29 FB |
1093 | } |
1094 | ||
a7812ae4 | 1095 | static inline void tcg_gen_st32_i64(TCGv_i64 arg1, TCGv_i64 arg2, |
ac56dd48 | 1096 | tcg_target_long offset) |
c896fe29 | 1097 | { |
a7812ae4 | 1098 | tcg_gen_ldst_op_i64(INDEX_op_st32_i64, arg1, arg2, offset); |
c896fe29 FB |
1099 | } |
1100 | ||
a7812ae4 | 1101 | static inline void tcg_gen_st_i64(TCGv_i64 arg1, TCGv_i64 arg2, tcg_target_long offset) |
c896fe29 | 1102 | { |
a7812ae4 | 1103 | tcg_gen_ldst_op_i64(INDEX_op_st_i64, arg1, arg2, offset); |
c896fe29 FB |
1104 | } |
1105 | ||
a7812ae4 | 1106 | static inline void tcg_gen_add_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
c896fe29 | 1107 | { |
a7812ae4 | 1108 | tcg_gen_op3_i64(INDEX_op_add_i64, ret, arg1, arg2); |
c896fe29 FB |
1109 | } |
1110 | ||
a7812ae4 | 1111 | static inline void tcg_gen_sub_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
c896fe29 | 1112 | { |
a7812ae4 | 1113 | tcg_gen_op3_i64(INDEX_op_sub_i64, ret, arg1, arg2); |
c896fe29 FB |
1114 | } |
1115 | ||
a7812ae4 | 1116 | static inline void tcg_gen_and_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
c896fe29 | 1117 | { |
7fc81051 AJ |
1118 | if (TCGV_EQUAL_I64(arg1, arg2)) { |
1119 | tcg_gen_mov_i64(ret, arg1); | |
1120 | } else { | |
1121 | tcg_gen_op3_i64(INDEX_op_and_i64, ret, arg1, arg2); | |
1122 | } | |
c896fe29 FB |
1123 | } |
1124 | ||
a7812ae4 | 1125 | static inline void tcg_gen_andi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
c896fe29 | 1126 | { |
a7812ae4 | 1127 | TCGv_i64 t0 = tcg_const_i64(arg2); |
e8996ee0 | 1128 | tcg_gen_and_i64(ret, arg1, t0); |
a7812ae4 | 1129 | tcg_temp_free_i64(t0); |
c896fe29 FB |
1130 | } |
1131 | ||
a7812ae4 | 1132 | static inline void tcg_gen_or_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
c896fe29 | 1133 | { |
7fc81051 AJ |
1134 | if (TCGV_EQUAL_I64(arg1, arg2)) { |
1135 | tcg_gen_mov_i64(ret, arg1); | |
1136 | } else { | |
1137 | tcg_gen_op3_i64(INDEX_op_or_i64, ret, arg1, arg2); | |
1138 | } | |
c896fe29 FB |
1139 | } |
1140 | ||
a7812ae4 | 1141 | static inline void tcg_gen_ori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
c896fe29 | 1142 | { |
a7812ae4 | 1143 | TCGv_i64 t0 = tcg_const_i64(arg2); |
e8996ee0 | 1144 | tcg_gen_or_i64(ret, arg1, t0); |
a7812ae4 | 1145 | tcg_temp_free_i64(t0); |
c896fe29 FB |
1146 | } |
1147 | ||
a7812ae4 | 1148 | static inline void tcg_gen_xor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
c896fe29 | 1149 | { |
7fc81051 AJ |
1150 | if (TCGV_EQUAL_I64(arg1, arg2)) { |
1151 | tcg_gen_movi_i64(ret, 0); | |
1152 | } else { | |
1153 | tcg_gen_op3_i64(INDEX_op_xor_i64, ret, arg1, arg2); | |
1154 | } | |
c896fe29 FB |
1155 | } |
1156 | ||
a7812ae4 | 1157 | static inline void tcg_gen_xori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
c896fe29 | 1158 | { |
a7812ae4 | 1159 | TCGv_i64 t0 = tcg_const_i64(arg2); |
e8996ee0 | 1160 | tcg_gen_xor_i64(ret, arg1, t0); |
a7812ae4 | 1161 | tcg_temp_free_i64(t0); |
c896fe29 FB |
1162 | } |
1163 | ||
a7812ae4 | 1164 | static inline void tcg_gen_shl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
c896fe29 | 1165 | { |
a7812ae4 | 1166 | tcg_gen_op3_i64(INDEX_op_shl_i64, ret, arg1, arg2); |
c896fe29 FB |
1167 | } |
1168 | ||
a7812ae4 | 1169 | static inline void tcg_gen_shli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
c896fe29 | 1170 | { |
34151a20 FB |
1171 | if (arg2 == 0) { |
1172 | tcg_gen_mov_i64(ret, arg1); | |
1173 | } else { | |
a7812ae4 | 1174 | TCGv_i64 t0 = tcg_const_i64(arg2); |
e8996ee0 | 1175 | tcg_gen_shl_i64(ret, arg1, t0); |
a7812ae4 | 1176 | tcg_temp_free_i64(t0); |
34151a20 | 1177 | } |
c896fe29 FB |
1178 | } |
1179 | ||
a7812ae4 | 1180 | static inline void tcg_gen_shr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
c896fe29 | 1181 | { |
a7812ae4 | 1182 | tcg_gen_op3_i64(INDEX_op_shr_i64, ret, arg1, arg2); |
c896fe29 FB |
1183 | } |
1184 | ||
a7812ae4 | 1185 | static inline void tcg_gen_shri_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
c896fe29 | 1186 | { |
34151a20 FB |
1187 | if (arg2 == 0) { |
1188 | tcg_gen_mov_i64(ret, arg1); | |
1189 | } else { | |
a7812ae4 | 1190 | TCGv_i64 t0 = tcg_const_i64(arg2); |
e8996ee0 | 1191 | tcg_gen_shr_i64(ret, arg1, t0); |
a7812ae4 | 1192 | tcg_temp_free_i64(t0); |
34151a20 | 1193 | } |
c896fe29 FB |
1194 | } |
1195 | ||
a7812ae4 | 1196 | static inline void tcg_gen_sar_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
c896fe29 | 1197 | { |
a7812ae4 | 1198 | tcg_gen_op3_i64(INDEX_op_sar_i64, ret, arg1, arg2); |
c896fe29 FB |
1199 | } |
1200 | ||
a7812ae4 | 1201 | static inline void tcg_gen_sari_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
c896fe29 | 1202 | { |
34151a20 FB |
1203 | if (arg2 == 0) { |
1204 | tcg_gen_mov_i64(ret, arg1); | |
1205 | } else { | |
a7812ae4 | 1206 | TCGv_i64 t0 = tcg_const_i64(arg2); |
e8996ee0 | 1207 | tcg_gen_sar_i64(ret, arg1, t0); |
a7812ae4 | 1208 | tcg_temp_free_i64(t0); |
34151a20 | 1209 | } |
c896fe29 FB |
1210 | } |
1211 | ||
8a56e840 RH |
1212 | static inline void tcg_gen_brcond_i64(TCGCond cond, TCGv_i64 arg1, |
1213 | TCGv_i64 arg2, int label_index) | |
c896fe29 | 1214 | { |
a7812ae4 | 1215 | tcg_gen_op4ii_i64(INDEX_op_brcond_i64, arg1, arg2, cond, label_index); |
c896fe29 FB |
1216 | } |
1217 | ||
8a56e840 | 1218 | static inline void tcg_gen_setcond_i64(TCGCond cond, TCGv_i64 ret, |
5105c556 AJ |
1219 | TCGv_i64 arg1, TCGv_i64 arg2) |
1220 | { | |
1221 | tcg_gen_op4i_i64(INDEX_op_setcond_i64, ret, arg1, arg2, cond); | |
1222 | } | |
1223 | ||
a7812ae4 | 1224 | static inline void tcg_gen_mul_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
c896fe29 | 1225 | { |
a7812ae4 | 1226 | tcg_gen_op3_i64(INDEX_op_mul_i64, ret, arg1, arg2); |
c896fe29 FB |
1227 | } |
1228 | ||
1229 | #ifdef TCG_TARGET_HAS_div_i64 | |
a7812ae4 | 1230 | static inline void tcg_gen_div_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
c896fe29 | 1231 | { |
a7812ae4 | 1232 | tcg_gen_op3_i64(INDEX_op_div_i64, ret, arg1, arg2); |
c896fe29 FB |
1233 | } |
1234 | ||
a7812ae4 | 1235 | static inline void tcg_gen_rem_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
c896fe29 | 1236 | { |
a7812ae4 | 1237 | tcg_gen_op3_i64(INDEX_op_rem_i64, ret, arg1, arg2); |
c896fe29 FB |
1238 | } |
1239 | ||
a7812ae4 | 1240 | static inline void tcg_gen_divu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
c896fe29 | 1241 | { |
a7812ae4 | 1242 | tcg_gen_op3_i64(INDEX_op_divu_i64, ret, arg1, arg2); |
c896fe29 FB |
1243 | } |
1244 | ||
a7812ae4 | 1245 | static inline void tcg_gen_remu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
c896fe29 | 1246 | { |
a7812ae4 | 1247 | tcg_gen_op3_i64(INDEX_op_remu_i64, ret, arg1, arg2); |
c896fe29 | 1248 | } |
31d66551 | 1249 | #elif defined(TCG_TARGET_HAS_div2_i64) |
a7812ae4 | 1250 | static inline void tcg_gen_div_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
c896fe29 | 1251 | { |
a7812ae4 PB |
1252 | TCGv_i64 t0; |
1253 | t0 = tcg_temp_new_i64(); | |
c896fe29 | 1254 | tcg_gen_sari_i64(t0, arg1, 63); |
a7812ae4 PB |
1255 | tcg_gen_op5_i64(INDEX_op_div2_i64, ret, t0, arg1, t0, arg2); |
1256 | tcg_temp_free_i64(t0); | |
c896fe29 FB |
1257 | } |
1258 | ||
a7812ae4 | 1259 | static inline void tcg_gen_rem_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
c896fe29 | 1260 | { |
a7812ae4 PB |
1261 | TCGv_i64 t0; |
1262 | t0 = tcg_temp_new_i64(); | |
c896fe29 | 1263 | tcg_gen_sari_i64(t0, arg1, 63); |
a7812ae4 PB |
1264 | tcg_gen_op5_i64(INDEX_op_div2_i64, t0, ret, arg1, t0, arg2); |
1265 | tcg_temp_free_i64(t0); | |
c896fe29 FB |
1266 | } |
1267 | ||
a7812ae4 | 1268 | static inline void tcg_gen_divu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
c896fe29 | 1269 | { |
a7812ae4 PB |
1270 | TCGv_i64 t0; |
1271 | t0 = tcg_temp_new_i64(); | |
c896fe29 | 1272 | tcg_gen_movi_i64(t0, 0); |
a7812ae4 PB |
1273 | tcg_gen_op5_i64(INDEX_op_divu2_i64, ret, t0, arg1, t0, arg2); |
1274 | tcg_temp_free_i64(t0); | |
c896fe29 FB |
1275 | } |
1276 | ||
a7812ae4 | 1277 | static inline void tcg_gen_remu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
c896fe29 | 1278 | { |
a7812ae4 PB |
1279 | TCGv_i64 t0; |
1280 | t0 = tcg_temp_new_i64(); | |
c896fe29 | 1281 | tcg_gen_movi_i64(t0, 0); |
a7812ae4 PB |
1282 | tcg_gen_op5_i64(INDEX_op_divu2_i64, t0, ret, arg1, t0, arg2); |
1283 | tcg_temp_free_i64(t0); | |
c896fe29 | 1284 | } |
31d66551 AJ |
1285 | #else |
1286 | static inline void tcg_gen_div_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) | |
1287 | { | |
2bece2c8 RH |
1288 | int sizemask = 0; |
1289 | /* Return value and both arguments are 64-bit and signed. */ | |
1290 | sizemask |= tcg_gen_sizemask(0, 1, 1); | |
1291 | sizemask |= tcg_gen_sizemask(1, 1, 1); | |
1292 | sizemask |= tcg_gen_sizemask(2, 1, 1); | |
1293 | ||
1294 | tcg_gen_helper64(tcg_helper_div_i64, sizemask, ret, arg1, arg2); | |
31d66551 AJ |
1295 | } |
1296 | ||
1297 | static inline void tcg_gen_rem_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) | |
1298 | { | |
2bece2c8 RH |
1299 | int sizemask = 0; |
1300 | /* Return value and both arguments are 64-bit and signed. */ | |
1301 | sizemask |= tcg_gen_sizemask(0, 1, 1); | |
1302 | sizemask |= tcg_gen_sizemask(1, 1, 1); | |
1303 | sizemask |= tcg_gen_sizemask(2, 1, 1); | |
1304 | ||
1305 | tcg_gen_helper64(tcg_helper_rem_i64, sizemask, ret, arg1, arg2); | |
31d66551 AJ |
1306 | } |
1307 | ||
1308 | static inline void tcg_gen_divu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) | |
1309 | { | |
2bece2c8 RH |
1310 | int sizemask = 0; |
1311 | /* Return value and both arguments are 64-bit and unsigned. */ | |
1312 | sizemask |= tcg_gen_sizemask(0, 1, 0); | |
1313 | sizemask |= tcg_gen_sizemask(1, 1, 0); | |
1314 | sizemask |= tcg_gen_sizemask(2, 1, 0); | |
1315 | ||
1316 | tcg_gen_helper64(tcg_helper_divu_i64, sizemask, ret, arg1, arg2); | |
31d66551 AJ |
1317 | } |
1318 | ||
1319 | static inline void tcg_gen_remu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) | |
1320 | { | |
2bece2c8 RH |
1321 | int sizemask = 0; |
1322 | /* Return value and both arguments are 64-bit and unsigned. */ | |
1323 | sizemask |= tcg_gen_sizemask(0, 1, 0); | |
1324 | sizemask |= tcg_gen_sizemask(1, 1, 0); | |
1325 | sizemask |= tcg_gen_sizemask(2, 1, 0); | |
1326 | ||
1327 | tcg_gen_helper64(tcg_helper_remu_i64, sizemask, ret, arg1, arg2); | |
31d66551 | 1328 | } |
c896fe29 FB |
1329 | #endif |
1330 | ||
1331 | #endif | |
1332 | ||
a7812ae4 | 1333 | static inline void tcg_gen_addi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
6359706f AJ |
1334 | { |
1335 | /* some cases can be optimized here */ | |
1336 | if (arg2 == 0) { | |
1337 | tcg_gen_mov_i64(ret, arg1); | |
1338 | } else { | |
a7812ae4 | 1339 | TCGv_i64 t0 = tcg_const_i64(arg2); |
6359706f | 1340 | tcg_gen_add_i64(ret, arg1, t0); |
a7812ae4 | 1341 | tcg_temp_free_i64(t0); |
6359706f AJ |
1342 | } |
1343 | } | |
1344 | ||
a7812ae4 | 1345 | static inline void tcg_gen_subfi_i64(TCGv_i64 ret, int64_t arg1, TCGv_i64 arg2) |
0045734a | 1346 | { |
a7812ae4 | 1347 | TCGv_i64 t0 = tcg_const_i64(arg1); |
0045734a | 1348 | tcg_gen_sub_i64(ret, t0, arg2); |
a7812ae4 | 1349 | tcg_temp_free_i64(t0); |
0045734a AJ |
1350 | } |
1351 | ||
a7812ae4 | 1352 | static inline void tcg_gen_subi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
6359706f AJ |
1353 | { |
1354 | /* some cases can be optimized here */ | |
1355 | if (arg2 == 0) { | |
1356 | tcg_gen_mov_i64(ret, arg1); | |
1357 | } else { | |
a7812ae4 | 1358 | TCGv_i64 t0 = tcg_const_i64(arg2); |
6359706f | 1359 | tcg_gen_sub_i64(ret, arg1, t0); |
a7812ae4 | 1360 | tcg_temp_free_i64(t0); |
6359706f AJ |
1361 | } |
1362 | } | |
8a56e840 RH |
1363 | static inline void tcg_gen_brcondi_i64(TCGCond cond, TCGv_i64 arg1, |
1364 | int64_t arg2, int label_index) | |
f02bb954 | 1365 | { |
a7812ae4 | 1366 | TCGv_i64 t0 = tcg_const_i64(arg2); |
f02bb954 | 1367 | tcg_gen_brcond_i64(cond, arg1, t0, label_index); |
a7812ae4 | 1368 | tcg_temp_free_i64(t0); |
f02bb954 AJ |
1369 | } |
1370 | ||
8a56e840 RH |
1371 | static inline void tcg_gen_setcondi_i64(TCGCond cond, TCGv_i64 ret, |
1372 | TCGv_i64 arg1, int64_t arg2) | |
5105c556 AJ |
1373 | { |
1374 | TCGv_i64 t0 = tcg_const_i64(arg2); | |
1375 | tcg_gen_setcond_i64(cond, ret, arg1, t0); | |
1376 | tcg_temp_free_i64(t0); | |
1377 | } | |
1378 | ||
a7812ae4 | 1379 | static inline void tcg_gen_muli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
f02bb954 | 1380 | { |
a7812ae4 | 1381 | TCGv_i64 t0 = tcg_const_i64(arg2); |
f02bb954 | 1382 | tcg_gen_mul_i64(ret, arg1, t0); |
a7812ae4 | 1383 | tcg_temp_free_i64(t0); |
f02bb954 AJ |
1384 | } |
1385 | ||
6359706f | 1386 | |
c896fe29 FB |
1387 | /***************************************/ |
1388 | /* optional operations */ | |
1389 | ||
a7812ae4 | 1390 | static inline void tcg_gen_ext8s_i32(TCGv_i32 ret, TCGv_i32 arg) |
c896fe29 FB |
1391 | { |
1392 | #ifdef TCG_TARGET_HAS_ext8s_i32 | |
a7812ae4 | 1393 | tcg_gen_op2_i32(INDEX_op_ext8s_i32, ret, arg); |
c896fe29 FB |
1394 | #else |
1395 | tcg_gen_shli_i32(ret, arg, 24); | |
5ff9d6a4 | 1396 | tcg_gen_sari_i32(ret, ret, 24); |
c896fe29 FB |
1397 | #endif |
1398 | } | |
1399 | ||
a7812ae4 | 1400 | static inline void tcg_gen_ext16s_i32(TCGv_i32 ret, TCGv_i32 arg) |
c896fe29 FB |
1401 | { |
1402 | #ifdef TCG_TARGET_HAS_ext16s_i32 | |
a7812ae4 | 1403 | tcg_gen_op2_i32(INDEX_op_ext16s_i32, ret, arg); |
c896fe29 FB |
1404 | #else |
1405 | tcg_gen_shli_i32(ret, arg, 16); | |
5ff9d6a4 | 1406 | tcg_gen_sari_i32(ret, ret, 16); |
c896fe29 FB |
1407 | #endif |
1408 | } | |
1409 | ||
a7812ae4 | 1410 | static inline void tcg_gen_ext8u_i32(TCGv_i32 ret, TCGv_i32 arg) |
86831435 | 1411 | { |
cfc86988 AJ |
1412 | #ifdef TCG_TARGET_HAS_ext8u_i32 |
1413 | tcg_gen_op2_i32(INDEX_op_ext8u_i32, ret, arg); | |
1414 | #else | |
86831435 | 1415 | tcg_gen_andi_i32(ret, arg, 0xffu); |
cfc86988 | 1416 | #endif |
86831435 PB |
1417 | } |
1418 | ||
a7812ae4 | 1419 | static inline void tcg_gen_ext16u_i32(TCGv_i32 ret, TCGv_i32 arg) |
86831435 | 1420 | { |
cfc86988 AJ |
1421 | #ifdef TCG_TARGET_HAS_ext16u_i32 |
1422 | tcg_gen_op2_i32(INDEX_op_ext16u_i32, ret, arg); | |
1423 | #else | |
86831435 | 1424 | tcg_gen_andi_i32(ret, arg, 0xffffu); |
cfc86988 | 1425 | #endif |
86831435 PB |
1426 | } |
1427 | ||
c896fe29 | 1428 | /* Note: we assume the two high bytes are set to zero */ |
a7812ae4 | 1429 | static inline void tcg_gen_bswap16_i32(TCGv_i32 ret, TCGv_i32 arg) |
c896fe29 FB |
1430 | { |
1431 | #ifdef TCG_TARGET_HAS_bswap16_i32 | |
a7812ae4 | 1432 | tcg_gen_op2_i32(INDEX_op_bswap16_i32, ret, arg); |
c896fe29 | 1433 | #else |
dfa1a3f1 | 1434 | TCGv_i32 t0 = tcg_temp_new_i32(); |
c896fe29 | 1435 | |
dfa1a3f1 AJ |
1436 | tcg_gen_ext8u_i32(t0, arg); |
1437 | tcg_gen_shli_i32(t0, t0, 8); | |
1438 | tcg_gen_shri_i32(ret, arg, 8); | |
1439 | tcg_gen_or_i32(ret, ret, t0); | |
a7812ae4 | 1440 | tcg_temp_free_i32(t0); |
c896fe29 FB |
1441 | #endif |
1442 | } | |
1443 | ||
66896cb8 | 1444 | static inline void tcg_gen_bswap32_i32(TCGv_i32 ret, TCGv_i32 arg) |
c896fe29 | 1445 | { |
66896cb8 AJ |
1446 | #ifdef TCG_TARGET_HAS_bswap32_i32 |
1447 | tcg_gen_op2_i32(INDEX_op_bswap32_i32, ret, arg); | |
c896fe29 | 1448 | #else |
a7812ae4 PB |
1449 | TCGv_i32 t0, t1; |
1450 | t0 = tcg_temp_new_i32(); | |
1451 | t1 = tcg_temp_new_i32(); | |
c896fe29 FB |
1452 | |
1453 | tcg_gen_shli_i32(t0, arg, 24); | |
1454 | ||
1455 | tcg_gen_andi_i32(t1, arg, 0x0000ff00); | |
1456 | tcg_gen_shli_i32(t1, t1, 8); | |
1457 | tcg_gen_or_i32(t0, t0, t1); | |
1458 | ||
1459 | tcg_gen_shri_i32(t1, arg, 8); | |
1460 | tcg_gen_andi_i32(t1, t1, 0x0000ff00); | |
1461 | tcg_gen_or_i32(t0, t0, t1); | |
1462 | ||
1463 | tcg_gen_shri_i32(t1, arg, 24); | |
1464 | tcg_gen_or_i32(ret, t0, t1); | |
a7812ae4 PB |
1465 | tcg_temp_free_i32(t0); |
1466 | tcg_temp_free_i32(t1); | |
c896fe29 FB |
1467 | #endif |
1468 | } | |
1469 | ||
1470 | #if TCG_TARGET_REG_BITS == 32 | |
a7812ae4 | 1471 | static inline void tcg_gen_ext8s_i64(TCGv_i64 ret, TCGv_i64 arg) |
c896fe29 | 1472 | { |
a7812ae4 PB |
1473 | tcg_gen_ext8s_i32(TCGV_LOW(ret), TCGV_LOW(arg)); |
1474 | tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31); | |
c896fe29 FB |
1475 | } |
1476 | ||
a7812ae4 | 1477 | static inline void tcg_gen_ext16s_i64(TCGv_i64 ret, TCGv_i64 arg) |
c896fe29 | 1478 | { |
a7812ae4 PB |
1479 | tcg_gen_ext16s_i32(TCGV_LOW(ret), TCGV_LOW(arg)); |
1480 | tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31); | |
c896fe29 FB |
1481 | } |
1482 | ||
a7812ae4 | 1483 | static inline void tcg_gen_ext32s_i64(TCGv_i64 ret, TCGv_i64 arg) |
c896fe29 | 1484 | { |
a7812ae4 PB |
1485 | tcg_gen_mov_i32(TCGV_LOW(ret), TCGV_LOW(arg)); |
1486 | tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31); | |
c896fe29 FB |
1487 | } |
1488 | ||
a7812ae4 | 1489 | static inline void tcg_gen_ext8u_i64(TCGv_i64 ret, TCGv_i64 arg) |
86831435 | 1490 | { |
a7812ae4 | 1491 | tcg_gen_ext8u_i32(TCGV_LOW(ret), TCGV_LOW(arg)); |
86831435 PB |
1492 | tcg_gen_movi_i32(TCGV_HIGH(ret), 0); |
1493 | } | |
1494 | ||
a7812ae4 | 1495 | static inline void tcg_gen_ext16u_i64(TCGv_i64 ret, TCGv_i64 arg) |
86831435 | 1496 | { |
a7812ae4 | 1497 | tcg_gen_ext16u_i32(TCGV_LOW(ret), TCGV_LOW(arg)); |
86831435 PB |
1498 | tcg_gen_movi_i32(TCGV_HIGH(ret), 0); |
1499 | } | |
1500 | ||
a7812ae4 | 1501 | static inline void tcg_gen_ext32u_i64(TCGv_i64 ret, TCGv_i64 arg) |
86831435 | 1502 | { |
a7812ae4 | 1503 | tcg_gen_mov_i32(TCGV_LOW(ret), TCGV_LOW(arg)); |
86831435 PB |
1504 | tcg_gen_movi_i32(TCGV_HIGH(ret), 0); |
1505 | } | |
1506 | ||
a7812ae4 | 1507 | static inline void tcg_gen_trunc_i64_i32(TCGv_i32 ret, TCGv_i64 arg) |
c896fe29 | 1508 | { |
a7812ae4 | 1509 | tcg_gen_mov_i32(ret, TCGV_LOW(arg)); |
c896fe29 FB |
1510 | } |
1511 | ||
a7812ae4 | 1512 | static inline void tcg_gen_extu_i32_i64(TCGv_i64 ret, TCGv_i32 arg) |
c896fe29 | 1513 | { |
a7812ae4 | 1514 | tcg_gen_mov_i32(TCGV_LOW(ret), arg); |
ac56dd48 | 1515 | tcg_gen_movi_i32(TCGV_HIGH(ret), 0); |
c896fe29 FB |
1516 | } |
1517 | ||
a7812ae4 | 1518 | static inline void tcg_gen_ext_i32_i64(TCGv_i64 ret, TCGv_i32 arg) |
c896fe29 | 1519 | { |
a7812ae4 PB |
1520 | tcg_gen_mov_i32(TCGV_LOW(ret), arg); |
1521 | tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31); | |
c896fe29 FB |
1522 | } |
1523 | ||
9a5c57fd AJ |
1524 | /* Note: we assume the six high bytes are set to zero */ |
1525 | static inline void tcg_gen_bswap16_i64(TCGv_i64 ret, TCGv_i64 arg) | |
1526 | { | |
1527 | tcg_gen_mov_i32(TCGV_HIGH(ret), TCGV_HIGH(arg)); | |
1528 | tcg_gen_bswap16_i32(TCGV_LOW(ret), TCGV_LOW(arg)); | |
1529 | } | |
1530 | ||
1531 | /* Note: we assume the four high bytes are set to zero */ | |
1532 | static inline void tcg_gen_bswap32_i64(TCGv_i64 ret, TCGv_i64 arg) | |
1533 | { | |
1534 | tcg_gen_mov_i32(TCGV_HIGH(ret), TCGV_HIGH(arg)); | |
1535 | tcg_gen_bswap32_i32(TCGV_LOW(ret), TCGV_LOW(arg)); | |
1536 | } | |
1537 | ||
66896cb8 | 1538 | static inline void tcg_gen_bswap64_i64(TCGv_i64 ret, TCGv_i64 arg) |
c896fe29 | 1539 | { |
a7812ae4 PB |
1540 | TCGv_i32 t0, t1; |
1541 | t0 = tcg_temp_new_i32(); | |
1542 | t1 = tcg_temp_new_i32(); | |
c896fe29 | 1543 | |
66896cb8 AJ |
1544 | tcg_gen_bswap32_i32(t0, TCGV_LOW(arg)); |
1545 | tcg_gen_bswap32_i32(t1, TCGV_HIGH(arg)); | |
a7812ae4 | 1546 | tcg_gen_mov_i32(TCGV_LOW(ret), t1); |
ac56dd48 | 1547 | tcg_gen_mov_i32(TCGV_HIGH(ret), t0); |
a7812ae4 PB |
1548 | tcg_temp_free_i32(t0); |
1549 | tcg_temp_free_i32(t1); | |
c896fe29 FB |
1550 | } |
1551 | #else | |
1552 | ||
a7812ae4 | 1553 | static inline void tcg_gen_ext8s_i64(TCGv_i64 ret, TCGv_i64 arg) |
c896fe29 FB |
1554 | { |
1555 | #ifdef TCG_TARGET_HAS_ext8s_i64 | |
a7812ae4 | 1556 | tcg_gen_op2_i64(INDEX_op_ext8s_i64, ret, arg); |
c896fe29 FB |
1557 | #else |
1558 | tcg_gen_shli_i64(ret, arg, 56); | |
5ff9d6a4 | 1559 | tcg_gen_sari_i64(ret, ret, 56); |
c896fe29 FB |
1560 | #endif |
1561 | } | |
1562 | ||
a7812ae4 | 1563 | static inline void tcg_gen_ext16s_i64(TCGv_i64 ret, TCGv_i64 arg) |
c896fe29 FB |
1564 | { |
1565 | #ifdef TCG_TARGET_HAS_ext16s_i64 | |
a7812ae4 | 1566 | tcg_gen_op2_i64(INDEX_op_ext16s_i64, ret, arg); |
c896fe29 FB |
1567 | #else |
1568 | tcg_gen_shli_i64(ret, arg, 48); | |
5ff9d6a4 | 1569 | tcg_gen_sari_i64(ret, ret, 48); |
c896fe29 FB |
1570 | #endif |
1571 | } | |
1572 | ||
a7812ae4 | 1573 | static inline void tcg_gen_ext32s_i64(TCGv_i64 ret, TCGv_i64 arg) |
c896fe29 FB |
1574 | { |
1575 | #ifdef TCG_TARGET_HAS_ext32s_i64 | |
a7812ae4 | 1576 | tcg_gen_op2_i64(INDEX_op_ext32s_i64, ret, arg); |
c896fe29 FB |
1577 | #else |
1578 | tcg_gen_shli_i64(ret, arg, 32); | |
5ff9d6a4 | 1579 | tcg_gen_sari_i64(ret, ret, 32); |
c896fe29 FB |
1580 | #endif |
1581 | } | |
1582 | ||
a7812ae4 | 1583 | static inline void tcg_gen_ext8u_i64(TCGv_i64 ret, TCGv_i64 arg) |
86831435 | 1584 | { |
cfc86988 AJ |
1585 | #ifdef TCG_TARGET_HAS_ext8u_i64 |
1586 | tcg_gen_op2_i64(INDEX_op_ext8u_i64, ret, arg); | |
1587 | #else | |
86831435 | 1588 | tcg_gen_andi_i64(ret, arg, 0xffu); |
cfc86988 | 1589 | #endif |
86831435 PB |
1590 | } |
1591 | ||
a7812ae4 | 1592 | static inline void tcg_gen_ext16u_i64(TCGv_i64 ret, TCGv_i64 arg) |
86831435 | 1593 | { |
cfc86988 AJ |
1594 | #ifdef TCG_TARGET_HAS_ext16u_i64 |
1595 | tcg_gen_op2_i64(INDEX_op_ext16u_i64, ret, arg); | |
1596 | #else | |
86831435 | 1597 | tcg_gen_andi_i64(ret, arg, 0xffffu); |
cfc86988 | 1598 | #endif |
86831435 PB |
1599 | } |
1600 | ||
a7812ae4 | 1601 | static inline void tcg_gen_ext32u_i64(TCGv_i64 ret, TCGv_i64 arg) |
86831435 | 1602 | { |
cfc86988 AJ |
1603 | #ifdef TCG_TARGET_HAS_ext32u_i64 |
1604 | tcg_gen_op2_i64(INDEX_op_ext32u_i64, ret, arg); | |
1605 | #else | |
86831435 | 1606 | tcg_gen_andi_i64(ret, arg, 0xffffffffu); |
cfc86988 | 1607 | #endif |
86831435 PB |
1608 | } |
1609 | ||
c896fe29 | 1610 | /* Note: we assume the target supports move between 32 and 64 bit |
ac56dd48 | 1611 | registers. This will probably break MIPS64 targets. */ |
a7812ae4 | 1612 | static inline void tcg_gen_trunc_i64_i32(TCGv_i32 ret, TCGv_i64 arg) |
c896fe29 | 1613 | { |
a7812ae4 | 1614 | tcg_gen_mov_i32(ret, MAKE_TCGV_I32(GET_TCGV_I64(arg))); |
c896fe29 FB |
1615 | } |
1616 | ||
1617 | /* Note: we assume the target supports move between 32 and 64 bit | |
1618 | registers */ | |
a7812ae4 | 1619 | static inline void tcg_gen_extu_i32_i64(TCGv_i64 ret, TCGv_i32 arg) |
c896fe29 | 1620 | { |
cfc86988 | 1621 | tcg_gen_ext32u_i64(ret, MAKE_TCGV_I64(GET_TCGV_I32(arg))); |
c896fe29 FB |
1622 | } |
1623 | ||
1624 | /* Note: we assume the target supports move between 32 and 64 bit | |
1625 | registers */ | |
a7812ae4 | 1626 | static inline void tcg_gen_ext_i32_i64(TCGv_i64 ret, TCGv_i32 arg) |
c896fe29 | 1627 | { |
a7812ae4 | 1628 | tcg_gen_ext32s_i64(ret, MAKE_TCGV_I64(GET_TCGV_I32(arg))); |
c896fe29 FB |
1629 | } |
1630 | ||
9a5c57fd AJ |
1631 | /* Note: we assume the six high bytes are set to zero */ |
1632 | static inline void tcg_gen_bswap16_i64(TCGv_i64 ret, TCGv_i64 arg) | |
1633 | { | |
1634 | #ifdef TCG_TARGET_HAS_bswap16_i64 | |
1635 | tcg_gen_op2_i64(INDEX_op_bswap16_i64, ret, arg); | |
1636 | #else | |
1637 | TCGv_i64 t0 = tcg_temp_new_i64(); | |
1638 | ||
1639 | tcg_gen_ext8u_i64(t0, arg); | |
1640 | tcg_gen_shli_i64(t0, t0, 8); | |
1641 | tcg_gen_shri_i64(ret, arg, 8); | |
1642 | tcg_gen_or_i64(ret, ret, t0); | |
1643 | tcg_temp_free_i64(t0); | |
1644 | #endif | |
1645 | } | |
1646 | ||
1647 | /* Note: we assume the four high bytes are set to zero */ | |
1648 | static inline void tcg_gen_bswap32_i64(TCGv_i64 ret, TCGv_i64 arg) | |
1649 | { | |
1650 | #ifdef TCG_TARGET_HAS_bswap32_i64 | |
1651 | tcg_gen_op2_i64(INDEX_op_bswap32_i64, ret, arg); | |
1652 | #else | |
1653 | TCGv_i64 t0, t1; | |
1654 | t0 = tcg_temp_new_i64(); | |
1655 | t1 = tcg_temp_new_i64(); | |
1656 | ||
1657 | tcg_gen_shli_i64(t0, arg, 24); | |
1658 | tcg_gen_ext32u_i64(t0, t0); | |
1659 | ||
1660 | tcg_gen_andi_i64(t1, arg, 0x0000ff00); | |
1661 | tcg_gen_shli_i64(t1, t1, 8); | |
1662 | tcg_gen_or_i64(t0, t0, t1); | |
1663 | ||
1664 | tcg_gen_shri_i64(t1, arg, 8); | |
1665 | tcg_gen_andi_i64(t1, t1, 0x0000ff00); | |
1666 | tcg_gen_or_i64(t0, t0, t1); | |
1667 | ||
1668 | tcg_gen_shri_i64(t1, arg, 24); | |
1669 | tcg_gen_or_i64(ret, t0, t1); | |
1670 | tcg_temp_free_i64(t0); | |
1671 | tcg_temp_free_i64(t1); | |
1672 | #endif | |
1673 | } | |
1674 | ||
66896cb8 | 1675 | static inline void tcg_gen_bswap64_i64(TCGv_i64 ret, TCGv_i64 arg) |
c896fe29 | 1676 | { |
66896cb8 AJ |
1677 | #ifdef TCG_TARGET_HAS_bswap64_i64 |
1678 | tcg_gen_op2_i64(INDEX_op_bswap64_i64, ret, arg); | |
c896fe29 | 1679 | #else |
b348113d SW |
1680 | TCGv_i64 t0 = tcg_temp_new_i64(); |
1681 | TCGv_i64 t1 = tcg_temp_new_i64(); | |
c896fe29 FB |
1682 | |
1683 | tcg_gen_shli_i64(t0, arg, 56); | |
1684 | ||
1685 | tcg_gen_andi_i64(t1, arg, 0x0000ff00); | |
1686 | tcg_gen_shli_i64(t1, t1, 40); | |
1687 | tcg_gen_or_i64(t0, t0, t1); | |
1688 | ||
1689 | tcg_gen_andi_i64(t1, arg, 0x00ff0000); | |
1690 | tcg_gen_shli_i64(t1, t1, 24); | |
1691 | tcg_gen_or_i64(t0, t0, t1); | |
1692 | ||
1693 | tcg_gen_andi_i64(t1, arg, 0xff000000); | |
1694 | tcg_gen_shli_i64(t1, t1, 8); | |
1695 | tcg_gen_or_i64(t0, t0, t1); | |
1696 | ||
1697 | tcg_gen_shri_i64(t1, arg, 8); | |
1698 | tcg_gen_andi_i64(t1, t1, 0xff000000); | |
1699 | tcg_gen_or_i64(t0, t0, t1); | |
1700 | ||
1701 | tcg_gen_shri_i64(t1, arg, 24); | |
1702 | tcg_gen_andi_i64(t1, t1, 0x00ff0000); | |
1703 | tcg_gen_or_i64(t0, t0, t1); | |
1704 | ||
1705 | tcg_gen_shri_i64(t1, arg, 40); | |
1706 | tcg_gen_andi_i64(t1, t1, 0x0000ff00); | |
1707 | tcg_gen_or_i64(t0, t0, t1); | |
1708 | ||
1709 | tcg_gen_shri_i64(t1, arg, 56); | |
1710 | tcg_gen_or_i64(ret, t0, t1); | |
b348113d SW |
1711 | tcg_temp_free_i64(t0); |
1712 | tcg_temp_free_i64(t1); | |
c896fe29 FB |
1713 | #endif |
1714 | } | |
1715 | ||
1716 | #endif | |
1717 | ||
a7812ae4 | 1718 | static inline void tcg_gen_neg_i32(TCGv_i32 ret, TCGv_i32 arg) |
390efc54 PB |
1719 | { |
1720 | #ifdef TCG_TARGET_HAS_neg_i32 | |
a7812ae4 | 1721 | tcg_gen_op2_i32(INDEX_op_neg_i32, ret, arg); |
390efc54 | 1722 | #else |
a7812ae4 | 1723 | TCGv_i32 t0 = tcg_const_i32(0); |
e8996ee0 | 1724 | tcg_gen_sub_i32(ret, t0, arg); |
a7812ae4 | 1725 | tcg_temp_free_i32(t0); |
390efc54 PB |
1726 | #endif |
1727 | } | |
1728 | ||
a7812ae4 | 1729 | static inline void tcg_gen_neg_i64(TCGv_i64 ret, TCGv_i64 arg) |
390efc54 PB |
1730 | { |
1731 | #ifdef TCG_TARGET_HAS_neg_i64 | |
a7812ae4 | 1732 | tcg_gen_op2_i64(INDEX_op_neg_i64, ret, arg); |
390efc54 | 1733 | #else |
a7812ae4 | 1734 | TCGv_i64 t0 = tcg_const_i64(0); |
e8996ee0 | 1735 | tcg_gen_sub_i64(ret, t0, arg); |
a7812ae4 | 1736 | tcg_temp_free_i64(t0); |
390efc54 PB |
1737 | #endif |
1738 | } | |
1739 | ||
a7812ae4 | 1740 | static inline void tcg_gen_not_i32(TCGv_i32 ret, TCGv_i32 arg) |
0b6ce4cf | 1741 | { |
d2604285 AJ |
1742 | #ifdef TCG_TARGET_HAS_not_i32 |
1743 | tcg_gen_op2_i32(INDEX_op_not_i32, ret, arg); | |
1744 | #else | |
e8996ee0 | 1745 | tcg_gen_xori_i32(ret, arg, -1); |
d2604285 | 1746 | #endif |
0b6ce4cf FB |
1747 | } |
1748 | ||
a7812ae4 | 1749 | static inline void tcg_gen_not_i64(TCGv_i64 ret, TCGv_i64 arg) |
0b6ce4cf | 1750 | { |
d2604285 | 1751 | #ifdef TCG_TARGET_HAS_not_i64 |
43e860ef | 1752 | tcg_gen_op2_i64(INDEX_op_not_i64, ret, arg); |
a10f9f4f RH |
1753 | #elif defined(TCG_TARGET_HAS_not_i32) && TCG_TARGET_REG_BITS == 32 |
1754 | tcg_gen_not_i32(TCGV_LOW(ret), TCGV_LOW(arg)); | |
1755 | tcg_gen_not_i32(TCGV_HIGH(ret), TCGV_HIGH(arg)); | |
d2604285 | 1756 | #else |
e8996ee0 | 1757 | tcg_gen_xori_i64(ret, arg, -1); |
d2604285 | 1758 | #endif |
0b6ce4cf | 1759 | } |
5ff9d6a4 | 1760 | |
a7812ae4 | 1761 | static inline void tcg_gen_discard_i32(TCGv_i32 arg) |
5ff9d6a4 | 1762 | { |
a7812ae4 | 1763 | tcg_gen_op1_i32(INDEX_op_discard, arg); |
5ff9d6a4 FB |
1764 | } |
1765 | ||
1766 | #if TCG_TARGET_REG_BITS == 32 | |
a7812ae4 | 1767 | static inline void tcg_gen_discard_i64(TCGv_i64 arg) |
5ff9d6a4 | 1768 | { |
a7812ae4 | 1769 | tcg_gen_discard_i32(TCGV_LOW(arg)); |
5ff9d6a4 FB |
1770 | tcg_gen_discard_i32(TCGV_HIGH(arg)); |
1771 | } | |
1772 | #else | |
a7812ae4 | 1773 | static inline void tcg_gen_discard_i64(TCGv_i64 arg) |
5ff9d6a4 | 1774 | { |
a7812ae4 | 1775 | tcg_gen_op1_i64(INDEX_op_discard, arg); |
5ff9d6a4 FB |
1776 | } |
1777 | #endif | |
1778 | ||
a7812ae4 | 1779 | static inline void tcg_gen_concat_i32_i64(TCGv_i64 dest, TCGv_i32 low, TCGv_i32 high) |
36aa55dc PB |
1780 | { |
1781 | #if TCG_TARGET_REG_BITS == 32 | |
a7812ae4 | 1782 | tcg_gen_mov_i32(TCGV_LOW(dest), low); |
36aa55dc PB |
1783 | tcg_gen_mov_i32(TCGV_HIGH(dest), high); |
1784 | #else | |
a7812ae4 | 1785 | TCGv_i64 tmp = tcg_temp_new_i64(); |
36aa55dc PB |
1786 | /* This extension is only needed for type correctness. |
1787 | We may be able to do better given target specific information. */ | |
1788 | tcg_gen_extu_i32_i64(tmp, high); | |
1789 | tcg_gen_shli_i64(tmp, tmp, 32); | |
1790 | tcg_gen_extu_i32_i64(dest, low); | |
1791 | tcg_gen_or_i64(dest, dest, tmp); | |
a7812ae4 | 1792 | tcg_temp_free_i64(tmp); |
36aa55dc PB |
1793 | #endif |
1794 | } | |
1795 | ||
a7812ae4 | 1796 | static inline void tcg_gen_concat32_i64(TCGv_i64 dest, TCGv_i64 low, TCGv_i64 high) |
945ca823 BS |
1797 | { |
1798 | #if TCG_TARGET_REG_BITS == 32 | |
a7812ae4 | 1799 | tcg_gen_concat_i32_i64(dest, TCGV_LOW(low), TCGV_LOW(high)); |
945ca823 | 1800 | #else |
a7812ae4 | 1801 | TCGv_i64 tmp = tcg_temp_new_i64(); |
88422e2e | 1802 | tcg_gen_ext32u_i64(dest, low); |
945ca823 | 1803 | tcg_gen_shli_i64(tmp, high, 32); |
88422e2e | 1804 | tcg_gen_or_i64(dest, dest, tmp); |
a7812ae4 | 1805 | tcg_temp_free_i64(tmp); |
945ca823 BS |
1806 | #endif |
1807 | } | |
1808 | ||
a7812ae4 | 1809 | static inline void tcg_gen_andc_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
f24cb33e | 1810 | { |
241cbed4 RH |
1811 | #ifdef TCG_TARGET_HAS_andc_i32 |
1812 | tcg_gen_op3_i32(INDEX_op_andc_i32, ret, arg1, arg2); | |
1813 | #else | |
a7812ae4 PB |
1814 | TCGv_i32 t0; |
1815 | t0 = tcg_temp_new_i32(); | |
f24cb33e AJ |
1816 | tcg_gen_not_i32(t0, arg2); |
1817 | tcg_gen_and_i32(ret, arg1, t0); | |
a7812ae4 | 1818 | tcg_temp_free_i32(t0); |
241cbed4 | 1819 | #endif |
f24cb33e AJ |
1820 | } |
1821 | ||
a7812ae4 | 1822 | static inline void tcg_gen_andc_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
f24cb33e | 1823 | { |
241cbed4 RH |
1824 | #ifdef TCG_TARGET_HAS_andc_i64 |
1825 | tcg_gen_op3_i64(INDEX_op_andc_i64, ret, arg1, arg2); | |
1826 | #elif defined(TCG_TARGET_HAS_andc_i32) && TCG_TARGET_REG_BITS == 32 | |
1827 | tcg_gen_andc_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2)); | |
1828 | tcg_gen_andc_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2)); | |
1829 | #else | |
a7812ae4 PB |
1830 | TCGv_i64 t0; |
1831 | t0 = tcg_temp_new_i64(); | |
f24cb33e AJ |
1832 | tcg_gen_not_i64(t0, arg2); |
1833 | tcg_gen_and_i64(ret, arg1, t0); | |
a7812ae4 | 1834 | tcg_temp_free_i64(t0); |
241cbed4 | 1835 | #endif |
f24cb33e AJ |
1836 | } |
1837 | ||
a7812ae4 | 1838 | static inline void tcg_gen_eqv_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
f24cb33e | 1839 | { |
8d625cf1 RH |
1840 | #ifdef TCG_TARGET_HAS_eqv_i32 |
1841 | tcg_gen_op3_i32(INDEX_op_eqv_i32, ret, arg1, arg2); | |
1842 | #else | |
7fc81051 AJ |
1843 | tcg_gen_xor_i32(ret, arg1, arg2); |
1844 | tcg_gen_not_i32(ret, ret); | |
8d625cf1 | 1845 | #endif |
f24cb33e AJ |
1846 | } |
1847 | ||
a7812ae4 | 1848 | static inline void tcg_gen_eqv_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
f24cb33e | 1849 | { |
8d625cf1 RH |
1850 | #ifdef TCG_TARGET_HAS_eqv_i64 |
1851 | tcg_gen_op3_i64(INDEX_op_eqv_i64, ret, arg1, arg2); | |
1852 | #elif defined(TCG_TARGET_HAS_eqv_i32) && TCG_TARGET_REG_BITS == 32 | |
1853 | tcg_gen_eqv_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2)); | |
1854 | tcg_gen_eqv_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2)); | |
1855 | #else | |
7fc81051 AJ |
1856 | tcg_gen_xor_i64(ret, arg1, arg2); |
1857 | tcg_gen_not_i64(ret, ret); | |
8d625cf1 | 1858 | #endif |
f24cb33e AJ |
1859 | } |
1860 | ||
a7812ae4 | 1861 | static inline void tcg_gen_nand_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
f24cb33e | 1862 | { |
9940a96b RH |
1863 | #ifdef TCG_TARGET_HAS_nand_i32 |
1864 | tcg_gen_op3_i32(INDEX_op_nand_i32, ret, arg1, arg2); | |
1865 | #else | |
7fc81051 AJ |
1866 | tcg_gen_and_i32(ret, arg1, arg2); |
1867 | tcg_gen_not_i32(ret, ret); | |
9940a96b | 1868 | #endif |
f24cb33e AJ |
1869 | } |
1870 | ||
a7812ae4 | 1871 | static inline void tcg_gen_nand_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
f24cb33e | 1872 | { |
9940a96b RH |
1873 | #ifdef TCG_TARGET_HAS_nand_i64 |
1874 | tcg_gen_op3_i64(INDEX_op_nand_i64, ret, arg1, arg2); | |
1875 | #elif defined(TCG_TARGET_HAS_nand_i32) && TCG_TARGET_REG_BITS == 32 | |
1876 | tcg_gen_nand_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2)); | |
1877 | tcg_gen_nand_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2)); | |
1878 | #else | |
7fc81051 AJ |
1879 | tcg_gen_and_i64(ret, arg1, arg2); |
1880 | tcg_gen_not_i64(ret, ret); | |
9940a96b | 1881 | #endif |
f24cb33e AJ |
1882 | } |
1883 | ||
a7812ae4 | 1884 | static inline void tcg_gen_nor_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
f24cb33e | 1885 | { |
32d98fbd RH |
1886 | #ifdef TCG_TARGET_HAS_nor_i32 |
1887 | tcg_gen_op3_i32(INDEX_op_nor_i32, ret, arg1, arg2); | |
1888 | #else | |
7fc81051 AJ |
1889 | tcg_gen_or_i32(ret, arg1, arg2); |
1890 | tcg_gen_not_i32(ret, ret); | |
32d98fbd | 1891 | #endif |
f24cb33e AJ |
1892 | } |
1893 | ||
a7812ae4 | 1894 | static inline void tcg_gen_nor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
f24cb33e | 1895 | { |
32d98fbd RH |
1896 | #ifdef TCG_TARGET_HAS_nor_i64 |
1897 | tcg_gen_op3_i64(INDEX_op_nor_i64, ret, arg1, arg2); | |
1898 | #elif defined(TCG_TARGET_HAS_nor_i32) && TCG_TARGET_REG_BITS == 32 | |
1899 | tcg_gen_nor_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2)); | |
1900 | tcg_gen_nor_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2)); | |
1901 | #else | |
7fc81051 AJ |
1902 | tcg_gen_or_i64(ret, arg1, arg2); |
1903 | tcg_gen_not_i64(ret, ret); | |
32d98fbd | 1904 | #endif |
f24cb33e AJ |
1905 | } |
1906 | ||
a7812ae4 | 1907 | static inline void tcg_gen_orc_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
f24cb33e | 1908 | { |
791d1262 RH |
1909 | #ifdef TCG_TARGET_HAS_orc_i32 |
1910 | tcg_gen_op3_i32(INDEX_op_orc_i32, ret, arg1, arg2); | |
1911 | #else | |
a7812ae4 PB |
1912 | TCGv_i32 t0; |
1913 | t0 = tcg_temp_new_i32(); | |
f24cb33e AJ |
1914 | tcg_gen_not_i32(t0, arg2); |
1915 | tcg_gen_or_i32(ret, arg1, t0); | |
a7812ae4 | 1916 | tcg_temp_free_i32(t0); |
791d1262 | 1917 | #endif |
f24cb33e AJ |
1918 | } |
1919 | ||
a7812ae4 | 1920 | static inline void tcg_gen_orc_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
f24cb33e | 1921 | { |
791d1262 RH |
1922 | #ifdef TCG_TARGET_HAS_orc_i64 |
1923 | tcg_gen_op3_i64(INDEX_op_orc_i64, ret, arg1, arg2); | |
1924 | #elif defined(TCG_TARGET_HAS_orc_i32) && TCG_TARGET_REG_BITS == 32 | |
1925 | tcg_gen_orc_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2)); | |
1926 | tcg_gen_orc_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2)); | |
1927 | #else | |
a7812ae4 PB |
1928 | TCGv_i64 t0; |
1929 | t0 = tcg_temp_new_i64(); | |
f24cb33e AJ |
1930 | tcg_gen_not_i64(t0, arg2); |
1931 | tcg_gen_or_i64(ret, arg1, t0); | |
a7812ae4 | 1932 | tcg_temp_free_i64(t0); |
791d1262 | 1933 | #endif |
f24cb33e AJ |
1934 | } |
1935 | ||
a7812ae4 | 1936 | static inline void tcg_gen_rotl_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
15824571 | 1937 | { |
d42f183c AJ |
1938 | #ifdef TCG_TARGET_HAS_rot_i32 |
1939 | tcg_gen_op3_i32(INDEX_op_rotl_i32, ret, arg1, arg2); | |
1940 | #else | |
a7812ae4 | 1941 | TCGv_i32 t0, t1; |
15824571 | 1942 | |
a7812ae4 PB |
1943 | t0 = tcg_temp_new_i32(); |
1944 | t1 = tcg_temp_new_i32(); | |
15824571 AJ |
1945 | tcg_gen_shl_i32(t0, arg1, arg2); |
1946 | tcg_gen_subfi_i32(t1, 32, arg2); | |
1947 | tcg_gen_shr_i32(t1, arg1, t1); | |
1948 | tcg_gen_or_i32(ret, t0, t1); | |
a7812ae4 PB |
1949 | tcg_temp_free_i32(t0); |
1950 | tcg_temp_free_i32(t1); | |
d42f183c | 1951 | #endif |
15824571 AJ |
1952 | } |
1953 | ||
a7812ae4 | 1954 | static inline void tcg_gen_rotl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
15824571 | 1955 | { |
d42f183c AJ |
1956 | #ifdef TCG_TARGET_HAS_rot_i64 |
1957 | tcg_gen_op3_i64(INDEX_op_rotl_i64, ret, arg1, arg2); | |
1958 | #else | |
a7812ae4 | 1959 | TCGv_i64 t0, t1; |
15824571 | 1960 | |
a7812ae4 PB |
1961 | t0 = tcg_temp_new_i64(); |
1962 | t1 = tcg_temp_new_i64(); | |
15824571 AJ |
1963 | tcg_gen_shl_i64(t0, arg1, arg2); |
1964 | tcg_gen_subfi_i64(t1, 64, arg2); | |
1965 | tcg_gen_shr_i64(t1, arg1, t1); | |
1966 | tcg_gen_or_i64(ret, t0, t1); | |
a7812ae4 PB |
1967 | tcg_temp_free_i64(t0); |
1968 | tcg_temp_free_i64(t1); | |
d42f183c | 1969 | #endif |
15824571 AJ |
1970 | } |
1971 | ||
a7812ae4 | 1972 | static inline void tcg_gen_rotli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) |
15824571 AJ |
1973 | { |
1974 | /* some cases can be optimized here */ | |
1975 | if (arg2 == 0) { | |
1976 | tcg_gen_mov_i32(ret, arg1); | |
1977 | } else { | |
d42f183c AJ |
1978 | #ifdef TCG_TARGET_HAS_rot_i32 |
1979 | TCGv_i32 t0 = tcg_const_i32(arg2); | |
1980 | tcg_gen_rotl_i32(ret, arg1, t0); | |
1981 | tcg_temp_free_i32(t0); | |
1982 | #else | |
a7812ae4 PB |
1983 | TCGv_i32 t0, t1; |
1984 | t0 = tcg_temp_new_i32(); | |
1985 | t1 = tcg_temp_new_i32(); | |
15824571 AJ |
1986 | tcg_gen_shli_i32(t0, arg1, arg2); |
1987 | tcg_gen_shri_i32(t1, arg1, 32 - arg2); | |
1988 | tcg_gen_or_i32(ret, t0, t1); | |
a7812ae4 PB |
1989 | tcg_temp_free_i32(t0); |
1990 | tcg_temp_free_i32(t1); | |
d42f183c | 1991 | #endif |
15824571 AJ |
1992 | } |
1993 | } | |
1994 | ||
a7812ae4 | 1995 | static inline void tcg_gen_rotli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
15824571 AJ |
1996 | { |
1997 | /* some cases can be optimized here */ | |
1998 | if (arg2 == 0) { | |
1999 | tcg_gen_mov_i64(ret, arg1); | |
2000 | } else { | |
d42f183c AJ |
2001 | #ifdef TCG_TARGET_HAS_rot_i64 |
2002 | TCGv_i64 t0 = tcg_const_i64(arg2); | |
2003 | tcg_gen_rotl_i64(ret, arg1, t0); | |
2004 | tcg_temp_free_i64(t0); | |
2005 | #else | |
a7812ae4 PB |
2006 | TCGv_i64 t0, t1; |
2007 | t0 = tcg_temp_new_i64(); | |
2008 | t1 = tcg_temp_new_i64(); | |
15824571 AJ |
2009 | tcg_gen_shli_i64(t0, arg1, arg2); |
2010 | tcg_gen_shri_i64(t1, arg1, 64 - arg2); | |
2011 | tcg_gen_or_i64(ret, t0, t1); | |
a7812ae4 PB |
2012 | tcg_temp_free_i64(t0); |
2013 | tcg_temp_free_i64(t1); | |
d42f183c | 2014 | #endif |
15824571 AJ |
2015 | } |
2016 | } | |
2017 | ||
a7812ae4 | 2018 | static inline void tcg_gen_rotr_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
15824571 | 2019 | { |
d42f183c AJ |
2020 | #ifdef TCG_TARGET_HAS_rot_i32 |
2021 | tcg_gen_op3_i32(INDEX_op_rotr_i32, ret, arg1, arg2); | |
2022 | #else | |
a7812ae4 | 2023 | TCGv_i32 t0, t1; |
15824571 | 2024 | |
a7812ae4 PB |
2025 | t0 = tcg_temp_new_i32(); |
2026 | t1 = tcg_temp_new_i32(); | |
15824571 AJ |
2027 | tcg_gen_shr_i32(t0, arg1, arg2); |
2028 | tcg_gen_subfi_i32(t1, 32, arg2); | |
2029 | tcg_gen_shl_i32(t1, arg1, t1); | |
2030 | tcg_gen_or_i32(ret, t0, t1); | |
a7812ae4 PB |
2031 | tcg_temp_free_i32(t0); |
2032 | tcg_temp_free_i32(t1); | |
d42f183c | 2033 | #endif |
15824571 AJ |
2034 | } |
2035 | ||
a7812ae4 | 2036 | static inline void tcg_gen_rotr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
15824571 | 2037 | { |
d42f183c AJ |
2038 | #ifdef TCG_TARGET_HAS_rot_i64 |
2039 | tcg_gen_op3_i64(INDEX_op_rotr_i64, ret, arg1, arg2); | |
2040 | #else | |
a7812ae4 | 2041 | TCGv_i64 t0, t1; |
15824571 | 2042 | |
a7812ae4 PB |
2043 | t0 = tcg_temp_new_i64(); |
2044 | t1 = tcg_temp_new_i64(); | |
d9885a0b | 2045 | tcg_gen_shr_i64(t0, arg1, arg2); |
15824571 AJ |
2046 | tcg_gen_subfi_i64(t1, 64, arg2); |
2047 | tcg_gen_shl_i64(t1, arg1, t1); | |
2048 | tcg_gen_or_i64(ret, t0, t1); | |
a7812ae4 PB |
2049 | tcg_temp_free_i64(t0); |
2050 | tcg_temp_free_i64(t1); | |
d42f183c | 2051 | #endif |
15824571 AJ |
2052 | } |
2053 | ||
a7812ae4 | 2054 | static inline void tcg_gen_rotri_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) |
15824571 AJ |
2055 | { |
2056 | /* some cases can be optimized here */ | |
2057 | if (arg2 == 0) { | |
2058 | tcg_gen_mov_i32(ret, arg1); | |
2059 | } else { | |
2060 | tcg_gen_rotli_i32(ret, arg1, 32 - arg2); | |
2061 | } | |
2062 | } | |
2063 | ||
a7812ae4 | 2064 | static inline void tcg_gen_rotri_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
15824571 AJ |
2065 | { |
2066 | /* some cases can be optimized here */ | |
2067 | if (arg2 == 0) { | |
de3526b2 | 2068 | tcg_gen_mov_i64(ret, arg1); |
15824571 AJ |
2069 | } else { |
2070 | tcg_gen_rotli_i64(ret, arg1, 64 - arg2); | |
2071 | } | |
2072 | } | |
2073 | ||
c896fe29 FB |
2074 | /***************************************/ |
2075 | /* QEMU specific operations. Their type depend on the QEMU CPU | |
2076 | type. */ | |
2077 | #ifndef TARGET_LONG_BITS | |
2078 | #error must include QEMU headers | |
2079 | #endif | |
2080 | ||
a7812ae4 PB |
2081 | #if TARGET_LONG_BITS == 32 |
2082 | #define TCGv TCGv_i32 | |
2083 | #define tcg_temp_new() tcg_temp_new_i32() | |
2084 | #define tcg_global_reg_new tcg_global_reg_new_i32 | |
2085 | #define tcg_global_mem_new tcg_global_mem_new_i32 | |
df9247b2 | 2086 | #define tcg_temp_local_new() tcg_temp_local_new_i32() |
a7812ae4 PB |
2087 | #define tcg_temp_free tcg_temp_free_i32 |
2088 | #define tcg_gen_qemu_ldst_op tcg_gen_op3i_i32 | |
2089 | #define tcg_gen_qemu_ldst_op_i64 tcg_gen_qemu_ldst_op_i64_i32 | |
2090 | #define TCGV_UNUSED(x) TCGV_UNUSED_I32(x) | |
fe75bcf7 | 2091 | #define TCGV_EQUAL(a, b) TCGV_EQUAL_I32(a, b) |
a7812ae4 PB |
2092 | #else |
2093 | #define TCGv TCGv_i64 | |
2094 | #define tcg_temp_new() tcg_temp_new_i64() | |
2095 | #define tcg_global_reg_new tcg_global_reg_new_i64 | |
2096 | #define tcg_global_mem_new tcg_global_mem_new_i64 | |
df9247b2 | 2097 | #define tcg_temp_local_new() tcg_temp_local_new_i64() |
a7812ae4 PB |
2098 | #define tcg_temp_free tcg_temp_free_i64 |
2099 | #define tcg_gen_qemu_ldst_op tcg_gen_op3i_i64 | |
2100 | #define tcg_gen_qemu_ldst_op_i64 tcg_gen_qemu_ldst_op_i64_i64 | |
2101 | #define TCGV_UNUSED(x) TCGV_UNUSED_I64(x) | |
fe75bcf7 | 2102 | #define TCGV_EQUAL(a, b) TCGV_EQUAL_I64(a, b) |
a7812ae4 PB |
2103 | #endif |
2104 | ||
7e4597d7 FB |
2105 | /* debug info: write the PC of the corresponding QEMU CPU instruction */ |
2106 | static inline void tcg_gen_debug_insn_start(uint64_t pc) | |
2107 | { | |
2108 | /* XXX: must really use a 32 bit size for TCGArg in all cases */ | |
2109 | #if TARGET_LONG_BITS > TCG_TARGET_REG_BITS | |
bcb0126f PB |
2110 | tcg_gen_op2ii(INDEX_op_debug_insn_start, |
2111 | (uint32_t)(pc), (uint32_t)(pc >> 32)); | |
7e4597d7 FB |
2112 | #else |
2113 | tcg_gen_op1i(INDEX_op_debug_insn_start, pc); | |
2114 | #endif | |
2115 | } | |
2116 | ||
c896fe29 FB |
2117 | static inline void tcg_gen_exit_tb(tcg_target_long val) |
2118 | { | |
ac56dd48 | 2119 | tcg_gen_op1i(INDEX_op_exit_tb, val); |
c896fe29 FB |
2120 | } |
2121 | ||
2122 | static inline void tcg_gen_goto_tb(int idx) | |
2123 | { | |
ac56dd48 | 2124 | tcg_gen_op1i(INDEX_op_goto_tb, idx); |
c896fe29 FB |
2125 | } |
2126 | ||
2127 | #if TCG_TARGET_REG_BITS == 32 | |
ac56dd48 | 2128 | static inline void tcg_gen_qemu_ld8u(TCGv ret, TCGv addr, int mem_index) |
c896fe29 FB |
2129 | { |
2130 | #if TARGET_LONG_BITS == 32 | |
a7812ae4 | 2131 | tcg_gen_op3i_i32(INDEX_op_qemu_ld8u, ret, addr, mem_index); |
c896fe29 | 2132 | #else |
a7812ae4 PB |
2133 | tcg_gen_op4i_i32(INDEX_op_qemu_ld8u, TCGV_LOW(ret), TCGV_LOW(addr), |
2134 | TCGV_HIGH(addr), mem_index); | |
ac56dd48 | 2135 | tcg_gen_movi_i32(TCGV_HIGH(ret), 0); |
c896fe29 FB |
2136 | #endif |
2137 | } | |
2138 | ||
ac56dd48 | 2139 | static inline void tcg_gen_qemu_ld8s(TCGv ret, TCGv addr, int mem_index) |
c896fe29 FB |
2140 | { |
2141 | #if TARGET_LONG_BITS == 32 | |
a7812ae4 | 2142 | tcg_gen_op3i_i32(INDEX_op_qemu_ld8s, ret, addr, mem_index); |
c896fe29 | 2143 | #else |
a7812ae4 PB |
2144 | tcg_gen_op4i_i32(INDEX_op_qemu_ld8s, TCGV_LOW(ret), TCGV_LOW(addr), |
2145 | TCGV_HIGH(addr), mem_index); | |
2146 | tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31); | |
c896fe29 FB |
2147 | #endif |
2148 | } | |
2149 | ||
ac56dd48 | 2150 | static inline void tcg_gen_qemu_ld16u(TCGv ret, TCGv addr, int mem_index) |
c896fe29 FB |
2151 | { |
2152 | #if TARGET_LONG_BITS == 32 | |
a7812ae4 | 2153 | tcg_gen_op3i_i32(INDEX_op_qemu_ld16u, ret, addr, mem_index); |
c896fe29 | 2154 | #else |
a7812ae4 PB |
2155 | tcg_gen_op4i_i32(INDEX_op_qemu_ld16u, TCGV_LOW(ret), TCGV_LOW(addr), |
2156 | TCGV_HIGH(addr), mem_index); | |
ac56dd48 | 2157 | tcg_gen_movi_i32(TCGV_HIGH(ret), 0); |
c896fe29 FB |
2158 | #endif |
2159 | } | |
2160 | ||
ac56dd48 | 2161 | static inline void tcg_gen_qemu_ld16s(TCGv ret, TCGv addr, int mem_index) |
c896fe29 FB |
2162 | { |
2163 | #if TARGET_LONG_BITS == 32 | |
a7812ae4 | 2164 | tcg_gen_op3i_i32(INDEX_op_qemu_ld16s, ret, addr, mem_index); |
c896fe29 | 2165 | #else |
a7812ae4 PB |
2166 | tcg_gen_op4i_i32(INDEX_op_qemu_ld16s, TCGV_LOW(ret), TCGV_LOW(addr), |
2167 | TCGV_HIGH(addr), mem_index); | |
2168 | tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31); | |
c896fe29 FB |
2169 | #endif |
2170 | } | |
2171 | ||
ac56dd48 | 2172 | static inline void tcg_gen_qemu_ld32u(TCGv ret, TCGv addr, int mem_index) |
c896fe29 FB |
2173 | { |
2174 | #if TARGET_LONG_BITS == 32 | |
86feb1c8 | 2175 | tcg_gen_op3i_i32(INDEX_op_qemu_ld32, ret, addr, mem_index); |
c896fe29 | 2176 | #else |
86feb1c8 | 2177 | tcg_gen_op4i_i32(INDEX_op_qemu_ld32, TCGV_LOW(ret), TCGV_LOW(addr), |
a7812ae4 | 2178 | TCGV_HIGH(addr), mem_index); |
ac56dd48 | 2179 | tcg_gen_movi_i32(TCGV_HIGH(ret), 0); |
c896fe29 FB |
2180 | #endif |
2181 | } | |
2182 | ||
ac56dd48 | 2183 | static inline void tcg_gen_qemu_ld32s(TCGv ret, TCGv addr, int mem_index) |
c896fe29 FB |
2184 | { |
2185 | #if TARGET_LONG_BITS == 32 | |
86feb1c8 | 2186 | tcg_gen_op3i_i32(INDEX_op_qemu_ld32, ret, addr, mem_index); |
c896fe29 | 2187 | #else |
86feb1c8 | 2188 | tcg_gen_op4i_i32(INDEX_op_qemu_ld32, TCGV_LOW(ret), TCGV_LOW(addr), |
a7812ae4 PB |
2189 | TCGV_HIGH(addr), mem_index); |
2190 | tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31); | |
c896fe29 FB |
2191 | #endif |
2192 | } | |
2193 | ||
a7812ae4 | 2194 | static inline void tcg_gen_qemu_ld64(TCGv_i64 ret, TCGv addr, int mem_index) |
c896fe29 FB |
2195 | { |
2196 | #if TARGET_LONG_BITS == 32 | |
a7812ae4 | 2197 | tcg_gen_op4i_i32(INDEX_op_qemu_ld64, TCGV_LOW(ret), TCGV_HIGH(ret), addr, mem_index); |
c896fe29 | 2198 | #else |
a7812ae4 PB |
2199 | tcg_gen_op5i_i32(INDEX_op_qemu_ld64, TCGV_LOW(ret), TCGV_HIGH(ret), |
2200 | TCGV_LOW(addr), TCGV_HIGH(addr), mem_index); | |
c896fe29 FB |
2201 | #endif |
2202 | } | |
2203 | ||
ac56dd48 | 2204 | static inline void tcg_gen_qemu_st8(TCGv arg, TCGv addr, int mem_index) |
c896fe29 FB |
2205 | { |
2206 | #if TARGET_LONG_BITS == 32 | |
a7812ae4 | 2207 | tcg_gen_op3i_i32(INDEX_op_qemu_st8, arg, addr, mem_index); |
c896fe29 | 2208 | #else |
a7812ae4 PB |
2209 | tcg_gen_op4i_i32(INDEX_op_qemu_st8, TCGV_LOW(arg), TCGV_LOW(addr), |
2210 | TCGV_HIGH(addr), mem_index); | |
c896fe29 FB |
2211 | #endif |
2212 | } | |
2213 | ||
ac56dd48 | 2214 | static inline void tcg_gen_qemu_st16(TCGv arg, TCGv addr, int mem_index) |
c896fe29 FB |
2215 | { |
2216 | #if TARGET_LONG_BITS == 32 | |
a7812ae4 | 2217 | tcg_gen_op3i_i32(INDEX_op_qemu_st16, arg, addr, mem_index); |
c896fe29 | 2218 | #else |
a7812ae4 PB |
2219 | tcg_gen_op4i_i32(INDEX_op_qemu_st16, TCGV_LOW(arg), TCGV_LOW(addr), |
2220 | TCGV_HIGH(addr), mem_index); | |
c896fe29 FB |
2221 | #endif |
2222 | } | |
2223 | ||
ac56dd48 | 2224 | static inline void tcg_gen_qemu_st32(TCGv arg, TCGv addr, int mem_index) |
c896fe29 FB |
2225 | { |
2226 | #if TARGET_LONG_BITS == 32 | |
a7812ae4 | 2227 | tcg_gen_op3i_i32(INDEX_op_qemu_st32, arg, addr, mem_index); |
c896fe29 | 2228 | #else |
a7812ae4 PB |
2229 | tcg_gen_op4i_i32(INDEX_op_qemu_st32, TCGV_LOW(arg), TCGV_LOW(addr), |
2230 | TCGV_HIGH(addr), mem_index); | |
c896fe29 FB |
2231 | #endif |
2232 | } | |
2233 | ||
a7812ae4 | 2234 | static inline void tcg_gen_qemu_st64(TCGv_i64 arg, TCGv addr, int mem_index) |
c896fe29 FB |
2235 | { |
2236 | #if TARGET_LONG_BITS == 32 | |
a7812ae4 PB |
2237 | tcg_gen_op4i_i32(INDEX_op_qemu_st64, TCGV_LOW(arg), TCGV_HIGH(arg), addr, |
2238 | mem_index); | |
c896fe29 | 2239 | #else |
a7812ae4 PB |
2240 | tcg_gen_op5i_i32(INDEX_op_qemu_st64, TCGV_LOW(arg), TCGV_HIGH(arg), |
2241 | TCGV_LOW(addr), TCGV_HIGH(addr), mem_index); | |
c896fe29 FB |
2242 | #endif |
2243 | } | |
2244 | ||
56b8f567 | 2245 | #define tcg_gen_ld_ptr tcg_gen_ld_i32 |
a768e4b2 | 2246 | #define tcg_gen_discard_ptr tcg_gen_discard_i32 |
f8422f52 | 2247 | |
c896fe29 FB |
2248 | #else /* TCG_TARGET_REG_BITS == 32 */ |
2249 | ||
ac56dd48 | 2250 | static inline void tcg_gen_qemu_ld8u(TCGv ret, TCGv addr, int mem_index) |
c896fe29 | 2251 | { |
a7812ae4 | 2252 | tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld8u, ret, addr, mem_index); |
c896fe29 FB |
2253 | } |
2254 | ||
ac56dd48 | 2255 | static inline void tcg_gen_qemu_ld8s(TCGv ret, TCGv addr, int mem_index) |
c896fe29 | 2256 | { |
a7812ae4 | 2257 | tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld8s, ret, addr, mem_index); |
c896fe29 FB |
2258 | } |
2259 | ||
ac56dd48 | 2260 | static inline void tcg_gen_qemu_ld16u(TCGv ret, TCGv addr, int mem_index) |
c896fe29 | 2261 | { |
a7812ae4 | 2262 | tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld16u, ret, addr, mem_index); |
c896fe29 FB |
2263 | } |
2264 | ||
ac56dd48 | 2265 | static inline void tcg_gen_qemu_ld16s(TCGv ret, TCGv addr, int mem_index) |
c896fe29 | 2266 | { |
a7812ae4 | 2267 | tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld16s, ret, addr, mem_index); |
c896fe29 FB |
2268 | } |
2269 | ||
ac56dd48 | 2270 | static inline void tcg_gen_qemu_ld32u(TCGv ret, TCGv addr, int mem_index) |
c896fe29 | 2271 | { |
3e1dbadd RH |
2272 | #if TARGET_LONG_BITS == 32 |
2273 | tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld32, ret, addr, mem_index); | |
2274 | #else | |
a7812ae4 | 2275 | tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld32u, ret, addr, mem_index); |
3e1dbadd | 2276 | #endif |
c896fe29 FB |
2277 | } |
2278 | ||
ac56dd48 | 2279 | static inline void tcg_gen_qemu_ld32s(TCGv ret, TCGv addr, int mem_index) |
c896fe29 | 2280 | { |
3e1dbadd RH |
2281 | #if TARGET_LONG_BITS == 32 |
2282 | tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld32, ret, addr, mem_index); | |
2283 | #else | |
a7812ae4 | 2284 | tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld32s, ret, addr, mem_index); |
3e1dbadd | 2285 | #endif |
c896fe29 FB |
2286 | } |
2287 | ||
a7812ae4 | 2288 | static inline void tcg_gen_qemu_ld64(TCGv_i64 ret, TCGv addr, int mem_index) |
c896fe29 | 2289 | { |
a7812ae4 | 2290 | tcg_gen_qemu_ldst_op_i64(INDEX_op_qemu_ld64, ret, addr, mem_index); |
c896fe29 FB |
2291 | } |
2292 | ||
ac56dd48 | 2293 | static inline void tcg_gen_qemu_st8(TCGv arg, TCGv addr, int mem_index) |
c896fe29 | 2294 | { |
a7812ae4 | 2295 | tcg_gen_qemu_ldst_op(INDEX_op_qemu_st8, arg, addr, mem_index); |
c896fe29 FB |
2296 | } |
2297 | ||
ac56dd48 | 2298 | static inline void tcg_gen_qemu_st16(TCGv arg, TCGv addr, int mem_index) |
c896fe29 | 2299 | { |
a7812ae4 | 2300 | tcg_gen_qemu_ldst_op(INDEX_op_qemu_st16, arg, addr, mem_index); |
c896fe29 FB |
2301 | } |
2302 | ||
ac56dd48 | 2303 | static inline void tcg_gen_qemu_st32(TCGv arg, TCGv addr, int mem_index) |
c896fe29 | 2304 | { |
a7812ae4 | 2305 | tcg_gen_qemu_ldst_op(INDEX_op_qemu_st32, arg, addr, mem_index); |
c896fe29 FB |
2306 | } |
2307 | ||
a7812ae4 | 2308 | static inline void tcg_gen_qemu_st64(TCGv_i64 arg, TCGv addr, int mem_index) |
c896fe29 | 2309 | { |
a7812ae4 | 2310 | tcg_gen_qemu_ldst_op_i64(INDEX_op_qemu_st64, arg, addr, mem_index); |
c896fe29 FB |
2311 | } |
2312 | ||
56b8f567 | 2313 | #define tcg_gen_ld_ptr tcg_gen_ld_i64 |
a768e4b2 | 2314 | #define tcg_gen_discard_ptr tcg_gen_discard_i64 |
f8422f52 | 2315 | |
c896fe29 | 2316 | #endif /* TCG_TARGET_REG_BITS != 32 */ |
f8422f52 BS |
2317 | |
2318 | #if TARGET_LONG_BITS == 64 | |
f8422f52 BS |
2319 | #define tcg_gen_movi_tl tcg_gen_movi_i64 |
2320 | #define tcg_gen_mov_tl tcg_gen_mov_i64 | |
2321 | #define tcg_gen_ld8u_tl tcg_gen_ld8u_i64 | |
2322 | #define tcg_gen_ld8s_tl tcg_gen_ld8s_i64 | |
2323 | #define tcg_gen_ld16u_tl tcg_gen_ld16u_i64 | |
2324 | #define tcg_gen_ld16s_tl tcg_gen_ld16s_i64 | |
2325 | #define tcg_gen_ld32u_tl tcg_gen_ld32u_i64 | |
2326 | #define tcg_gen_ld32s_tl tcg_gen_ld32s_i64 | |
2327 | #define tcg_gen_ld_tl tcg_gen_ld_i64 | |
2328 | #define tcg_gen_st8_tl tcg_gen_st8_i64 | |
2329 | #define tcg_gen_st16_tl tcg_gen_st16_i64 | |
2330 | #define tcg_gen_st32_tl tcg_gen_st32_i64 | |
2331 | #define tcg_gen_st_tl tcg_gen_st_i64 | |
2332 | #define tcg_gen_add_tl tcg_gen_add_i64 | |
2333 | #define tcg_gen_addi_tl tcg_gen_addi_i64 | |
2334 | #define tcg_gen_sub_tl tcg_gen_sub_i64 | |
390efc54 | 2335 | #define tcg_gen_neg_tl tcg_gen_neg_i64 |
10460c8a | 2336 | #define tcg_gen_subfi_tl tcg_gen_subfi_i64 |
f8422f52 BS |
2337 | #define tcg_gen_subi_tl tcg_gen_subi_i64 |
2338 | #define tcg_gen_and_tl tcg_gen_and_i64 | |
2339 | #define tcg_gen_andi_tl tcg_gen_andi_i64 | |
2340 | #define tcg_gen_or_tl tcg_gen_or_i64 | |
2341 | #define tcg_gen_ori_tl tcg_gen_ori_i64 | |
2342 | #define tcg_gen_xor_tl tcg_gen_xor_i64 | |
2343 | #define tcg_gen_xori_tl tcg_gen_xori_i64 | |
0b6ce4cf | 2344 | #define tcg_gen_not_tl tcg_gen_not_i64 |
f8422f52 BS |
2345 | #define tcg_gen_shl_tl tcg_gen_shl_i64 |
2346 | #define tcg_gen_shli_tl tcg_gen_shli_i64 | |
2347 | #define tcg_gen_shr_tl tcg_gen_shr_i64 | |
2348 | #define tcg_gen_shri_tl tcg_gen_shri_i64 | |
2349 | #define tcg_gen_sar_tl tcg_gen_sar_i64 | |
2350 | #define tcg_gen_sari_tl tcg_gen_sari_i64 | |
0cf767d6 | 2351 | #define tcg_gen_brcond_tl tcg_gen_brcond_i64 |
cb63669a | 2352 | #define tcg_gen_brcondi_tl tcg_gen_brcondi_i64 |
be210acb | 2353 | #define tcg_gen_setcond_tl tcg_gen_setcond_i64 |
add1e7ea | 2354 | #define tcg_gen_setcondi_tl tcg_gen_setcondi_i64 |
f730fd27 TS |
2355 | #define tcg_gen_mul_tl tcg_gen_mul_i64 |
2356 | #define tcg_gen_muli_tl tcg_gen_muli_i64 | |
ab36421e AJ |
2357 | #define tcg_gen_div_tl tcg_gen_div_i64 |
2358 | #define tcg_gen_rem_tl tcg_gen_rem_i64 | |
864951af AJ |
2359 | #define tcg_gen_divu_tl tcg_gen_divu_i64 |
2360 | #define tcg_gen_remu_tl tcg_gen_remu_i64 | |
a768e4b2 | 2361 | #define tcg_gen_discard_tl tcg_gen_discard_i64 |
e429073d BS |
2362 | #define tcg_gen_trunc_tl_i32 tcg_gen_trunc_i64_i32 |
2363 | #define tcg_gen_trunc_i64_tl tcg_gen_mov_i64 | |
2364 | #define tcg_gen_extu_i32_tl tcg_gen_extu_i32_i64 | |
2365 | #define tcg_gen_ext_i32_tl tcg_gen_ext_i32_i64 | |
2366 | #define tcg_gen_extu_tl_i64 tcg_gen_mov_i64 | |
2367 | #define tcg_gen_ext_tl_i64 tcg_gen_mov_i64 | |
0b6ce4cf FB |
2368 | #define tcg_gen_ext8u_tl tcg_gen_ext8u_i64 |
2369 | #define tcg_gen_ext8s_tl tcg_gen_ext8s_i64 | |
2370 | #define tcg_gen_ext16u_tl tcg_gen_ext16u_i64 | |
2371 | #define tcg_gen_ext16s_tl tcg_gen_ext16s_i64 | |
2372 | #define tcg_gen_ext32u_tl tcg_gen_ext32u_i64 | |
2373 | #define tcg_gen_ext32s_tl tcg_gen_ext32s_i64 | |
911d79ba AJ |
2374 | #define tcg_gen_bswap16_tl tcg_gen_bswap16_i64 |
2375 | #define tcg_gen_bswap32_tl tcg_gen_bswap32_i64 | |
2376 | #define tcg_gen_bswap64_tl tcg_gen_bswap64_i64 | |
945ca823 | 2377 | #define tcg_gen_concat_tl_i64 tcg_gen_concat32_i64 |
f24cb33e AJ |
2378 | #define tcg_gen_andc_tl tcg_gen_andc_i64 |
2379 | #define tcg_gen_eqv_tl tcg_gen_eqv_i64 | |
2380 | #define tcg_gen_nand_tl tcg_gen_nand_i64 | |
2381 | #define tcg_gen_nor_tl tcg_gen_nor_i64 | |
2382 | #define tcg_gen_orc_tl tcg_gen_orc_i64 | |
15824571 AJ |
2383 | #define tcg_gen_rotl_tl tcg_gen_rotl_i64 |
2384 | #define tcg_gen_rotli_tl tcg_gen_rotli_i64 | |
2385 | #define tcg_gen_rotr_tl tcg_gen_rotr_i64 | |
2386 | #define tcg_gen_rotri_tl tcg_gen_rotri_i64 | |
a98824ac | 2387 | #define tcg_const_tl tcg_const_i64 |
bdffd4a9 | 2388 | #define tcg_const_local_tl tcg_const_local_i64 |
f8422f52 | 2389 | #else |
f8422f52 BS |
2390 | #define tcg_gen_movi_tl tcg_gen_movi_i32 |
2391 | #define tcg_gen_mov_tl tcg_gen_mov_i32 | |
2392 | #define tcg_gen_ld8u_tl tcg_gen_ld8u_i32 | |
2393 | #define tcg_gen_ld8s_tl tcg_gen_ld8s_i32 | |
2394 | #define tcg_gen_ld16u_tl tcg_gen_ld16u_i32 | |
2395 | #define tcg_gen_ld16s_tl tcg_gen_ld16s_i32 | |
2396 | #define tcg_gen_ld32u_tl tcg_gen_ld_i32 | |
2397 | #define tcg_gen_ld32s_tl tcg_gen_ld_i32 | |
2398 | #define tcg_gen_ld_tl tcg_gen_ld_i32 | |
2399 | #define tcg_gen_st8_tl tcg_gen_st8_i32 | |
2400 | #define tcg_gen_st16_tl tcg_gen_st16_i32 | |
2401 | #define tcg_gen_st32_tl tcg_gen_st_i32 | |
2402 | #define tcg_gen_st_tl tcg_gen_st_i32 | |
2403 | #define tcg_gen_add_tl tcg_gen_add_i32 | |
2404 | #define tcg_gen_addi_tl tcg_gen_addi_i32 | |
2405 | #define tcg_gen_sub_tl tcg_gen_sub_i32 | |
390efc54 | 2406 | #define tcg_gen_neg_tl tcg_gen_neg_i32 |
0045734a | 2407 | #define tcg_gen_subfi_tl tcg_gen_subfi_i32 |
f8422f52 BS |
2408 | #define tcg_gen_subi_tl tcg_gen_subi_i32 |
2409 | #define tcg_gen_and_tl tcg_gen_and_i32 | |
2410 | #define tcg_gen_andi_tl tcg_gen_andi_i32 | |
2411 | #define tcg_gen_or_tl tcg_gen_or_i32 | |
2412 | #define tcg_gen_ori_tl tcg_gen_ori_i32 | |
2413 | #define tcg_gen_xor_tl tcg_gen_xor_i32 | |
2414 | #define tcg_gen_xori_tl tcg_gen_xori_i32 | |
0b6ce4cf | 2415 | #define tcg_gen_not_tl tcg_gen_not_i32 |
f8422f52 BS |
2416 | #define tcg_gen_shl_tl tcg_gen_shl_i32 |
2417 | #define tcg_gen_shli_tl tcg_gen_shli_i32 | |
2418 | #define tcg_gen_shr_tl tcg_gen_shr_i32 | |
2419 | #define tcg_gen_shri_tl tcg_gen_shri_i32 | |
2420 | #define tcg_gen_sar_tl tcg_gen_sar_i32 | |
2421 | #define tcg_gen_sari_tl tcg_gen_sari_i32 | |
0cf767d6 | 2422 | #define tcg_gen_brcond_tl tcg_gen_brcond_i32 |
cb63669a | 2423 | #define tcg_gen_brcondi_tl tcg_gen_brcondi_i32 |
be210acb | 2424 | #define tcg_gen_setcond_tl tcg_gen_setcond_i32 |
add1e7ea | 2425 | #define tcg_gen_setcondi_tl tcg_gen_setcondi_i32 |
f730fd27 TS |
2426 | #define tcg_gen_mul_tl tcg_gen_mul_i32 |
2427 | #define tcg_gen_muli_tl tcg_gen_muli_i32 | |
ab36421e AJ |
2428 | #define tcg_gen_div_tl tcg_gen_div_i32 |
2429 | #define tcg_gen_rem_tl tcg_gen_rem_i32 | |
864951af AJ |
2430 | #define tcg_gen_divu_tl tcg_gen_divu_i32 |
2431 | #define tcg_gen_remu_tl tcg_gen_remu_i32 | |
a768e4b2 | 2432 | #define tcg_gen_discard_tl tcg_gen_discard_i32 |
e429073d BS |
2433 | #define tcg_gen_trunc_tl_i32 tcg_gen_mov_i32 |
2434 | #define tcg_gen_trunc_i64_tl tcg_gen_trunc_i64_i32 | |
2435 | #define tcg_gen_extu_i32_tl tcg_gen_mov_i32 | |
2436 | #define tcg_gen_ext_i32_tl tcg_gen_mov_i32 | |
2437 | #define tcg_gen_extu_tl_i64 tcg_gen_extu_i32_i64 | |
2438 | #define tcg_gen_ext_tl_i64 tcg_gen_ext_i32_i64 | |
0b6ce4cf FB |
2439 | #define tcg_gen_ext8u_tl tcg_gen_ext8u_i32 |
2440 | #define tcg_gen_ext8s_tl tcg_gen_ext8s_i32 | |
2441 | #define tcg_gen_ext16u_tl tcg_gen_ext16u_i32 | |
2442 | #define tcg_gen_ext16s_tl tcg_gen_ext16s_i32 | |
2443 | #define tcg_gen_ext32u_tl tcg_gen_mov_i32 | |
2444 | #define tcg_gen_ext32s_tl tcg_gen_mov_i32 | |
911d79ba AJ |
2445 | #define tcg_gen_bswap16_tl tcg_gen_bswap16_i32 |
2446 | #define tcg_gen_bswap32_tl tcg_gen_bswap32_i32 | |
945ca823 | 2447 | #define tcg_gen_concat_tl_i64 tcg_gen_concat_i32_i64 |
f24cb33e AJ |
2448 | #define tcg_gen_andc_tl tcg_gen_andc_i32 |
2449 | #define tcg_gen_eqv_tl tcg_gen_eqv_i32 | |
2450 | #define tcg_gen_nand_tl tcg_gen_nand_i32 | |
2451 | #define tcg_gen_nor_tl tcg_gen_nor_i32 | |
2452 | #define tcg_gen_orc_tl tcg_gen_orc_i32 | |
15824571 AJ |
2453 | #define tcg_gen_rotl_tl tcg_gen_rotl_i32 |
2454 | #define tcg_gen_rotli_tl tcg_gen_rotli_i32 | |
2455 | #define tcg_gen_rotr_tl tcg_gen_rotr_i32 | |
2456 | #define tcg_gen_rotri_tl tcg_gen_rotri_i32 | |
a98824ac | 2457 | #define tcg_const_tl tcg_const_i32 |
bdffd4a9 | 2458 | #define tcg_const_local_tl tcg_const_local_i32 |
f8422f52 | 2459 | #endif |
6ddbc6e4 PB |
2460 | |
2461 | #if TCG_TARGET_REG_BITS == 32 | |
48d38ca5 | 2462 | #define tcg_gen_add_ptr tcg_gen_add_i32 |
6ddbc6e4 | 2463 | #define tcg_gen_addi_ptr tcg_gen_addi_i32 |
48d38ca5 | 2464 | #define tcg_gen_ext_i32_ptr tcg_gen_mov_i32 |
6ddbc6e4 | 2465 | #else /* TCG_TARGET_REG_BITS == 32 */ |
48d38ca5 | 2466 | #define tcg_gen_add_ptr tcg_gen_add_i64 |
6ddbc6e4 | 2467 | #define tcg_gen_addi_ptr tcg_gen_addi_i64 |
48d38ca5 | 2468 | #define tcg_gen_ext_i32_ptr tcg_gen_ext_i32_i64 |
6ddbc6e4 | 2469 | #endif /* TCG_TARGET_REG_BITS != 32 */ |