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c896fe29 FB |
1 | /* |
2 | * Tiny Code Generator for QEMU | |
3 | * | |
4 | * Copyright (c) 2008 Fabrice Bellard | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
24 | #include "tcg.h" | |
25 | ||
c896fe29 FB |
26 | int gen_new_label(void); |
27 | ||
a7812ae4 | 28 | static inline void tcg_gen_op1_i32(int opc, TCGv_i32 arg1) |
c896fe29 FB |
29 | { |
30 | *gen_opc_ptr++ = opc; | |
a7812ae4 PB |
31 | *gen_opparam_ptr++ = GET_TCGV_I32(arg1); |
32 | } | |
33 | ||
34 | static inline void tcg_gen_op1_i64(int opc, TCGv_i64 arg1) | |
35 | { | |
36 | *gen_opc_ptr++ = opc; | |
37 | *gen_opparam_ptr++ = GET_TCGV_I64(arg1); | |
c896fe29 FB |
38 | } |
39 | ||
ac56dd48 | 40 | static inline void tcg_gen_op1i(int opc, TCGArg arg1) |
c896fe29 FB |
41 | { |
42 | *gen_opc_ptr++ = opc; | |
43 | *gen_opparam_ptr++ = arg1; | |
c896fe29 FB |
44 | } |
45 | ||
a7812ae4 PB |
46 | static inline void tcg_gen_op2_i32(int opc, TCGv_i32 arg1, TCGv_i32 arg2) |
47 | { | |
48 | *gen_opc_ptr++ = opc; | |
49 | *gen_opparam_ptr++ = GET_TCGV_I32(arg1); | |
50 | *gen_opparam_ptr++ = GET_TCGV_I32(arg2); | |
51 | } | |
52 | ||
53 | static inline void tcg_gen_op2_i64(int opc, TCGv_i64 arg1, TCGv_i64 arg2) | |
54 | { | |
55 | *gen_opc_ptr++ = opc; | |
56 | *gen_opparam_ptr++ = GET_TCGV_I64(arg1); | |
57 | *gen_opparam_ptr++ = GET_TCGV_I64(arg2); | |
58 | } | |
59 | ||
60 | static inline void tcg_gen_op2i_i32(int opc, TCGv_i32 arg1, TCGArg arg2) | |
c896fe29 FB |
61 | { |
62 | *gen_opc_ptr++ = opc; | |
a7812ae4 PB |
63 | *gen_opparam_ptr++ = GET_TCGV_I32(arg1); |
64 | *gen_opparam_ptr++ = arg2; | |
c896fe29 FB |
65 | } |
66 | ||
a7812ae4 | 67 | static inline void tcg_gen_op2i_i64(int opc, TCGv_i64 arg1, TCGArg arg2) |
c896fe29 FB |
68 | { |
69 | *gen_opc_ptr++ = opc; | |
a7812ae4 | 70 | *gen_opparam_ptr++ = GET_TCGV_I64(arg1); |
c896fe29 | 71 | *gen_opparam_ptr++ = arg2; |
ac56dd48 PB |
72 | } |
73 | ||
bcb0126f PB |
74 | static inline void tcg_gen_op2ii(int opc, TCGArg arg1, TCGArg arg2) |
75 | { | |
76 | *gen_opc_ptr++ = opc; | |
77 | *gen_opparam_ptr++ = arg1; | |
78 | *gen_opparam_ptr++ = arg2; | |
79 | } | |
80 | ||
a7812ae4 PB |
81 | static inline void tcg_gen_op3_i32(int opc, TCGv_i32 arg1, TCGv_i32 arg2, |
82 | TCGv_i32 arg3) | |
83 | { | |
84 | *gen_opc_ptr++ = opc; | |
85 | *gen_opparam_ptr++ = GET_TCGV_I32(arg1); | |
86 | *gen_opparam_ptr++ = GET_TCGV_I32(arg2); | |
87 | *gen_opparam_ptr++ = GET_TCGV_I32(arg3); | |
88 | } | |
89 | ||
90 | static inline void tcg_gen_op3_i64(int opc, TCGv_i64 arg1, TCGv_i64 arg2, | |
91 | TCGv_i64 arg3) | |
92 | { | |
93 | *gen_opc_ptr++ = opc; | |
94 | *gen_opparam_ptr++ = GET_TCGV_I64(arg1); | |
95 | *gen_opparam_ptr++ = GET_TCGV_I64(arg2); | |
96 | *gen_opparam_ptr++ = GET_TCGV_I64(arg3); | |
97 | } | |
98 | ||
99 | static inline void tcg_gen_op3i_i32(int opc, TCGv_i32 arg1, TCGv_i32 arg2, | |
100 | TCGArg arg3) | |
ac56dd48 PB |
101 | { |
102 | *gen_opc_ptr++ = opc; | |
a7812ae4 PB |
103 | *gen_opparam_ptr++ = GET_TCGV_I32(arg1); |
104 | *gen_opparam_ptr++ = GET_TCGV_I32(arg2); | |
105 | *gen_opparam_ptr++ = arg3; | |
ac56dd48 PB |
106 | } |
107 | ||
a7812ae4 PB |
108 | static inline void tcg_gen_op3i_i64(int opc, TCGv_i64 arg1, TCGv_i64 arg2, |
109 | TCGArg arg3) | |
ac56dd48 PB |
110 | { |
111 | *gen_opc_ptr++ = opc; | |
a7812ae4 PB |
112 | *gen_opparam_ptr++ = GET_TCGV_I64(arg1); |
113 | *gen_opparam_ptr++ = GET_TCGV_I64(arg2); | |
c896fe29 | 114 | *gen_opparam_ptr++ = arg3; |
ac56dd48 PB |
115 | } |
116 | ||
a7812ae4 PB |
117 | static inline void tcg_gen_ldst_op_i32(int opc, TCGv_i32 val, TCGv_ptr base, |
118 | TCGArg offset) | |
119 | { | |
120 | *gen_opc_ptr++ = opc; | |
121 | *gen_opparam_ptr++ = GET_TCGV_I32(val); | |
122 | *gen_opparam_ptr++ = GET_TCGV_PTR(base); | |
123 | *gen_opparam_ptr++ = offset; | |
124 | } | |
125 | ||
126 | static inline void tcg_gen_ldst_op_i64(int opc, TCGv_i64 val, TCGv_ptr base, | |
127 | TCGArg offset) | |
128 | { | |
129 | *gen_opc_ptr++ = opc; | |
a810a2de | 130 | *gen_opparam_ptr++ = GET_TCGV_I64(val); |
a7812ae4 PB |
131 | *gen_opparam_ptr++ = GET_TCGV_PTR(base); |
132 | *gen_opparam_ptr++ = offset; | |
133 | } | |
134 | ||
135 | static inline void tcg_gen_qemu_ldst_op_i64_i32(int opc, TCGv_i64 val, TCGv_i32 addr, | |
136 | TCGArg mem_index) | |
137 | { | |
138 | *gen_opc_ptr++ = opc; | |
139 | *gen_opparam_ptr++ = GET_TCGV_I64(val); | |
140 | *gen_opparam_ptr++ = GET_TCGV_I32(addr); | |
141 | *gen_opparam_ptr++ = mem_index; | |
142 | } | |
143 | ||
144 | static inline void tcg_gen_qemu_ldst_op_i64_i64(int opc, TCGv_i64 val, TCGv_i64 addr, | |
145 | TCGArg mem_index) | |
146 | { | |
147 | *gen_opc_ptr++ = opc; | |
148 | *gen_opparam_ptr++ = GET_TCGV_I64(val); | |
149 | *gen_opparam_ptr++ = GET_TCGV_I64(addr); | |
150 | *gen_opparam_ptr++ = mem_index; | |
151 | } | |
152 | ||
153 | static inline void tcg_gen_op4_i32(int opc, TCGv_i32 arg1, TCGv_i32 arg2, | |
154 | TCGv_i32 arg3, TCGv_i32 arg4) | |
155 | { | |
156 | *gen_opc_ptr++ = opc; | |
157 | *gen_opparam_ptr++ = GET_TCGV_I32(arg1); | |
158 | *gen_opparam_ptr++ = GET_TCGV_I32(arg2); | |
159 | *gen_opparam_ptr++ = GET_TCGV_I32(arg3); | |
160 | *gen_opparam_ptr++ = GET_TCGV_I32(arg4); | |
161 | } | |
162 | ||
163 | static inline void tcg_gen_op4_i64(int opc, TCGv_i64 arg1, TCGv_i64 arg2, | |
a810a2de | 164 | TCGv_i64 arg3, TCGv_i64 arg4) |
a7812ae4 PB |
165 | { |
166 | *gen_opc_ptr++ = opc; | |
167 | *gen_opparam_ptr++ = GET_TCGV_I64(arg1); | |
168 | *gen_opparam_ptr++ = GET_TCGV_I64(arg2); | |
169 | *gen_opparam_ptr++ = GET_TCGV_I64(arg3); | |
170 | *gen_opparam_ptr++ = GET_TCGV_I64(arg4); | |
171 | } | |
172 | ||
173 | static inline void tcg_gen_op4i_i32(int opc, TCGv_i32 arg1, TCGv_i32 arg2, | |
174 | TCGv_i32 arg3, TCGArg arg4) | |
175 | { | |
176 | *gen_opc_ptr++ = opc; | |
177 | *gen_opparam_ptr++ = GET_TCGV_I32(arg1); | |
178 | *gen_opparam_ptr++ = GET_TCGV_I32(arg2); | |
179 | *gen_opparam_ptr++ = GET_TCGV_I32(arg3); | |
180 | *gen_opparam_ptr++ = arg4; | |
181 | } | |
182 | ||
183 | static inline void tcg_gen_op4i_i64(int opc, TCGv_i64 arg1, TCGv_i64 arg2, | |
184 | TCGv_i64 arg3, TCGArg arg4) | |
ac56dd48 PB |
185 | { |
186 | *gen_opc_ptr++ = opc; | |
a7812ae4 PB |
187 | *gen_opparam_ptr++ = GET_TCGV_I64(arg1); |
188 | *gen_opparam_ptr++ = GET_TCGV_I64(arg2); | |
189 | *gen_opparam_ptr++ = GET_TCGV_I64(arg3); | |
190 | *gen_opparam_ptr++ = arg4; | |
ac56dd48 PB |
191 | } |
192 | ||
a7812ae4 PB |
193 | static inline void tcg_gen_op4ii_i32(int opc, TCGv_i32 arg1, TCGv_i32 arg2, |
194 | TCGArg arg3, TCGArg arg4) | |
ac56dd48 PB |
195 | { |
196 | *gen_opc_ptr++ = opc; | |
a7812ae4 PB |
197 | *gen_opparam_ptr++ = GET_TCGV_I32(arg1); |
198 | *gen_opparam_ptr++ = GET_TCGV_I32(arg2); | |
199 | *gen_opparam_ptr++ = arg3; | |
c896fe29 FB |
200 | *gen_opparam_ptr++ = arg4; |
201 | } | |
202 | ||
a7812ae4 PB |
203 | static inline void tcg_gen_op4ii_i64(int opc, TCGv_i64 arg1, TCGv_i64 arg2, |
204 | TCGArg arg3, TCGArg arg4) | |
c896fe29 FB |
205 | { |
206 | *gen_opc_ptr++ = opc; | |
a7812ae4 PB |
207 | *gen_opparam_ptr++ = GET_TCGV_I64(arg1); |
208 | *gen_opparam_ptr++ = GET_TCGV_I64(arg2); | |
c896fe29 FB |
209 | *gen_opparam_ptr++ = arg3; |
210 | *gen_opparam_ptr++ = arg4; | |
ac56dd48 PB |
211 | } |
212 | ||
a7812ae4 PB |
213 | static inline void tcg_gen_op5_i32(int opc, TCGv_i32 arg1, TCGv_i32 arg2, |
214 | TCGv_i32 arg3, TCGv_i32 arg4, TCGv_i32 arg5) | |
215 | { | |
216 | *gen_opc_ptr++ = opc; | |
217 | *gen_opparam_ptr++ = GET_TCGV_I32(arg1); | |
218 | *gen_opparam_ptr++ = GET_TCGV_I32(arg2); | |
219 | *gen_opparam_ptr++ = GET_TCGV_I32(arg3); | |
220 | *gen_opparam_ptr++ = GET_TCGV_I32(arg4); | |
221 | *gen_opparam_ptr++ = GET_TCGV_I32(arg5); | |
222 | } | |
223 | ||
224 | static inline void tcg_gen_op5_i64(int opc, TCGv_i64 arg1, TCGv_i64 arg2, | |
225 | TCGv_i64 arg3, TCGv_i64 arg4, TCGv_i64 arg5) | |
226 | { | |
227 | *gen_opc_ptr++ = opc; | |
228 | *gen_opparam_ptr++ = GET_TCGV_I64(arg1); | |
229 | *gen_opparam_ptr++ = GET_TCGV_I64(arg2); | |
230 | *gen_opparam_ptr++ = GET_TCGV_I64(arg3); | |
231 | *gen_opparam_ptr++ = GET_TCGV_I64(arg4); | |
232 | *gen_opparam_ptr++ = GET_TCGV_I64(arg5); | |
233 | } | |
234 | ||
235 | static inline void tcg_gen_op5i_i32(int opc, TCGv_i32 arg1, TCGv_i32 arg2, | |
236 | TCGv_i32 arg3, TCGv_i32 arg4, TCGArg arg5) | |
ac56dd48 PB |
237 | { |
238 | *gen_opc_ptr++ = opc; | |
a7812ae4 PB |
239 | *gen_opparam_ptr++ = GET_TCGV_I32(arg1); |
240 | *gen_opparam_ptr++ = GET_TCGV_I32(arg2); | |
241 | *gen_opparam_ptr++ = GET_TCGV_I32(arg3); | |
242 | *gen_opparam_ptr++ = GET_TCGV_I32(arg4); | |
243 | *gen_opparam_ptr++ = arg5; | |
ac56dd48 PB |
244 | } |
245 | ||
a7812ae4 PB |
246 | static inline void tcg_gen_op5i_i64(int opc, TCGv_i64 arg1, TCGv_i64 arg2, |
247 | TCGv_i64 arg3, TCGv_i64 arg4, TCGArg arg5) | |
ac56dd48 PB |
248 | { |
249 | *gen_opc_ptr++ = opc; | |
a7812ae4 PB |
250 | *gen_opparam_ptr++ = GET_TCGV_I64(arg1); |
251 | *gen_opparam_ptr++ = GET_TCGV_I64(arg2); | |
252 | *gen_opparam_ptr++ = GET_TCGV_I64(arg3); | |
253 | *gen_opparam_ptr++ = GET_TCGV_I64(arg4); | |
c896fe29 FB |
254 | *gen_opparam_ptr++ = arg5; |
255 | } | |
256 | ||
a7812ae4 PB |
257 | static inline void tcg_gen_op6_i32(int opc, TCGv_i32 arg1, TCGv_i32 arg2, |
258 | TCGv_i32 arg3, TCGv_i32 arg4, TCGv_i32 arg5, | |
259 | TCGv_i32 arg6) | |
260 | { | |
261 | *gen_opc_ptr++ = opc; | |
262 | *gen_opparam_ptr++ = GET_TCGV_I32(arg1); | |
263 | *gen_opparam_ptr++ = GET_TCGV_I32(arg2); | |
264 | *gen_opparam_ptr++ = GET_TCGV_I32(arg3); | |
265 | *gen_opparam_ptr++ = GET_TCGV_I32(arg4); | |
266 | *gen_opparam_ptr++ = GET_TCGV_I32(arg5); | |
267 | *gen_opparam_ptr++ = GET_TCGV_I32(arg6); | |
268 | } | |
269 | ||
270 | static inline void tcg_gen_op6_i64(int opc, TCGv_i64 arg1, TCGv_i64 arg2, | |
271 | TCGv_i64 arg3, TCGv_i64 arg4, TCGv_i64 arg5, | |
272 | TCGv_i64 arg6) | |
c896fe29 FB |
273 | { |
274 | *gen_opc_ptr++ = opc; | |
a7812ae4 PB |
275 | *gen_opparam_ptr++ = GET_TCGV_I64(arg1); |
276 | *gen_opparam_ptr++ = GET_TCGV_I64(arg2); | |
277 | *gen_opparam_ptr++ = GET_TCGV_I64(arg3); | |
278 | *gen_opparam_ptr++ = GET_TCGV_I64(arg4); | |
279 | *gen_opparam_ptr++ = GET_TCGV_I64(arg5); | |
280 | *gen_opparam_ptr++ = GET_TCGV_I64(arg6); | |
ac56dd48 PB |
281 | } |
282 | ||
be210acb RH |
283 | static inline void tcg_gen_op6i_i32(int opc, TCGv_i32 arg1, TCGv_i32 arg2, |
284 | TCGv_i32 arg3, TCGv_i32 arg4, | |
285 | TCGv_i32 arg5, TCGArg arg6) | |
286 | { | |
287 | *gen_opc_ptr++ = opc; | |
288 | *gen_opparam_ptr++ = GET_TCGV_I32(arg1); | |
289 | *gen_opparam_ptr++ = GET_TCGV_I32(arg2); | |
290 | *gen_opparam_ptr++ = GET_TCGV_I32(arg3); | |
291 | *gen_opparam_ptr++ = GET_TCGV_I32(arg4); | |
292 | *gen_opparam_ptr++ = GET_TCGV_I32(arg5); | |
293 | *gen_opparam_ptr++ = arg6; | |
294 | } | |
295 | ||
296 | static inline void tcg_gen_op6i_i64(int opc, TCGv_i64 arg1, TCGv_i64 arg2, | |
297 | TCGv_i64 arg3, TCGv_i64 arg4, | |
298 | TCGv_i64 arg5, TCGArg arg6) | |
299 | { | |
300 | *gen_opc_ptr++ = opc; | |
301 | *gen_opparam_ptr++ = GET_TCGV_I64(arg1); | |
302 | *gen_opparam_ptr++ = GET_TCGV_I64(arg2); | |
303 | *gen_opparam_ptr++ = GET_TCGV_I64(arg3); | |
304 | *gen_opparam_ptr++ = GET_TCGV_I64(arg4); | |
305 | *gen_opparam_ptr++ = GET_TCGV_I64(arg5); | |
306 | *gen_opparam_ptr++ = arg6; | |
307 | } | |
308 | ||
a7812ae4 PB |
309 | static inline void tcg_gen_op6ii_i32(int opc, TCGv_i32 arg1, TCGv_i32 arg2, |
310 | TCGv_i32 arg3, TCGv_i32 arg4, TCGArg arg5, | |
311 | TCGArg arg6) | |
ac56dd48 PB |
312 | { |
313 | *gen_opc_ptr++ = opc; | |
a7812ae4 PB |
314 | *gen_opparam_ptr++ = GET_TCGV_I32(arg1); |
315 | *gen_opparam_ptr++ = GET_TCGV_I32(arg2); | |
316 | *gen_opparam_ptr++ = GET_TCGV_I32(arg3); | |
317 | *gen_opparam_ptr++ = GET_TCGV_I32(arg4); | |
318 | *gen_opparam_ptr++ = arg5; | |
319 | *gen_opparam_ptr++ = arg6; | |
320 | } | |
321 | ||
322 | static inline void tcg_gen_op6ii_i64(int opc, TCGv_i64 arg1, TCGv_i64 arg2, | |
323 | TCGv_i64 arg3, TCGv_i64 arg4, TCGArg arg5, | |
324 | TCGArg arg6) | |
325 | { | |
326 | *gen_opc_ptr++ = opc; | |
327 | *gen_opparam_ptr++ = GET_TCGV_I64(arg1); | |
328 | *gen_opparam_ptr++ = GET_TCGV_I64(arg2); | |
329 | *gen_opparam_ptr++ = GET_TCGV_I64(arg3); | |
330 | *gen_opparam_ptr++ = GET_TCGV_I64(arg4); | |
c896fe29 FB |
331 | *gen_opparam_ptr++ = arg5; |
332 | *gen_opparam_ptr++ = arg6; | |
333 | } | |
334 | ||
335 | static inline void gen_set_label(int n) | |
336 | { | |
ac56dd48 | 337 | tcg_gen_op1i(INDEX_op_set_label, n); |
c896fe29 FB |
338 | } |
339 | ||
fb50d413 BS |
340 | static inline void tcg_gen_br(int label) |
341 | { | |
342 | tcg_gen_op1i(INDEX_op_br, label); | |
343 | } | |
344 | ||
a7812ae4 | 345 | static inline void tcg_gen_mov_i32(TCGv_i32 ret, TCGv_i32 arg) |
c896fe29 | 346 | { |
fe75bcf7 | 347 | if (!TCGV_EQUAL_I32(ret, arg)) |
a7812ae4 | 348 | tcg_gen_op2_i32(INDEX_op_mov_i32, ret, arg); |
c896fe29 FB |
349 | } |
350 | ||
a7812ae4 | 351 | static inline void tcg_gen_movi_i32(TCGv_i32 ret, int32_t arg) |
c896fe29 | 352 | { |
a7812ae4 | 353 | tcg_gen_op2i_i32(INDEX_op_movi_i32, ret, arg); |
c896fe29 FB |
354 | } |
355 | ||
356 | /* helper calls */ | |
a7812ae4 PB |
357 | static inline void tcg_gen_helperN(void *func, int flags, int sizemask, |
358 | TCGArg ret, int nargs, TCGArg *args) | |
359 | { | |
360 | TCGv_ptr fn; | |
361 | fn = tcg_const_ptr((tcg_target_long)func); | |
362 | tcg_gen_callN(&tcg_ctx, fn, flags, sizemask, ret, | |
363 | nargs, args); | |
364 | tcg_temp_free_ptr(fn); | |
365 | } | |
c896fe29 | 366 | |
a7812ae4 PB |
367 | /* FIXME: Should this be pure? */ |
368 | static inline void tcg_gen_helper64(void *func, TCGv_i64 ret, | |
369 | TCGv_i64 a, TCGv_i64 b) | |
c896fe29 | 370 | { |
a7812ae4 PB |
371 | TCGv_ptr fn; |
372 | TCGArg args[2]; | |
373 | fn = tcg_const_ptr((tcg_target_long)func); | |
374 | args[0] = GET_TCGV_I64(a); | |
375 | args[1] = GET_TCGV_I64(b); | |
376 | tcg_gen_callN(&tcg_ctx, fn, 0, 7, GET_TCGV_I64(ret), 2, args); | |
377 | tcg_temp_free_ptr(fn); | |
f8422f52 BS |
378 | } |
379 | ||
c896fe29 FB |
380 | /* 32 bit ops */ |
381 | ||
a7812ae4 | 382 | static inline void tcg_gen_ld8u_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset) |
c896fe29 | 383 | { |
a7812ae4 | 384 | tcg_gen_ldst_op_i32(INDEX_op_ld8u_i32, ret, arg2, offset); |
c896fe29 FB |
385 | } |
386 | ||
a7812ae4 | 387 | static inline void tcg_gen_ld8s_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset) |
c896fe29 | 388 | { |
a7812ae4 | 389 | tcg_gen_ldst_op_i32(INDEX_op_ld8s_i32, ret, arg2, offset); |
c896fe29 FB |
390 | } |
391 | ||
a7812ae4 | 392 | static inline void tcg_gen_ld16u_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset) |
c896fe29 | 393 | { |
a7812ae4 | 394 | tcg_gen_ldst_op_i32(INDEX_op_ld16u_i32, ret, arg2, offset); |
c896fe29 FB |
395 | } |
396 | ||
a7812ae4 | 397 | static inline void tcg_gen_ld16s_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset) |
c896fe29 | 398 | { |
a7812ae4 | 399 | tcg_gen_ldst_op_i32(INDEX_op_ld16s_i32, ret, arg2, offset); |
c896fe29 FB |
400 | } |
401 | ||
a7812ae4 | 402 | static inline void tcg_gen_ld_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset) |
c896fe29 | 403 | { |
a7812ae4 | 404 | tcg_gen_ldst_op_i32(INDEX_op_ld_i32, ret, arg2, offset); |
c896fe29 FB |
405 | } |
406 | ||
a7812ae4 | 407 | static inline void tcg_gen_st8_i32(TCGv_i32 arg1, TCGv_ptr arg2, tcg_target_long offset) |
c896fe29 | 408 | { |
a7812ae4 | 409 | tcg_gen_ldst_op_i32(INDEX_op_st8_i32, arg1, arg2, offset); |
c896fe29 FB |
410 | } |
411 | ||
a7812ae4 | 412 | static inline void tcg_gen_st16_i32(TCGv_i32 arg1, TCGv_ptr arg2, tcg_target_long offset) |
c896fe29 | 413 | { |
a7812ae4 | 414 | tcg_gen_ldst_op_i32(INDEX_op_st16_i32, arg1, arg2, offset); |
c896fe29 FB |
415 | } |
416 | ||
a7812ae4 | 417 | static inline void tcg_gen_st_i32(TCGv_i32 arg1, TCGv_ptr arg2, tcg_target_long offset) |
c896fe29 | 418 | { |
a7812ae4 | 419 | tcg_gen_ldst_op_i32(INDEX_op_st_i32, arg1, arg2, offset); |
c896fe29 FB |
420 | } |
421 | ||
a7812ae4 | 422 | static inline void tcg_gen_add_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
c896fe29 | 423 | { |
a7812ae4 | 424 | tcg_gen_op3_i32(INDEX_op_add_i32, ret, arg1, arg2); |
c896fe29 FB |
425 | } |
426 | ||
a7812ae4 | 427 | static inline void tcg_gen_addi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) |
c896fe29 | 428 | { |
7089442c BS |
429 | /* some cases can be optimized here */ |
430 | if (arg2 == 0) { | |
431 | tcg_gen_mov_i32(ret, arg1); | |
432 | } else { | |
a7812ae4 | 433 | TCGv_i32 t0 = tcg_const_i32(arg2); |
e8996ee0 | 434 | tcg_gen_add_i32(ret, arg1, t0); |
a7812ae4 | 435 | tcg_temp_free_i32(t0); |
7089442c | 436 | } |
c896fe29 FB |
437 | } |
438 | ||
a7812ae4 | 439 | static inline void tcg_gen_sub_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
c896fe29 | 440 | { |
a7812ae4 | 441 | tcg_gen_op3_i32(INDEX_op_sub_i32, ret, arg1, arg2); |
c896fe29 FB |
442 | } |
443 | ||
a7812ae4 | 444 | static inline void tcg_gen_subfi_i32(TCGv_i32 ret, int32_t arg1, TCGv_i32 arg2) |
0045734a | 445 | { |
a7812ae4 | 446 | TCGv_i32 t0 = tcg_const_i32(arg1); |
0045734a | 447 | tcg_gen_sub_i32(ret, t0, arg2); |
a7812ae4 | 448 | tcg_temp_free_i32(t0); |
0045734a AJ |
449 | } |
450 | ||
a7812ae4 | 451 | static inline void tcg_gen_subi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) |
c896fe29 | 452 | { |
7089442c BS |
453 | /* some cases can be optimized here */ |
454 | if (arg2 == 0) { | |
455 | tcg_gen_mov_i32(ret, arg1); | |
456 | } else { | |
a7812ae4 | 457 | TCGv_i32 t0 = tcg_const_i32(arg2); |
e8996ee0 | 458 | tcg_gen_sub_i32(ret, arg1, t0); |
a7812ae4 | 459 | tcg_temp_free_i32(t0); |
7089442c | 460 | } |
c896fe29 FB |
461 | } |
462 | ||
a7812ae4 | 463 | static inline void tcg_gen_and_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
c896fe29 | 464 | { |
7fc81051 AJ |
465 | if (TCGV_EQUAL_I32(arg1, arg2)) { |
466 | tcg_gen_mov_i32(ret, arg1); | |
467 | } else { | |
468 | tcg_gen_op3_i32(INDEX_op_and_i32, ret, arg1, arg2); | |
469 | } | |
c896fe29 FB |
470 | } |
471 | ||
a7812ae4 | 472 | static inline void tcg_gen_andi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) |
c896fe29 FB |
473 | { |
474 | /* some cases can be optimized here */ | |
475 | if (arg2 == 0) { | |
476 | tcg_gen_movi_i32(ret, 0); | |
477 | } else if (arg2 == 0xffffffff) { | |
478 | tcg_gen_mov_i32(ret, arg1); | |
479 | } else { | |
a7812ae4 | 480 | TCGv_i32 t0 = tcg_const_i32(arg2); |
e8996ee0 | 481 | tcg_gen_and_i32(ret, arg1, t0); |
a7812ae4 | 482 | tcg_temp_free_i32(t0); |
c896fe29 FB |
483 | } |
484 | } | |
485 | ||
a7812ae4 | 486 | static inline void tcg_gen_or_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
c896fe29 | 487 | { |
7fc81051 AJ |
488 | if (TCGV_EQUAL_I32(arg1, arg2)) { |
489 | tcg_gen_mov_i32(ret, arg1); | |
490 | } else { | |
491 | tcg_gen_op3_i32(INDEX_op_or_i32, ret, arg1, arg2); | |
492 | } | |
c896fe29 FB |
493 | } |
494 | ||
a7812ae4 | 495 | static inline void tcg_gen_ori_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) |
c896fe29 FB |
496 | { |
497 | /* some cases can be optimized here */ | |
498 | if (arg2 == 0xffffffff) { | |
7089442c | 499 | tcg_gen_movi_i32(ret, 0xffffffff); |
c896fe29 FB |
500 | } else if (arg2 == 0) { |
501 | tcg_gen_mov_i32(ret, arg1); | |
502 | } else { | |
a7812ae4 | 503 | TCGv_i32 t0 = tcg_const_i32(arg2); |
e8996ee0 | 504 | tcg_gen_or_i32(ret, arg1, t0); |
a7812ae4 | 505 | tcg_temp_free_i32(t0); |
c896fe29 FB |
506 | } |
507 | } | |
508 | ||
a7812ae4 | 509 | static inline void tcg_gen_xor_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
c896fe29 | 510 | { |
7fc81051 AJ |
511 | if (TCGV_EQUAL_I32(arg1, arg2)) { |
512 | tcg_gen_movi_i32(ret, 0); | |
513 | } else { | |
514 | tcg_gen_op3_i32(INDEX_op_xor_i32, ret, arg1, arg2); | |
515 | } | |
c896fe29 FB |
516 | } |
517 | ||
a7812ae4 | 518 | static inline void tcg_gen_xori_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) |
c896fe29 FB |
519 | { |
520 | /* some cases can be optimized here */ | |
521 | if (arg2 == 0) { | |
522 | tcg_gen_mov_i32(ret, arg1); | |
523 | } else { | |
a7812ae4 | 524 | TCGv_i32 t0 = tcg_const_i32(arg2); |
e8996ee0 | 525 | tcg_gen_xor_i32(ret, arg1, t0); |
a7812ae4 | 526 | tcg_temp_free_i32(t0); |
c896fe29 FB |
527 | } |
528 | } | |
529 | ||
a7812ae4 | 530 | static inline void tcg_gen_shl_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
c896fe29 | 531 | { |
a7812ae4 | 532 | tcg_gen_op3_i32(INDEX_op_shl_i32, ret, arg1, arg2); |
c896fe29 FB |
533 | } |
534 | ||
a7812ae4 | 535 | static inline void tcg_gen_shli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) |
c896fe29 | 536 | { |
34151a20 FB |
537 | if (arg2 == 0) { |
538 | tcg_gen_mov_i32(ret, arg1); | |
539 | } else { | |
a7812ae4 | 540 | TCGv_i32 t0 = tcg_const_i32(arg2); |
e8996ee0 | 541 | tcg_gen_shl_i32(ret, arg1, t0); |
a7812ae4 | 542 | tcg_temp_free_i32(t0); |
34151a20 | 543 | } |
c896fe29 FB |
544 | } |
545 | ||
a7812ae4 | 546 | static inline void tcg_gen_shr_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
c896fe29 | 547 | { |
a7812ae4 | 548 | tcg_gen_op3_i32(INDEX_op_shr_i32, ret, arg1, arg2); |
c896fe29 FB |
549 | } |
550 | ||
a7812ae4 | 551 | static inline void tcg_gen_shri_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) |
c896fe29 | 552 | { |
34151a20 FB |
553 | if (arg2 == 0) { |
554 | tcg_gen_mov_i32(ret, arg1); | |
555 | } else { | |
a7812ae4 | 556 | TCGv_i32 t0 = tcg_const_i32(arg2); |
e8996ee0 | 557 | tcg_gen_shr_i32(ret, arg1, t0); |
a7812ae4 | 558 | tcg_temp_free_i32(t0); |
34151a20 | 559 | } |
c896fe29 FB |
560 | } |
561 | ||
a7812ae4 | 562 | static inline void tcg_gen_sar_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
c896fe29 | 563 | { |
a7812ae4 | 564 | tcg_gen_op3_i32(INDEX_op_sar_i32, ret, arg1, arg2); |
c896fe29 FB |
565 | } |
566 | ||
a7812ae4 | 567 | static inline void tcg_gen_sari_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) |
c896fe29 | 568 | { |
34151a20 FB |
569 | if (arg2 == 0) { |
570 | tcg_gen_mov_i32(ret, arg1); | |
571 | } else { | |
a7812ae4 | 572 | TCGv_i32 t0 = tcg_const_i32(arg2); |
e8996ee0 | 573 | tcg_gen_sar_i32(ret, arg1, t0); |
a7812ae4 | 574 | tcg_temp_free_i32(t0); |
34151a20 | 575 | } |
c896fe29 FB |
576 | } |
577 | ||
a7812ae4 | 578 | static inline void tcg_gen_brcond_i32(int cond, TCGv_i32 arg1, TCGv_i32 arg2, |
c896fe29 FB |
579 | int label_index) |
580 | { | |
a7812ae4 | 581 | tcg_gen_op4ii_i32(INDEX_op_brcond_i32, arg1, arg2, cond, label_index); |
c896fe29 FB |
582 | } |
583 | ||
a7812ae4 | 584 | static inline void tcg_gen_brcondi_i32(int cond, TCGv_i32 arg1, int32_t arg2, |
cb63669a PB |
585 | int label_index) |
586 | { | |
a7812ae4 | 587 | TCGv_i32 t0 = tcg_const_i32(arg2); |
cb63669a | 588 | tcg_gen_brcond_i32(cond, arg1, t0, label_index); |
a7812ae4 | 589 | tcg_temp_free_i32(t0); |
cb63669a PB |
590 | } |
591 | ||
5105c556 AJ |
592 | static inline void tcg_gen_setcond_i32(int cond, TCGv_i32 ret, |
593 | TCGv_i32 arg1, TCGv_i32 arg2) | |
594 | { | |
595 | tcg_gen_op4i_i32(INDEX_op_setcond_i32, ret, arg1, arg2, cond); | |
596 | } | |
597 | ||
598 | static inline void tcg_gen_setcondi_i32(int cond, TCGv_i32 ret, TCGv_i32 arg1, | |
599 | int32_t arg2) | |
600 | { | |
601 | TCGv_i32 t0 = tcg_const_i32(arg2); | |
602 | tcg_gen_setcond_i32(cond, ret, arg1, t0); | |
603 | tcg_temp_free_i32(t0); | |
604 | } | |
605 | ||
a7812ae4 | 606 | static inline void tcg_gen_mul_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
c896fe29 | 607 | { |
a7812ae4 | 608 | tcg_gen_op3_i32(INDEX_op_mul_i32, ret, arg1, arg2); |
c896fe29 FB |
609 | } |
610 | ||
a7812ae4 | 611 | static inline void tcg_gen_muli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) |
f730fd27 | 612 | { |
a7812ae4 | 613 | TCGv_i32 t0 = tcg_const_i32(arg2); |
e8996ee0 | 614 | tcg_gen_mul_i32(ret, arg1, t0); |
a7812ae4 | 615 | tcg_temp_free_i32(t0); |
f730fd27 TS |
616 | } |
617 | ||
c896fe29 | 618 | #ifdef TCG_TARGET_HAS_div_i32 |
a7812ae4 | 619 | static inline void tcg_gen_div_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
c896fe29 | 620 | { |
a7812ae4 | 621 | tcg_gen_op3_i32(INDEX_op_div_i32, ret, arg1, arg2); |
c896fe29 FB |
622 | } |
623 | ||
a7812ae4 | 624 | static inline void tcg_gen_rem_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
c896fe29 | 625 | { |
a7812ae4 | 626 | tcg_gen_op3_i32(INDEX_op_rem_i32, ret, arg1, arg2); |
c896fe29 FB |
627 | } |
628 | ||
a7812ae4 | 629 | static inline void tcg_gen_divu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
c896fe29 | 630 | { |
a7812ae4 | 631 | tcg_gen_op3_i32(INDEX_op_divu_i32, ret, arg1, arg2); |
c896fe29 FB |
632 | } |
633 | ||
a7812ae4 | 634 | static inline void tcg_gen_remu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
c896fe29 | 635 | { |
a7812ae4 | 636 | tcg_gen_op3_i32(INDEX_op_remu_i32, ret, arg1, arg2); |
c896fe29 FB |
637 | } |
638 | #else | |
a7812ae4 | 639 | static inline void tcg_gen_div_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
c896fe29 | 640 | { |
a7812ae4 PB |
641 | TCGv_i32 t0; |
642 | t0 = tcg_temp_new_i32(); | |
c896fe29 | 643 | tcg_gen_sari_i32(t0, arg1, 31); |
a7812ae4 PB |
644 | tcg_gen_op5_i32(INDEX_op_div2_i32, ret, t0, arg1, t0, arg2); |
645 | tcg_temp_free_i32(t0); | |
c896fe29 FB |
646 | } |
647 | ||
a7812ae4 | 648 | static inline void tcg_gen_rem_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
c896fe29 | 649 | { |
a7812ae4 PB |
650 | TCGv_i32 t0; |
651 | t0 = tcg_temp_new_i32(); | |
c896fe29 | 652 | tcg_gen_sari_i32(t0, arg1, 31); |
a7812ae4 PB |
653 | tcg_gen_op5_i32(INDEX_op_div2_i32, t0, ret, arg1, t0, arg2); |
654 | tcg_temp_free_i32(t0); | |
c896fe29 FB |
655 | } |
656 | ||
a7812ae4 | 657 | static inline void tcg_gen_divu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
c896fe29 | 658 | { |
a7812ae4 PB |
659 | TCGv_i32 t0; |
660 | t0 = tcg_temp_new_i32(); | |
c896fe29 | 661 | tcg_gen_movi_i32(t0, 0); |
a7812ae4 PB |
662 | tcg_gen_op5_i32(INDEX_op_divu2_i32, ret, t0, arg1, t0, arg2); |
663 | tcg_temp_free_i32(t0); | |
c896fe29 FB |
664 | } |
665 | ||
a7812ae4 | 666 | static inline void tcg_gen_remu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
c896fe29 | 667 | { |
a7812ae4 PB |
668 | TCGv_i32 t0; |
669 | t0 = tcg_temp_new_i32(); | |
c896fe29 | 670 | tcg_gen_movi_i32(t0, 0); |
a7812ae4 PB |
671 | tcg_gen_op5_i32(INDEX_op_divu2_i32, t0, ret, arg1, t0, arg2); |
672 | tcg_temp_free_i32(t0); | |
c896fe29 FB |
673 | } |
674 | #endif | |
675 | ||
676 | #if TCG_TARGET_REG_BITS == 32 | |
677 | ||
a7812ae4 | 678 | static inline void tcg_gen_mov_i64(TCGv_i64 ret, TCGv_i64 arg) |
c896fe29 | 679 | { |
fe75bcf7 | 680 | if (!TCGV_EQUAL_I64(ret, arg)) { |
a7812ae4 | 681 | tcg_gen_mov_i32(TCGV_LOW(ret), TCGV_LOW(arg)); |
4d07272d BS |
682 | tcg_gen_mov_i32(TCGV_HIGH(ret), TCGV_HIGH(arg)); |
683 | } | |
c896fe29 FB |
684 | } |
685 | ||
a7812ae4 | 686 | static inline void tcg_gen_movi_i64(TCGv_i64 ret, int64_t arg) |
c896fe29 | 687 | { |
a7812ae4 | 688 | tcg_gen_movi_i32(TCGV_LOW(ret), arg); |
ac56dd48 | 689 | tcg_gen_movi_i32(TCGV_HIGH(ret), arg >> 32); |
c896fe29 FB |
690 | } |
691 | ||
a7812ae4 PB |
692 | static inline void tcg_gen_ld8u_i64(TCGv_i64 ret, TCGv_ptr arg2, |
693 | tcg_target_long offset) | |
c896fe29 | 694 | { |
a7812ae4 | 695 | tcg_gen_ld8u_i32(TCGV_LOW(ret), arg2, offset); |
ac56dd48 | 696 | tcg_gen_movi_i32(TCGV_HIGH(ret), 0); |
c896fe29 FB |
697 | } |
698 | ||
a7812ae4 PB |
699 | static inline void tcg_gen_ld8s_i64(TCGv_i64 ret, TCGv_ptr arg2, |
700 | tcg_target_long offset) | |
c896fe29 | 701 | { |
a7812ae4 PB |
702 | tcg_gen_ld8s_i32(TCGV_LOW(ret), arg2, offset); |
703 | tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_HIGH(ret), 31); | |
c896fe29 FB |
704 | } |
705 | ||
a7812ae4 PB |
706 | static inline void tcg_gen_ld16u_i64(TCGv_i64 ret, TCGv_ptr arg2, |
707 | tcg_target_long offset) | |
c896fe29 | 708 | { |
a747723b | 709 | tcg_gen_ld16u_i32(TCGV_LOW(ret), arg2, offset); |
ac56dd48 | 710 | tcg_gen_movi_i32(TCGV_HIGH(ret), 0); |
c896fe29 FB |
711 | } |
712 | ||
a7812ae4 PB |
713 | static inline void tcg_gen_ld16s_i64(TCGv_i64 ret, TCGv_ptr arg2, |
714 | tcg_target_long offset) | |
c896fe29 | 715 | { |
a7812ae4 PB |
716 | tcg_gen_ld16s_i32(TCGV_LOW(ret), arg2, offset); |
717 | tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31); | |
c896fe29 FB |
718 | } |
719 | ||
a7812ae4 PB |
720 | static inline void tcg_gen_ld32u_i64(TCGv_i64 ret, TCGv_ptr arg2, |
721 | tcg_target_long offset) | |
c896fe29 | 722 | { |
a7812ae4 | 723 | tcg_gen_ld_i32(TCGV_LOW(ret), arg2, offset); |
ac56dd48 | 724 | tcg_gen_movi_i32(TCGV_HIGH(ret), 0); |
c896fe29 FB |
725 | } |
726 | ||
a7812ae4 PB |
727 | static inline void tcg_gen_ld32s_i64(TCGv_i64 ret, TCGv_ptr arg2, |
728 | tcg_target_long offset) | |
c896fe29 | 729 | { |
a7812ae4 PB |
730 | tcg_gen_ld_i32(TCGV_LOW(ret), arg2, offset); |
731 | tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31); | |
c896fe29 FB |
732 | } |
733 | ||
a7812ae4 PB |
734 | static inline void tcg_gen_ld_i64(TCGv_i64 ret, TCGv_ptr arg2, |
735 | tcg_target_long offset) | |
c896fe29 FB |
736 | { |
737 | /* since arg2 and ret have different types, they cannot be the | |
738 | same temporary */ | |
739 | #ifdef TCG_TARGET_WORDS_BIGENDIAN | |
ac56dd48 | 740 | tcg_gen_ld_i32(TCGV_HIGH(ret), arg2, offset); |
a7812ae4 | 741 | tcg_gen_ld_i32(TCGV_LOW(ret), arg2, offset + 4); |
c896fe29 | 742 | #else |
a7812ae4 | 743 | tcg_gen_ld_i32(TCGV_LOW(ret), arg2, offset); |
ac56dd48 | 744 | tcg_gen_ld_i32(TCGV_HIGH(ret), arg2, offset + 4); |
c896fe29 FB |
745 | #endif |
746 | } | |
747 | ||
a7812ae4 PB |
748 | static inline void tcg_gen_st8_i64(TCGv_i64 arg1, TCGv_ptr arg2, |
749 | tcg_target_long offset) | |
c896fe29 | 750 | { |
a7812ae4 | 751 | tcg_gen_st8_i32(TCGV_LOW(arg1), arg2, offset); |
c896fe29 FB |
752 | } |
753 | ||
a7812ae4 PB |
754 | static inline void tcg_gen_st16_i64(TCGv_i64 arg1, TCGv_ptr arg2, |
755 | tcg_target_long offset) | |
c896fe29 | 756 | { |
a7812ae4 | 757 | tcg_gen_st16_i32(TCGV_LOW(arg1), arg2, offset); |
c896fe29 FB |
758 | } |
759 | ||
a7812ae4 PB |
760 | static inline void tcg_gen_st32_i64(TCGv_i64 arg1, TCGv_ptr arg2, |
761 | tcg_target_long offset) | |
c896fe29 | 762 | { |
a7812ae4 | 763 | tcg_gen_st_i32(TCGV_LOW(arg1), arg2, offset); |
c896fe29 FB |
764 | } |
765 | ||
a7812ae4 PB |
766 | static inline void tcg_gen_st_i64(TCGv_i64 arg1, TCGv_ptr arg2, |
767 | tcg_target_long offset) | |
c896fe29 FB |
768 | { |
769 | #ifdef TCG_TARGET_WORDS_BIGENDIAN | |
ac56dd48 | 770 | tcg_gen_st_i32(TCGV_HIGH(arg1), arg2, offset); |
a7812ae4 | 771 | tcg_gen_st_i32(TCGV_LOW(arg1), arg2, offset + 4); |
c896fe29 | 772 | #else |
a7812ae4 | 773 | tcg_gen_st_i32(TCGV_LOW(arg1), arg2, offset); |
ac56dd48 | 774 | tcg_gen_st_i32(TCGV_HIGH(arg1), arg2, offset + 4); |
c896fe29 FB |
775 | #endif |
776 | } | |
777 | ||
a7812ae4 | 778 | static inline void tcg_gen_add_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
c896fe29 | 779 | { |
a7812ae4 PB |
780 | tcg_gen_op6_i32(INDEX_op_add2_i32, TCGV_LOW(ret), TCGV_HIGH(ret), |
781 | TCGV_LOW(arg1), TCGV_HIGH(arg1), TCGV_LOW(arg2), | |
782 | TCGV_HIGH(arg2)); | |
c896fe29 FB |
783 | } |
784 | ||
a7812ae4 | 785 | static inline void tcg_gen_sub_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
c896fe29 | 786 | { |
a7812ae4 PB |
787 | tcg_gen_op6_i32(INDEX_op_sub2_i32, TCGV_LOW(ret), TCGV_HIGH(ret), |
788 | TCGV_LOW(arg1), TCGV_HIGH(arg1), TCGV_LOW(arg2), | |
789 | TCGV_HIGH(arg2)); | |
c896fe29 FB |
790 | } |
791 | ||
a7812ae4 | 792 | static inline void tcg_gen_and_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
c896fe29 | 793 | { |
a7812ae4 | 794 | tcg_gen_and_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2)); |
ac56dd48 | 795 | tcg_gen_and_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2)); |
c896fe29 FB |
796 | } |
797 | ||
a7812ae4 | 798 | static inline void tcg_gen_andi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
c896fe29 | 799 | { |
e5105083 AJ |
800 | tcg_gen_andi_i32(TCGV_LOW(ret), TCGV_LOW(arg1), arg2); |
801 | tcg_gen_andi_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), arg2 >> 32); | |
c896fe29 FB |
802 | } |
803 | ||
a7812ae4 | 804 | static inline void tcg_gen_or_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
c896fe29 | 805 | { |
e5105083 AJ |
806 | tcg_gen_or_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2)); |
807 | tcg_gen_or_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2)); | |
c896fe29 FB |
808 | } |
809 | ||
a7812ae4 | 810 | static inline void tcg_gen_ori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
c896fe29 | 811 | { |
a7812ae4 | 812 | tcg_gen_ori_i32(TCGV_LOW(ret), TCGV_LOW(arg1), arg2); |
ac56dd48 | 813 | tcg_gen_ori_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), arg2 >> 32); |
c896fe29 FB |
814 | } |
815 | ||
a7812ae4 | 816 | static inline void tcg_gen_xor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
c896fe29 | 817 | { |
e5105083 AJ |
818 | tcg_gen_xor_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2)); |
819 | tcg_gen_xor_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2)); | |
c896fe29 FB |
820 | } |
821 | ||
a7812ae4 | 822 | static inline void tcg_gen_xori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
c896fe29 | 823 | { |
a7812ae4 | 824 | tcg_gen_xori_i32(TCGV_LOW(ret), TCGV_LOW(arg1), arg2); |
ac56dd48 | 825 | tcg_gen_xori_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), arg2 >> 32); |
c896fe29 FB |
826 | } |
827 | ||
828 | /* XXX: use generic code when basic block handling is OK or CPU | |
829 | specific code (x86) */ | |
a7812ae4 | 830 | static inline void tcg_gen_shl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
c896fe29 | 831 | { |
a7812ae4 | 832 | tcg_gen_helper64(tcg_helper_shl_i64, ret, arg1, arg2); |
c896fe29 FB |
833 | } |
834 | ||
a7812ae4 | 835 | static inline void tcg_gen_shli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
c896fe29 FB |
836 | { |
837 | tcg_gen_shifti_i64(ret, arg1, arg2, 0, 0); | |
838 | } | |
839 | ||
a7812ae4 | 840 | static inline void tcg_gen_shr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
c896fe29 | 841 | { |
a7812ae4 | 842 | tcg_gen_helper64(tcg_helper_shr_i64, ret, arg1, arg2); |
c896fe29 FB |
843 | } |
844 | ||
a7812ae4 | 845 | static inline void tcg_gen_shri_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
c896fe29 FB |
846 | { |
847 | tcg_gen_shifti_i64(ret, arg1, arg2, 1, 0); | |
848 | } | |
849 | ||
a7812ae4 | 850 | static inline void tcg_gen_sar_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
c896fe29 | 851 | { |
a7812ae4 | 852 | tcg_gen_helper64(tcg_helper_sar_i64, ret, arg1, arg2); |
c896fe29 FB |
853 | } |
854 | ||
a7812ae4 | 855 | static inline void tcg_gen_sari_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
c896fe29 FB |
856 | { |
857 | tcg_gen_shifti_i64(ret, arg1, arg2, 1, 1); | |
858 | } | |
859 | ||
a7812ae4 | 860 | static inline void tcg_gen_brcond_i64(int cond, TCGv_i64 arg1, TCGv_i64 arg2, |
c896fe29 FB |
861 | int label_index) |
862 | { | |
a7812ae4 PB |
863 | tcg_gen_op6ii_i32(INDEX_op_brcond2_i32, |
864 | TCGV_LOW(arg1), TCGV_HIGH(arg1), TCGV_LOW(arg2), | |
865 | TCGV_HIGH(arg2), cond, label_index); | |
c896fe29 FB |
866 | } |
867 | ||
5105c556 AJ |
868 | static inline void tcg_gen_setcond_i64(int cond, TCGv_i64 ret, |
869 | TCGv_i64 arg1, TCGv_i64 arg2) | |
870 | { | |
871 | tcg_gen_op6i_i32(INDEX_op_setcond2_i32, TCGV_LOW(ret), | |
872 | TCGV_LOW(arg1), TCGV_HIGH(arg1), | |
873 | TCGV_LOW(arg2), TCGV_HIGH(arg2), cond); | |
874 | tcg_gen_movi_i32(TCGV_HIGH(ret), 0); | |
875 | } | |
876 | ||
a7812ae4 | 877 | static inline void tcg_gen_mul_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
c896fe29 | 878 | { |
a7812ae4 PB |
879 | TCGv_i64 t0; |
880 | TCGv_i32 t1; | |
c896fe29 | 881 | |
a7812ae4 PB |
882 | t0 = tcg_temp_new_i64(); |
883 | t1 = tcg_temp_new_i32(); | |
884 | ||
885 | tcg_gen_op4_i32(INDEX_op_mulu2_i32, TCGV_LOW(t0), TCGV_HIGH(t0), | |
886 | TCGV_LOW(arg1), TCGV_LOW(arg2)); | |
887 | ||
888 | tcg_gen_mul_i32(t1, TCGV_LOW(arg1), TCGV_HIGH(arg2)); | |
ac56dd48 | 889 | tcg_gen_add_i32(TCGV_HIGH(t0), TCGV_HIGH(t0), t1); |
a7812ae4 | 890 | tcg_gen_mul_i32(t1, TCGV_HIGH(arg1), TCGV_LOW(arg2)); |
ac56dd48 | 891 | tcg_gen_add_i32(TCGV_HIGH(t0), TCGV_HIGH(t0), t1); |
a7812ae4 | 892 | |
c896fe29 | 893 | tcg_gen_mov_i64(ret, t0); |
a7812ae4 PB |
894 | tcg_temp_free_i64(t0); |
895 | tcg_temp_free_i32(t1); | |
c896fe29 FB |
896 | } |
897 | ||
a7812ae4 | 898 | static inline void tcg_gen_div_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
c896fe29 | 899 | { |
a7812ae4 | 900 | tcg_gen_helper64(tcg_helper_div_i64, ret, arg1, arg2); |
c896fe29 FB |
901 | } |
902 | ||
a7812ae4 | 903 | static inline void tcg_gen_rem_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
c896fe29 | 904 | { |
a7812ae4 | 905 | tcg_gen_helper64(tcg_helper_rem_i64, ret, arg1, arg2); |
c896fe29 FB |
906 | } |
907 | ||
a7812ae4 | 908 | static inline void tcg_gen_divu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
c896fe29 | 909 | { |
a7812ae4 | 910 | tcg_gen_helper64(tcg_helper_divu_i64, ret, arg1, arg2); |
c896fe29 FB |
911 | } |
912 | ||
a7812ae4 | 913 | static inline void tcg_gen_remu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
c896fe29 | 914 | { |
a7812ae4 | 915 | tcg_gen_helper64(tcg_helper_remu_i64, ret, arg1, arg2); |
c896fe29 FB |
916 | } |
917 | ||
918 | #else | |
919 | ||
a7812ae4 | 920 | static inline void tcg_gen_mov_i64(TCGv_i64 ret, TCGv_i64 arg) |
c896fe29 | 921 | { |
fe75bcf7 | 922 | if (!TCGV_EQUAL_I64(ret, arg)) |
a7812ae4 | 923 | tcg_gen_op2_i64(INDEX_op_mov_i64, ret, arg); |
c896fe29 FB |
924 | } |
925 | ||
a7812ae4 | 926 | static inline void tcg_gen_movi_i64(TCGv_i64 ret, int64_t arg) |
c896fe29 | 927 | { |
a7812ae4 | 928 | tcg_gen_op2i_i64(INDEX_op_movi_i64, ret, arg); |
c896fe29 FB |
929 | } |
930 | ||
a7812ae4 | 931 | static inline void tcg_gen_ld8u_i64(TCGv_i64 ret, TCGv_i64 arg2, |
ac56dd48 | 932 | tcg_target_long offset) |
c896fe29 | 933 | { |
a7812ae4 | 934 | tcg_gen_ldst_op_i64(INDEX_op_ld8u_i64, ret, arg2, offset); |
c896fe29 FB |
935 | } |
936 | ||
a7812ae4 | 937 | static inline void tcg_gen_ld8s_i64(TCGv_i64 ret, TCGv_i64 arg2, |
ac56dd48 | 938 | tcg_target_long offset) |
c896fe29 | 939 | { |
a7812ae4 | 940 | tcg_gen_ldst_op_i64(INDEX_op_ld8s_i64, ret, arg2, offset); |
c896fe29 FB |
941 | } |
942 | ||
a7812ae4 | 943 | static inline void tcg_gen_ld16u_i64(TCGv_i64 ret, TCGv_i64 arg2, |
ac56dd48 | 944 | tcg_target_long offset) |
c896fe29 | 945 | { |
a7812ae4 | 946 | tcg_gen_ldst_op_i64(INDEX_op_ld16u_i64, ret, arg2, offset); |
c896fe29 FB |
947 | } |
948 | ||
a7812ae4 | 949 | static inline void tcg_gen_ld16s_i64(TCGv_i64 ret, TCGv_i64 arg2, |
ac56dd48 | 950 | tcg_target_long offset) |
c896fe29 | 951 | { |
a7812ae4 | 952 | tcg_gen_ldst_op_i64(INDEX_op_ld16s_i64, ret, arg2, offset); |
c896fe29 FB |
953 | } |
954 | ||
a7812ae4 | 955 | static inline void tcg_gen_ld32u_i64(TCGv_i64 ret, TCGv_i64 arg2, |
ac56dd48 | 956 | tcg_target_long offset) |
c896fe29 | 957 | { |
a7812ae4 | 958 | tcg_gen_ldst_op_i64(INDEX_op_ld32u_i64, ret, arg2, offset); |
c896fe29 FB |
959 | } |
960 | ||
a7812ae4 | 961 | static inline void tcg_gen_ld32s_i64(TCGv_i64 ret, TCGv_i64 arg2, |
ac56dd48 | 962 | tcg_target_long offset) |
c896fe29 | 963 | { |
a7812ae4 | 964 | tcg_gen_ldst_op_i64(INDEX_op_ld32s_i64, ret, arg2, offset); |
c896fe29 FB |
965 | } |
966 | ||
a7812ae4 | 967 | static inline void tcg_gen_ld_i64(TCGv_i64 ret, TCGv_i64 arg2, tcg_target_long offset) |
c896fe29 | 968 | { |
a7812ae4 | 969 | tcg_gen_ldst_op_i64(INDEX_op_ld_i64, ret, arg2, offset); |
c896fe29 FB |
970 | } |
971 | ||
a7812ae4 | 972 | static inline void tcg_gen_st8_i64(TCGv_i64 arg1, TCGv_i64 arg2, |
ac56dd48 | 973 | tcg_target_long offset) |
c896fe29 | 974 | { |
a7812ae4 | 975 | tcg_gen_ldst_op_i64(INDEX_op_st8_i64, arg1, arg2, offset); |
c896fe29 FB |
976 | } |
977 | ||
a7812ae4 | 978 | static inline void tcg_gen_st16_i64(TCGv_i64 arg1, TCGv_i64 arg2, |
ac56dd48 | 979 | tcg_target_long offset) |
c896fe29 | 980 | { |
a7812ae4 | 981 | tcg_gen_ldst_op_i64(INDEX_op_st16_i64, arg1, arg2, offset); |
c896fe29 FB |
982 | } |
983 | ||
a7812ae4 | 984 | static inline void tcg_gen_st32_i64(TCGv_i64 arg1, TCGv_i64 arg2, |
ac56dd48 | 985 | tcg_target_long offset) |
c896fe29 | 986 | { |
a7812ae4 | 987 | tcg_gen_ldst_op_i64(INDEX_op_st32_i64, arg1, arg2, offset); |
c896fe29 FB |
988 | } |
989 | ||
a7812ae4 | 990 | static inline void tcg_gen_st_i64(TCGv_i64 arg1, TCGv_i64 arg2, tcg_target_long offset) |
c896fe29 | 991 | { |
a7812ae4 | 992 | tcg_gen_ldst_op_i64(INDEX_op_st_i64, arg1, arg2, offset); |
c896fe29 FB |
993 | } |
994 | ||
a7812ae4 | 995 | static inline void tcg_gen_add_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
c896fe29 | 996 | { |
a7812ae4 | 997 | tcg_gen_op3_i64(INDEX_op_add_i64, ret, arg1, arg2); |
c896fe29 FB |
998 | } |
999 | ||
a7812ae4 | 1000 | static inline void tcg_gen_sub_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
c896fe29 | 1001 | { |
a7812ae4 | 1002 | tcg_gen_op3_i64(INDEX_op_sub_i64, ret, arg1, arg2); |
c896fe29 FB |
1003 | } |
1004 | ||
a7812ae4 | 1005 | static inline void tcg_gen_and_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
c896fe29 | 1006 | { |
7fc81051 AJ |
1007 | if (TCGV_EQUAL_I64(arg1, arg2)) { |
1008 | tcg_gen_mov_i64(ret, arg1); | |
1009 | } else { | |
1010 | tcg_gen_op3_i64(INDEX_op_and_i64, ret, arg1, arg2); | |
1011 | } | |
c896fe29 FB |
1012 | } |
1013 | ||
a7812ae4 | 1014 | static inline void tcg_gen_andi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
c896fe29 | 1015 | { |
a7812ae4 | 1016 | TCGv_i64 t0 = tcg_const_i64(arg2); |
e8996ee0 | 1017 | tcg_gen_and_i64(ret, arg1, t0); |
a7812ae4 | 1018 | tcg_temp_free_i64(t0); |
c896fe29 FB |
1019 | } |
1020 | ||
a7812ae4 | 1021 | static inline void tcg_gen_or_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
c896fe29 | 1022 | { |
7fc81051 AJ |
1023 | if (TCGV_EQUAL_I64(arg1, arg2)) { |
1024 | tcg_gen_mov_i64(ret, arg1); | |
1025 | } else { | |
1026 | tcg_gen_op3_i64(INDEX_op_or_i64, ret, arg1, arg2); | |
1027 | } | |
c896fe29 FB |
1028 | } |
1029 | ||
a7812ae4 | 1030 | static inline void tcg_gen_ori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
c896fe29 | 1031 | { |
a7812ae4 | 1032 | TCGv_i64 t0 = tcg_const_i64(arg2); |
e8996ee0 | 1033 | tcg_gen_or_i64(ret, arg1, t0); |
a7812ae4 | 1034 | tcg_temp_free_i64(t0); |
c896fe29 FB |
1035 | } |
1036 | ||
a7812ae4 | 1037 | static inline void tcg_gen_xor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
c896fe29 | 1038 | { |
7fc81051 AJ |
1039 | if (TCGV_EQUAL_I64(arg1, arg2)) { |
1040 | tcg_gen_movi_i64(ret, 0); | |
1041 | } else { | |
1042 | tcg_gen_op3_i64(INDEX_op_xor_i64, ret, arg1, arg2); | |
1043 | } | |
c896fe29 FB |
1044 | } |
1045 | ||
a7812ae4 | 1046 | static inline void tcg_gen_xori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
c896fe29 | 1047 | { |
a7812ae4 | 1048 | TCGv_i64 t0 = tcg_const_i64(arg2); |
e8996ee0 | 1049 | tcg_gen_xor_i64(ret, arg1, t0); |
a7812ae4 | 1050 | tcg_temp_free_i64(t0); |
c896fe29 FB |
1051 | } |
1052 | ||
a7812ae4 | 1053 | static inline void tcg_gen_shl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
c896fe29 | 1054 | { |
a7812ae4 | 1055 | tcg_gen_op3_i64(INDEX_op_shl_i64, ret, arg1, arg2); |
c896fe29 FB |
1056 | } |
1057 | ||
a7812ae4 | 1058 | static inline void tcg_gen_shli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
c896fe29 | 1059 | { |
34151a20 FB |
1060 | if (arg2 == 0) { |
1061 | tcg_gen_mov_i64(ret, arg1); | |
1062 | } else { | |
a7812ae4 | 1063 | TCGv_i64 t0 = tcg_const_i64(arg2); |
e8996ee0 | 1064 | tcg_gen_shl_i64(ret, arg1, t0); |
a7812ae4 | 1065 | tcg_temp_free_i64(t0); |
34151a20 | 1066 | } |
c896fe29 FB |
1067 | } |
1068 | ||
a7812ae4 | 1069 | static inline void tcg_gen_shr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
c896fe29 | 1070 | { |
a7812ae4 | 1071 | tcg_gen_op3_i64(INDEX_op_shr_i64, ret, arg1, arg2); |
c896fe29 FB |
1072 | } |
1073 | ||
a7812ae4 | 1074 | static inline void tcg_gen_shri_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
c896fe29 | 1075 | { |
34151a20 FB |
1076 | if (arg2 == 0) { |
1077 | tcg_gen_mov_i64(ret, arg1); | |
1078 | } else { | |
a7812ae4 | 1079 | TCGv_i64 t0 = tcg_const_i64(arg2); |
e8996ee0 | 1080 | tcg_gen_shr_i64(ret, arg1, t0); |
a7812ae4 | 1081 | tcg_temp_free_i64(t0); |
34151a20 | 1082 | } |
c896fe29 FB |
1083 | } |
1084 | ||
a7812ae4 | 1085 | static inline void tcg_gen_sar_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
c896fe29 | 1086 | { |
a7812ae4 | 1087 | tcg_gen_op3_i64(INDEX_op_sar_i64, ret, arg1, arg2); |
c896fe29 FB |
1088 | } |
1089 | ||
a7812ae4 | 1090 | static inline void tcg_gen_sari_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
c896fe29 | 1091 | { |
34151a20 FB |
1092 | if (arg2 == 0) { |
1093 | tcg_gen_mov_i64(ret, arg1); | |
1094 | } else { | |
a7812ae4 | 1095 | TCGv_i64 t0 = tcg_const_i64(arg2); |
e8996ee0 | 1096 | tcg_gen_sar_i64(ret, arg1, t0); |
a7812ae4 | 1097 | tcg_temp_free_i64(t0); |
34151a20 | 1098 | } |
c896fe29 FB |
1099 | } |
1100 | ||
a7812ae4 | 1101 | static inline void tcg_gen_brcond_i64(int cond, TCGv_i64 arg1, TCGv_i64 arg2, |
c896fe29 FB |
1102 | int label_index) |
1103 | { | |
a7812ae4 | 1104 | tcg_gen_op4ii_i64(INDEX_op_brcond_i64, arg1, arg2, cond, label_index); |
c896fe29 FB |
1105 | } |
1106 | ||
5105c556 AJ |
1107 | static inline void tcg_gen_setcond_i64(int cond, TCGv_i64 ret, |
1108 | TCGv_i64 arg1, TCGv_i64 arg2) | |
1109 | { | |
1110 | tcg_gen_op4i_i64(INDEX_op_setcond_i64, ret, arg1, arg2, cond); | |
1111 | } | |
1112 | ||
a7812ae4 | 1113 | static inline void tcg_gen_mul_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
c896fe29 | 1114 | { |
a7812ae4 | 1115 | tcg_gen_op3_i64(INDEX_op_mul_i64, ret, arg1, arg2); |
c896fe29 FB |
1116 | } |
1117 | ||
1118 | #ifdef TCG_TARGET_HAS_div_i64 | |
a7812ae4 | 1119 | static inline void tcg_gen_div_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
c896fe29 | 1120 | { |
a7812ae4 | 1121 | tcg_gen_op3_i64(INDEX_op_div_i64, ret, arg1, arg2); |
c896fe29 FB |
1122 | } |
1123 | ||
a7812ae4 | 1124 | static inline void tcg_gen_rem_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
c896fe29 | 1125 | { |
a7812ae4 | 1126 | tcg_gen_op3_i64(INDEX_op_rem_i64, ret, arg1, arg2); |
c896fe29 FB |
1127 | } |
1128 | ||
a7812ae4 | 1129 | static inline void tcg_gen_divu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
c896fe29 | 1130 | { |
a7812ae4 | 1131 | tcg_gen_op3_i64(INDEX_op_divu_i64, ret, arg1, arg2); |
c896fe29 FB |
1132 | } |
1133 | ||
a7812ae4 | 1134 | static inline void tcg_gen_remu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
c896fe29 | 1135 | { |
a7812ae4 | 1136 | tcg_gen_op3_i64(INDEX_op_remu_i64, ret, arg1, arg2); |
c896fe29 FB |
1137 | } |
1138 | #else | |
a7812ae4 | 1139 | static inline void tcg_gen_div_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
c896fe29 | 1140 | { |
a7812ae4 PB |
1141 | TCGv_i64 t0; |
1142 | t0 = tcg_temp_new_i64(); | |
c896fe29 | 1143 | tcg_gen_sari_i64(t0, arg1, 63); |
a7812ae4 PB |
1144 | tcg_gen_op5_i64(INDEX_op_div2_i64, ret, t0, arg1, t0, arg2); |
1145 | tcg_temp_free_i64(t0); | |
c896fe29 FB |
1146 | } |
1147 | ||
a7812ae4 | 1148 | static inline void tcg_gen_rem_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
c896fe29 | 1149 | { |
a7812ae4 PB |
1150 | TCGv_i64 t0; |
1151 | t0 = tcg_temp_new_i64(); | |
c896fe29 | 1152 | tcg_gen_sari_i64(t0, arg1, 63); |
a7812ae4 PB |
1153 | tcg_gen_op5_i64(INDEX_op_div2_i64, t0, ret, arg1, t0, arg2); |
1154 | tcg_temp_free_i64(t0); | |
c896fe29 FB |
1155 | } |
1156 | ||
a7812ae4 | 1157 | static inline void tcg_gen_divu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
c896fe29 | 1158 | { |
a7812ae4 PB |
1159 | TCGv_i64 t0; |
1160 | t0 = tcg_temp_new_i64(); | |
c896fe29 | 1161 | tcg_gen_movi_i64(t0, 0); |
a7812ae4 PB |
1162 | tcg_gen_op5_i64(INDEX_op_divu2_i64, ret, t0, arg1, t0, arg2); |
1163 | tcg_temp_free_i64(t0); | |
c896fe29 FB |
1164 | } |
1165 | ||
a7812ae4 | 1166 | static inline void tcg_gen_remu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
c896fe29 | 1167 | { |
a7812ae4 PB |
1168 | TCGv_i64 t0; |
1169 | t0 = tcg_temp_new_i64(); | |
c896fe29 | 1170 | tcg_gen_movi_i64(t0, 0); |
a7812ae4 PB |
1171 | tcg_gen_op5_i64(INDEX_op_divu2_i64, t0, ret, arg1, t0, arg2); |
1172 | tcg_temp_free_i64(t0); | |
c896fe29 FB |
1173 | } |
1174 | #endif | |
1175 | ||
1176 | #endif | |
1177 | ||
a7812ae4 | 1178 | static inline void tcg_gen_addi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
6359706f AJ |
1179 | { |
1180 | /* some cases can be optimized here */ | |
1181 | if (arg2 == 0) { | |
1182 | tcg_gen_mov_i64(ret, arg1); | |
1183 | } else { | |
a7812ae4 | 1184 | TCGv_i64 t0 = tcg_const_i64(arg2); |
6359706f | 1185 | tcg_gen_add_i64(ret, arg1, t0); |
a7812ae4 | 1186 | tcg_temp_free_i64(t0); |
6359706f AJ |
1187 | } |
1188 | } | |
1189 | ||
a7812ae4 | 1190 | static inline void tcg_gen_subfi_i64(TCGv_i64 ret, int64_t arg1, TCGv_i64 arg2) |
0045734a | 1191 | { |
a7812ae4 | 1192 | TCGv_i64 t0 = tcg_const_i64(arg1); |
0045734a | 1193 | tcg_gen_sub_i64(ret, t0, arg2); |
a7812ae4 | 1194 | tcg_temp_free_i64(t0); |
0045734a AJ |
1195 | } |
1196 | ||
a7812ae4 | 1197 | static inline void tcg_gen_subi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
6359706f AJ |
1198 | { |
1199 | /* some cases can be optimized here */ | |
1200 | if (arg2 == 0) { | |
1201 | tcg_gen_mov_i64(ret, arg1); | |
1202 | } else { | |
a7812ae4 | 1203 | TCGv_i64 t0 = tcg_const_i64(arg2); |
6359706f | 1204 | tcg_gen_sub_i64(ret, arg1, t0); |
a7812ae4 | 1205 | tcg_temp_free_i64(t0); |
6359706f AJ |
1206 | } |
1207 | } | |
a7812ae4 | 1208 | static inline void tcg_gen_brcondi_i64(int cond, TCGv_i64 arg1, int64_t arg2, |
f02bb954 AJ |
1209 | int label_index) |
1210 | { | |
a7812ae4 | 1211 | TCGv_i64 t0 = tcg_const_i64(arg2); |
f02bb954 | 1212 | tcg_gen_brcond_i64(cond, arg1, t0, label_index); |
a7812ae4 | 1213 | tcg_temp_free_i64(t0); |
f02bb954 AJ |
1214 | } |
1215 | ||
5105c556 AJ |
1216 | static inline void tcg_gen_setcondi_i64(int cond, TCGv_i64 ret, TCGv_i64 arg1, |
1217 | int64_t arg2) | |
1218 | { | |
1219 | TCGv_i64 t0 = tcg_const_i64(arg2); | |
1220 | tcg_gen_setcond_i64(cond, ret, arg1, t0); | |
1221 | tcg_temp_free_i64(t0); | |
1222 | } | |
1223 | ||
a7812ae4 | 1224 | static inline void tcg_gen_muli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
f02bb954 | 1225 | { |
a7812ae4 | 1226 | TCGv_i64 t0 = tcg_const_i64(arg2); |
f02bb954 | 1227 | tcg_gen_mul_i64(ret, arg1, t0); |
a7812ae4 | 1228 | tcg_temp_free_i64(t0); |
f02bb954 AJ |
1229 | } |
1230 | ||
6359706f | 1231 | |
c896fe29 FB |
1232 | /***************************************/ |
1233 | /* optional operations */ | |
1234 | ||
a7812ae4 | 1235 | static inline void tcg_gen_ext8s_i32(TCGv_i32 ret, TCGv_i32 arg) |
c896fe29 FB |
1236 | { |
1237 | #ifdef TCG_TARGET_HAS_ext8s_i32 | |
a7812ae4 | 1238 | tcg_gen_op2_i32(INDEX_op_ext8s_i32, ret, arg); |
c896fe29 FB |
1239 | #else |
1240 | tcg_gen_shli_i32(ret, arg, 24); | |
5ff9d6a4 | 1241 | tcg_gen_sari_i32(ret, ret, 24); |
c896fe29 FB |
1242 | #endif |
1243 | } | |
1244 | ||
a7812ae4 | 1245 | static inline void tcg_gen_ext16s_i32(TCGv_i32 ret, TCGv_i32 arg) |
c896fe29 FB |
1246 | { |
1247 | #ifdef TCG_TARGET_HAS_ext16s_i32 | |
a7812ae4 | 1248 | tcg_gen_op2_i32(INDEX_op_ext16s_i32, ret, arg); |
c896fe29 FB |
1249 | #else |
1250 | tcg_gen_shli_i32(ret, arg, 16); | |
5ff9d6a4 | 1251 | tcg_gen_sari_i32(ret, ret, 16); |
c896fe29 FB |
1252 | #endif |
1253 | } | |
1254 | ||
a7812ae4 | 1255 | static inline void tcg_gen_ext8u_i32(TCGv_i32 ret, TCGv_i32 arg) |
86831435 | 1256 | { |
cfc86988 AJ |
1257 | #ifdef TCG_TARGET_HAS_ext8u_i32 |
1258 | tcg_gen_op2_i32(INDEX_op_ext8u_i32, ret, arg); | |
1259 | #else | |
86831435 | 1260 | tcg_gen_andi_i32(ret, arg, 0xffu); |
cfc86988 | 1261 | #endif |
86831435 PB |
1262 | } |
1263 | ||
a7812ae4 | 1264 | static inline void tcg_gen_ext16u_i32(TCGv_i32 ret, TCGv_i32 arg) |
86831435 | 1265 | { |
cfc86988 AJ |
1266 | #ifdef TCG_TARGET_HAS_ext16u_i32 |
1267 | tcg_gen_op2_i32(INDEX_op_ext16u_i32, ret, arg); | |
1268 | #else | |
86831435 | 1269 | tcg_gen_andi_i32(ret, arg, 0xffffu); |
cfc86988 | 1270 | #endif |
86831435 PB |
1271 | } |
1272 | ||
c896fe29 | 1273 | /* Note: we assume the two high bytes are set to zero */ |
a7812ae4 | 1274 | static inline void tcg_gen_bswap16_i32(TCGv_i32 ret, TCGv_i32 arg) |
c896fe29 FB |
1275 | { |
1276 | #ifdef TCG_TARGET_HAS_bswap16_i32 | |
a7812ae4 | 1277 | tcg_gen_op2_i32(INDEX_op_bswap16_i32, ret, arg); |
c896fe29 | 1278 | #else |
dfa1a3f1 | 1279 | TCGv_i32 t0 = tcg_temp_new_i32(); |
c896fe29 | 1280 | |
dfa1a3f1 AJ |
1281 | tcg_gen_ext8u_i32(t0, arg); |
1282 | tcg_gen_shli_i32(t0, t0, 8); | |
1283 | tcg_gen_shri_i32(ret, arg, 8); | |
1284 | tcg_gen_or_i32(ret, ret, t0); | |
a7812ae4 | 1285 | tcg_temp_free_i32(t0); |
c896fe29 FB |
1286 | #endif |
1287 | } | |
1288 | ||
66896cb8 | 1289 | static inline void tcg_gen_bswap32_i32(TCGv_i32 ret, TCGv_i32 arg) |
c896fe29 | 1290 | { |
66896cb8 AJ |
1291 | #ifdef TCG_TARGET_HAS_bswap32_i32 |
1292 | tcg_gen_op2_i32(INDEX_op_bswap32_i32, ret, arg); | |
c896fe29 | 1293 | #else |
a7812ae4 PB |
1294 | TCGv_i32 t0, t1; |
1295 | t0 = tcg_temp_new_i32(); | |
1296 | t1 = tcg_temp_new_i32(); | |
c896fe29 FB |
1297 | |
1298 | tcg_gen_shli_i32(t0, arg, 24); | |
1299 | ||
1300 | tcg_gen_andi_i32(t1, arg, 0x0000ff00); | |
1301 | tcg_gen_shli_i32(t1, t1, 8); | |
1302 | tcg_gen_or_i32(t0, t0, t1); | |
1303 | ||
1304 | tcg_gen_shri_i32(t1, arg, 8); | |
1305 | tcg_gen_andi_i32(t1, t1, 0x0000ff00); | |
1306 | tcg_gen_or_i32(t0, t0, t1); | |
1307 | ||
1308 | tcg_gen_shri_i32(t1, arg, 24); | |
1309 | tcg_gen_or_i32(ret, t0, t1); | |
a7812ae4 PB |
1310 | tcg_temp_free_i32(t0); |
1311 | tcg_temp_free_i32(t1); | |
c896fe29 FB |
1312 | #endif |
1313 | } | |
1314 | ||
1315 | #if TCG_TARGET_REG_BITS == 32 | |
a7812ae4 | 1316 | static inline void tcg_gen_ext8s_i64(TCGv_i64 ret, TCGv_i64 arg) |
c896fe29 | 1317 | { |
a7812ae4 PB |
1318 | tcg_gen_ext8s_i32(TCGV_LOW(ret), TCGV_LOW(arg)); |
1319 | tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31); | |
c896fe29 FB |
1320 | } |
1321 | ||
a7812ae4 | 1322 | static inline void tcg_gen_ext16s_i64(TCGv_i64 ret, TCGv_i64 arg) |
c896fe29 | 1323 | { |
a7812ae4 PB |
1324 | tcg_gen_ext16s_i32(TCGV_LOW(ret), TCGV_LOW(arg)); |
1325 | tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31); | |
c896fe29 FB |
1326 | } |
1327 | ||
a7812ae4 | 1328 | static inline void tcg_gen_ext32s_i64(TCGv_i64 ret, TCGv_i64 arg) |
c896fe29 | 1329 | { |
a7812ae4 PB |
1330 | tcg_gen_mov_i32(TCGV_LOW(ret), TCGV_LOW(arg)); |
1331 | tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31); | |
c896fe29 FB |
1332 | } |
1333 | ||
a7812ae4 | 1334 | static inline void tcg_gen_ext8u_i64(TCGv_i64 ret, TCGv_i64 arg) |
86831435 | 1335 | { |
a7812ae4 | 1336 | tcg_gen_ext8u_i32(TCGV_LOW(ret), TCGV_LOW(arg)); |
86831435 PB |
1337 | tcg_gen_movi_i32(TCGV_HIGH(ret), 0); |
1338 | } | |
1339 | ||
a7812ae4 | 1340 | static inline void tcg_gen_ext16u_i64(TCGv_i64 ret, TCGv_i64 arg) |
86831435 | 1341 | { |
a7812ae4 | 1342 | tcg_gen_ext16u_i32(TCGV_LOW(ret), TCGV_LOW(arg)); |
86831435 PB |
1343 | tcg_gen_movi_i32(TCGV_HIGH(ret), 0); |
1344 | } | |
1345 | ||
a7812ae4 | 1346 | static inline void tcg_gen_ext32u_i64(TCGv_i64 ret, TCGv_i64 arg) |
86831435 | 1347 | { |
a7812ae4 | 1348 | tcg_gen_mov_i32(TCGV_LOW(ret), TCGV_LOW(arg)); |
86831435 PB |
1349 | tcg_gen_movi_i32(TCGV_HIGH(ret), 0); |
1350 | } | |
1351 | ||
a7812ae4 | 1352 | static inline void tcg_gen_trunc_i64_i32(TCGv_i32 ret, TCGv_i64 arg) |
c896fe29 | 1353 | { |
a7812ae4 | 1354 | tcg_gen_mov_i32(ret, TCGV_LOW(arg)); |
c896fe29 FB |
1355 | } |
1356 | ||
a7812ae4 | 1357 | static inline void tcg_gen_extu_i32_i64(TCGv_i64 ret, TCGv_i32 arg) |
c896fe29 | 1358 | { |
a7812ae4 | 1359 | tcg_gen_mov_i32(TCGV_LOW(ret), arg); |
ac56dd48 | 1360 | tcg_gen_movi_i32(TCGV_HIGH(ret), 0); |
c896fe29 FB |
1361 | } |
1362 | ||
a7812ae4 | 1363 | static inline void tcg_gen_ext_i32_i64(TCGv_i64 ret, TCGv_i32 arg) |
c896fe29 | 1364 | { |
a7812ae4 PB |
1365 | tcg_gen_mov_i32(TCGV_LOW(ret), arg); |
1366 | tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31); | |
c896fe29 FB |
1367 | } |
1368 | ||
9a5c57fd AJ |
1369 | /* Note: we assume the six high bytes are set to zero */ |
1370 | static inline void tcg_gen_bswap16_i64(TCGv_i64 ret, TCGv_i64 arg) | |
1371 | { | |
1372 | tcg_gen_mov_i32(TCGV_HIGH(ret), TCGV_HIGH(arg)); | |
1373 | tcg_gen_bswap16_i32(TCGV_LOW(ret), TCGV_LOW(arg)); | |
1374 | } | |
1375 | ||
1376 | /* Note: we assume the four high bytes are set to zero */ | |
1377 | static inline void tcg_gen_bswap32_i64(TCGv_i64 ret, TCGv_i64 arg) | |
1378 | { | |
1379 | tcg_gen_mov_i32(TCGV_HIGH(ret), TCGV_HIGH(arg)); | |
1380 | tcg_gen_bswap32_i32(TCGV_LOW(ret), TCGV_LOW(arg)); | |
1381 | } | |
1382 | ||
66896cb8 | 1383 | static inline void tcg_gen_bswap64_i64(TCGv_i64 ret, TCGv_i64 arg) |
c896fe29 | 1384 | { |
a7812ae4 PB |
1385 | TCGv_i32 t0, t1; |
1386 | t0 = tcg_temp_new_i32(); | |
1387 | t1 = tcg_temp_new_i32(); | |
c896fe29 | 1388 | |
66896cb8 AJ |
1389 | tcg_gen_bswap32_i32(t0, TCGV_LOW(arg)); |
1390 | tcg_gen_bswap32_i32(t1, TCGV_HIGH(arg)); | |
a7812ae4 | 1391 | tcg_gen_mov_i32(TCGV_LOW(ret), t1); |
ac56dd48 | 1392 | tcg_gen_mov_i32(TCGV_HIGH(ret), t0); |
a7812ae4 PB |
1393 | tcg_temp_free_i32(t0); |
1394 | tcg_temp_free_i32(t1); | |
c896fe29 FB |
1395 | } |
1396 | #else | |
1397 | ||
a7812ae4 | 1398 | static inline void tcg_gen_ext8s_i64(TCGv_i64 ret, TCGv_i64 arg) |
c896fe29 FB |
1399 | { |
1400 | #ifdef TCG_TARGET_HAS_ext8s_i64 | |
a7812ae4 | 1401 | tcg_gen_op2_i64(INDEX_op_ext8s_i64, ret, arg); |
c896fe29 FB |
1402 | #else |
1403 | tcg_gen_shli_i64(ret, arg, 56); | |
5ff9d6a4 | 1404 | tcg_gen_sari_i64(ret, ret, 56); |
c896fe29 FB |
1405 | #endif |
1406 | } | |
1407 | ||
a7812ae4 | 1408 | static inline void tcg_gen_ext16s_i64(TCGv_i64 ret, TCGv_i64 arg) |
c896fe29 FB |
1409 | { |
1410 | #ifdef TCG_TARGET_HAS_ext16s_i64 | |
a7812ae4 | 1411 | tcg_gen_op2_i64(INDEX_op_ext16s_i64, ret, arg); |
c896fe29 FB |
1412 | #else |
1413 | tcg_gen_shli_i64(ret, arg, 48); | |
5ff9d6a4 | 1414 | tcg_gen_sari_i64(ret, ret, 48); |
c896fe29 FB |
1415 | #endif |
1416 | } | |
1417 | ||
a7812ae4 | 1418 | static inline void tcg_gen_ext32s_i64(TCGv_i64 ret, TCGv_i64 arg) |
c896fe29 FB |
1419 | { |
1420 | #ifdef TCG_TARGET_HAS_ext32s_i64 | |
a7812ae4 | 1421 | tcg_gen_op2_i64(INDEX_op_ext32s_i64, ret, arg); |
c896fe29 FB |
1422 | #else |
1423 | tcg_gen_shli_i64(ret, arg, 32); | |
5ff9d6a4 | 1424 | tcg_gen_sari_i64(ret, ret, 32); |
c896fe29 FB |
1425 | #endif |
1426 | } | |
1427 | ||
a7812ae4 | 1428 | static inline void tcg_gen_ext8u_i64(TCGv_i64 ret, TCGv_i64 arg) |
86831435 | 1429 | { |
cfc86988 AJ |
1430 | #ifdef TCG_TARGET_HAS_ext8u_i64 |
1431 | tcg_gen_op2_i64(INDEX_op_ext8u_i64, ret, arg); | |
1432 | #else | |
86831435 | 1433 | tcg_gen_andi_i64(ret, arg, 0xffu); |
cfc86988 | 1434 | #endif |
86831435 PB |
1435 | } |
1436 | ||
a7812ae4 | 1437 | static inline void tcg_gen_ext16u_i64(TCGv_i64 ret, TCGv_i64 arg) |
86831435 | 1438 | { |
cfc86988 AJ |
1439 | #ifdef TCG_TARGET_HAS_ext16u_i64 |
1440 | tcg_gen_op2_i64(INDEX_op_ext16u_i64, ret, arg); | |
1441 | #else | |
86831435 | 1442 | tcg_gen_andi_i64(ret, arg, 0xffffu); |
cfc86988 | 1443 | #endif |
86831435 PB |
1444 | } |
1445 | ||
a7812ae4 | 1446 | static inline void tcg_gen_ext32u_i64(TCGv_i64 ret, TCGv_i64 arg) |
86831435 | 1447 | { |
cfc86988 AJ |
1448 | #ifdef TCG_TARGET_HAS_ext32u_i64 |
1449 | tcg_gen_op2_i64(INDEX_op_ext32u_i64, ret, arg); | |
1450 | #else | |
86831435 | 1451 | tcg_gen_andi_i64(ret, arg, 0xffffffffu); |
cfc86988 | 1452 | #endif |
86831435 PB |
1453 | } |
1454 | ||
c896fe29 | 1455 | /* Note: we assume the target supports move between 32 and 64 bit |
ac56dd48 | 1456 | registers. This will probably break MIPS64 targets. */ |
a7812ae4 | 1457 | static inline void tcg_gen_trunc_i64_i32(TCGv_i32 ret, TCGv_i64 arg) |
c896fe29 | 1458 | { |
a7812ae4 | 1459 | tcg_gen_mov_i32(ret, MAKE_TCGV_I32(GET_TCGV_I64(arg))); |
c896fe29 FB |
1460 | } |
1461 | ||
1462 | /* Note: we assume the target supports move between 32 and 64 bit | |
1463 | registers */ | |
a7812ae4 | 1464 | static inline void tcg_gen_extu_i32_i64(TCGv_i64 ret, TCGv_i32 arg) |
c896fe29 | 1465 | { |
cfc86988 | 1466 | tcg_gen_ext32u_i64(ret, MAKE_TCGV_I64(GET_TCGV_I32(arg))); |
c896fe29 FB |
1467 | } |
1468 | ||
1469 | /* Note: we assume the target supports move between 32 and 64 bit | |
1470 | registers */ | |
a7812ae4 | 1471 | static inline void tcg_gen_ext_i32_i64(TCGv_i64 ret, TCGv_i32 arg) |
c896fe29 | 1472 | { |
a7812ae4 | 1473 | tcg_gen_ext32s_i64(ret, MAKE_TCGV_I64(GET_TCGV_I32(arg))); |
c896fe29 FB |
1474 | } |
1475 | ||
9a5c57fd AJ |
1476 | /* Note: we assume the six high bytes are set to zero */ |
1477 | static inline void tcg_gen_bswap16_i64(TCGv_i64 ret, TCGv_i64 arg) | |
1478 | { | |
1479 | #ifdef TCG_TARGET_HAS_bswap16_i64 | |
1480 | tcg_gen_op2_i64(INDEX_op_bswap16_i64, ret, arg); | |
1481 | #else | |
1482 | TCGv_i64 t0 = tcg_temp_new_i64(); | |
1483 | ||
1484 | tcg_gen_ext8u_i64(t0, arg); | |
1485 | tcg_gen_shli_i64(t0, t0, 8); | |
1486 | tcg_gen_shri_i64(ret, arg, 8); | |
1487 | tcg_gen_or_i64(ret, ret, t0); | |
1488 | tcg_temp_free_i64(t0); | |
1489 | #endif | |
1490 | } | |
1491 | ||
1492 | /* Note: we assume the four high bytes are set to zero */ | |
1493 | static inline void tcg_gen_bswap32_i64(TCGv_i64 ret, TCGv_i64 arg) | |
1494 | { | |
1495 | #ifdef TCG_TARGET_HAS_bswap32_i64 | |
1496 | tcg_gen_op2_i64(INDEX_op_bswap32_i64, ret, arg); | |
1497 | #else | |
1498 | TCGv_i64 t0, t1; | |
1499 | t0 = tcg_temp_new_i64(); | |
1500 | t1 = tcg_temp_new_i64(); | |
1501 | ||
1502 | tcg_gen_shli_i64(t0, arg, 24); | |
1503 | tcg_gen_ext32u_i64(t0, t0); | |
1504 | ||
1505 | tcg_gen_andi_i64(t1, arg, 0x0000ff00); | |
1506 | tcg_gen_shli_i64(t1, t1, 8); | |
1507 | tcg_gen_or_i64(t0, t0, t1); | |
1508 | ||
1509 | tcg_gen_shri_i64(t1, arg, 8); | |
1510 | tcg_gen_andi_i64(t1, t1, 0x0000ff00); | |
1511 | tcg_gen_or_i64(t0, t0, t1); | |
1512 | ||
1513 | tcg_gen_shri_i64(t1, arg, 24); | |
1514 | tcg_gen_or_i64(ret, t0, t1); | |
1515 | tcg_temp_free_i64(t0); | |
1516 | tcg_temp_free_i64(t1); | |
1517 | #endif | |
1518 | } | |
1519 | ||
66896cb8 | 1520 | static inline void tcg_gen_bswap64_i64(TCGv_i64 ret, TCGv_i64 arg) |
c896fe29 | 1521 | { |
66896cb8 AJ |
1522 | #ifdef TCG_TARGET_HAS_bswap64_i64 |
1523 | tcg_gen_op2_i64(INDEX_op_bswap64_i64, ret, arg); | |
c896fe29 | 1524 | #else |
b348113d SW |
1525 | TCGv_i64 t0 = tcg_temp_new_i64(); |
1526 | TCGv_i64 t1 = tcg_temp_new_i64(); | |
c896fe29 FB |
1527 | |
1528 | tcg_gen_shli_i64(t0, arg, 56); | |
1529 | ||
1530 | tcg_gen_andi_i64(t1, arg, 0x0000ff00); | |
1531 | tcg_gen_shli_i64(t1, t1, 40); | |
1532 | tcg_gen_or_i64(t0, t0, t1); | |
1533 | ||
1534 | tcg_gen_andi_i64(t1, arg, 0x00ff0000); | |
1535 | tcg_gen_shli_i64(t1, t1, 24); | |
1536 | tcg_gen_or_i64(t0, t0, t1); | |
1537 | ||
1538 | tcg_gen_andi_i64(t1, arg, 0xff000000); | |
1539 | tcg_gen_shli_i64(t1, t1, 8); | |
1540 | tcg_gen_or_i64(t0, t0, t1); | |
1541 | ||
1542 | tcg_gen_shri_i64(t1, arg, 8); | |
1543 | tcg_gen_andi_i64(t1, t1, 0xff000000); | |
1544 | tcg_gen_or_i64(t0, t0, t1); | |
1545 | ||
1546 | tcg_gen_shri_i64(t1, arg, 24); | |
1547 | tcg_gen_andi_i64(t1, t1, 0x00ff0000); | |
1548 | tcg_gen_or_i64(t0, t0, t1); | |
1549 | ||
1550 | tcg_gen_shri_i64(t1, arg, 40); | |
1551 | tcg_gen_andi_i64(t1, t1, 0x0000ff00); | |
1552 | tcg_gen_or_i64(t0, t0, t1); | |
1553 | ||
1554 | tcg_gen_shri_i64(t1, arg, 56); | |
1555 | tcg_gen_or_i64(ret, t0, t1); | |
b348113d SW |
1556 | tcg_temp_free_i64(t0); |
1557 | tcg_temp_free_i64(t1); | |
c896fe29 FB |
1558 | #endif |
1559 | } | |
1560 | ||
1561 | #endif | |
1562 | ||
a7812ae4 | 1563 | static inline void tcg_gen_neg_i32(TCGv_i32 ret, TCGv_i32 arg) |
390efc54 PB |
1564 | { |
1565 | #ifdef TCG_TARGET_HAS_neg_i32 | |
a7812ae4 | 1566 | tcg_gen_op2_i32(INDEX_op_neg_i32, ret, arg); |
390efc54 | 1567 | #else |
a7812ae4 | 1568 | TCGv_i32 t0 = tcg_const_i32(0); |
e8996ee0 | 1569 | tcg_gen_sub_i32(ret, t0, arg); |
a7812ae4 | 1570 | tcg_temp_free_i32(t0); |
390efc54 PB |
1571 | #endif |
1572 | } | |
1573 | ||
a7812ae4 | 1574 | static inline void tcg_gen_neg_i64(TCGv_i64 ret, TCGv_i64 arg) |
390efc54 PB |
1575 | { |
1576 | #ifdef TCG_TARGET_HAS_neg_i64 | |
a7812ae4 | 1577 | tcg_gen_op2_i64(INDEX_op_neg_i64, ret, arg); |
390efc54 | 1578 | #else |
a7812ae4 | 1579 | TCGv_i64 t0 = tcg_const_i64(0); |
e8996ee0 | 1580 | tcg_gen_sub_i64(ret, t0, arg); |
a7812ae4 | 1581 | tcg_temp_free_i64(t0); |
390efc54 PB |
1582 | #endif |
1583 | } | |
1584 | ||
a7812ae4 | 1585 | static inline void tcg_gen_not_i32(TCGv_i32 ret, TCGv_i32 arg) |
0b6ce4cf | 1586 | { |
d2604285 AJ |
1587 | #ifdef TCG_TARGET_HAS_not_i32 |
1588 | tcg_gen_op2_i32(INDEX_op_not_i32, ret, arg); | |
1589 | #else | |
e8996ee0 | 1590 | tcg_gen_xori_i32(ret, arg, -1); |
d2604285 | 1591 | #endif |
0b6ce4cf FB |
1592 | } |
1593 | ||
a7812ae4 | 1594 | static inline void tcg_gen_not_i64(TCGv_i64 ret, TCGv_i64 arg) |
0b6ce4cf | 1595 | { |
d2604285 | 1596 | #ifdef TCG_TARGET_HAS_not_i64 |
43e860ef | 1597 | tcg_gen_op2_i64(INDEX_op_not_i64, ret, arg); |
d2604285 | 1598 | #else |
e8996ee0 | 1599 | tcg_gen_xori_i64(ret, arg, -1); |
d2604285 | 1600 | #endif |
0b6ce4cf | 1601 | } |
5ff9d6a4 | 1602 | |
a7812ae4 | 1603 | static inline void tcg_gen_discard_i32(TCGv_i32 arg) |
5ff9d6a4 | 1604 | { |
a7812ae4 | 1605 | tcg_gen_op1_i32(INDEX_op_discard, arg); |
5ff9d6a4 FB |
1606 | } |
1607 | ||
1608 | #if TCG_TARGET_REG_BITS == 32 | |
a7812ae4 | 1609 | static inline void tcg_gen_discard_i64(TCGv_i64 arg) |
5ff9d6a4 | 1610 | { |
a7812ae4 | 1611 | tcg_gen_discard_i32(TCGV_LOW(arg)); |
5ff9d6a4 FB |
1612 | tcg_gen_discard_i32(TCGV_HIGH(arg)); |
1613 | } | |
1614 | #else | |
a7812ae4 | 1615 | static inline void tcg_gen_discard_i64(TCGv_i64 arg) |
5ff9d6a4 | 1616 | { |
a7812ae4 | 1617 | tcg_gen_op1_i64(INDEX_op_discard, arg); |
5ff9d6a4 FB |
1618 | } |
1619 | #endif | |
1620 | ||
a7812ae4 | 1621 | static inline void tcg_gen_concat_i32_i64(TCGv_i64 dest, TCGv_i32 low, TCGv_i32 high) |
36aa55dc PB |
1622 | { |
1623 | #if TCG_TARGET_REG_BITS == 32 | |
a7812ae4 | 1624 | tcg_gen_mov_i32(TCGV_LOW(dest), low); |
36aa55dc PB |
1625 | tcg_gen_mov_i32(TCGV_HIGH(dest), high); |
1626 | #else | |
a7812ae4 | 1627 | TCGv_i64 tmp = tcg_temp_new_i64(); |
36aa55dc PB |
1628 | /* This extension is only needed for type correctness. |
1629 | We may be able to do better given target specific information. */ | |
1630 | tcg_gen_extu_i32_i64(tmp, high); | |
1631 | tcg_gen_shli_i64(tmp, tmp, 32); | |
1632 | tcg_gen_extu_i32_i64(dest, low); | |
1633 | tcg_gen_or_i64(dest, dest, tmp); | |
a7812ae4 | 1634 | tcg_temp_free_i64(tmp); |
36aa55dc PB |
1635 | #endif |
1636 | } | |
1637 | ||
a7812ae4 | 1638 | static inline void tcg_gen_concat32_i64(TCGv_i64 dest, TCGv_i64 low, TCGv_i64 high) |
945ca823 BS |
1639 | { |
1640 | #if TCG_TARGET_REG_BITS == 32 | |
a7812ae4 | 1641 | tcg_gen_concat_i32_i64(dest, TCGV_LOW(low), TCGV_LOW(high)); |
945ca823 | 1642 | #else |
a7812ae4 | 1643 | TCGv_i64 tmp = tcg_temp_new_i64(); |
88422e2e | 1644 | tcg_gen_ext32u_i64(dest, low); |
945ca823 | 1645 | tcg_gen_shli_i64(tmp, high, 32); |
88422e2e | 1646 | tcg_gen_or_i64(dest, dest, tmp); |
a7812ae4 | 1647 | tcg_temp_free_i64(tmp); |
945ca823 BS |
1648 | #endif |
1649 | } | |
1650 | ||
a7812ae4 | 1651 | static inline void tcg_gen_andc_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
f24cb33e | 1652 | { |
a7812ae4 PB |
1653 | TCGv_i32 t0; |
1654 | t0 = tcg_temp_new_i32(); | |
f24cb33e AJ |
1655 | tcg_gen_not_i32(t0, arg2); |
1656 | tcg_gen_and_i32(ret, arg1, t0); | |
a7812ae4 | 1657 | tcg_temp_free_i32(t0); |
f24cb33e AJ |
1658 | } |
1659 | ||
a7812ae4 | 1660 | static inline void tcg_gen_andc_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
f24cb33e | 1661 | { |
a7812ae4 PB |
1662 | TCGv_i64 t0; |
1663 | t0 = tcg_temp_new_i64(); | |
f24cb33e AJ |
1664 | tcg_gen_not_i64(t0, arg2); |
1665 | tcg_gen_and_i64(ret, arg1, t0); | |
a7812ae4 | 1666 | tcg_temp_free_i64(t0); |
f24cb33e AJ |
1667 | } |
1668 | ||
a7812ae4 | 1669 | static inline void tcg_gen_eqv_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
f24cb33e | 1670 | { |
7fc81051 AJ |
1671 | tcg_gen_xor_i32(ret, arg1, arg2); |
1672 | tcg_gen_not_i32(ret, ret); | |
f24cb33e AJ |
1673 | } |
1674 | ||
a7812ae4 | 1675 | static inline void tcg_gen_eqv_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
f24cb33e | 1676 | { |
7fc81051 AJ |
1677 | tcg_gen_xor_i64(ret, arg1, arg2); |
1678 | tcg_gen_not_i64(ret, ret); | |
f24cb33e AJ |
1679 | } |
1680 | ||
a7812ae4 | 1681 | static inline void tcg_gen_nand_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
f24cb33e | 1682 | { |
7fc81051 AJ |
1683 | tcg_gen_and_i32(ret, arg1, arg2); |
1684 | tcg_gen_not_i32(ret, ret); | |
f24cb33e AJ |
1685 | } |
1686 | ||
a7812ae4 | 1687 | static inline void tcg_gen_nand_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
f24cb33e | 1688 | { |
7fc81051 AJ |
1689 | tcg_gen_and_i64(ret, arg1, arg2); |
1690 | tcg_gen_not_i64(ret, ret); | |
f24cb33e AJ |
1691 | } |
1692 | ||
a7812ae4 | 1693 | static inline void tcg_gen_nor_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
f24cb33e | 1694 | { |
7fc81051 AJ |
1695 | tcg_gen_or_i32(ret, arg1, arg2); |
1696 | tcg_gen_not_i32(ret, ret); | |
f24cb33e AJ |
1697 | } |
1698 | ||
a7812ae4 | 1699 | static inline void tcg_gen_nor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
f24cb33e | 1700 | { |
7fc81051 AJ |
1701 | tcg_gen_or_i64(ret, arg1, arg2); |
1702 | tcg_gen_not_i64(ret, ret); | |
f24cb33e AJ |
1703 | } |
1704 | ||
a7812ae4 | 1705 | static inline void tcg_gen_orc_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
f24cb33e | 1706 | { |
a7812ae4 PB |
1707 | TCGv_i32 t0; |
1708 | t0 = tcg_temp_new_i32(); | |
f24cb33e AJ |
1709 | tcg_gen_not_i32(t0, arg2); |
1710 | tcg_gen_or_i32(ret, arg1, t0); | |
a7812ae4 | 1711 | tcg_temp_free_i32(t0); |
f24cb33e AJ |
1712 | } |
1713 | ||
a7812ae4 | 1714 | static inline void tcg_gen_orc_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
f24cb33e | 1715 | { |
a7812ae4 PB |
1716 | TCGv_i64 t0; |
1717 | t0 = tcg_temp_new_i64(); | |
f24cb33e AJ |
1718 | tcg_gen_not_i64(t0, arg2); |
1719 | tcg_gen_or_i64(ret, arg1, t0); | |
a7812ae4 | 1720 | tcg_temp_free_i64(t0); |
f24cb33e AJ |
1721 | } |
1722 | ||
a7812ae4 | 1723 | static inline void tcg_gen_rotl_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
15824571 | 1724 | { |
d42f183c AJ |
1725 | #ifdef TCG_TARGET_HAS_rot_i32 |
1726 | tcg_gen_op3_i32(INDEX_op_rotl_i32, ret, arg1, arg2); | |
1727 | #else | |
a7812ae4 | 1728 | TCGv_i32 t0, t1; |
15824571 | 1729 | |
a7812ae4 PB |
1730 | t0 = tcg_temp_new_i32(); |
1731 | t1 = tcg_temp_new_i32(); | |
15824571 AJ |
1732 | tcg_gen_shl_i32(t0, arg1, arg2); |
1733 | tcg_gen_subfi_i32(t1, 32, arg2); | |
1734 | tcg_gen_shr_i32(t1, arg1, t1); | |
1735 | tcg_gen_or_i32(ret, t0, t1); | |
a7812ae4 PB |
1736 | tcg_temp_free_i32(t0); |
1737 | tcg_temp_free_i32(t1); | |
d42f183c | 1738 | #endif |
15824571 AJ |
1739 | } |
1740 | ||
a7812ae4 | 1741 | static inline void tcg_gen_rotl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
15824571 | 1742 | { |
d42f183c AJ |
1743 | #ifdef TCG_TARGET_HAS_rot_i64 |
1744 | tcg_gen_op3_i64(INDEX_op_rotl_i64, ret, arg1, arg2); | |
1745 | #else | |
a7812ae4 | 1746 | TCGv_i64 t0, t1; |
15824571 | 1747 | |
a7812ae4 PB |
1748 | t0 = tcg_temp_new_i64(); |
1749 | t1 = tcg_temp_new_i64(); | |
15824571 AJ |
1750 | tcg_gen_shl_i64(t0, arg1, arg2); |
1751 | tcg_gen_subfi_i64(t1, 64, arg2); | |
1752 | tcg_gen_shr_i64(t1, arg1, t1); | |
1753 | tcg_gen_or_i64(ret, t0, t1); | |
a7812ae4 PB |
1754 | tcg_temp_free_i64(t0); |
1755 | tcg_temp_free_i64(t1); | |
d42f183c | 1756 | #endif |
15824571 AJ |
1757 | } |
1758 | ||
a7812ae4 | 1759 | static inline void tcg_gen_rotli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) |
15824571 AJ |
1760 | { |
1761 | /* some cases can be optimized here */ | |
1762 | if (arg2 == 0) { | |
1763 | tcg_gen_mov_i32(ret, arg1); | |
1764 | } else { | |
d42f183c AJ |
1765 | #ifdef TCG_TARGET_HAS_rot_i32 |
1766 | TCGv_i32 t0 = tcg_const_i32(arg2); | |
1767 | tcg_gen_rotl_i32(ret, arg1, t0); | |
1768 | tcg_temp_free_i32(t0); | |
1769 | #else | |
a7812ae4 PB |
1770 | TCGv_i32 t0, t1; |
1771 | t0 = tcg_temp_new_i32(); | |
1772 | t1 = tcg_temp_new_i32(); | |
15824571 AJ |
1773 | tcg_gen_shli_i32(t0, arg1, arg2); |
1774 | tcg_gen_shri_i32(t1, arg1, 32 - arg2); | |
1775 | tcg_gen_or_i32(ret, t0, t1); | |
a7812ae4 PB |
1776 | tcg_temp_free_i32(t0); |
1777 | tcg_temp_free_i32(t1); | |
d42f183c | 1778 | #endif |
15824571 AJ |
1779 | } |
1780 | } | |
1781 | ||
a7812ae4 | 1782 | static inline void tcg_gen_rotli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
15824571 AJ |
1783 | { |
1784 | /* some cases can be optimized here */ | |
1785 | if (arg2 == 0) { | |
1786 | tcg_gen_mov_i64(ret, arg1); | |
1787 | } else { | |
d42f183c AJ |
1788 | #ifdef TCG_TARGET_HAS_rot_i64 |
1789 | TCGv_i64 t0 = tcg_const_i64(arg2); | |
1790 | tcg_gen_rotl_i64(ret, arg1, t0); | |
1791 | tcg_temp_free_i64(t0); | |
1792 | #else | |
a7812ae4 PB |
1793 | TCGv_i64 t0, t1; |
1794 | t0 = tcg_temp_new_i64(); | |
1795 | t1 = tcg_temp_new_i64(); | |
15824571 AJ |
1796 | tcg_gen_shli_i64(t0, arg1, arg2); |
1797 | tcg_gen_shri_i64(t1, arg1, 64 - arg2); | |
1798 | tcg_gen_or_i64(ret, t0, t1); | |
a7812ae4 PB |
1799 | tcg_temp_free_i64(t0); |
1800 | tcg_temp_free_i64(t1); | |
d42f183c | 1801 | #endif |
15824571 AJ |
1802 | } |
1803 | } | |
1804 | ||
a7812ae4 | 1805 | static inline void tcg_gen_rotr_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
15824571 | 1806 | { |
d42f183c AJ |
1807 | #ifdef TCG_TARGET_HAS_rot_i32 |
1808 | tcg_gen_op3_i32(INDEX_op_rotr_i32, ret, arg1, arg2); | |
1809 | #else | |
a7812ae4 | 1810 | TCGv_i32 t0, t1; |
15824571 | 1811 | |
a7812ae4 PB |
1812 | t0 = tcg_temp_new_i32(); |
1813 | t1 = tcg_temp_new_i32(); | |
15824571 AJ |
1814 | tcg_gen_shr_i32(t0, arg1, arg2); |
1815 | tcg_gen_subfi_i32(t1, 32, arg2); | |
1816 | tcg_gen_shl_i32(t1, arg1, t1); | |
1817 | tcg_gen_or_i32(ret, t0, t1); | |
a7812ae4 PB |
1818 | tcg_temp_free_i32(t0); |
1819 | tcg_temp_free_i32(t1); | |
d42f183c | 1820 | #endif |
15824571 AJ |
1821 | } |
1822 | ||
a7812ae4 | 1823 | static inline void tcg_gen_rotr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
15824571 | 1824 | { |
d42f183c AJ |
1825 | #ifdef TCG_TARGET_HAS_rot_i64 |
1826 | tcg_gen_op3_i64(INDEX_op_rotr_i64, ret, arg1, arg2); | |
1827 | #else | |
a7812ae4 | 1828 | TCGv_i64 t0, t1; |
15824571 | 1829 | |
a7812ae4 PB |
1830 | t0 = tcg_temp_new_i64(); |
1831 | t1 = tcg_temp_new_i64(); | |
d9885a0b | 1832 | tcg_gen_shr_i64(t0, arg1, arg2); |
15824571 AJ |
1833 | tcg_gen_subfi_i64(t1, 64, arg2); |
1834 | tcg_gen_shl_i64(t1, arg1, t1); | |
1835 | tcg_gen_or_i64(ret, t0, t1); | |
a7812ae4 PB |
1836 | tcg_temp_free_i64(t0); |
1837 | tcg_temp_free_i64(t1); | |
d42f183c | 1838 | #endif |
15824571 AJ |
1839 | } |
1840 | ||
a7812ae4 | 1841 | static inline void tcg_gen_rotri_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) |
15824571 AJ |
1842 | { |
1843 | /* some cases can be optimized here */ | |
1844 | if (arg2 == 0) { | |
1845 | tcg_gen_mov_i32(ret, arg1); | |
1846 | } else { | |
1847 | tcg_gen_rotli_i32(ret, arg1, 32 - arg2); | |
1848 | } | |
1849 | } | |
1850 | ||
a7812ae4 | 1851 | static inline void tcg_gen_rotri_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
15824571 AJ |
1852 | { |
1853 | /* some cases can be optimized here */ | |
1854 | if (arg2 == 0) { | |
de3526b2 | 1855 | tcg_gen_mov_i64(ret, arg1); |
15824571 AJ |
1856 | } else { |
1857 | tcg_gen_rotli_i64(ret, arg1, 64 - arg2); | |
1858 | } | |
1859 | } | |
1860 | ||
c896fe29 FB |
1861 | /***************************************/ |
1862 | /* QEMU specific operations. Their type depend on the QEMU CPU | |
1863 | type. */ | |
1864 | #ifndef TARGET_LONG_BITS | |
1865 | #error must include QEMU headers | |
1866 | #endif | |
1867 | ||
a7812ae4 PB |
1868 | #if TARGET_LONG_BITS == 32 |
1869 | #define TCGv TCGv_i32 | |
1870 | #define tcg_temp_new() tcg_temp_new_i32() | |
1871 | #define tcg_global_reg_new tcg_global_reg_new_i32 | |
1872 | #define tcg_global_mem_new tcg_global_mem_new_i32 | |
df9247b2 | 1873 | #define tcg_temp_local_new() tcg_temp_local_new_i32() |
a7812ae4 PB |
1874 | #define tcg_temp_free tcg_temp_free_i32 |
1875 | #define tcg_gen_qemu_ldst_op tcg_gen_op3i_i32 | |
1876 | #define tcg_gen_qemu_ldst_op_i64 tcg_gen_qemu_ldst_op_i64_i32 | |
1877 | #define TCGV_UNUSED(x) TCGV_UNUSED_I32(x) | |
fe75bcf7 | 1878 | #define TCGV_EQUAL(a, b) TCGV_EQUAL_I32(a, b) |
a7812ae4 PB |
1879 | #else |
1880 | #define TCGv TCGv_i64 | |
1881 | #define tcg_temp_new() tcg_temp_new_i64() | |
1882 | #define tcg_global_reg_new tcg_global_reg_new_i64 | |
1883 | #define tcg_global_mem_new tcg_global_mem_new_i64 | |
df9247b2 | 1884 | #define tcg_temp_local_new() tcg_temp_local_new_i64() |
a7812ae4 PB |
1885 | #define tcg_temp_free tcg_temp_free_i64 |
1886 | #define tcg_gen_qemu_ldst_op tcg_gen_op3i_i64 | |
1887 | #define tcg_gen_qemu_ldst_op_i64 tcg_gen_qemu_ldst_op_i64_i64 | |
1888 | #define TCGV_UNUSED(x) TCGV_UNUSED_I64(x) | |
fe75bcf7 | 1889 | #define TCGV_EQUAL(a, b) TCGV_EQUAL_I64(a, b) |
a7812ae4 PB |
1890 | #endif |
1891 | ||
7e4597d7 FB |
1892 | /* debug info: write the PC of the corresponding QEMU CPU instruction */ |
1893 | static inline void tcg_gen_debug_insn_start(uint64_t pc) | |
1894 | { | |
1895 | /* XXX: must really use a 32 bit size for TCGArg in all cases */ | |
1896 | #if TARGET_LONG_BITS > TCG_TARGET_REG_BITS | |
bcb0126f PB |
1897 | tcg_gen_op2ii(INDEX_op_debug_insn_start, |
1898 | (uint32_t)(pc), (uint32_t)(pc >> 32)); | |
7e4597d7 FB |
1899 | #else |
1900 | tcg_gen_op1i(INDEX_op_debug_insn_start, pc); | |
1901 | #endif | |
1902 | } | |
1903 | ||
c896fe29 FB |
1904 | static inline void tcg_gen_exit_tb(tcg_target_long val) |
1905 | { | |
ac56dd48 | 1906 | tcg_gen_op1i(INDEX_op_exit_tb, val); |
c896fe29 FB |
1907 | } |
1908 | ||
1909 | static inline void tcg_gen_goto_tb(int idx) | |
1910 | { | |
ac56dd48 | 1911 | tcg_gen_op1i(INDEX_op_goto_tb, idx); |
c896fe29 FB |
1912 | } |
1913 | ||
1914 | #if TCG_TARGET_REG_BITS == 32 | |
ac56dd48 | 1915 | static inline void tcg_gen_qemu_ld8u(TCGv ret, TCGv addr, int mem_index) |
c896fe29 FB |
1916 | { |
1917 | #if TARGET_LONG_BITS == 32 | |
a7812ae4 | 1918 | tcg_gen_op3i_i32(INDEX_op_qemu_ld8u, ret, addr, mem_index); |
c896fe29 | 1919 | #else |
a7812ae4 PB |
1920 | tcg_gen_op4i_i32(INDEX_op_qemu_ld8u, TCGV_LOW(ret), TCGV_LOW(addr), |
1921 | TCGV_HIGH(addr), mem_index); | |
ac56dd48 | 1922 | tcg_gen_movi_i32(TCGV_HIGH(ret), 0); |
c896fe29 FB |
1923 | #endif |
1924 | } | |
1925 | ||
ac56dd48 | 1926 | static inline void tcg_gen_qemu_ld8s(TCGv ret, TCGv addr, int mem_index) |
c896fe29 FB |
1927 | { |
1928 | #if TARGET_LONG_BITS == 32 | |
a7812ae4 | 1929 | tcg_gen_op3i_i32(INDEX_op_qemu_ld8s, ret, addr, mem_index); |
c896fe29 | 1930 | #else |
a7812ae4 PB |
1931 | tcg_gen_op4i_i32(INDEX_op_qemu_ld8s, TCGV_LOW(ret), TCGV_LOW(addr), |
1932 | TCGV_HIGH(addr), mem_index); | |
1933 | tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31); | |
c896fe29 FB |
1934 | #endif |
1935 | } | |
1936 | ||
ac56dd48 | 1937 | static inline void tcg_gen_qemu_ld16u(TCGv ret, TCGv addr, int mem_index) |
c896fe29 FB |
1938 | { |
1939 | #if TARGET_LONG_BITS == 32 | |
a7812ae4 | 1940 | tcg_gen_op3i_i32(INDEX_op_qemu_ld16u, ret, addr, mem_index); |
c896fe29 | 1941 | #else |
a7812ae4 PB |
1942 | tcg_gen_op4i_i32(INDEX_op_qemu_ld16u, TCGV_LOW(ret), TCGV_LOW(addr), |
1943 | TCGV_HIGH(addr), mem_index); | |
ac56dd48 | 1944 | tcg_gen_movi_i32(TCGV_HIGH(ret), 0); |
c896fe29 FB |
1945 | #endif |
1946 | } | |
1947 | ||
ac56dd48 | 1948 | static inline void tcg_gen_qemu_ld16s(TCGv ret, TCGv addr, int mem_index) |
c896fe29 FB |
1949 | { |
1950 | #if TARGET_LONG_BITS == 32 | |
a7812ae4 | 1951 | tcg_gen_op3i_i32(INDEX_op_qemu_ld16s, ret, addr, mem_index); |
c896fe29 | 1952 | #else |
a7812ae4 PB |
1953 | tcg_gen_op4i_i32(INDEX_op_qemu_ld16s, TCGV_LOW(ret), TCGV_LOW(addr), |
1954 | TCGV_HIGH(addr), mem_index); | |
1955 | tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31); | |
c896fe29 FB |
1956 | #endif |
1957 | } | |
1958 | ||
ac56dd48 | 1959 | static inline void tcg_gen_qemu_ld32u(TCGv ret, TCGv addr, int mem_index) |
c896fe29 FB |
1960 | { |
1961 | #if TARGET_LONG_BITS == 32 | |
a7812ae4 | 1962 | tcg_gen_op3i_i32(INDEX_op_qemu_ld32u, ret, addr, mem_index); |
c896fe29 | 1963 | #else |
a7812ae4 PB |
1964 | tcg_gen_op4i_i32(INDEX_op_qemu_ld32u, TCGV_LOW(ret), TCGV_LOW(addr), |
1965 | TCGV_HIGH(addr), mem_index); | |
ac56dd48 | 1966 | tcg_gen_movi_i32(TCGV_HIGH(ret), 0); |
c896fe29 FB |
1967 | #endif |
1968 | } | |
1969 | ||
ac56dd48 | 1970 | static inline void tcg_gen_qemu_ld32s(TCGv ret, TCGv addr, int mem_index) |
c896fe29 FB |
1971 | { |
1972 | #if TARGET_LONG_BITS == 32 | |
a7812ae4 | 1973 | tcg_gen_op3i_i32(INDEX_op_qemu_ld32u, ret, addr, mem_index); |
c896fe29 | 1974 | #else |
a7812ae4 PB |
1975 | tcg_gen_op4i_i32(INDEX_op_qemu_ld32u, TCGV_LOW(ret), TCGV_LOW(addr), |
1976 | TCGV_HIGH(addr), mem_index); | |
1977 | tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31); | |
c896fe29 FB |
1978 | #endif |
1979 | } | |
1980 | ||
a7812ae4 | 1981 | static inline void tcg_gen_qemu_ld64(TCGv_i64 ret, TCGv addr, int mem_index) |
c896fe29 FB |
1982 | { |
1983 | #if TARGET_LONG_BITS == 32 | |
a7812ae4 | 1984 | tcg_gen_op4i_i32(INDEX_op_qemu_ld64, TCGV_LOW(ret), TCGV_HIGH(ret), addr, mem_index); |
c896fe29 | 1985 | #else |
a7812ae4 PB |
1986 | tcg_gen_op5i_i32(INDEX_op_qemu_ld64, TCGV_LOW(ret), TCGV_HIGH(ret), |
1987 | TCGV_LOW(addr), TCGV_HIGH(addr), mem_index); | |
c896fe29 FB |
1988 | #endif |
1989 | } | |
1990 | ||
ac56dd48 | 1991 | static inline void tcg_gen_qemu_st8(TCGv arg, TCGv addr, int mem_index) |
c896fe29 FB |
1992 | { |
1993 | #if TARGET_LONG_BITS == 32 | |
a7812ae4 | 1994 | tcg_gen_op3i_i32(INDEX_op_qemu_st8, arg, addr, mem_index); |
c896fe29 | 1995 | #else |
a7812ae4 PB |
1996 | tcg_gen_op4i_i32(INDEX_op_qemu_st8, TCGV_LOW(arg), TCGV_LOW(addr), |
1997 | TCGV_HIGH(addr), mem_index); | |
c896fe29 FB |
1998 | #endif |
1999 | } | |
2000 | ||
ac56dd48 | 2001 | static inline void tcg_gen_qemu_st16(TCGv arg, TCGv addr, int mem_index) |
c896fe29 FB |
2002 | { |
2003 | #if TARGET_LONG_BITS == 32 | |
a7812ae4 | 2004 | tcg_gen_op3i_i32(INDEX_op_qemu_st16, arg, addr, mem_index); |
c896fe29 | 2005 | #else |
a7812ae4 PB |
2006 | tcg_gen_op4i_i32(INDEX_op_qemu_st16, TCGV_LOW(arg), TCGV_LOW(addr), |
2007 | TCGV_HIGH(addr), mem_index); | |
c896fe29 FB |
2008 | #endif |
2009 | } | |
2010 | ||
ac56dd48 | 2011 | static inline void tcg_gen_qemu_st32(TCGv arg, TCGv addr, int mem_index) |
c896fe29 FB |
2012 | { |
2013 | #if TARGET_LONG_BITS == 32 | |
a7812ae4 | 2014 | tcg_gen_op3i_i32(INDEX_op_qemu_st32, arg, addr, mem_index); |
c896fe29 | 2015 | #else |
a7812ae4 PB |
2016 | tcg_gen_op4i_i32(INDEX_op_qemu_st32, TCGV_LOW(arg), TCGV_LOW(addr), |
2017 | TCGV_HIGH(addr), mem_index); | |
c896fe29 FB |
2018 | #endif |
2019 | } | |
2020 | ||
a7812ae4 | 2021 | static inline void tcg_gen_qemu_st64(TCGv_i64 arg, TCGv addr, int mem_index) |
c896fe29 FB |
2022 | { |
2023 | #if TARGET_LONG_BITS == 32 | |
a7812ae4 PB |
2024 | tcg_gen_op4i_i32(INDEX_op_qemu_st64, TCGV_LOW(arg), TCGV_HIGH(arg), addr, |
2025 | mem_index); | |
c896fe29 | 2026 | #else |
a7812ae4 PB |
2027 | tcg_gen_op5i_i32(INDEX_op_qemu_st64, TCGV_LOW(arg), TCGV_HIGH(arg), |
2028 | TCGV_LOW(addr), TCGV_HIGH(addr), mem_index); | |
c896fe29 FB |
2029 | #endif |
2030 | } | |
2031 | ||
56b8f567 | 2032 | #define tcg_gen_ld_ptr tcg_gen_ld_i32 |
a768e4b2 | 2033 | #define tcg_gen_discard_ptr tcg_gen_discard_i32 |
f8422f52 | 2034 | |
c896fe29 FB |
2035 | #else /* TCG_TARGET_REG_BITS == 32 */ |
2036 | ||
ac56dd48 | 2037 | static inline void tcg_gen_qemu_ld8u(TCGv ret, TCGv addr, int mem_index) |
c896fe29 | 2038 | { |
a7812ae4 | 2039 | tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld8u, ret, addr, mem_index); |
c896fe29 FB |
2040 | } |
2041 | ||
ac56dd48 | 2042 | static inline void tcg_gen_qemu_ld8s(TCGv ret, TCGv addr, int mem_index) |
c896fe29 | 2043 | { |
a7812ae4 | 2044 | tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld8s, ret, addr, mem_index); |
c896fe29 FB |
2045 | } |
2046 | ||
ac56dd48 | 2047 | static inline void tcg_gen_qemu_ld16u(TCGv ret, TCGv addr, int mem_index) |
c896fe29 | 2048 | { |
a7812ae4 | 2049 | tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld16u, ret, addr, mem_index); |
c896fe29 FB |
2050 | } |
2051 | ||
ac56dd48 | 2052 | static inline void tcg_gen_qemu_ld16s(TCGv ret, TCGv addr, int mem_index) |
c896fe29 | 2053 | { |
a7812ae4 | 2054 | tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld16s, ret, addr, mem_index); |
c896fe29 FB |
2055 | } |
2056 | ||
ac56dd48 | 2057 | static inline void tcg_gen_qemu_ld32u(TCGv ret, TCGv addr, int mem_index) |
c896fe29 | 2058 | { |
a7812ae4 | 2059 | tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld32u, ret, addr, mem_index); |
c896fe29 FB |
2060 | } |
2061 | ||
ac56dd48 | 2062 | static inline void tcg_gen_qemu_ld32s(TCGv ret, TCGv addr, int mem_index) |
c896fe29 | 2063 | { |
a7812ae4 | 2064 | tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld32s, ret, addr, mem_index); |
c896fe29 FB |
2065 | } |
2066 | ||
a7812ae4 | 2067 | static inline void tcg_gen_qemu_ld64(TCGv_i64 ret, TCGv addr, int mem_index) |
c896fe29 | 2068 | { |
a7812ae4 | 2069 | tcg_gen_qemu_ldst_op_i64(INDEX_op_qemu_ld64, ret, addr, mem_index); |
c896fe29 FB |
2070 | } |
2071 | ||
ac56dd48 | 2072 | static inline void tcg_gen_qemu_st8(TCGv arg, TCGv addr, int mem_index) |
c896fe29 | 2073 | { |
a7812ae4 | 2074 | tcg_gen_qemu_ldst_op(INDEX_op_qemu_st8, arg, addr, mem_index); |
c896fe29 FB |
2075 | } |
2076 | ||
ac56dd48 | 2077 | static inline void tcg_gen_qemu_st16(TCGv arg, TCGv addr, int mem_index) |
c896fe29 | 2078 | { |
a7812ae4 | 2079 | tcg_gen_qemu_ldst_op(INDEX_op_qemu_st16, arg, addr, mem_index); |
c896fe29 FB |
2080 | } |
2081 | ||
ac56dd48 | 2082 | static inline void tcg_gen_qemu_st32(TCGv arg, TCGv addr, int mem_index) |
c896fe29 | 2083 | { |
a7812ae4 | 2084 | tcg_gen_qemu_ldst_op(INDEX_op_qemu_st32, arg, addr, mem_index); |
c896fe29 FB |
2085 | } |
2086 | ||
a7812ae4 | 2087 | static inline void tcg_gen_qemu_st64(TCGv_i64 arg, TCGv addr, int mem_index) |
c896fe29 | 2088 | { |
a7812ae4 | 2089 | tcg_gen_qemu_ldst_op_i64(INDEX_op_qemu_st64, arg, addr, mem_index); |
c896fe29 FB |
2090 | } |
2091 | ||
56b8f567 | 2092 | #define tcg_gen_ld_ptr tcg_gen_ld_i64 |
a768e4b2 | 2093 | #define tcg_gen_discard_ptr tcg_gen_discard_i64 |
f8422f52 | 2094 | |
c896fe29 | 2095 | #endif /* TCG_TARGET_REG_BITS != 32 */ |
f8422f52 BS |
2096 | |
2097 | #if TARGET_LONG_BITS == 64 | |
2098 | #define TCG_TYPE_TL TCG_TYPE_I64 | |
2099 | #define tcg_gen_movi_tl tcg_gen_movi_i64 | |
2100 | #define tcg_gen_mov_tl tcg_gen_mov_i64 | |
2101 | #define tcg_gen_ld8u_tl tcg_gen_ld8u_i64 | |
2102 | #define tcg_gen_ld8s_tl tcg_gen_ld8s_i64 | |
2103 | #define tcg_gen_ld16u_tl tcg_gen_ld16u_i64 | |
2104 | #define tcg_gen_ld16s_tl tcg_gen_ld16s_i64 | |
2105 | #define tcg_gen_ld32u_tl tcg_gen_ld32u_i64 | |
2106 | #define tcg_gen_ld32s_tl tcg_gen_ld32s_i64 | |
2107 | #define tcg_gen_ld_tl tcg_gen_ld_i64 | |
2108 | #define tcg_gen_st8_tl tcg_gen_st8_i64 | |
2109 | #define tcg_gen_st16_tl tcg_gen_st16_i64 | |
2110 | #define tcg_gen_st32_tl tcg_gen_st32_i64 | |
2111 | #define tcg_gen_st_tl tcg_gen_st_i64 | |
2112 | #define tcg_gen_add_tl tcg_gen_add_i64 | |
2113 | #define tcg_gen_addi_tl tcg_gen_addi_i64 | |
2114 | #define tcg_gen_sub_tl tcg_gen_sub_i64 | |
390efc54 | 2115 | #define tcg_gen_neg_tl tcg_gen_neg_i64 |
10460c8a | 2116 | #define tcg_gen_subfi_tl tcg_gen_subfi_i64 |
f8422f52 BS |
2117 | #define tcg_gen_subi_tl tcg_gen_subi_i64 |
2118 | #define tcg_gen_and_tl tcg_gen_and_i64 | |
2119 | #define tcg_gen_andi_tl tcg_gen_andi_i64 | |
2120 | #define tcg_gen_or_tl tcg_gen_or_i64 | |
2121 | #define tcg_gen_ori_tl tcg_gen_ori_i64 | |
2122 | #define tcg_gen_xor_tl tcg_gen_xor_i64 | |
2123 | #define tcg_gen_xori_tl tcg_gen_xori_i64 | |
0b6ce4cf | 2124 | #define tcg_gen_not_tl tcg_gen_not_i64 |
f8422f52 BS |
2125 | #define tcg_gen_shl_tl tcg_gen_shl_i64 |
2126 | #define tcg_gen_shli_tl tcg_gen_shli_i64 | |
2127 | #define tcg_gen_shr_tl tcg_gen_shr_i64 | |
2128 | #define tcg_gen_shri_tl tcg_gen_shri_i64 | |
2129 | #define tcg_gen_sar_tl tcg_gen_sar_i64 | |
2130 | #define tcg_gen_sari_tl tcg_gen_sari_i64 | |
0cf767d6 | 2131 | #define tcg_gen_brcond_tl tcg_gen_brcond_i64 |
cb63669a | 2132 | #define tcg_gen_brcondi_tl tcg_gen_brcondi_i64 |
be210acb | 2133 | #define tcg_gen_setcond_tl tcg_gen_setcond_i64 |
add1e7ea | 2134 | #define tcg_gen_setcondi_tl tcg_gen_setcondi_i64 |
f730fd27 TS |
2135 | #define tcg_gen_mul_tl tcg_gen_mul_i64 |
2136 | #define tcg_gen_muli_tl tcg_gen_muli_i64 | |
ab36421e AJ |
2137 | #define tcg_gen_div_tl tcg_gen_div_i64 |
2138 | #define tcg_gen_rem_tl tcg_gen_rem_i64 | |
864951af AJ |
2139 | #define tcg_gen_divu_tl tcg_gen_divu_i64 |
2140 | #define tcg_gen_remu_tl tcg_gen_remu_i64 | |
a768e4b2 | 2141 | #define tcg_gen_discard_tl tcg_gen_discard_i64 |
e429073d BS |
2142 | #define tcg_gen_trunc_tl_i32 tcg_gen_trunc_i64_i32 |
2143 | #define tcg_gen_trunc_i64_tl tcg_gen_mov_i64 | |
2144 | #define tcg_gen_extu_i32_tl tcg_gen_extu_i32_i64 | |
2145 | #define tcg_gen_ext_i32_tl tcg_gen_ext_i32_i64 | |
2146 | #define tcg_gen_extu_tl_i64 tcg_gen_mov_i64 | |
2147 | #define tcg_gen_ext_tl_i64 tcg_gen_mov_i64 | |
0b6ce4cf FB |
2148 | #define tcg_gen_ext8u_tl tcg_gen_ext8u_i64 |
2149 | #define tcg_gen_ext8s_tl tcg_gen_ext8s_i64 | |
2150 | #define tcg_gen_ext16u_tl tcg_gen_ext16u_i64 | |
2151 | #define tcg_gen_ext16s_tl tcg_gen_ext16s_i64 | |
2152 | #define tcg_gen_ext32u_tl tcg_gen_ext32u_i64 | |
2153 | #define tcg_gen_ext32s_tl tcg_gen_ext32s_i64 | |
911d79ba AJ |
2154 | #define tcg_gen_bswap16_tl tcg_gen_bswap16_i64 |
2155 | #define tcg_gen_bswap32_tl tcg_gen_bswap32_i64 | |
2156 | #define tcg_gen_bswap64_tl tcg_gen_bswap64_i64 | |
945ca823 | 2157 | #define tcg_gen_concat_tl_i64 tcg_gen_concat32_i64 |
f24cb33e AJ |
2158 | #define tcg_gen_andc_tl tcg_gen_andc_i64 |
2159 | #define tcg_gen_eqv_tl tcg_gen_eqv_i64 | |
2160 | #define tcg_gen_nand_tl tcg_gen_nand_i64 | |
2161 | #define tcg_gen_nor_tl tcg_gen_nor_i64 | |
2162 | #define tcg_gen_orc_tl tcg_gen_orc_i64 | |
15824571 AJ |
2163 | #define tcg_gen_rotl_tl tcg_gen_rotl_i64 |
2164 | #define tcg_gen_rotli_tl tcg_gen_rotli_i64 | |
2165 | #define tcg_gen_rotr_tl tcg_gen_rotr_i64 | |
2166 | #define tcg_gen_rotri_tl tcg_gen_rotri_i64 | |
a98824ac | 2167 | #define tcg_const_tl tcg_const_i64 |
bdffd4a9 | 2168 | #define tcg_const_local_tl tcg_const_local_i64 |
f8422f52 BS |
2169 | #else |
2170 | #define TCG_TYPE_TL TCG_TYPE_I32 | |
2171 | #define tcg_gen_movi_tl tcg_gen_movi_i32 | |
2172 | #define tcg_gen_mov_tl tcg_gen_mov_i32 | |
2173 | #define tcg_gen_ld8u_tl tcg_gen_ld8u_i32 | |
2174 | #define tcg_gen_ld8s_tl tcg_gen_ld8s_i32 | |
2175 | #define tcg_gen_ld16u_tl tcg_gen_ld16u_i32 | |
2176 | #define tcg_gen_ld16s_tl tcg_gen_ld16s_i32 | |
2177 | #define tcg_gen_ld32u_tl tcg_gen_ld_i32 | |
2178 | #define tcg_gen_ld32s_tl tcg_gen_ld_i32 | |
2179 | #define tcg_gen_ld_tl tcg_gen_ld_i32 | |
2180 | #define tcg_gen_st8_tl tcg_gen_st8_i32 | |
2181 | #define tcg_gen_st16_tl tcg_gen_st16_i32 | |
2182 | #define tcg_gen_st32_tl tcg_gen_st_i32 | |
2183 | #define tcg_gen_st_tl tcg_gen_st_i32 | |
2184 | #define tcg_gen_add_tl tcg_gen_add_i32 | |
2185 | #define tcg_gen_addi_tl tcg_gen_addi_i32 | |
2186 | #define tcg_gen_sub_tl tcg_gen_sub_i32 | |
390efc54 | 2187 | #define tcg_gen_neg_tl tcg_gen_neg_i32 |
0045734a | 2188 | #define tcg_gen_subfi_tl tcg_gen_subfi_i32 |
f8422f52 BS |
2189 | #define tcg_gen_subi_tl tcg_gen_subi_i32 |
2190 | #define tcg_gen_and_tl tcg_gen_and_i32 | |
2191 | #define tcg_gen_andi_tl tcg_gen_andi_i32 | |
2192 | #define tcg_gen_or_tl tcg_gen_or_i32 | |
2193 | #define tcg_gen_ori_tl tcg_gen_ori_i32 | |
2194 | #define tcg_gen_xor_tl tcg_gen_xor_i32 | |
2195 | #define tcg_gen_xori_tl tcg_gen_xori_i32 | |
0b6ce4cf | 2196 | #define tcg_gen_not_tl tcg_gen_not_i32 |
f8422f52 BS |
2197 | #define tcg_gen_shl_tl tcg_gen_shl_i32 |
2198 | #define tcg_gen_shli_tl tcg_gen_shli_i32 | |
2199 | #define tcg_gen_shr_tl tcg_gen_shr_i32 | |
2200 | #define tcg_gen_shri_tl tcg_gen_shri_i32 | |
2201 | #define tcg_gen_sar_tl tcg_gen_sar_i32 | |
2202 | #define tcg_gen_sari_tl tcg_gen_sari_i32 | |
0cf767d6 | 2203 | #define tcg_gen_brcond_tl tcg_gen_brcond_i32 |
cb63669a | 2204 | #define tcg_gen_brcondi_tl tcg_gen_brcondi_i32 |
be210acb | 2205 | #define tcg_gen_setcond_tl tcg_gen_setcond_i32 |
add1e7ea | 2206 | #define tcg_gen_setcondi_tl tcg_gen_setcondi_i32 |
f730fd27 TS |
2207 | #define tcg_gen_mul_tl tcg_gen_mul_i32 |
2208 | #define tcg_gen_muli_tl tcg_gen_muli_i32 | |
ab36421e AJ |
2209 | #define tcg_gen_div_tl tcg_gen_div_i32 |
2210 | #define tcg_gen_rem_tl tcg_gen_rem_i32 | |
864951af AJ |
2211 | #define tcg_gen_divu_tl tcg_gen_divu_i32 |
2212 | #define tcg_gen_remu_tl tcg_gen_remu_i32 | |
a768e4b2 | 2213 | #define tcg_gen_discard_tl tcg_gen_discard_i32 |
e429073d BS |
2214 | #define tcg_gen_trunc_tl_i32 tcg_gen_mov_i32 |
2215 | #define tcg_gen_trunc_i64_tl tcg_gen_trunc_i64_i32 | |
2216 | #define tcg_gen_extu_i32_tl tcg_gen_mov_i32 | |
2217 | #define tcg_gen_ext_i32_tl tcg_gen_mov_i32 | |
2218 | #define tcg_gen_extu_tl_i64 tcg_gen_extu_i32_i64 | |
2219 | #define tcg_gen_ext_tl_i64 tcg_gen_ext_i32_i64 | |
0b6ce4cf FB |
2220 | #define tcg_gen_ext8u_tl tcg_gen_ext8u_i32 |
2221 | #define tcg_gen_ext8s_tl tcg_gen_ext8s_i32 | |
2222 | #define tcg_gen_ext16u_tl tcg_gen_ext16u_i32 | |
2223 | #define tcg_gen_ext16s_tl tcg_gen_ext16s_i32 | |
2224 | #define tcg_gen_ext32u_tl tcg_gen_mov_i32 | |
2225 | #define tcg_gen_ext32s_tl tcg_gen_mov_i32 | |
911d79ba AJ |
2226 | #define tcg_gen_bswap16_tl tcg_gen_bswap16_i32 |
2227 | #define tcg_gen_bswap32_tl tcg_gen_bswap32_i32 | |
945ca823 | 2228 | #define tcg_gen_concat_tl_i64 tcg_gen_concat_i32_i64 |
f24cb33e AJ |
2229 | #define tcg_gen_andc_tl tcg_gen_andc_i32 |
2230 | #define tcg_gen_eqv_tl tcg_gen_eqv_i32 | |
2231 | #define tcg_gen_nand_tl tcg_gen_nand_i32 | |
2232 | #define tcg_gen_nor_tl tcg_gen_nor_i32 | |
2233 | #define tcg_gen_orc_tl tcg_gen_orc_i32 | |
15824571 AJ |
2234 | #define tcg_gen_rotl_tl tcg_gen_rotl_i32 |
2235 | #define tcg_gen_rotli_tl tcg_gen_rotli_i32 | |
2236 | #define tcg_gen_rotr_tl tcg_gen_rotr_i32 | |
2237 | #define tcg_gen_rotri_tl tcg_gen_rotri_i32 | |
a98824ac | 2238 | #define tcg_const_tl tcg_const_i32 |
bdffd4a9 | 2239 | #define tcg_const_local_tl tcg_const_local_i32 |
f8422f52 | 2240 | #endif |
6ddbc6e4 PB |
2241 | |
2242 | #if TCG_TARGET_REG_BITS == 32 | |
48d38ca5 | 2243 | #define tcg_gen_add_ptr tcg_gen_add_i32 |
6ddbc6e4 | 2244 | #define tcg_gen_addi_ptr tcg_gen_addi_i32 |
48d38ca5 | 2245 | #define tcg_gen_ext_i32_ptr tcg_gen_mov_i32 |
6ddbc6e4 | 2246 | #else /* TCG_TARGET_REG_BITS == 32 */ |
48d38ca5 | 2247 | #define tcg_gen_add_ptr tcg_gen_add_i64 |
6ddbc6e4 | 2248 | #define tcg_gen_addi_ptr tcg_gen_addi_i64 |
48d38ca5 | 2249 | #define tcg_gen_ext_i32_ptr tcg_gen_ext_i32_i64 |
6ddbc6e4 | 2250 | #endif /* TCG_TARGET_REG_BITS != 32 */ |