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c896fe29 FB |
1 | /* |
2 | * Tiny Code Generator for QEMU | |
3 | * | |
4 | * Copyright (c) 2008 Fabrice Bellard | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
24 | #include "tcg.h" | |
25 | ||
c896fe29 FB |
26 | int gen_new_label(void); |
27 | ||
a7812ae4 | 28 | static inline void tcg_gen_op1_i32(int opc, TCGv_i32 arg1) |
c896fe29 FB |
29 | { |
30 | *gen_opc_ptr++ = opc; | |
a7812ae4 PB |
31 | *gen_opparam_ptr++ = GET_TCGV_I32(arg1); |
32 | } | |
33 | ||
34 | static inline void tcg_gen_op1_i64(int opc, TCGv_i64 arg1) | |
35 | { | |
36 | *gen_opc_ptr++ = opc; | |
37 | *gen_opparam_ptr++ = GET_TCGV_I64(arg1); | |
c896fe29 FB |
38 | } |
39 | ||
ac56dd48 | 40 | static inline void tcg_gen_op1i(int opc, TCGArg arg1) |
c896fe29 FB |
41 | { |
42 | *gen_opc_ptr++ = opc; | |
43 | *gen_opparam_ptr++ = arg1; | |
c896fe29 FB |
44 | } |
45 | ||
a7812ae4 PB |
46 | static inline void tcg_gen_op2_i32(int opc, TCGv_i32 arg1, TCGv_i32 arg2) |
47 | { | |
48 | *gen_opc_ptr++ = opc; | |
49 | *gen_opparam_ptr++ = GET_TCGV_I32(arg1); | |
50 | *gen_opparam_ptr++ = GET_TCGV_I32(arg2); | |
51 | } | |
52 | ||
53 | static inline void tcg_gen_op2_i64(int opc, TCGv_i64 arg1, TCGv_i64 arg2) | |
54 | { | |
55 | *gen_opc_ptr++ = opc; | |
56 | *gen_opparam_ptr++ = GET_TCGV_I64(arg1); | |
57 | *gen_opparam_ptr++ = GET_TCGV_I64(arg2); | |
58 | } | |
59 | ||
60 | static inline void tcg_gen_op2i_i32(int opc, TCGv_i32 arg1, TCGArg arg2) | |
c896fe29 FB |
61 | { |
62 | *gen_opc_ptr++ = opc; | |
a7812ae4 PB |
63 | *gen_opparam_ptr++ = GET_TCGV_I32(arg1); |
64 | *gen_opparam_ptr++ = arg2; | |
c896fe29 FB |
65 | } |
66 | ||
a7812ae4 | 67 | static inline void tcg_gen_op2i_i64(int opc, TCGv_i64 arg1, TCGArg arg2) |
c896fe29 FB |
68 | { |
69 | *gen_opc_ptr++ = opc; | |
a7812ae4 | 70 | *gen_opparam_ptr++ = GET_TCGV_I64(arg1); |
c896fe29 | 71 | *gen_opparam_ptr++ = arg2; |
ac56dd48 PB |
72 | } |
73 | ||
bcb0126f PB |
74 | static inline void tcg_gen_op2ii(int opc, TCGArg arg1, TCGArg arg2) |
75 | { | |
76 | *gen_opc_ptr++ = opc; | |
77 | *gen_opparam_ptr++ = arg1; | |
78 | *gen_opparam_ptr++ = arg2; | |
79 | } | |
80 | ||
a7812ae4 PB |
81 | static inline void tcg_gen_op3_i32(int opc, TCGv_i32 arg1, TCGv_i32 arg2, |
82 | TCGv_i32 arg3) | |
83 | { | |
84 | *gen_opc_ptr++ = opc; | |
85 | *gen_opparam_ptr++ = GET_TCGV_I32(arg1); | |
86 | *gen_opparam_ptr++ = GET_TCGV_I32(arg2); | |
87 | *gen_opparam_ptr++ = GET_TCGV_I32(arg3); | |
88 | } | |
89 | ||
90 | static inline void tcg_gen_op3_i64(int opc, TCGv_i64 arg1, TCGv_i64 arg2, | |
91 | TCGv_i64 arg3) | |
92 | { | |
93 | *gen_opc_ptr++ = opc; | |
94 | *gen_opparam_ptr++ = GET_TCGV_I64(arg1); | |
95 | *gen_opparam_ptr++ = GET_TCGV_I64(arg2); | |
96 | *gen_opparam_ptr++ = GET_TCGV_I64(arg3); | |
97 | } | |
98 | ||
99 | static inline void tcg_gen_op3i_i32(int opc, TCGv_i32 arg1, TCGv_i32 arg2, | |
100 | TCGArg arg3) | |
ac56dd48 PB |
101 | { |
102 | *gen_opc_ptr++ = opc; | |
a7812ae4 PB |
103 | *gen_opparam_ptr++ = GET_TCGV_I32(arg1); |
104 | *gen_opparam_ptr++ = GET_TCGV_I32(arg2); | |
105 | *gen_opparam_ptr++ = arg3; | |
ac56dd48 PB |
106 | } |
107 | ||
a7812ae4 PB |
108 | static inline void tcg_gen_op3i_i64(int opc, TCGv_i64 arg1, TCGv_i64 arg2, |
109 | TCGArg arg3) | |
ac56dd48 PB |
110 | { |
111 | *gen_opc_ptr++ = opc; | |
a7812ae4 PB |
112 | *gen_opparam_ptr++ = GET_TCGV_I64(arg1); |
113 | *gen_opparam_ptr++ = GET_TCGV_I64(arg2); | |
c896fe29 | 114 | *gen_opparam_ptr++ = arg3; |
ac56dd48 PB |
115 | } |
116 | ||
a7812ae4 PB |
117 | static inline void tcg_gen_ldst_op_i32(int opc, TCGv_i32 val, TCGv_ptr base, |
118 | TCGArg offset) | |
119 | { | |
120 | *gen_opc_ptr++ = opc; | |
121 | *gen_opparam_ptr++ = GET_TCGV_I32(val); | |
122 | *gen_opparam_ptr++ = GET_TCGV_PTR(base); | |
123 | *gen_opparam_ptr++ = offset; | |
124 | } | |
125 | ||
126 | static inline void tcg_gen_ldst_op_i64(int opc, TCGv_i64 val, TCGv_ptr base, | |
127 | TCGArg offset) | |
128 | { | |
129 | *gen_opc_ptr++ = opc; | |
a810a2de | 130 | *gen_opparam_ptr++ = GET_TCGV_I64(val); |
a7812ae4 PB |
131 | *gen_opparam_ptr++ = GET_TCGV_PTR(base); |
132 | *gen_opparam_ptr++ = offset; | |
133 | } | |
134 | ||
135 | static inline void tcg_gen_qemu_ldst_op_i64_i32(int opc, TCGv_i64 val, TCGv_i32 addr, | |
136 | TCGArg mem_index) | |
137 | { | |
138 | *gen_opc_ptr++ = opc; | |
139 | *gen_opparam_ptr++ = GET_TCGV_I64(val); | |
140 | *gen_opparam_ptr++ = GET_TCGV_I32(addr); | |
141 | *gen_opparam_ptr++ = mem_index; | |
142 | } | |
143 | ||
144 | static inline void tcg_gen_qemu_ldst_op_i64_i64(int opc, TCGv_i64 val, TCGv_i64 addr, | |
145 | TCGArg mem_index) | |
146 | { | |
147 | *gen_opc_ptr++ = opc; | |
148 | *gen_opparam_ptr++ = GET_TCGV_I64(val); | |
149 | *gen_opparam_ptr++ = GET_TCGV_I64(addr); | |
150 | *gen_opparam_ptr++ = mem_index; | |
151 | } | |
152 | ||
153 | static inline void tcg_gen_op4_i32(int opc, TCGv_i32 arg1, TCGv_i32 arg2, | |
154 | TCGv_i32 arg3, TCGv_i32 arg4) | |
155 | { | |
156 | *gen_opc_ptr++ = opc; | |
157 | *gen_opparam_ptr++ = GET_TCGV_I32(arg1); | |
158 | *gen_opparam_ptr++ = GET_TCGV_I32(arg2); | |
159 | *gen_opparam_ptr++ = GET_TCGV_I32(arg3); | |
160 | *gen_opparam_ptr++ = GET_TCGV_I32(arg4); | |
161 | } | |
162 | ||
163 | static inline void tcg_gen_op4_i64(int opc, TCGv_i64 arg1, TCGv_i64 arg2, | |
a810a2de | 164 | TCGv_i64 arg3, TCGv_i64 arg4) |
a7812ae4 PB |
165 | { |
166 | *gen_opc_ptr++ = opc; | |
167 | *gen_opparam_ptr++ = GET_TCGV_I64(arg1); | |
168 | *gen_opparam_ptr++ = GET_TCGV_I64(arg2); | |
169 | *gen_opparam_ptr++ = GET_TCGV_I64(arg3); | |
170 | *gen_opparam_ptr++ = GET_TCGV_I64(arg4); | |
171 | } | |
172 | ||
173 | static inline void tcg_gen_op4i_i32(int opc, TCGv_i32 arg1, TCGv_i32 arg2, | |
174 | TCGv_i32 arg3, TCGArg arg4) | |
175 | { | |
176 | *gen_opc_ptr++ = opc; | |
177 | *gen_opparam_ptr++ = GET_TCGV_I32(arg1); | |
178 | *gen_opparam_ptr++ = GET_TCGV_I32(arg2); | |
179 | *gen_opparam_ptr++ = GET_TCGV_I32(arg3); | |
180 | *gen_opparam_ptr++ = arg4; | |
181 | } | |
182 | ||
183 | static inline void tcg_gen_op4i_i64(int opc, TCGv_i64 arg1, TCGv_i64 arg2, | |
184 | TCGv_i64 arg3, TCGArg arg4) | |
ac56dd48 PB |
185 | { |
186 | *gen_opc_ptr++ = opc; | |
a7812ae4 PB |
187 | *gen_opparam_ptr++ = GET_TCGV_I64(arg1); |
188 | *gen_opparam_ptr++ = GET_TCGV_I64(arg2); | |
189 | *gen_opparam_ptr++ = GET_TCGV_I64(arg3); | |
190 | *gen_opparam_ptr++ = arg4; | |
ac56dd48 PB |
191 | } |
192 | ||
a7812ae4 PB |
193 | static inline void tcg_gen_op4ii_i32(int opc, TCGv_i32 arg1, TCGv_i32 arg2, |
194 | TCGArg arg3, TCGArg arg4) | |
ac56dd48 PB |
195 | { |
196 | *gen_opc_ptr++ = opc; | |
a7812ae4 PB |
197 | *gen_opparam_ptr++ = GET_TCGV_I32(arg1); |
198 | *gen_opparam_ptr++ = GET_TCGV_I32(arg2); | |
199 | *gen_opparam_ptr++ = arg3; | |
c896fe29 FB |
200 | *gen_opparam_ptr++ = arg4; |
201 | } | |
202 | ||
a7812ae4 PB |
203 | static inline void tcg_gen_op4ii_i64(int opc, TCGv_i64 arg1, TCGv_i64 arg2, |
204 | TCGArg arg3, TCGArg arg4) | |
c896fe29 FB |
205 | { |
206 | *gen_opc_ptr++ = opc; | |
a7812ae4 PB |
207 | *gen_opparam_ptr++ = GET_TCGV_I64(arg1); |
208 | *gen_opparam_ptr++ = GET_TCGV_I64(arg2); | |
c896fe29 FB |
209 | *gen_opparam_ptr++ = arg3; |
210 | *gen_opparam_ptr++ = arg4; | |
ac56dd48 PB |
211 | } |
212 | ||
a7812ae4 PB |
213 | static inline void tcg_gen_op5_i32(int opc, TCGv_i32 arg1, TCGv_i32 arg2, |
214 | TCGv_i32 arg3, TCGv_i32 arg4, TCGv_i32 arg5) | |
215 | { | |
216 | *gen_opc_ptr++ = opc; | |
217 | *gen_opparam_ptr++ = GET_TCGV_I32(arg1); | |
218 | *gen_opparam_ptr++ = GET_TCGV_I32(arg2); | |
219 | *gen_opparam_ptr++ = GET_TCGV_I32(arg3); | |
220 | *gen_opparam_ptr++ = GET_TCGV_I32(arg4); | |
221 | *gen_opparam_ptr++ = GET_TCGV_I32(arg5); | |
222 | } | |
223 | ||
224 | static inline void tcg_gen_op5_i64(int opc, TCGv_i64 arg1, TCGv_i64 arg2, | |
225 | TCGv_i64 arg3, TCGv_i64 arg4, TCGv_i64 arg5) | |
226 | { | |
227 | *gen_opc_ptr++ = opc; | |
228 | *gen_opparam_ptr++ = GET_TCGV_I64(arg1); | |
229 | *gen_opparam_ptr++ = GET_TCGV_I64(arg2); | |
230 | *gen_opparam_ptr++ = GET_TCGV_I64(arg3); | |
231 | *gen_opparam_ptr++ = GET_TCGV_I64(arg4); | |
232 | *gen_opparam_ptr++ = GET_TCGV_I64(arg5); | |
233 | } | |
234 | ||
235 | static inline void tcg_gen_op5i_i32(int opc, TCGv_i32 arg1, TCGv_i32 arg2, | |
236 | TCGv_i32 arg3, TCGv_i32 arg4, TCGArg arg5) | |
ac56dd48 PB |
237 | { |
238 | *gen_opc_ptr++ = opc; | |
a7812ae4 PB |
239 | *gen_opparam_ptr++ = GET_TCGV_I32(arg1); |
240 | *gen_opparam_ptr++ = GET_TCGV_I32(arg2); | |
241 | *gen_opparam_ptr++ = GET_TCGV_I32(arg3); | |
242 | *gen_opparam_ptr++ = GET_TCGV_I32(arg4); | |
243 | *gen_opparam_ptr++ = arg5; | |
ac56dd48 PB |
244 | } |
245 | ||
a7812ae4 PB |
246 | static inline void tcg_gen_op5i_i64(int opc, TCGv_i64 arg1, TCGv_i64 arg2, |
247 | TCGv_i64 arg3, TCGv_i64 arg4, TCGArg arg5) | |
ac56dd48 PB |
248 | { |
249 | *gen_opc_ptr++ = opc; | |
a7812ae4 PB |
250 | *gen_opparam_ptr++ = GET_TCGV_I64(arg1); |
251 | *gen_opparam_ptr++ = GET_TCGV_I64(arg2); | |
252 | *gen_opparam_ptr++ = GET_TCGV_I64(arg3); | |
253 | *gen_opparam_ptr++ = GET_TCGV_I64(arg4); | |
c896fe29 FB |
254 | *gen_opparam_ptr++ = arg5; |
255 | } | |
256 | ||
a7812ae4 PB |
257 | static inline void tcg_gen_op6_i32(int opc, TCGv_i32 arg1, TCGv_i32 arg2, |
258 | TCGv_i32 arg3, TCGv_i32 arg4, TCGv_i32 arg5, | |
259 | TCGv_i32 arg6) | |
260 | { | |
261 | *gen_opc_ptr++ = opc; | |
262 | *gen_opparam_ptr++ = GET_TCGV_I32(arg1); | |
263 | *gen_opparam_ptr++ = GET_TCGV_I32(arg2); | |
264 | *gen_opparam_ptr++ = GET_TCGV_I32(arg3); | |
265 | *gen_opparam_ptr++ = GET_TCGV_I32(arg4); | |
266 | *gen_opparam_ptr++ = GET_TCGV_I32(arg5); | |
267 | *gen_opparam_ptr++ = GET_TCGV_I32(arg6); | |
268 | } | |
269 | ||
270 | static inline void tcg_gen_op6_i64(int opc, TCGv_i64 arg1, TCGv_i64 arg2, | |
271 | TCGv_i64 arg3, TCGv_i64 arg4, TCGv_i64 arg5, | |
272 | TCGv_i64 arg6) | |
c896fe29 FB |
273 | { |
274 | *gen_opc_ptr++ = opc; | |
a7812ae4 PB |
275 | *gen_opparam_ptr++ = GET_TCGV_I64(arg1); |
276 | *gen_opparam_ptr++ = GET_TCGV_I64(arg2); | |
277 | *gen_opparam_ptr++ = GET_TCGV_I64(arg3); | |
278 | *gen_opparam_ptr++ = GET_TCGV_I64(arg4); | |
279 | *gen_opparam_ptr++ = GET_TCGV_I64(arg5); | |
280 | *gen_opparam_ptr++ = GET_TCGV_I64(arg6); | |
ac56dd48 PB |
281 | } |
282 | ||
be210acb RH |
283 | static inline void tcg_gen_op6i_i32(int opc, TCGv_i32 arg1, TCGv_i32 arg2, |
284 | TCGv_i32 arg3, TCGv_i32 arg4, | |
285 | TCGv_i32 arg5, TCGArg arg6) | |
286 | { | |
287 | *gen_opc_ptr++ = opc; | |
288 | *gen_opparam_ptr++ = GET_TCGV_I32(arg1); | |
289 | *gen_opparam_ptr++ = GET_TCGV_I32(arg2); | |
290 | *gen_opparam_ptr++ = GET_TCGV_I32(arg3); | |
291 | *gen_opparam_ptr++ = GET_TCGV_I32(arg4); | |
292 | *gen_opparam_ptr++ = GET_TCGV_I32(arg5); | |
293 | *gen_opparam_ptr++ = arg6; | |
294 | } | |
295 | ||
296 | static inline void tcg_gen_op6i_i64(int opc, TCGv_i64 arg1, TCGv_i64 arg2, | |
297 | TCGv_i64 arg3, TCGv_i64 arg4, | |
298 | TCGv_i64 arg5, TCGArg arg6) | |
299 | { | |
300 | *gen_opc_ptr++ = opc; | |
301 | *gen_opparam_ptr++ = GET_TCGV_I64(arg1); | |
302 | *gen_opparam_ptr++ = GET_TCGV_I64(arg2); | |
303 | *gen_opparam_ptr++ = GET_TCGV_I64(arg3); | |
304 | *gen_opparam_ptr++ = GET_TCGV_I64(arg4); | |
305 | *gen_opparam_ptr++ = GET_TCGV_I64(arg5); | |
306 | *gen_opparam_ptr++ = arg6; | |
307 | } | |
308 | ||
a7812ae4 PB |
309 | static inline void tcg_gen_op6ii_i32(int opc, TCGv_i32 arg1, TCGv_i32 arg2, |
310 | TCGv_i32 arg3, TCGv_i32 arg4, TCGArg arg5, | |
311 | TCGArg arg6) | |
ac56dd48 PB |
312 | { |
313 | *gen_opc_ptr++ = opc; | |
a7812ae4 PB |
314 | *gen_opparam_ptr++ = GET_TCGV_I32(arg1); |
315 | *gen_opparam_ptr++ = GET_TCGV_I32(arg2); | |
316 | *gen_opparam_ptr++ = GET_TCGV_I32(arg3); | |
317 | *gen_opparam_ptr++ = GET_TCGV_I32(arg4); | |
318 | *gen_opparam_ptr++ = arg5; | |
319 | *gen_opparam_ptr++ = arg6; | |
320 | } | |
321 | ||
322 | static inline void tcg_gen_op6ii_i64(int opc, TCGv_i64 arg1, TCGv_i64 arg2, | |
323 | TCGv_i64 arg3, TCGv_i64 arg4, TCGArg arg5, | |
324 | TCGArg arg6) | |
325 | { | |
326 | *gen_opc_ptr++ = opc; | |
327 | *gen_opparam_ptr++ = GET_TCGV_I64(arg1); | |
328 | *gen_opparam_ptr++ = GET_TCGV_I64(arg2); | |
329 | *gen_opparam_ptr++ = GET_TCGV_I64(arg3); | |
330 | *gen_opparam_ptr++ = GET_TCGV_I64(arg4); | |
c896fe29 FB |
331 | *gen_opparam_ptr++ = arg5; |
332 | *gen_opparam_ptr++ = arg6; | |
333 | } | |
334 | ||
335 | static inline void gen_set_label(int n) | |
336 | { | |
ac56dd48 | 337 | tcg_gen_op1i(INDEX_op_set_label, n); |
c896fe29 FB |
338 | } |
339 | ||
fb50d413 BS |
340 | static inline void tcg_gen_br(int label) |
341 | { | |
342 | tcg_gen_op1i(INDEX_op_br, label); | |
343 | } | |
344 | ||
a7812ae4 | 345 | static inline void tcg_gen_mov_i32(TCGv_i32 ret, TCGv_i32 arg) |
c896fe29 | 346 | { |
fe75bcf7 | 347 | if (!TCGV_EQUAL_I32(ret, arg)) |
a7812ae4 | 348 | tcg_gen_op2_i32(INDEX_op_mov_i32, ret, arg); |
c896fe29 FB |
349 | } |
350 | ||
a7812ae4 | 351 | static inline void tcg_gen_movi_i32(TCGv_i32 ret, int32_t arg) |
c896fe29 | 352 | { |
a7812ae4 | 353 | tcg_gen_op2i_i32(INDEX_op_movi_i32, ret, arg); |
c896fe29 FB |
354 | } |
355 | ||
356 | /* helper calls */ | |
a7812ae4 PB |
357 | static inline void tcg_gen_helperN(void *func, int flags, int sizemask, |
358 | TCGArg ret, int nargs, TCGArg *args) | |
359 | { | |
360 | TCGv_ptr fn; | |
361 | fn = tcg_const_ptr((tcg_target_long)func); | |
362 | tcg_gen_callN(&tcg_ctx, fn, flags, sizemask, ret, | |
363 | nargs, args); | |
364 | tcg_temp_free_ptr(fn); | |
365 | } | |
c896fe29 | 366 | |
dbfff4de AJ |
367 | /* Note: Both tcg_gen_helper32() and tcg_gen_helper64() are currently |
368 | reserved for helpers in tcg-runtime.c. These helpers are all const | |
369 | and pure, hence the call to tcg_gen_callN() with TCG_CALL_CONST | | |
370 | TCG_CALL_PURE. This may need to be adjusted if these functions | |
371 | start to be used with other helpers. */ | |
31d66551 AJ |
372 | static inline void tcg_gen_helper32(void *func, TCGv_i32 ret, |
373 | TCGv_i32 a, TCGv_i32 b) | |
374 | { | |
375 | TCGv_ptr fn; | |
376 | TCGArg args[2]; | |
377 | fn = tcg_const_ptr((tcg_target_long)func); | |
378 | args[0] = GET_TCGV_I32(a); | |
379 | args[1] = GET_TCGV_I32(b); | |
dbfff4de AJ |
380 | tcg_gen_callN(&tcg_ctx, fn, TCG_CALL_CONST | TCG_CALL_PURE, |
381 | 0, GET_TCGV_I32(ret), 2, args); | |
31d66551 AJ |
382 | tcg_temp_free_ptr(fn); |
383 | } | |
384 | ||
a7812ae4 PB |
385 | static inline void tcg_gen_helper64(void *func, TCGv_i64 ret, |
386 | TCGv_i64 a, TCGv_i64 b) | |
c896fe29 | 387 | { |
a7812ae4 PB |
388 | TCGv_ptr fn; |
389 | TCGArg args[2]; | |
390 | fn = tcg_const_ptr((tcg_target_long)func); | |
391 | args[0] = GET_TCGV_I64(a); | |
392 | args[1] = GET_TCGV_I64(b); | |
dbfff4de AJ |
393 | tcg_gen_callN(&tcg_ctx, fn, TCG_CALL_CONST | TCG_CALL_PURE, |
394 | 7, GET_TCGV_I64(ret), 2, args); | |
a7812ae4 | 395 | tcg_temp_free_ptr(fn); |
f8422f52 BS |
396 | } |
397 | ||
c896fe29 FB |
398 | /* 32 bit ops */ |
399 | ||
a7812ae4 | 400 | static inline void tcg_gen_ld8u_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset) |
c896fe29 | 401 | { |
a7812ae4 | 402 | tcg_gen_ldst_op_i32(INDEX_op_ld8u_i32, ret, arg2, offset); |
c896fe29 FB |
403 | } |
404 | ||
a7812ae4 | 405 | static inline void tcg_gen_ld8s_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset) |
c896fe29 | 406 | { |
a7812ae4 | 407 | tcg_gen_ldst_op_i32(INDEX_op_ld8s_i32, ret, arg2, offset); |
c896fe29 FB |
408 | } |
409 | ||
a7812ae4 | 410 | static inline void tcg_gen_ld16u_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset) |
c896fe29 | 411 | { |
a7812ae4 | 412 | tcg_gen_ldst_op_i32(INDEX_op_ld16u_i32, ret, arg2, offset); |
c896fe29 FB |
413 | } |
414 | ||
a7812ae4 | 415 | static inline void tcg_gen_ld16s_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset) |
c896fe29 | 416 | { |
a7812ae4 | 417 | tcg_gen_ldst_op_i32(INDEX_op_ld16s_i32, ret, arg2, offset); |
c896fe29 FB |
418 | } |
419 | ||
a7812ae4 | 420 | static inline void tcg_gen_ld_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset) |
c896fe29 | 421 | { |
a7812ae4 | 422 | tcg_gen_ldst_op_i32(INDEX_op_ld_i32, ret, arg2, offset); |
c896fe29 FB |
423 | } |
424 | ||
a7812ae4 | 425 | static inline void tcg_gen_st8_i32(TCGv_i32 arg1, TCGv_ptr arg2, tcg_target_long offset) |
c896fe29 | 426 | { |
a7812ae4 | 427 | tcg_gen_ldst_op_i32(INDEX_op_st8_i32, arg1, arg2, offset); |
c896fe29 FB |
428 | } |
429 | ||
a7812ae4 | 430 | static inline void tcg_gen_st16_i32(TCGv_i32 arg1, TCGv_ptr arg2, tcg_target_long offset) |
c896fe29 | 431 | { |
a7812ae4 | 432 | tcg_gen_ldst_op_i32(INDEX_op_st16_i32, arg1, arg2, offset); |
c896fe29 FB |
433 | } |
434 | ||
a7812ae4 | 435 | static inline void tcg_gen_st_i32(TCGv_i32 arg1, TCGv_ptr arg2, tcg_target_long offset) |
c896fe29 | 436 | { |
a7812ae4 | 437 | tcg_gen_ldst_op_i32(INDEX_op_st_i32, arg1, arg2, offset); |
c896fe29 FB |
438 | } |
439 | ||
a7812ae4 | 440 | static inline void tcg_gen_add_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
c896fe29 | 441 | { |
a7812ae4 | 442 | tcg_gen_op3_i32(INDEX_op_add_i32, ret, arg1, arg2); |
c896fe29 FB |
443 | } |
444 | ||
a7812ae4 | 445 | static inline void tcg_gen_addi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) |
c896fe29 | 446 | { |
7089442c BS |
447 | /* some cases can be optimized here */ |
448 | if (arg2 == 0) { | |
449 | tcg_gen_mov_i32(ret, arg1); | |
450 | } else { | |
a7812ae4 | 451 | TCGv_i32 t0 = tcg_const_i32(arg2); |
e8996ee0 | 452 | tcg_gen_add_i32(ret, arg1, t0); |
a7812ae4 | 453 | tcg_temp_free_i32(t0); |
7089442c | 454 | } |
c896fe29 FB |
455 | } |
456 | ||
a7812ae4 | 457 | static inline void tcg_gen_sub_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
c896fe29 | 458 | { |
a7812ae4 | 459 | tcg_gen_op3_i32(INDEX_op_sub_i32, ret, arg1, arg2); |
c896fe29 FB |
460 | } |
461 | ||
a7812ae4 | 462 | static inline void tcg_gen_subfi_i32(TCGv_i32 ret, int32_t arg1, TCGv_i32 arg2) |
0045734a | 463 | { |
a7812ae4 | 464 | TCGv_i32 t0 = tcg_const_i32(arg1); |
0045734a | 465 | tcg_gen_sub_i32(ret, t0, arg2); |
a7812ae4 | 466 | tcg_temp_free_i32(t0); |
0045734a AJ |
467 | } |
468 | ||
a7812ae4 | 469 | static inline void tcg_gen_subi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) |
c896fe29 | 470 | { |
7089442c BS |
471 | /* some cases can be optimized here */ |
472 | if (arg2 == 0) { | |
473 | tcg_gen_mov_i32(ret, arg1); | |
474 | } else { | |
a7812ae4 | 475 | TCGv_i32 t0 = tcg_const_i32(arg2); |
e8996ee0 | 476 | tcg_gen_sub_i32(ret, arg1, t0); |
a7812ae4 | 477 | tcg_temp_free_i32(t0); |
7089442c | 478 | } |
c896fe29 FB |
479 | } |
480 | ||
a7812ae4 | 481 | static inline void tcg_gen_and_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
c896fe29 | 482 | { |
7fc81051 AJ |
483 | if (TCGV_EQUAL_I32(arg1, arg2)) { |
484 | tcg_gen_mov_i32(ret, arg1); | |
485 | } else { | |
486 | tcg_gen_op3_i32(INDEX_op_and_i32, ret, arg1, arg2); | |
487 | } | |
c896fe29 FB |
488 | } |
489 | ||
a7812ae4 | 490 | static inline void tcg_gen_andi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) |
c896fe29 FB |
491 | { |
492 | /* some cases can be optimized here */ | |
493 | if (arg2 == 0) { | |
494 | tcg_gen_movi_i32(ret, 0); | |
495 | } else if (arg2 == 0xffffffff) { | |
496 | tcg_gen_mov_i32(ret, arg1); | |
497 | } else { | |
a7812ae4 | 498 | TCGv_i32 t0 = tcg_const_i32(arg2); |
e8996ee0 | 499 | tcg_gen_and_i32(ret, arg1, t0); |
a7812ae4 | 500 | tcg_temp_free_i32(t0); |
c896fe29 FB |
501 | } |
502 | } | |
503 | ||
a7812ae4 | 504 | static inline void tcg_gen_or_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
c896fe29 | 505 | { |
7fc81051 AJ |
506 | if (TCGV_EQUAL_I32(arg1, arg2)) { |
507 | tcg_gen_mov_i32(ret, arg1); | |
508 | } else { | |
509 | tcg_gen_op3_i32(INDEX_op_or_i32, ret, arg1, arg2); | |
510 | } | |
c896fe29 FB |
511 | } |
512 | ||
a7812ae4 | 513 | static inline void tcg_gen_ori_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) |
c896fe29 FB |
514 | { |
515 | /* some cases can be optimized here */ | |
516 | if (arg2 == 0xffffffff) { | |
7089442c | 517 | tcg_gen_movi_i32(ret, 0xffffffff); |
c896fe29 FB |
518 | } else if (arg2 == 0) { |
519 | tcg_gen_mov_i32(ret, arg1); | |
520 | } else { | |
a7812ae4 | 521 | TCGv_i32 t0 = tcg_const_i32(arg2); |
e8996ee0 | 522 | tcg_gen_or_i32(ret, arg1, t0); |
a7812ae4 | 523 | tcg_temp_free_i32(t0); |
c896fe29 FB |
524 | } |
525 | } | |
526 | ||
a7812ae4 | 527 | static inline void tcg_gen_xor_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
c896fe29 | 528 | { |
7fc81051 AJ |
529 | if (TCGV_EQUAL_I32(arg1, arg2)) { |
530 | tcg_gen_movi_i32(ret, 0); | |
531 | } else { | |
532 | tcg_gen_op3_i32(INDEX_op_xor_i32, ret, arg1, arg2); | |
533 | } | |
c896fe29 FB |
534 | } |
535 | ||
a7812ae4 | 536 | static inline void tcg_gen_xori_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) |
c896fe29 FB |
537 | { |
538 | /* some cases can be optimized here */ | |
539 | if (arg2 == 0) { | |
540 | tcg_gen_mov_i32(ret, arg1); | |
541 | } else { | |
a7812ae4 | 542 | TCGv_i32 t0 = tcg_const_i32(arg2); |
e8996ee0 | 543 | tcg_gen_xor_i32(ret, arg1, t0); |
a7812ae4 | 544 | tcg_temp_free_i32(t0); |
c896fe29 FB |
545 | } |
546 | } | |
547 | ||
a7812ae4 | 548 | static inline void tcg_gen_shl_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
c896fe29 | 549 | { |
a7812ae4 | 550 | tcg_gen_op3_i32(INDEX_op_shl_i32, ret, arg1, arg2); |
c896fe29 FB |
551 | } |
552 | ||
a7812ae4 | 553 | static inline void tcg_gen_shli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) |
c896fe29 | 554 | { |
34151a20 FB |
555 | if (arg2 == 0) { |
556 | tcg_gen_mov_i32(ret, arg1); | |
557 | } else { | |
a7812ae4 | 558 | TCGv_i32 t0 = tcg_const_i32(arg2); |
e8996ee0 | 559 | tcg_gen_shl_i32(ret, arg1, t0); |
a7812ae4 | 560 | tcg_temp_free_i32(t0); |
34151a20 | 561 | } |
c896fe29 FB |
562 | } |
563 | ||
a7812ae4 | 564 | static inline void tcg_gen_shr_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
c896fe29 | 565 | { |
a7812ae4 | 566 | tcg_gen_op3_i32(INDEX_op_shr_i32, ret, arg1, arg2); |
c896fe29 FB |
567 | } |
568 | ||
a7812ae4 | 569 | static inline void tcg_gen_shri_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) |
c896fe29 | 570 | { |
34151a20 FB |
571 | if (arg2 == 0) { |
572 | tcg_gen_mov_i32(ret, arg1); | |
573 | } else { | |
a7812ae4 | 574 | TCGv_i32 t0 = tcg_const_i32(arg2); |
e8996ee0 | 575 | tcg_gen_shr_i32(ret, arg1, t0); |
a7812ae4 | 576 | tcg_temp_free_i32(t0); |
34151a20 | 577 | } |
c896fe29 FB |
578 | } |
579 | ||
a7812ae4 | 580 | static inline void tcg_gen_sar_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
c896fe29 | 581 | { |
a7812ae4 | 582 | tcg_gen_op3_i32(INDEX_op_sar_i32, ret, arg1, arg2); |
c896fe29 FB |
583 | } |
584 | ||
a7812ae4 | 585 | static inline void tcg_gen_sari_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) |
c896fe29 | 586 | { |
34151a20 FB |
587 | if (arg2 == 0) { |
588 | tcg_gen_mov_i32(ret, arg1); | |
589 | } else { | |
a7812ae4 | 590 | TCGv_i32 t0 = tcg_const_i32(arg2); |
e8996ee0 | 591 | tcg_gen_sar_i32(ret, arg1, t0); |
a7812ae4 | 592 | tcg_temp_free_i32(t0); |
34151a20 | 593 | } |
c896fe29 FB |
594 | } |
595 | ||
a7812ae4 | 596 | static inline void tcg_gen_brcond_i32(int cond, TCGv_i32 arg1, TCGv_i32 arg2, |
c896fe29 FB |
597 | int label_index) |
598 | { | |
a7812ae4 | 599 | tcg_gen_op4ii_i32(INDEX_op_brcond_i32, arg1, arg2, cond, label_index); |
c896fe29 FB |
600 | } |
601 | ||
a7812ae4 | 602 | static inline void tcg_gen_brcondi_i32(int cond, TCGv_i32 arg1, int32_t arg2, |
cb63669a PB |
603 | int label_index) |
604 | { | |
a7812ae4 | 605 | TCGv_i32 t0 = tcg_const_i32(arg2); |
cb63669a | 606 | tcg_gen_brcond_i32(cond, arg1, t0, label_index); |
a7812ae4 | 607 | tcg_temp_free_i32(t0); |
cb63669a PB |
608 | } |
609 | ||
5105c556 AJ |
610 | static inline void tcg_gen_setcond_i32(int cond, TCGv_i32 ret, |
611 | TCGv_i32 arg1, TCGv_i32 arg2) | |
612 | { | |
613 | tcg_gen_op4i_i32(INDEX_op_setcond_i32, ret, arg1, arg2, cond); | |
614 | } | |
615 | ||
616 | static inline void tcg_gen_setcondi_i32(int cond, TCGv_i32 ret, TCGv_i32 arg1, | |
617 | int32_t arg2) | |
618 | { | |
619 | TCGv_i32 t0 = tcg_const_i32(arg2); | |
620 | tcg_gen_setcond_i32(cond, ret, arg1, t0); | |
621 | tcg_temp_free_i32(t0); | |
622 | } | |
623 | ||
a7812ae4 | 624 | static inline void tcg_gen_mul_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
c896fe29 | 625 | { |
a7812ae4 | 626 | tcg_gen_op3_i32(INDEX_op_mul_i32, ret, arg1, arg2); |
c896fe29 FB |
627 | } |
628 | ||
a7812ae4 | 629 | static inline void tcg_gen_muli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) |
f730fd27 | 630 | { |
a7812ae4 | 631 | TCGv_i32 t0 = tcg_const_i32(arg2); |
e8996ee0 | 632 | tcg_gen_mul_i32(ret, arg1, t0); |
a7812ae4 | 633 | tcg_temp_free_i32(t0); |
f730fd27 TS |
634 | } |
635 | ||
c896fe29 | 636 | #ifdef TCG_TARGET_HAS_div_i32 |
a7812ae4 | 637 | static inline void tcg_gen_div_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
c896fe29 | 638 | { |
a7812ae4 | 639 | tcg_gen_op3_i32(INDEX_op_div_i32, ret, arg1, arg2); |
c896fe29 FB |
640 | } |
641 | ||
a7812ae4 | 642 | static inline void tcg_gen_rem_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
c896fe29 | 643 | { |
a7812ae4 | 644 | tcg_gen_op3_i32(INDEX_op_rem_i32, ret, arg1, arg2); |
c896fe29 FB |
645 | } |
646 | ||
a7812ae4 | 647 | static inline void tcg_gen_divu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
c896fe29 | 648 | { |
a7812ae4 | 649 | tcg_gen_op3_i32(INDEX_op_divu_i32, ret, arg1, arg2); |
c896fe29 FB |
650 | } |
651 | ||
a7812ae4 | 652 | static inline void tcg_gen_remu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
c896fe29 | 653 | { |
a7812ae4 | 654 | tcg_gen_op3_i32(INDEX_op_remu_i32, ret, arg1, arg2); |
c896fe29 | 655 | } |
31d66551 | 656 | #elif defined(TCG_TARGET_HAS_div2_i32) |
a7812ae4 | 657 | static inline void tcg_gen_div_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
c896fe29 | 658 | { |
a7812ae4 PB |
659 | TCGv_i32 t0; |
660 | t0 = tcg_temp_new_i32(); | |
c896fe29 | 661 | tcg_gen_sari_i32(t0, arg1, 31); |
a7812ae4 PB |
662 | tcg_gen_op5_i32(INDEX_op_div2_i32, ret, t0, arg1, t0, arg2); |
663 | tcg_temp_free_i32(t0); | |
c896fe29 FB |
664 | } |
665 | ||
a7812ae4 | 666 | static inline void tcg_gen_rem_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
c896fe29 | 667 | { |
a7812ae4 PB |
668 | TCGv_i32 t0; |
669 | t0 = tcg_temp_new_i32(); | |
c896fe29 | 670 | tcg_gen_sari_i32(t0, arg1, 31); |
a7812ae4 PB |
671 | tcg_gen_op5_i32(INDEX_op_div2_i32, t0, ret, arg1, t0, arg2); |
672 | tcg_temp_free_i32(t0); | |
c896fe29 FB |
673 | } |
674 | ||
a7812ae4 | 675 | static inline void tcg_gen_divu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
c896fe29 | 676 | { |
a7812ae4 PB |
677 | TCGv_i32 t0; |
678 | t0 = tcg_temp_new_i32(); | |
c896fe29 | 679 | tcg_gen_movi_i32(t0, 0); |
a7812ae4 PB |
680 | tcg_gen_op5_i32(INDEX_op_divu2_i32, ret, t0, arg1, t0, arg2); |
681 | tcg_temp_free_i32(t0); | |
c896fe29 FB |
682 | } |
683 | ||
a7812ae4 | 684 | static inline void tcg_gen_remu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
c896fe29 | 685 | { |
a7812ae4 PB |
686 | TCGv_i32 t0; |
687 | t0 = tcg_temp_new_i32(); | |
c896fe29 | 688 | tcg_gen_movi_i32(t0, 0); |
a7812ae4 PB |
689 | tcg_gen_op5_i32(INDEX_op_divu2_i32, t0, ret, arg1, t0, arg2); |
690 | tcg_temp_free_i32(t0); | |
c896fe29 | 691 | } |
31d66551 AJ |
692 | #else |
693 | static inline void tcg_gen_div_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) | |
694 | { | |
695 | tcg_gen_helper32(tcg_helper_div_i32, ret, arg1, arg2); | |
696 | } | |
697 | ||
698 | static inline void tcg_gen_rem_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) | |
699 | { | |
700 | tcg_gen_helper32(tcg_helper_rem_i32, ret, arg1, arg2); | |
701 | } | |
702 | ||
703 | static inline void tcg_gen_divu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) | |
704 | { | |
705 | tcg_gen_helper32(tcg_helper_divu_i32, ret, arg1, arg2); | |
706 | } | |
707 | ||
708 | static inline void tcg_gen_remu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) | |
709 | { | |
710 | tcg_gen_helper32(tcg_helper_remu_i32, ret, arg1, arg2); | |
711 | } | |
c896fe29 FB |
712 | #endif |
713 | ||
714 | #if TCG_TARGET_REG_BITS == 32 | |
715 | ||
a7812ae4 | 716 | static inline void tcg_gen_mov_i64(TCGv_i64 ret, TCGv_i64 arg) |
c896fe29 | 717 | { |
fe75bcf7 | 718 | if (!TCGV_EQUAL_I64(ret, arg)) { |
a7812ae4 | 719 | tcg_gen_mov_i32(TCGV_LOW(ret), TCGV_LOW(arg)); |
4d07272d BS |
720 | tcg_gen_mov_i32(TCGV_HIGH(ret), TCGV_HIGH(arg)); |
721 | } | |
c896fe29 FB |
722 | } |
723 | ||
a7812ae4 | 724 | static inline void tcg_gen_movi_i64(TCGv_i64 ret, int64_t arg) |
c896fe29 | 725 | { |
a7812ae4 | 726 | tcg_gen_movi_i32(TCGV_LOW(ret), arg); |
ac56dd48 | 727 | tcg_gen_movi_i32(TCGV_HIGH(ret), arg >> 32); |
c896fe29 FB |
728 | } |
729 | ||
a7812ae4 PB |
730 | static inline void tcg_gen_ld8u_i64(TCGv_i64 ret, TCGv_ptr arg2, |
731 | tcg_target_long offset) | |
c896fe29 | 732 | { |
a7812ae4 | 733 | tcg_gen_ld8u_i32(TCGV_LOW(ret), arg2, offset); |
ac56dd48 | 734 | tcg_gen_movi_i32(TCGV_HIGH(ret), 0); |
c896fe29 FB |
735 | } |
736 | ||
a7812ae4 PB |
737 | static inline void tcg_gen_ld8s_i64(TCGv_i64 ret, TCGv_ptr arg2, |
738 | tcg_target_long offset) | |
c896fe29 | 739 | { |
a7812ae4 PB |
740 | tcg_gen_ld8s_i32(TCGV_LOW(ret), arg2, offset); |
741 | tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_HIGH(ret), 31); | |
c896fe29 FB |
742 | } |
743 | ||
a7812ae4 PB |
744 | static inline void tcg_gen_ld16u_i64(TCGv_i64 ret, TCGv_ptr arg2, |
745 | tcg_target_long offset) | |
c896fe29 | 746 | { |
a747723b | 747 | tcg_gen_ld16u_i32(TCGV_LOW(ret), arg2, offset); |
ac56dd48 | 748 | tcg_gen_movi_i32(TCGV_HIGH(ret), 0); |
c896fe29 FB |
749 | } |
750 | ||
a7812ae4 PB |
751 | static inline void tcg_gen_ld16s_i64(TCGv_i64 ret, TCGv_ptr arg2, |
752 | tcg_target_long offset) | |
c896fe29 | 753 | { |
a7812ae4 PB |
754 | tcg_gen_ld16s_i32(TCGV_LOW(ret), arg2, offset); |
755 | tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31); | |
c896fe29 FB |
756 | } |
757 | ||
a7812ae4 PB |
758 | static inline void tcg_gen_ld32u_i64(TCGv_i64 ret, TCGv_ptr arg2, |
759 | tcg_target_long offset) | |
c896fe29 | 760 | { |
a7812ae4 | 761 | tcg_gen_ld_i32(TCGV_LOW(ret), arg2, offset); |
ac56dd48 | 762 | tcg_gen_movi_i32(TCGV_HIGH(ret), 0); |
c896fe29 FB |
763 | } |
764 | ||
a7812ae4 PB |
765 | static inline void tcg_gen_ld32s_i64(TCGv_i64 ret, TCGv_ptr arg2, |
766 | tcg_target_long offset) | |
c896fe29 | 767 | { |
a7812ae4 PB |
768 | tcg_gen_ld_i32(TCGV_LOW(ret), arg2, offset); |
769 | tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31); | |
c896fe29 FB |
770 | } |
771 | ||
a7812ae4 PB |
772 | static inline void tcg_gen_ld_i64(TCGv_i64 ret, TCGv_ptr arg2, |
773 | tcg_target_long offset) | |
c896fe29 FB |
774 | { |
775 | /* since arg2 and ret have different types, they cannot be the | |
776 | same temporary */ | |
777 | #ifdef TCG_TARGET_WORDS_BIGENDIAN | |
ac56dd48 | 778 | tcg_gen_ld_i32(TCGV_HIGH(ret), arg2, offset); |
a7812ae4 | 779 | tcg_gen_ld_i32(TCGV_LOW(ret), arg2, offset + 4); |
c896fe29 | 780 | #else |
a7812ae4 | 781 | tcg_gen_ld_i32(TCGV_LOW(ret), arg2, offset); |
ac56dd48 | 782 | tcg_gen_ld_i32(TCGV_HIGH(ret), arg2, offset + 4); |
c896fe29 FB |
783 | #endif |
784 | } | |
785 | ||
a7812ae4 PB |
786 | static inline void tcg_gen_st8_i64(TCGv_i64 arg1, TCGv_ptr arg2, |
787 | tcg_target_long offset) | |
c896fe29 | 788 | { |
a7812ae4 | 789 | tcg_gen_st8_i32(TCGV_LOW(arg1), arg2, offset); |
c896fe29 FB |
790 | } |
791 | ||
a7812ae4 PB |
792 | static inline void tcg_gen_st16_i64(TCGv_i64 arg1, TCGv_ptr arg2, |
793 | tcg_target_long offset) | |
c896fe29 | 794 | { |
a7812ae4 | 795 | tcg_gen_st16_i32(TCGV_LOW(arg1), arg2, offset); |
c896fe29 FB |
796 | } |
797 | ||
a7812ae4 PB |
798 | static inline void tcg_gen_st32_i64(TCGv_i64 arg1, TCGv_ptr arg2, |
799 | tcg_target_long offset) | |
c896fe29 | 800 | { |
a7812ae4 | 801 | tcg_gen_st_i32(TCGV_LOW(arg1), arg2, offset); |
c896fe29 FB |
802 | } |
803 | ||
a7812ae4 PB |
804 | static inline void tcg_gen_st_i64(TCGv_i64 arg1, TCGv_ptr arg2, |
805 | tcg_target_long offset) | |
c896fe29 FB |
806 | { |
807 | #ifdef TCG_TARGET_WORDS_BIGENDIAN | |
ac56dd48 | 808 | tcg_gen_st_i32(TCGV_HIGH(arg1), arg2, offset); |
a7812ae4 | 809 | tcg_gen_st_i32(TCGV_LOW(arg1), arg2, offset + 4); |
c896fe29 | 810 | #else |
a7812ae4 | 811 | tcg_gen_st_i32(TCGV_LOW(arg1), arg2, offset); |
ac56dd48 | 812 | tcg_gen_st_i32(TCGV_HIGH(arg1), arg2, offset + 4); |
c896fe29 FB |
813 | #endif |
814 | } | |
815 | ||
a7812ae4 | 816 | static inline void tcg_gen_add_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
c896fe29 | 817 | { |
a7812ae4 PB |
818 | tcg_gen_op6_i32(INDEX_op_add2_i32, TCGV_LOW(ret), TCGV_HIGH(ret), |
819 | TCGV_LOW(arg1), TCGV_HIGH(arg1), TCGV_LOW(arg2), | |
820 | TCGV_HIGH(arg2)); | |
c896fe29 FB |
821 | } |
822 | ||
a7812ae4 | 823 | static inline void tcg_gen_sub_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
c896fe29 | 824 | { |
a7812ae4 PB |
825 | tcg_gen_op6_i32(INDEX_op_sub2_i32, TCGV_LOW(ret), TCGV_HIGH(ret), |
826 | TCGV_LOW(arg1), TCGV_HIGH(arg1), TCGV_LOW(arg2), | |
827 | TCGV_HIGH(arg2)); | |
c896fe29 FB |
828 | } |
829 | ||
a7812ae4 | 830 | static inline void tcg_gen_and_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
c896fe29 | 831 | { |
a7812ae4 | 832 | tcg_gen_and_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2)); |
ac56dd48 | 833 | tcg_gen_and_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2)); |
c896fe29 FB |
834 | } |
835 | ||
a7812ae4 | 836 | static inline void tcg_gen_andi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
c896fe29 | 837 | { |
e5105083 AJ |
838 | tcg_gen_andi_i32(TCGV_LOW(ret), TCGV_LOW(arg1), arg2); |
839 | tcg_gen_andi_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), arg2 >> 32); | |
c896fe29 FB |
840 | } |
841 | ||
a7812ae4 | 842 | static inline void tcg_gen_or_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
c896fe29 | 843 | { |
e5105083 AJ |
844 | tcg_gen_or_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2)); |
845 | tcg_gen_or_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2)); | |
c896fe29 FB |
846 | } |
847 | ||
a7812ae4 | 848 | static inline void tcg_gen_ori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
c896fe29 | 849 | { |
a7812ae4 | 850 | tcg_gen_ori_i32(TCGV_LOW(ret), TCGV_LOW(arg1), arg2); |
ac56dd48 | 851 | tcg_gen_ori_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), arg2 >> 32); |
c896fe29 FB |
852 | } |
853 | ||
a7812ae4 | 854 | static inline void tcg_gen_xor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
c896fe29 | 855 | { |
e5105083 AJ |
856 | tcg_gen_xor_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2)); |
857 | tcg_gen_xor_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2)); | |
c896fe29 FB |
858 | } |
859 | ||
a7812ae4 | 860 | static inline void tcg_gen_xori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
c896fe29 | 861 | { |
a7812ae4 | 862 | tcg_gen_xori_i32(TCGV_LOW(ret), TCGV_LOW(arg1), arg2); |
ac56dd48 | 863 | tcg_gen_xori_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), arg2 >> 32); |
c896fe29 FB |
864 | } |
865 | ||
866 | /* XXX: use generic code when basic block handling is OK or CPU | |
867 | specific code (x86) */ | |
a7812ae4 | 868 | static inline void tcg_gen_shl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
c896fe29 | 869 | { |
a7812ae4 | 870 | tcg_gen_helper64(tcg_helper_shl_i64, ret, arg1, arg2); |
c896fe29 FB |
871 | } |
872 | ||
a7812ae4 | 873 | static inline void tcg_gen_shli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
c896fe29 FB |
874 | { |
875 | tcg_gen_shifti_i64(ret, arg1, arg2, 0, 0); | |
876 | } | |
877 | ||
a7812ae4 | 878 | static inline void tcg_gen_shr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
c896fe29 | 879 | { |
a7812ae4 | 880 | tcg_gen_helper64(tcg_helper_shr_i64, ret, arg1, arg2); |
c896fe29 FB |
881 | } |
882 | ||
a7812ae4 | 883 | static inline void tcg_gen_shri_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
c896fe29 FB |
884 | { |
885 | tcg_gen_shifti_i64(ret, arg1, arg2, 1, 0); | |
886 | } | |
887 | ||
a7812ae4 | 888 | static inline void tcg_gen_sar_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
c896fe29 | 889 | { |
a7812ae4 | 890 | tcg_gen_helper64(tcg_helper_sar_i64, ret, arg1, arg2); |
c896fe29 FB |
891 | } |
892 | ||
a7812ae4 | 893 | static inline void tcg_gen_sari_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
c896fe29 FB |
894 | { |
895 | tcg_gen_shifti_i64(ret, arg1, arg2, 1, 1); | |
896 | } | |
897 | ||
a7812ae4 | 898 | static inline void tcg_gen_brcond_i64(int cond, TCGv_i64 arg1, TCGv_i64 arg2, |
c896fe29 FB |
899 | int label_index) |
900 | { | |
a7812ae4 PB |
901 | tcg_gen_op6ii_i32(INDEX_op_brcond2_i32, |
902 | TCGV_LOW(arg1), TCGV_HIGH(arg1), TCGV_LOW(arg2), | |
903 | TCGV_HIGH(arg2), cond, label_index); | |
c896fe29 FB |
904 | } |
905 | ||
5105c556 AJ |
906 | static inline void tcg_gen_setcond_i64(int cond, TCGv_i64 ret, |
907 | TCGv_i64 arg1, TCGv_i64 arg2) | |
908 | { | |
909 | tcg_gen_op6i_i32(INDEX_op_setcond2_i32, TCGV_LOW(ret), | |
910 | TCGV_LOW(arg1), TCGV_HIGH(arg1), | |
911 | TCGV_LOW(arg2), TCGV_HIGH(arg2), cond); | |
912 | tcg_gen_movi_i32(TCGV_HIGH(ret), 0); | |
913 | } | |
914 | ||
a7812ae4 | 915 | static inline void tcg_gen_mul_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
c896fe29 | 916 | { |
a7812ae4 PB |
917 | TCGv_i64 t0; |
918 | TCGv_i32 t1; | |
c896fe29 | 919 | |
a7812ae4 PB |
920 | t0 = tcg_temp_new_i64(); |
921 | t1 = tcg_temp_new_i32(); | |
922 | ||
923 | tcg_gen_op4_i32(INDEX_op_mulu2_i32, TCGV_LOW(t0), TCGV_HIGH(t0), | |
924 | TCGV_LOW(arg1), TCGV_LOW(arg2)); | |
925 | ||
926 | tcg_gen_mul_i32(t1, TCGV_LOW(arg1), TCGV_HIGH(arg2)); | |
ac56dd48 | 927 | tcg_gen_add_i32(TCGV_HIGH(t0), TCGV_HIGH(t0), t1); |
a7812ae4 | 928 | tcg_gen_mul_i32(t1, TCGV_HIGH(arg1), TCGV_LOW(arg2)); |
ac56dd48 | 929 | tcg_gen_add_i32(TCGV_HIGH(t0), TCGV_HIGH(t0), t1); |
a7812ae4 | 930 | |
c896fe29 | 931 | tcg_gen_mov_i64(ret, t0); |
a7812ae4 PB |
932 | tcg_temp_free_i64(t0); |
933 | tcg_temp_free_i32(t1); | |
c896fe29 FB |
934 | } |
935 | ||
a7812ae4 | 936 | static inline void tcg_gen_div_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
c896fe29 | 937 | { |
a7812ae4 | 938 | tcg_gen_helper64(tcg_helper_div_i64, ret, arg1, arg2); |
c896fe29 FB |
939 | } |
940 | ||
a7812ae4 | 941 | static inline void tcg_gen_rem_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
c896fe29 | 942 | { |
a7812ae4 | 943 | tcg_gen_helper64(tcg_helper_rem_i64, ret, arg1, arg2); |
c896fe29 FB |
944 | } |
945 | ||
a7812ae4 | 946 | static inline void tcg_gen_divu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
c896fe29 | 947 | { |
a7812ae4 | 948 | tcg_gen_helper64(tcg_helper_divu_i64, ret, arg1, arg2); |
c896fe29 FB |
949 | } |
950 | ||
a7812ae4 | 951 | static inline void tcg_gen_remu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
c896fe29 | 952 | { |
a7812ae4 | 953 | tcg_gen_helper64(tcg_helper_remu_i64, ret, arg1, arg2); |
c896fe29 FB |
954 | } |
955 | ||
956 | #else | |
957 | ||
a7812ae4 | 958 | static inline void tcg_gen_mov_i64(TCGv_i64 ret, TCGv_i64 arg) |
c896fe29 | 959 | { |
fe75bcf7 | 960 | if (!TCGV_EQUAL_I64(ret, arg)) |
a7812ae4 | 961 | tcg_gen_op2_i64(INDEX_op_mov_i64, ret, arg); |
c896fe29 FB |
962 | } |
963 | ||
a7812ae4 | 964 | static inline void tcg_gen_movi_i64(TCGv_i64 ret, int64_t arg) |
c896fe29 | 965 | { |
a7812ae4 | 966 | tcg_gen_op2i_i64(INDEX_op_movi_i64, ret, arg); |
c896fe29 FB |
967 | } |
968 | ||
a7812ae4 | 969 | static inline void tcg_gen_ld8u_i64(TCGv_i64 ret, TCGv_i64 arg2, |
ac56dd48 | 970 | tcg_target_long offset) |
c896fe29 | 971 | { |
a7812ae4 | 972 | tcg_gen_ldst_op_i64(INDEX_op_ld8u_i64, ret, arg2, offset); |
c896fe29 FB |
973 | } |
974 | ||
a7812ae4 | 975 | static inline void tcg_gen_ld8s_i64(TCGv_i64 ret, TCGv_i64 arg2, |
ac56dd48 | 976 | tcg_target_long offset) |
c896fe29 | 977 | { |
a7812ae4 | 978 | tcg_gen_ldst_op_i64(INDEX_op_ld8s_i64, ret, arg2, offset); |
c896fe29 FB |
979 | } |
980 | ||
a7812ae4 | 981 | static inline void tcg_gen_ld16u_i64(TCGv_i64 ret, TCGv_i64 arg2, |
ac56dd48 | 982 | tcg_target_long offset) |
c896fe29 | 983 | { |
a7812ae4 | 984 | tcg_gen_ldst_op_i64(INDEX_op_ld16u_i64, ret, arg2, offset); |
c896fe29 FB |
985 | } |
986 | ||
a7812ae4 | 987 | static inline void tcg_gen_ld16s_i64(TCGv_i64 ret, TCGv_i64 arg2, |
ac56dd48 | 988 | tcg_target_long offset) |
c896fe29 | 989 | { |
a7812ae4 | 990 | tcg_gen_ldst_op_i64(INDEX_op_ld16s_i64, ret, arg2, offset); |
c896fe29 FB |
991 | } |
992 | ||
a7812ae4 | 993 | static inline void tcg_gen_ld32u_i64(TCGv_i64 ret, TCGv_i64 arg2, |
ac56dd48 | 994 | tcg_target_long offset) |
c896fe29 | 995 | { |
a7812ae4 | 996 | tcg_gen_ldst_op_i64(INDEX_op_ld32u_i64, ret, arg2, offset); |
c896fe29 FB |
997 | } |
998 | ||
a7812ae4 | 999 | static inline void tcg_gen_ld32s_i64(TCGv_i64 ret, TCGv_i64 arg2, |
ac56dd48 | 1000 | tcg_target_long offset) |
c896fe29 | 1001 | { |
a7812ae4 | 1002 | tcg_gen_ldst_op_i64(INDEX_op_ld32s_i64, ret, arg2, offset); |
c896fe29 FB |
1003 | } |
1004 | ||
a7812ae4 | 1005 | static inline void tcg_gen_ld_i64(TCGv_i64 ret, TCGv_i64 arg2, tcg_target_long offset) |
c896fe29 | 1006 | { |
a7812ae4 | 1007 | tcg_gen_ldst_op_i64(INDEX_op_ld_i64, ret, arg2, offset); |
c896fe29 FB |
1008 | } |
1009 | ||
a7812ae4 | 1010 | static inline void tcg_gen_st8_i64(TCGv_i64 arg1, TCGv_i64 arg2, |
ac56dd48 | 1011 | tcg_target_long offset) |
c896fe29 | 1012 | { |
a7812ae4 | 1013 | tcg_gen_ldst_op_i64(INDEX_op_st8_i64, arg1, arg2, offset); |
c896fe29 FB |
1014 | } |
1015 | ||
a7812ae4 | 1016 | static inline void tcg_gen_st16_i64(TCGv_i64 arg1, TCGv_i64 arg2, |
ac56dd48 | 1017 | tcg_target_long offset) |
c896fe29 | 1018 | { |
a7812ae4 | 1019 | tcg_gen_ldst_op_i64(INDEX_op_st16_i64, arg1, arg2, offset); |
c896fe29 FB |
1020 | } |
1021 | ||
a7812ae4 | 1022 | static inline void tcg_gen_st32_i64(TCGv_i64 arg1, TCGv_i64 arg2, |
ac56dd48 | 1023 | tcg_target_long offset) |
c896fe29 | 1024 | { |
a7812ae4 | 1025 | tcg_gen_ldst_op_i64(INDEX_op_st32_i64, arg1, arg2, offset); |
c896fe29 FB |
1026 | } |
1027 | ||
a7812ae4 | 1028 | static inline void tcg_gen_st_i64(TCGv_i64 arg1, TCGv_i64 arg2, tcg_target_long offset) |
c896fe29 | 1029 | { |
a7812ae4 | 1030 | tcg_gen_ldst_op_i64(INDEX_op_st_i64, arg1, arg2, offset); |
c896fe29 FB |
1031 | } |
1032 | ||
a7812ae4 | 1033 | static inline void tcg_gen_add_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
c896fe29 | 1034 | { |
a7812ae4 | 1035 | tcg_gen_op3_i64(INDEX_op_add_i64, ret, arg1, arg2); |
c896fe29 FB |
1036 | } |
1037 | ||
a7812ae4 | 1038 | static inline void tcg_gen_sub_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
c896fe29 | 1039 | { |
a7812ae4 | 1040 | tcg_gen_op3_i64(INDEX_op_sub_i64, ret, arg1, arg2); |
c896fe29 FB |
1041 | } |
1042 | ||
a7812ae4 | 1043 | static inline void tcg_gen_and_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
c896fe29 | 1044 | { |
7fc81051 AJ |
1045 | if (TCGV_EQUAL_I64(arg1, arg2)) { |
1046 | tcg_gen_mov_i64(ret, arg1); | |
1047 | } else { | |
1048 | tcg_gen_op3_i64(INDEX_op_and_i64, ret, arg1, arg2); | |
1049 | } | |
c896fe29 FB |
1050 | } |
1051 | ||
a7812ae4 | 1052 | static inline void tcg_gen_andi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
c896fe29 | 1053 | { |
a7812ae4 | 1054 | TCGv_i64 t0 = tcg_const_i64(arg2); |
e8996ee0 | 1055 | tcg_gen_and_i64(ret, arg1, t0); |
a7812ae4 | 1056 | tcg_temp_free_i64(t0); |
c896fe29 FB |
1057 | } |
1058 | ||
a7812ae4 | 1059 | static inline void tcg_gen_or_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
c896fe29 | 1060 | { |
7fc81051 AJ |
1061 | if (TCGV_EQUAL_I64(arg1, arg2)) { |
1062 | tcg_gen_mov_i64(ret, arg1); | |
1063 | } else { | |
1064 | tcg_gen_op3_i64(INDEX_op_or_i64, ret, arg1, arg2); | |
1065 | } | |
c896fe29 FB |
1066 | } |
1067 | ||
a7812ae4 | 1068 | static inline void tcg_gen_ori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
c896fe29 | 1069 | { |
a7812ae4 | 1070 | TCGv_i64 t0 = tcg_const_i64(arg2); |
e8996ee0 | 1071 | tcg_gen_or_i64(ret, arg1, t0); |
a7812ae4 | 1072 | tcg_temp_free_i64(t0); |
c896fe29 FB |
1073 | } |
1074 | ||
a7812ae4 | 1075 | static inline void tcg_gen_xor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
c896fe29 | 1076 | { |
7fc81051 AJ |
1077 | if (TCGV_EQUAL_I64(arg1, arg2)) { |
1078 | tcg_gen_movi_i64(ret, 0); | |
1079 | } else { | |
1080 | tcg_gen_op3_i64(INDEX_op_xor_i64, ret, arg1, arg2); | |
1081 | } | |
c896fe29 FB |
1082 | } |
1083 | ||
a7812ae4 | 1084 | static inline void tcg_gen_xori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
c896fe29 | 1085 | { |
a7812ae4 | 1086 | TCGv_i64 t0 = tcg_const_i64(arg2); |
e8996ee0 | 1087 | tcg_gen_xor_i64(ret, arg1, t0); |
a7812ae4 | 1088 | tcg_temp_free_i64(t0); |
c896fe29 FB |
1089 | } |
1090 | ||
a7812ae4 | 1091 | static inline void tcg_gen_shl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
c896fe29 | 1092 | { |
a7812ae4 | 1093 | tcg_gen_op3_i64(INDEX_op_shl_i64, ret, arg1, arg2); |
c896fe29 FB |
1094 | } |
1095 | ||
a7812ae4 | 1096 | static inline void tcg_gen_shli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
c896fe29 | 1097 | { |
34151a20 FB |
1098 | if (arg2 == 0) { |
1099 | tcg_gen_mov_i64(ret, arg1); | |
1100 | } else { | |
a7812ae4 | 1101 | TCGv_i64 t0 = tcg_const_i64(arg2); |
e8996ee0 | 1102 | tcg_gen_shl_i64(ret, arg1, t0); |
a7812ae4 | 1103 | tcg_temp_free_i64(t0); |
34151a20 | 1104 | } |
c896fe29 FB |
1105 | } |
1106 | ||
a7812ae4 | 1107 | static inline void tcg_gen_shr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
c896fe29 | 1108 | { |
a7812ae4 | 1109 | tcg_gen_op3_i64(INDEX_op_shr_i64, ret, arg1, arg2); |
c896fe29 FB |
1110 | } |
1111 | ||
a7812ae4 | 1112 | static inline void tcg_gen_shri_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
c896fe29 | 1113 | { |
34151a20 FB |
1114 | if (arg2 == 0) { |
1115 | tcg_gen_mov_i64(ret, arg1); | |
1116 | } else { | |
a7812ae4 | 1117 | TCGv_i64 t0 = tcg_const_i64(arg2); |
e8996ee0 | 1118 | tcg_gen_shr_i64(ret, arg1, t0); |
a7812ae4 | 1119 | tcg_temp_free_i64(t0); |
34151a20 | 1120 | } |
c896fe29 FB |
1121 | } |
1122 | ||
a7812ae4 | 1123 | static inline void tcg_gen_sar_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
c896fe29 | 1124 | { |
a7812ae4 | 1125 | tcg_gen_op3_i64(INDEX_op_sar_i64, ret, arg1, arg2); |
c896fe29 FB |
1126 | } |
1127 | ||
a7812ae4 | 1128 | static inline void tcg_gen_sari_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
c896fe29 | 1129 | { |
34151a20 FB |
1130 | if (arg2 == 0) { |
1131 | tcg_gen_mov_i64(ret, arg1); | |
1132 | } else { | |
a7812ae4 | 1133 | TCGv_i64 t0 = tcg_const_i64(arg2); |
e8996ee0 | 1134 | tcg_gen_sar_i64(ret, arg1, t0); |
a7812ae4 | 1135 | tcg_temp_free_i64(t0); |
34151a20 | 1136 | } |
c896fe29 FB |
1137 | } |
1138 | ||
a7812ae4 | 1139 | static inline void tcg_gen_brcond_i64(int cond, TCGv_i64 arg1, TCGv_i64 arg2, |
c896fe29 FB |
1140 | int label_index) |
1141 | { | |
a7812ae4 | 1142 | tcg_gen_op4ii_i64(INDEX_op_brcond_i64, arg1, arg2, cond, label_index); |
c896fe29 FB |
1143 | } |
1144 | ||
5105c556 AJ |
1145 | static inline void tcg_gen_setcond_i64(int cond, TCGv_i64 ret, |
1146 | TCGv_i64 arg1, TCGv_i64 arg2) | |
1147 | { | |
1148 | tcg_gen_op4i_i64(INDEX_op_setcond_i64, ret, arg1, arg2, cond); | |
1149 | } | |
1150 | ||
a7812ae4 | 1151 | static inline void tcg_gen_mul_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
c896fe29 | 1152 | { |
a7812ae4 | 1153 | tcg_gen_op3_i64(INDEX_op_mul_i64, ret, arg1, arg2); |
c896fe29 FB |
1154 | } |
1155 | ||
1156 | #ifdef TCG_TARGET_HAS_div_i64 | |
a7812ae4 | 1157 | static inline void tcg_gen_div_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
c896fe29 | 1158 | { |
a7812ae4 | 1159 | tcg_gen_op3_i64(INDEX_op_div_i64, ret, arg1, arg2); |
c896fe29 FB |
1160 | } |
1161 | ||
a7812ae4 | 1162 | static inline void tcg_gen_rem_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
c896fe29 | 1163 | { |
a7812ae4 | 1164 | tcg_gen_op3_i64(INDEX_op_rem_i64, ret, arg1, arg2); |
c896fe29 FB |
1165 | } |
1166 | ||
a7812ae4 | 1167 | static inline void tcg_gen_divu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
c896fe29 | 1168 | { |
a7812ae4 | 1169 | tcg_gen_op3_i64(INDEX_op_divu_i64, ret, arg1, arg2); |
c896fe29 FB |
1170 | } |
1171 | ||
a7812ae4 | 1172 | static inline void tcg_gen_remu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
c896fe29 | 1173 | { |
a7812ae4 | 1174 | tcg_gen_op3_i64(INDEX_op_remu_i64, ret, arg1, arg2); |
c896fe29 | 1175 | } |
31d66551 | 1176 | #elif defined(TCG_TARGET_HAS_div2_i64) |
a7812ae4 | 1177 | static inline void tcg_gen_div_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
c896fe29 | 1178 | { |
a7812ae4 PB |
1179 | TCGv_i64 t0; |
1180 | t0 = tcg_temp_new_i64(); | |
c896fe29 | 1181 | tcg_gen_sari_i64(t0, arg1, 63); |
a7812ae4 PB |
1182 | tcg_gen_op5_i64(INDEX_op_div2_i64, ret, t0, arg1, t0, arg2); |
1183 | tcg_temp_free_i64(t0); | |
c896fe29 FB |
1184 | } |
1185 | ||
a7812ae4 | 1186 | static inline void tcg_gen_rem_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
c896fe29 | 1187 | { |
a7812ae4 PB |
1188 | TCGv_i64 t0; |
1189 | t0 = tcg_temp_new_i64(); | |
c896fe29 | 1190 | tcg_gen_sari_i64(t0, arg1, 63); |
a7812ae4 PB |
1191 | tcg_gen_op5_i64(INDEX_op_div2_i64, t0, ret, arg1, t0, arg2); |
1192 | tcg_temp_free_i64(t0); | |
c896fe29 FB |
1193 | } |
1194 | ||
a7812ae4 | 1195 | static inline void tcg_gen_divu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
c896fe29 | 1196 | { |
a7812ae4 PB |
1197 | TCGv_i64 t0; |
1198 | t0 = tcg_temp_new_i64(); | |
c896fe29 | 1199 | tcg_gen_movi_i64(t0, 0); |
a7812ae4 PB |
1200 | tcg_gen_op5_i64(INDEX_op_divu2_i64, ret, t0, arg1, t0, arg2); |
1201 | tcg_temp_free_i64(t0); | |
c896fe29 FB |
1202 | } |
1203 | ||
a7812ae4 | 1204 | static inline void tcg_gen_remu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
c896fe29 | 1205 | { |
a7812ae4 PB |
1206 | TCGv_i64 t0; |
1207 | t0 = tcg_temp_new_i64(); | |
c896fe29 | 1208 | tcg_gen_movi_i64(t0, 0); |
a7812ae4 PB |
1209 | tcg_gen_op5_i64(INDEX_op_divu2_i64, t0, ret, arg1, t0, arg2); |
1210 | tcg_temp_free_i64(t0); | |
c896fe29 | 1211 | } |
31d66551 AJ |
1212 | #else |
1213 | static inline void tcg_gen_div_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) | |
1214 | { | |
1215 | tcg_gen_helper64(tcg_helper_div_i64, ret, arg1, arg2); | |
1216 | } | |
1217 | ||
1218 | static inline void tcg_gen_rem_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) | |
1219 | { | |
1220 | tcg_gen_helper64(tcg_helper_rem_i64, ret, arg1, arg2); | |
1221 | } | |
1222 | ||
1223 | static inline void tcg_gen_divu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) | |
1224 | { | |
1225 | tcg_gen_helper64(tcg_helper_divu_i64, ret, arg1, arg2); | |
1226 | } | |
1227 | ||
1228 | static inline void tcg_gen_remu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) | |
1229 | { | |
1230 | tcg_gen_helper64(tcg_helper_remu_i64, ret, arg1, arg2); | |
1231 | } | |
c896fe29 FB |
1232 | #endif |
1233 | ||
1234 | #endif | |
1235 | ||
a7812ae4 | 1236 | static inline void tcg_gen_addi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
6359706f AJ |
1237 | { |
1238 | /* some cases can be optimized here */ | |
1239 | if (arg2 == 0) { | |
1240 | tcg_gen_mov_i64(ret, arg1); | |
1241 | } else { | |
a7812ae4 | 1242 | TCGv_i64 t0 = tcg_const_i64(arg2); |
6359706f | 1243 | tcg_gen_add_i64(ret, arg1, t0); |
a7812ae4 | 1244 | tcg_temp_free_i64(t0); |
6359706f AJ |
1245 | } |
1246 | } | |
1247 | ||
a7812ae4 | 1248 | static inline void tcg_gen_subfi_i64(TCGv_i64 ret, int64_t arg1, TCGv_i64 arg2) |
0045734a | 1249 | { |
a7812ae4 | 1250 | TCGv_i64 t0 = tcg_const_i64(arg1); |
0045734a | 1251 | tcg_gen_sub_i64(ret, t0, arg2); |
a7812ae4 | 1252 | tcg_temp_free_i64(t0); |
0045734a AJ |
1253 | } |
1254 | ||
a7812ae4 | 1255 | static inline void tcg_gen_subi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
6359706f AJ |
1256 | { |
1257 | /* some cases can be optimized here */ | |
1258 | if (arg2 == 0) { | |
1259 | tcg_gen_mov_i64(ret, arg1); | |
1260 | } else { | |
a7812ae4 | 1261 | TCGv_i64 t0 = tcg_const_i64(arg2); |
6359706f | 1262 | tcg_gen_sub_i64(ret, arg1, t0); |
a7812ae4 | 1263 | tcg_temp_free_i64(t0); |
6359706f AJ |
1264 | } |
1265 | } | |
a7812ae4 | 1266 | static inline void tcg_gen_brcondi_i64(int cond, TCGv_i64 arg1, int64_t arg2, |
f02bb954 AJ |
1267 | int label_index) |
1268 | { | |
a7812ae4 | 1269 | TCGv_i64 t0 = tcg_const_i64(arg2); |
f02bb954 | 1270 | tcg_gen_brcond_i64(cond, arg1, t0, label_index); |
a7812ae4 | 1271 | tcg_temp_free_i64(t0); |
f02bb954 AJ |
1272 | } |
1273 | ||
5105c556 AJ |
1274 | static inline void tcg_gen_setcondi_i64(int cond, TCGv_i64 ret, TCGv_i64 arg1, |
1275 | int64_t arg2) | |
1276 | { | |
1277 | TCGv_i64 t0 = tcg_const_i64(arg2); | |
1278 | tcg_gen_setcond_i64(cond, ret, arg1, t0); | |
1279 | tcg_temp_free_i64(t0); | |
1280 | } | |
1281 | ||
a7812ae4 | 1282 | static inline void tcg_gen_muli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
f02bb954 | 1283 | { |
a7812ae4 | 1284 | TCGv_i64 t0 = tcg_const_i64(arg2); |
f02bb954 | 1285 | tcg_gen_mul_i64(ret, arg1, t0); |
a7812ae4 | 1286 | tcg_temp_free_i64(t0); |
f02bb954 AJ |
1287 | } |
1288 | ||
6359706f | 1289 | |
c896fe29 FB |
1290 | /***************************************/ |
1291 | /* optional operations */ | |
1292 | ||
a7812ae4 | 1293 | static inline void tcg_gen_ext8s_i32(TCGv_i32 ret, TCGv_i32 arg) |
c896fe29 FB |
1294 | { |
1295 | #ifdef TCG_TARGET_HAS_ext8s_i32 | |
a7812ae4 | 1296 | tcg_gen_op2_i32(INDEX_op_ext8s_i32, ret, arg); |
c896fe29 FB |
1297 | #else |
1298 | tcg_gen_shli_i32(ret, arg, 24); | |
5ff9d6a4 | 1299 | tcg_gen_sari_i32(ret, ret, 24); |
c896fe29 FB |
1300 | #endif |
1301 | } | |
1302 | ||
a7812ae4 | 1303 | static inline void tcg_gen_ext16s_i32(TCGv_i32 ret, TCGv_i32 arg) |
c896fe29 FB |
1304 | { |
1305 | #ifdef TCG_TARGET_HAS_ext16s_i32 | |
a7812ae4 | 1306 | tcg_gen_op2_i32(INDEX_op_ext16s_i32, ret, arg); |
c896fe29 FB |
1307 | #else |
1308 | tcg_gen_shli_i32(ret, arg, 16); | |
5ff9d6a4 | 1309 | tcg_gen_sari_i32(ret, ret, 16); |
c896fe29 FB |
1310 | #endif |
1311 | } | |
1312 | ||
a7812ae4 | 1313 | static inline void tcg_gen_ext8u_i32(TCGv_i32 ret, TCGv_i32 arg) |
86831435 | 1314 | { |
cfc86988 AJ |
1315 | #ifdef TCG_TARGET_HAS_ext8u_i32 |
1316 | tcg_gen_op2_i32(INDEX_op_ext8u_i32, ret, arg); | |
1317 | #else | |
86831435 | 1318 | tcg_gen_andi_i32(ret, arg, 0xffu); |
cfc86988 | 1319 | #endif |
86831435 PB |
1320 | } |
1321 | ||
a7812ae4 | 1322 | static inline void tcg_gen_ext16u_i32(TCGv_i32 ret, TCGv_i32 arg) |
86831435 | 1323 | { |
cfc86988 AJ |
1324 | #ifdef TCG_TARGET_HAS_ext16u_i32 |
1325 | tcg_gen_op2_i32(INDEX_op_ext16u_i32, ret, arg); | |
1326 | #else | |
86831435 | 1327 | tcg_gen_andi_i32(ret, arg, 0xffffu); |
cfc86988 | 1328 | #endif |
86831435 PB |
1329 | } |
1330 | ||
c896fe29 | 1331 | /* Note: we assume the two high bytes are set to zero */ |
a7812ae4 | 1332 | static inline void tcg_gen_bswap16_i32(TCGv_i32 ret, TCGv_i32 arg) |
c896fe29 FB |
1333 | { |
1334 | #ifdef TCG_TARGET_HAS_bswap16_i32 | |
a7812ae4 | 1335 | tcg_gen_op2_i32(INDEX_op_bswap16_i32, ret, arg); |
c896fe29 | 1336 | #else |
dfa1a3f1 | 1337 | TCGv_i32 t0 = tcg_temp_new_i32(); |
c896fe29 | 1338 | |
dfa1a3f1 AJ |
1339 | tcg_gen_ext8u_i32(t0, arg); |
1340 | tcg_gen_shli_i32(t0, t0, 8); | |
1341 | tcg_gen_shri_i32(ret, arg, 8); | |
1342 | tcg_gen_or_i32(ret, ret, t0); | |
a7812ae4 | 1343 | tcg_temp_free_i32(t0); |
c896fe29 FB |
1344 | #endif |
1345 | } | |
1346 | ||
66896cb8 | 1347 | static inline void tcg_gen_bswap32_i32(TCGv_i32 ret, TCGv_i32 arg) |
c896fe29 | 1348 | { |
66896cb8 AJ |
1349 | #ifdef TCG_TARGET_HAS_bswap32_i32 |
1350 | tcg_gen_op2_i32(INDEX_op_bswap32_i32, ret, arg); | |
c896fe29 | 1351 | #else |
a7812ae4 PB |
1352 | TCGv_i32 t0, t1; |
1353 | t0 = tcg_temp_new_i32(); | |
1354 | t1 = tcg_temp_new_i32(); | |
c896fe29 FB |
1355 | |
1356 | tcg_gen_shli_i32(t0, arg, 24); | |
1357 | ||
1358 | tcg_gen_andi_i32(t1, arg, 0x0000ff00); | |
1359 | tcg_gen_shli_i32(t1, t1, 8); | |
1360 | tcg_gen_or_i32(t0, t0, t1); | |
1361 | ||
1362 | tcg_gen_shri_i32(t1, arg, 8); | |
1363 | tcg_gen_andi_i32(t1, t1, 0x0000ff00); | |
1364 | tcg_gen_or_i32(t0, t0, t1); | |
1365 | ||
1366 | tcg_gen_shri_i32(t1, arg, 24); | |
1367 | tcg_gen_or_i32(ret, t0, t1); | |
a7812ae4 PB |
1368 | tcg_temp_free_i32(t0); |
1369 | tcg_temp_free_i32(t1); | |
c896fe29 FB |
1370 | #endif |
1371 | } | |
1372 | ||
1373 | #if TCG_TARGET_REG_BITS == 32 | |
a7812ae4 | 1374 | static inline void tcg_gen_ext8s_i64(TCGv_i64 ret, TCGv_i64 arg) |
c896fe29 | 1375 | { |
a7812ae4 PB |
1376 | tcg_gen_ext8s_i32(TCGV_LOW(ret), TCGV_LOW(arg)); |
1377 | tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31); | |
c896fe29 FB |
1378 | } |
1379 | ||
a7812ae4 | 1380 | static inline void tcg_gen_ext16s_i64(TCGv_i64 ret, TCGv_i64 arg) |
c896fe29 | 1381 | { |
a7812ae4 PB |
1382 | tcg_gen_ext16s_i32(TCGV_LOW(ret), TCGV_LOW(arg)); |
1383 | tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31); | |
c896fe29 FB |
1384 | } |
1385 | ||
a7812ae4 | 1386 | static inline void tcg_gen_ext32s_i64(TCGv_i64 ret, TCGv_i64 arg) |
c896fe29 | 1387 | { |
a7812ae4 PB |
1388 | tcg_gen_mov_i32(TCGV_LOW(ret), TCGV_LOW(arg)); |
1389 | tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31); | |
c896fe29 FB |
1390 | } |
1391 | ||
a7812ae4 | 1392 | static inline void tcg_gen_ext8u_i64(TCGv_i64 ret, TCGv_i64 arg) |
86831435 | 1393 | { |
a7812ae4 | 1394 | tcg_gen_ext8u_i32(TCGV_LOW(ret), TCGV_LOW(arg)); |
86831435 PB |
1395 | tcg_gen_movi_i32(TCGV_HIGH(ret), 0); |
1396 | } | |
1397 | ||
a7812ae4 | 1398 | static inline void tcg_gen_ext16u_i64(TCGv_i64 ret, TCGv_i64 arg) |
86831435 | 1399 | { |
a7812ae4 | 1400 | tcg_gen_ext16u_i32(TCGV_LOW(ret), TCGV_LOW(arg)); |
86831435 PB |
1401 | tcg_gen_movi_i32(TCGV_HIGH(ret), 0); |
1402 | } | |
1403 | ||
a7812ae4 | 1404 | static inline void tcg_gen_ext32u_i64(TCGv_i64 ret, TCGv_i64 arg) |
86831435 | 1405 | { |
a7812ae4 | 1406 | tcg_gen_mov_i32(TCGV_LOW(ret), TCGV_LOW(arg)); |
86831435 PB |
1407 | tcg_gen_movi_i32(TCGV_HIGH(ret), 0); |
1408 | } | |
1409 | ||
a7812ae4 | 1410 | static inline void tcg_gen_trunc_i64_i32(TCGv_i32 ret, TCGv_i64 arg) |
c896fe29 | 1411 | { |
a7812ae4 | 1412 | tcg_gen_mov_i32(ret, TCGV_LOW(arg)); |
c896fe29 FB |
1413 | } |
1414 | ||
a7812ae4 | 1415 | static inline void tcg_gen_extu_i32_i64(TCGv_i64 ret, TCGv_i32 arg) |
c896fe29 | 1416 | { |
a7812ae4 | 1417 | tcg_gen_mov_i32(TCGV_LOW(ret), arg); |
ac56dd48 | 1418 | tcg_gen_movi_i32(TCGV_HIGH(ret), 0); |
c896fe29 FB |
1419 | } |
1420 | ||
a7812ae4 | 1421 | static inline void tcg_gen_ext_i32_i64(TCGv_i64 ret, TCGv_i32 arg) |
c896fe29 | 1422 | { |
a7812ae4 PB |
1423 | tcg_gen_mov_i32(TCGV_LOW(ret), arg); |
1424 | tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31); | |
c896fe29 FB |
1425 | } |
1426 | ||
9a5c57fd AJ |
1427 | /* Note: we assume the six high bytes are set to zero */ |
1428 | static inline void tcg_gen_bswap16_i64(TCGv_i64 ret, TCGv_i64 arg) | |
1429 | { | |
1430 | tcg_gen_mov_i32(TCGV_HIGH(ret), TCGV_HIGH(arg)); | |
1431 | tcg_gen_bswap16_i32(TCGV_LOW(ret), TCGV_LOW(arg)); | |
1432 | } | |
1433 | ||
1434 | /* Note: we assume the four high bytes are set to zero */ | |
1435 | static inline void tcg_gen_bswap32_i64(TCGv_i64 ret, TCGv_i64 arg) | |
1436 | { | |
1437 | tcg_gen_mov_i32(TCGV_HIGH(ret), TCGV_HIGH(arg)); | |
1438 | tcg_gen_bswap32_i32(TCGV_LOW(ret), TCGV_LOW(arg)); | |
1439 | } | |
1440 | ||
66896cb8 | 1441 | static inline void tcg_gen_bswap64_i64(TCGv_i64 ret, TCGv_i64 arg) |
c896fe29 | 1442 | { |
a7812ae4 PB |
1443 | TCGv_i32 t0, t1; |
1444 | t0 = tcg_temp_new_i32(); | |
1445 | t1 = tcg_temp_new_i32(); | |
c896fe29 | 1446 | |
66896cb8 AJ |
1447 | tcg_gen_bswap32_i32(t0, TCGV_LOW(arg)); |
1448 | tcg_gen_bswap32_i32(t1, TCGV_HIGH(arg)); | |
a7812ae4 | 1449 | tcg_gen_mov_i32(TCGV_LOW(ret), t1); |
ac56dd48 | 1450 | tcg_gen_mov_i32(TCGV_HIGH(ret), t0); |
a7812ae4 PB |
1451 | tcg_temp_free_i32(t0); |
1452 | tcg_temp_free_i32(t1); | |
c896fe29 FB |
1453 | } |
1454 | #else | |
1455 | ||
a7812ae4 | 1456 | static inline void tcg_gen_ext8s_i64(TCGv_i64 ret, TCGv_i64 arg) |
c896fe29 FB |
1457 | { |
1458 | #ifdef TCG_TARGET_HAS_ext8s_i64 | |
a7812ae4 | 1459 | tcg_gen_op2_i64(INDEX_op_ext8s_i64, ret, arg); |
c896fe29 FB |
1460 | #else |
1461 | tcg_gen_shli_i64(ret, arg, 56); | |
5ff9d6a4 | 1462 | tcg_gen_sari_i64(ret, ret, 56); |
c896fe29 FB |
1463 | #endif |
1464 | } | |
1465 | ||
a7812ae4 | 1466 | static inline void tcg_gen_ext16s_i64(TCGv_i64 ret, TCGv_i64 arg) |
c896fe29 FB |
1467 | { |
1468 | #ifdef TCG_TARGET_HAS_ext16s_i64 | |
a7812ae4 | 1469 | tcg_gen_op2_i64(INDEX_op_ext16s_i64, ret, arg); |
c896fe29 FB |
1470 | #else |
1471 | tcg_gen_shli_i64(ret, arg, 48); | |
5ff9d6a4 | 1472 | tcg_gen_sari_i64(ret, ret, 48); |
c896fe29 FB |
1473 | #endif |
1474 | } | |
1475 | ||
a7812ae4 | 1476 | static inline void tcg_gen_ext32s_i64(TCGv_i64 ret, TCGv_i64 arg) |
c896fe29 FB |
1477 | { |
1478 | #ifdef TCG_TARGET_HAS_ext32s_i64 | |
a7812ae4 | 1479 | tcg_gen_op2_i64(INDEX_op_ext32s_i64, ret, arg); |
c896fe29 FB |
1480 | #else |
1481 | tcg_gen_shli_i64(ret, arg, 32); | |
5ff9d6a4 | 1482 | tcg_gen_sari_i64(ret, ret, 32); |
c896fe29 FB |
1483 | #endif |
1484 | } | |
1485 | ||
a7812ae4 | 1486 | static inline void tcg_gen_ext8u_i64(TCGv_i64 ret, TCGv_i64 arg) |
86831435 | 1487 | { |
cfc86988 AJ |
1488 | #ifdef TCG_TARGET_HAS_ext8u_i64 |
1489 | tcg_gen_op2_i64(INDEX_op_ext8u_i64, ret, arg); | |
1490 | #else | |
86831435 | 1491 | tcg_gen_andi_i64(ret, arg, 0xffu); |
cfc86988 | 1492 | #endif |
86831435 PB |
1493 | } |
1494 | ||
a7812ae4 | 1495 | static inline void tcg_gen_ext16u_i64(TCGv_i64 ret, TCGv_i64 arg) |
86831435 | 1496 | { |
cfc86988 AJ |
1497 | #ifdef TCG_TARGET_HAS_ext16u_i64 |
1498 | tcg_gen_op2_i64(INDEX_op_ext16u_i64, ret, arg); | |
1499 | #else | |
86831435 | 1500 | tcg_gen_andi_i64(ret, arg, 0xffffu); |
cfc86988 | 1501 | #endif |
86831435 PB |
1502 | } |
1503 | ||
a7812ae4 | 1504 | static inline void tcg_gen_ext32u_i64(TCGv_i64 ret, TCGv_i64 arg) |
86831435 | 1505 | { |
cfc86988 AJ |
1506 | #ifdef TCG_TARGET_HAS_ext32u_i64 |
1507 | tcg_gen_op2_i64(INDEX_op_ext32u_i64, ret, arg); | |
1508 | #else | |
86831435 | 1509 | tcg_gen_andi_i64(ret, arg, 0xffffffffu); |
cfc86988 | 1510 | #endif |
86831435 PB |
1511 | } |
1512 | ||
c896fe29 | 1513 | /* Note: we assume the target supports move between 32 and 64 bit |
ac56dd48 | 1514 | registers. This will probably break MIPS64 targets. */ |
a7812ae4 | 1515 | static inline void tcg_gen_trunc_i64_i32(TCGv_i32 ret, TCGv_i64 arg) |
c896fe29 | 1516 | { |
a7812ae4 | 1517 | tcg_gen_mov_i32(ret, MAKE_TCGV_I32(GET_TCGV_I64(arg))); |
c896fe29 FB |
1518 | } |
1519 | ||
1520 | /* Note: we assume the target supports move between 32 and 64 bit | |
1521 | registers */ | |
a7812ae4 | 1522 | static inline void tcg_gen_extu_i32_i64(TCGv_i64 ret, TCGv_i32 arg) |
c896fe29 | 1523 | { |
cfc86988 | 1524 | tcg_gen_ext32u_i64(ret, MAKE_TCGV_I64(GET_TCGV_I32(arg))); |
c896fe29 FB |
1525 | } |
1526 | ||
1527 | /* Note: we assume the target supports move between 32 and 64 bit | |
1528 | registers */ | |
a7812ae4 | 1529 | static inline void tcg_gen_ext_i32_i64(TCGv_i64 ret, TCGv_i32 arg) |
c896fe29 | 1530 | { |
a7812ae4 | 1531 | tcg_gen_ext32s_i64(ret, MAKE_TCGV_I64(GET_TCGV_I32(arg))); |
c896fe29 FB |
1532 | } |
1533 | ||
9a5c57fd AJ |
1534 | /* Note: we assume the six high bytes are set to zero */ |
1535 | static inline void tcg_gen_bswap16_i64(TCGv_i64 ret, TCGv_i64 arg) | |
1536 | { | |
1537 | #ifdef TCG_TARGET_HAS_bswap16_i64 | |
1538 | tcg_gen_op2_i64(INDEX_op_bswap16_i64, ret, arg); | |
1539 | #else | |
1540 | TCGv_i64 t0 = tcg_temp_new_i64(); | |
1541 | ||
1542 | tcg_gen_ext8u_i64(t0, arg); | |
1543 | tcg_gen_shli_i64(t0, t0, 8); | |
1544 | tcg_gen_shri_i64(ret, arg, 8); | |
1545 | tcg_gen_or_i64(ret, ret, t0); | |
1546 | tcg_temp_free_i64(t0); | |
1547 | #endif | |
1548 | } | |
1549 | ||
1550 | /* Note: we assume the four high bytes are set to zero */ | |
1551 | static inline void tcg_gen_bswap32_i64(TCGv_i64 ret, TCGv_i64 arg) | |
1552 | { | |
1553 | #ifdef TCG_TARGET_HAS_bswap32_i64 | |
1554 | tcg_gen_op2_i64(INDEX_op_bswap32_i64, ret, arg); | |
1555 | #else | |
1556 | TCGv_i64 t0, t1; | |
1557 | t0 = tcg_temp_new_i64(); | |
1558 | t1 = tcg_temp_new_i64(); | |
1559 | ||
1560 | tcg_gen_shli_i64(t0, arg, 24); | |
1561 | tcg_gen_ext32u_i64(t0, t0); | |
1562 | ||
1563 | tcg_gen_andi_i64(t1, arg, 0x0000ff00); | |
1564 | tcg_gen_shli_i64(t1, t1, 8); | |
1565 | tcg_gen_or_i64(t0, t0, t1); | |
1566 | ||
1567 | tcg_gen_shri_i64(t1, arg, 8); | |
1568 | tcg_gen_andi_i64(t1, t1, 0x0000ff00); | |
1569 | tcg_gen_or_i64(t0, t0, t1); | |
1570 | ||
1571 | tcg_gen_shri_i64(t1, arg, 24); | |
1572 | tcg_gen_or_i64(ret, t0, t1); | |
1573 | tcg_temp_free_i64(t0); | |
1574 | tcg_temp_free_i64(t1); | |
1575 | #endif | |
1576 | } | |
1577 | ||
66896cb8 | 1578 | static inline void tcg_gen_bswap64_i64(TCGv_i64 ret, TCGv_i64 arg) |
c896fe29 | 1579 | { |
66896cb8 AJ |
1580 | #ifdef TCG_TARGET_HAS_bswap64_i64 |
1581 | tcg_gen_op2_i64(INDEX_op_bswap64_i64, ret, arg); | |
c896fe29 | 1582 | #else |
b348113d SW |
1583 | TCGv_i64 t0 = tcg_temp_new_i64(); |
1584 | TCGv_i64 t1 = tcg_temp_new_i64(); | |
c896fe29 FB |
1585 | |
1586 | tcg_gen_shli_i64(t0, arg, 56); | |
1587 | ||
1588 | tcg_gen_andi_i64(t1, arg, 0x0000ff00); | |
1589 | tcg_gen_shli_i64(t1, t1, 40); | |
1590 | tcg_gen_or_i64(t0, t0, t1); | |
1591 | ||
1592 | tcg_gen_andi_i64(t1, arg, 0x00ff0000); | |
1593 | tcg_gen_shli_i64(t1, t1, 24); | |
1594 | tcg_gen_or_i64(t0, t0, t1); | |
1595 | ||
1596 | tcg_gen_andi_i64(t1, arg, 0xff000000); | |
1597 | tcg_gen_shli_i64(t1, t1, 8); | |
1598 | tcg_gen_or_i64(t0, t0, t1); | |
1599 | ||
1600 | tcg_gen_shri_i64(t1, arg, 8); | |
1601 | tcg_gen_andi_i64(t1, t1, 0xff000000); | |
1602 | tcg_gen_or_i64(t0, t0, t1); | |
1603 | ||
1604 | tcg_gen_shri_i64(t1, arg, 24); | |
1605 | tcg_gen_andi_i64(t1, t1, 0x00ff0000); | |
1606 | tcg_gen_or_i64(t0, t0, t1); | |
1607 | ||
1608 | tcg_gen_shri_i64(t1, arg, 40); | |
1609 | tcg_gen_andi_i64(t1, t1, 0x0000ff00); | |
1610 | tcg_gen_or_i64(t0, t0, t1); | |
1611 | ||
1612 | tcg_gen_shri_i64(t1, arg, 56); | |
1613 | tcg_gen_or_i64(ret, t0, t1); | |
b348113d SW |
1614 | tcg_temp_free_i64(t0); |
1615 | tcg_temp_free_i64(t1); | |
c896fe29 FB |
1616 | #endif |
1617 | } | |
1618 | ||
1619 | #endif | |
1620 | ||
a7812ae4 | 1621 | static inline void tcg_gen_neg_i32(TCGv_i32 ret, TCGv_i32 arg) |
390efc54 PB |
1622 | { |
1623 | #ifdef TCG_TARGET_HAS_neg_i32 | |
a7812ae4 | 1624 | tcg_gen_op2_i32(INDEX_op_neg_i32, ret, arg); |
390efc54 | 1625 | #else |
a7812ae4 | 1626 | TCGv_i32 t0 = tcg_const_i32(0); |
e8996ee0 | 1627 | tcg_gen_sub_i32(ret, t0, arg); |
a7812ae4 | 1628 | tcg_temp_free_i32(t0); |
390efc54 PB |
1629 | #endif |
1630 | } | |
1631 | ||
a7812ae4 | 1632 | static inline void tcg_gen_neg_i64(TCGv_i64 ret, TCGv_i64 arg) |
390efc54 PB |
1633 | { |
1634 | #ifdef TCG_TARGET_HAS_neg_i64 | |
a7812ae4 | 1635 | tcg_gen_op2_i64(INDEX_op_neg_i64, ret, arg); |
390efc54 | 1636 | #else |
a7812ae4 | 1637 | TCGv_i64 t0 = tcg_const_i64(0); |
e8996ee0 | 1638 | tcg_gen_sub_i64(ret, t0, arg); |
a7812ae4 | 1639 | tcg_temp_free_i64(t0); |
390efc54 PB |
1640 | #endif |
1641 | } | |
1642 | ||
a7812ae4 | 1643 | static inline void tcg_gen_not_i32(TCGv_i32 ret, TCGv_i32 arg) |
0b6ce4cf | 1644 | { |
d2604285 AJ |
1645 | #ifdef TCG_TARGET_HAS_not_i32 |
1646 | tcg_gen_op2_i32(INDEX_op_not_i32, ret, arg); | |
1647 | #else | |
e8996ee0 | 1648 | tcg_gen_xori_i32(ret, arg, -1); |
d2604285 | 1649 | #endif |
0b6ce4cf FB |
1650 | } |
1651 | ||
a7812ae4 | 1652 | static inline void tcg_gen_not_i64(TCGv_i64 ret, TCGv_i64 arg) |
0b6ce4cf | 1653 | { |
d2604285 | 1654 | #ifdef TCG_TARGET_HAS_not_i64 |
43e860ef | 1655 | tcg_gen_op2_i64(INDEX_op_not_i64, ret, arg); |
d2604285 | 1656 | #else |
e8996ee0 | 1657 | tcg_gen_xori_i64(ret, arg, -1); |
d2604285 | 1658 | #endif |
0b6ce4cf | 1659 | } |
5ff9d6a4 | 1660 | |
a7812ae4 | 1661 | static inline void tcg_gen_discard_i32(TCGv_i32 arg) |
5ff9d6a4 | 1662 | { |
a7812ae4 | 1663 | tcg_gen_op1_i32(INDEX_op_discard, arg); |
5ff9d6a4 FB |
1664 | } |
1665 | ||
1666 | #if TCG_TARGET_REG_BITS == 32 | |
a7812ae4 | 1667 | static inline void tcg_gen_discard_i64(TCGv_i64 arg) |
5ff9d6a4 | 1668 | { |
a7812ae4 | 1669 | tcg_gen_discard_i32(TCGV_LOW(arg)); |
5ff9d6a4 FB |
1670 | tcg_gen_discard_i32(TCGV_HIGH(arg)); |
1671 | } | |
1672 | #else | |
a7812ae4 | 1673 | static inline void tcg_gen_discard_i64(TCGv_i64 arg) |
5ff9d6a4 | 1674 | { |
a7812ae4 | 1675 | tcg_gen_op1_i64(INDEX_op_discard, arg); |
5ff9d6a4 FB |
1676 | } |
1677 | #endif | |
1678 | ||
a7812ae4 | 1679 | static inline void tcg_gen_concat_i32_i64(TCGv_i64 dest, TCGv_i32 low, TCGv_i32 high) |
36aa55dc PB |
1680 | { |
1681 | #if TCG_TARGET_REG_BITS == 32 | |
a7812ae4 | 1682 | tcg_gen_mov_i32(TCGV_LOW(dest), low); |
36aa55dc PB |
1683 | tcg_gen_mov_i32(TCGV_HIGH(dest), high); |
1684 | #else | |
a7812ae4 | 1685 | TCGv_i64 tmp = tcg_temp_new_i64(); |
36aa55dc PB |
1686 | /* This extension is only needed for type correctness. |
1687 | We may be able to do better given target specific information. */ | |
1688 | tcg_gen_extu_i32_i64(tmp, high); | |
1689 | tcg_gen_shli_i64(tmp, tmp, 32); | |
1690 | tcg_gen_extu_i32_i64(dest, low); | |
1691 | tcg_gen_or_i64(dest, dest, tmp); | |
a7812ae4 | 1692 | tcg_temp_free_i64(tmp); |
36aa55dc PB |
1693 | #endif |
1694 | } | |
1695 | ||
a7812ae4 | 1696 | static inline void tcg_gen_concat32_i64(TCGv_i64 dest, TCGv_i64 low, TCGv_i64 high) |
945ca823 BS |
1697 | { |
1698 | #if TCG_TARGET_REG_BITS == 32 | |
a7812ae4 | 1699 | tcg_gen_concat_i32_i64(dest, TCGV_LOW(low), TCGV_LOW(high)); |
945ca823 | 1700 | #else |
a7812ae4 | 1701 | TCGv_i64 tmp = tcg_temp_new_i64(); |
88422e2e | 1702 | tcg_gen_ext32u_i64(dest, low); |
945ca823 | 1703 | tcg_gen_shli_i64(tmp, high, 32); |
88422e2e | 1704 | tcg_gen_or_i64(dest, dest, tmp); |
a7812ae4 | 1705 | tcg_temp_free_i64(tmp); |
945ca823 BS |
1706 | #endif |
1707 | } | |
1708 | ||
a7812ae4 | 1709 | static inline void tcg_gen_andc_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
f24cb33e | 1710 | { |
241cbed4 RH |
1711 | #ifdef TCG_TARGET_HAS_andc_i32 |
1712 | tcg_gen_op3_i32(INDEX_op_andc_i32, ret, arg1, arg2); | |
1713 | #else | |
a7812ae4 PB |
1714 | TCGv_i32 t0; |
1715 | t0 = tcg_temp_new_i32(); | |
f24cb33e AJ |
1716 | tcg_gen_not_i32(t0, arg2); |
1717 | tcg_gen_and_i32(ret, arg1, t0); | |
a7812ae4 | 1718 | tcg_temp_free_i32(t0); |
241cbed4 | 1719 | #endif |
f24cb33e AJ |
1720 | } |
1721 | ||
a7812ae4 | 1722 | static inline void tcg_gen_andc_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
f24cb33e | 1723 | { |
241cbed4 RH |
1724 | #ifdef TCG_TARGET_HAS_andc_i64 |
1725 | tcg_gen_op3_i64(INDEX_op_andc_i64, ret, arg1, arg2); | |
1726 | #elif defined(TCG_TARGET_HAS_andc_i32) && TCG_TARGET_REG_BITS == 32 | |
1727 | tcg_gen_andc_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2)); | |
1728 | tcg_gen_andc_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2)); | |
1729 | #else | |
a7812ae4 PB |
1730 | TCGv_i64 t0; |
1731 | t0 = tcg_temp_new_i64(); | |
f24cb33e AJ |
1732 | tcg_gen_not_i64(t0, arg2); |
1733 | tcg_gen_and_i64(ret, arg1, t0); | |
a7812ae4 | 1734 | tcg_temp_free_i64(t0); |
241cbed4 | 1735 | #endif |
f24cb33e AJ |
1736 | } |
1737 | ||
a7812ae4 | 1738 | static inline void tcg_gen_eqv_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
f24cb33e | 1739 | { |
7fc81051 AJ |
1740 | tcg_gen_xor_i32(ret, arg1, arg2); |
1741 | tcg_gen_not_i32(ret, ret); | |
f24cb33e AJ |
1742 | } |
1743 | ||
a7812ae4 | 1744 | static inline void tcg_gen_eqv_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
f24cb33e | 1745 | { |
7fc81051 AJ |
1746 | tcg_gen_xor_i64(ret, arg1, arg2); |
1747 | tcg_gen_not_i64(ret, ret); | |
f24cb33e AJ |
1748 | } |
1749 | ||
a7812ae4 | 1750 | static inline void tcg_gen_nand_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
f24cb33e | 1751 | { |
7fc81051 AJ |
1752 | tcg_gen_and_i32(ret, arg1, arg2); |
1753 | tcg_gen_not_i32(ret, ret); | |
f24cb33e AJ |
1754 | } |
1755 | ||
a7812ae4 | 1756 | static inline void tcg_gen_nand_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
f24cb33e | 1757 | { |
7fc81051 AJ |
1758 | tcg_gen_and_i64(ret, arg1, arg2); |
1759 | tcg_gen_not_i64(ret, ret); | |
f24cb33e AJ |
1760 | } |
1761 | ||
a7812ae4 | 1762 | static inline void tcg_gen_nor_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
f24cb33e | 1763 | { |
7fc81051 AJ |
1764 | tcg_gen_or_i32(ret, arg1, arg2); |
1765 | tcg_gen_not_i32(ret, ret); | |
f24cb33e AJ |
1766 | } |
1767 | ||
a7812ae4 | 1768 | static inline void tcg_gen_nor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
f24cb33e | 1769 | { |
7fc81051 AJ |
1770 | tcg_gen_or_i64(ret, arg1, arg2); |
1771 | tcg_gen_not_i64(ret, ret); | |
f24cb33e AJ |
1772 | } |
1773 | ||
a7812ae4 | 1774 | static inline void tcg_gen_orc_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
f24cb33e | 1775 | { |
791d1262 RH |
1776 | #ifdef TCG_TARGET_HAS_orc_i32 |
1777 | tcg_gen_op3_i32(INDEX_op_orc_i32, ret, arg1, arg2); | |
1778 | #else | |
a7812ae4 PB |
1779 | TCGv_i32 t0; |
1780 | t0 = tcg_temp_new_i32(); | |
f24cb33e AJ |
1781 | tcg_gen_not_i32(t0, arg2); |
1782 | tcg_gen_or_i32(ret, arg1, t0); | |
a7812ae4 | 1783 | tcg_temp_free_i32(t0); |
791d1262 | 1784 | #endif |
f24cb33e AJ |
1785 | } |
1786 | ||
a7812ae4 | 1787 | static inline void tcg_gen_orc_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
f24cb33e | 1788 | { |
791d1262 RH |
1789 | #ifdef TCG_TARGET_HAS_orc_i64 |
1790 | tcg_gen_op3_i64(INDEX_op_orc_i64, ret, arg1, arg2); | |
1791 | #elif defined(TCG_TARGET_HAS_orc_i32) && TCG_TARGET_REG_BITS == 32 | |
1792 | tcg_gen_orc_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2)); | |
1793 | tcg_gen_orc_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2)); | |
1794 | #else | |
a7812ae4 PB |
1795 | TCGv_i64 t0; |
1796 | t0 = tcg_temp_new_i64(); | |
f24cb33e AJ |
1797 | tcg_gen_not_i64(t0, arg2); |
1798 | tcg_gen_or_i64(ret, arg1, t0); | |
a7812ae4 | 1799 | tcg_temp_free_i64(t0); |
791d1262 | 1800 | #endif |
f24cb33e AJ |
1801 | } |
1802 | ||
a7812ae4 | 1803 | static inline void tcg_gen_rotl_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
15824571 | 1804 | { |
d42f183c AJ |
1805 | #ifdef TCG_TARGET_HAS_rot_i32 |
1806 | tcg_gen_op3_i32(INDEX_op_rotl_i32, ret, arg1, arg2); | |
1807 | #else | |
a7812ae4 | 1808 | TCGv_i32 t0, t1; |
15824571 | 1809 | |
a7812ae4 PB |
1810 | t0 = tcg_temp_new_i32(); |
1811 | t1 = tcg_temp_new_i32(); | |
15824571 AJ |
1812 | tcg_gen_shl_i32(t0, arg1, arg2); |
1813 | tcg_gen_subfi_i32(t1, 32, arg2); | |
1814 | tcg_gen_shr_i32(t1, arg1, t1); | |
1815 | tcg_gen_or_i32(ret, t0, t1); | |
a7812ae4 PB |
1816 | tcg_temp_free_i32(t0); |
1817 | tcg_temp_free_i32(t1); | |
d42f183c | 1818 | #endif |
15824571 AJ |
1819 | } |
1820 | ||
a7812ae4 | 1821 | static inline void tcg_gen_rotl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
15824571 | 1822 | { |
d42f183c AJ |
1823 | #ifdef TCG_TARGET_HAS_rot_i64 |
1824 | tcg_gen_op3_i64(INDEX_op_rotl_i64, ret, arg1, arg2); | |
1825 | #else | |
a7812ae4 | 1826 | TCGv_i64 t0, t1; |
15824571 | 1827 | |
a7812ae4 PB |
1828 | t0 = tcg_temp_new_i64(); |
1829 | t1 = tcg_temp_new_i64(); | |
15824571 AJ |
1830 | tcg_gen_shl_i64(t0, arg1, arg2); |
1831 | tcg_gen_subfi_i64(t1, 64, arg2); | |
1832 | tcg_gen_shr_i64(t1, arg1, t1); | |
1833 | tcg_gen_or_i64(ret, t0, t1); | |
a7812ae4 PB |
1834 | tcg_temp_free_i64(t0); |
1835 | tcg_temp_free_i64(t1); | |
d42f183c | 1836 | #endif |
15824571 AJ |
1837 | } |
1838 | ||
a7812ae4 | 1839 | static inline void tcg_gen_rotli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) |
15824571 AJ |
1840 | { |
1841 | /* some cases can be optimized here */ | |
1842 | if (arg2 == 0) { | |
1843 | tcg_gen_mov_i32(ret, arg1); | |
1844 | } else { | |
d42f183c AJ |
1845 | #ifdef TCG_TARGET_HAS_rot_i32 |
1846 | TCGv_i32 t0 = tcg_const_i32(arg2); | |
1847 | tcg_gen_rotl_i32(ret, arg1, t0); | |
1848 | tcg_temp_free_i32(t0); | |
1849 | #else | |
a7812ae4 PB |
1850 | TCGv_i32 t0, t1; |
1851 | t0 = tcg_temp_new_i32(); | |
1852 | t1 = tcg_temp_new_i32(); | |
15824571 AJ |
1853 | tcg_gen_shli_i32(t0, arg1, arg2); |
1854 | tcg_gen_shri_i32(t1, arg1, 32 - arg2); | |
1855 | tcg_gen_or_i32(ret, t0, t1); | |
a7812ae4 PB |
1856 | tcg_temp_free_i32(t0); |
1857 | tcg_temp_free_i32(t1); | |
d42f183c | 1858 | #endif |
15824571 AJ |
1859 | } |
1860 | } | |
1861 | ||
a7812ae4 | 1862 | static inline void tcg_gen_rotli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
15824571 AJ |
1863 | { |
1864 | /* some cases can be optimized here */ | |
1865 | if (arg2 == 0) { | |
1866 | tcg_gen_mov_i64(ret, arg1); | |
1867 | } else { | |
d42f183c AJ |
1868 | #ifdef TCG_TARGET_HAS_rot_i64 |
1869 | TCGv_i64 t0 = tcg_const_i64(arg2); | |
1870 | tcg_gen_rotl_i64(ret, arg1, t0); | |
1871 | tcg_temp_free_i64(t0); | |
1872 | #else | |
a7812ae4 PB |
1873 | TCGv_i64 t0, t1; |
1874 | t0 = tcg_temp_new_i64(); | |
1875 | t1 = tcg_temp_new_i64(); | |
15824571 AJ |
1876 | tcg_gen_shli_i64(t0, arg1, arg2); |
1877 | tcg_gen_shri_i64(t1, arg1, 64 - arg2); | |
1878 | tcg_gen_or_i64(ret, t0, t1); | |
a7812ae4 PB |
1879 | tcg_temp_free_i64(t0); |
1880 | tcg_temp_free_i64(t1); | |
d42f183c | 1881 | #endif |
15824571 AJ |
1882 | } |
1883 | } | |
1884 | ||
a7812ae4 | 1885 | static inline void tcg_gen_rotr_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
15824571 | 1886 | { |
d42f183c AJ |
1887 | #ifdef TCG_TARGET_HAS_rot_i32 |
1888 | tcg_gen_op3_i32(INDEX_op_rotr_i32, ret, arg1, arg2); | |
1889 | #else | |
a7812ae4 | 1890 | TCGv_i32 t0, t1; |
15824571 | 1891 | |
a7812ae4 PB |
1892 | t0 = tcg_temp_new_i32(); |
1893 | t1 = tcg_temp_new_i32(); | |
15824571 AJ |
1894 | tcg_gen_shr_i32(t0, arg1, arg2); |
1895 | tcg_gen_subfi_i32(t1, 32, arg2); | |
1896 | tcg_gen_shl_i32(t1, arg1, t1); | |
1897 | tcg_gen_or_i32(ret, t0, t1); | |
a7812ae4 PB |
1898 | tcg_temp_free_i32(t0); |
1899 | tcg_temp_free_i32(t1); | |
d42f183c | 1900 | #endif |
15824571 AJ |
1901 | } |
1902 | ||
a7812ae4 | 1903 | static inline void tcg_gen_rotr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
15824571 | 1904 | { |
d42f183c AJ |
1905 | #ifdef TCG_TARGET_HAS_rot_i64 |
1906 | tcg_gen_op3_i64(INDEX_op_rotr_i64, ret, arg1, arg2); | |
1907 | #else | |
a7812ae4 | 1908 | TCGv_i64 t0, t1; |
15824571 | 1909 | |
a7812ae4 PB |
1910 | t0 = tcg_temp_new_i64(); |
1911 | t1 = tcg_temp_new_i64(); | |
d9885a0b | 1912 | tcg_gen_shr_i64(t0, arg1, arg2); |
15824571 AJ |
1913 | tcg_gen_subfi_i64(t1, 64, arg2); |
1914 | tcg_gen_shl_i64(t1, arg1, t1); | |
1915 | tcg_gen_or_i64(ret, t0, t1); | |
a7812ae4 PB |
1916 | tcg_temp_free_i64(t0); |
1917 | tcg_temp_free_i64(t1); | |
d42f183c | 1918 | #endif |
15824571 AJ |
1919 | } |
1920 | ||
a7812ae4 | 1921 | static inline void tcg_gen_rotri_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) |
15824571 AJ |
1922 | { |
1923 | /* some cases can be optimized here */ | |
1924 | if (arg2 == 0) { | |
1925 | tcg_gen_mov_i32(ret, arg1); | |
1926 | } else { | |
1927 | tcg_gen_rotli_i32(ret, arg1, 32 - arg2); | |
1928 | } | |
1929 | } | |
1930 | ||
a7812ae4 | 1931 | static inline void tcg_gen_rotri_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
15824571 AJ |
1932 | { |
1933 | /* some cases can be optimized here */ | |
1934 | if (arg2 == 0) { | |
de3526b2 | 1935 | tcg_gen_mov_i64(ret, arg1); |
15824571 AJ |
1936 | } else { |
1937 | tcg_gen_rotli_i64(ret, arg1, 64 - arg2); | |
1938 | } | |
1939 | } | |
1940 | ||
c896fe29 FB |
1941 | /***************************************/ |
1942 | /* QEMU specific operations. Their type depend on the QEMU CPU | |
1943 | type. */ | |
1944 | #ifndef TARGET_LONG_BITS | |
1945 | #error must include QEMU headers | |
1946 | #endif | |
1947 | ||
a7812ae4 PB |
1948 | #if TARGET_LONG_BITS == 32 |
1949 | #define TCGv TCGv_i32 | |
1950 | #define tcg_temp_new() tcg_temp_new_i32() | |
1951 | #define tcg_global_reg_new tcg_global_reg_new_i32 | |
1952 | #define tcg_global_mem_new tcg_global_mem_new_i32 | |
df9247b2 | 1953 | #define tcg_temp_local_new() tcg_temp_local_new_i32() |
a7812ae4 PB |
1954 | #define tcg_temp_free tcg_temp_free_i32 |
1955 | #define tcg_gen_qemu_ldst_op tcg_gen_op3i_i32 | |
1956 | #define tcg_gen_qemu_ldst_op_i64 tcg_gen_qemu_ldst_op_i64_i32 | |
1957 | #define TCGV_UNUSED(x) TCGV_UNUSED_I32(x) | |
fe75bcf7 | 1958 | #define TCGV_EQUAL(a, b) TCGV_EQUAL_I32(a, b) |
a7812ae4 PB |
1959 | #else |
1960 | #define TCGv TCGv_i64 | |
1961 | #define tcg_temp_new() tcg_temp_new_i64() | |
1962 | #define tcg_global_reg_new tcg_global_reg_new_i64 | |
1963 | #define tcg_global_mem_new tcg_global_mem_new_i64 | |
df9247b2 | 1964 | #define tcg_temp_local_new() tcg_temp_local_new_i64() |
a7812ae4 PB |
1965 | #define tcg_temp_free tcg_temp_free_i64 |
1966 | #define tcg_gen_qemu_ldst_op tcg_gen_op3i_i64 | |
1967 | #define tcg_gen_qemu_ldst_op_i64 tcg_gen_qemu_ldst_op_i64_i64 | |
1968 | #define TCGV_UNUSED(x) TCGV_UNUSED_I64(x) | |
fe75bcf7 | 1969 | #define TCGV_EQUAL(a, b) TCGV_EQUAL_I64(a, b) |
a7812ae4 PB |
1970 | #endif |
1971 | ||
7e4597d7 FB |
1972 | /* debug info: write the PC of the corresponding QEMU CPU instruction */ |
1973 | static inline void tcg_gen_debug_insn_start(uint64_t pc) | |
1974 | { | |
1975 | /* XXX: must really use a 32 bit size for TCGArg in all cases */ | |
1976 | #if TARGET_LONG_BITS > TCG_TARGET_REG_BITS | |
bcb0126f PB |
1977 | tcg_gen_op2ii(INDEX_op_debug_insn_start, |
1978 | (uint32_t)(pc), (uint32_t)(pc >> 32)); | |
7e4597d7 FB |
1979 | #else |
1980 | tcg_gen_op1i(INDEX_op_debug_insn_start, pc); | |
1981 | #endif | |
1982 | } | |
1983 | ||
c896fe29 FB |
1984 | static inline void tcg_gen_exit_tb(tcg_target_long val) |
1985 | { | |
ac56dd48 | 1986 | tcg_gen_op1i(INDEX_op_exit_tb, val); |
c896fe29 FB |
1987 | } |
1988 | ||
1989 | static inline void tcg_gen_goto_tb(int idx) | |
1990 | { | |
ac56dd48 | 1991 | tcg_gen_op1i(INDEX_op_goto_tb, idx); |
c896fe29 FB |
1992 | } |
1993 | ||
1994 | #if TCG_TARGET_REG_BITS == 32 | |
ac56dd48 | 1995 | static inline void tcg_gen_qemu_ld8u(TCGv ret, TCGv addr, int mem_index) |
c896fe29 FB |
1996 | { |
1997 | #if TARGET_LONG_BITS == 32 | |
a7812ae4 | 1998 | tcg_gen_op3i_i32(INDEX_op_qemu_ld8u, ret, addr, mem_index); |
c896fe29 | 1999 | #else |
a7812ae4 PB |
2000 | tcg_gen_op4i_i32(INDEX_op_qemu_ld8u, TCGV_LOW(ret), TCGV_LOW(addr), |
2001 | TCGV_HIGH(addr), mem_index); | |
ac56dd48 | 2002 | tcg_gen_movi_i32(TCGV_HIGH(ret), 0); |
c896fe29 FB |
2003 | #endif |
2004 | } | |
2005 | ||
ac56dd48 | 2006 | static inline void tcg_gen_qemu_ld8s(TCGv ret, TCGv addr, int mem_index) |
c896fe29 FB |
2007 | { |
2008 | #if TARGET_LONG_BITS == 32 | |
a7812ae4 | 2009 | tcg_gen_op3i_i32(INDEX_op_qemu_ld8s, ret, addr, mem_index); |
c896fe29 | 2010 | #else |
a7812ae4 PB |
2011 | tcg_gen_op4i_i32(INDEX_op_qemu_ld8s, TCGV_LOW(ret), TCGV_LOW(addr), |
2012 | TCGV_HIGH(addr), mem_index); | |
2013 | tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31); | |
c896fe29 FB |
2014 | #endif |
2015 | } | |
2016 | ||
ac56dd48 | 2017 | static inline void tcg_gen_qemu_ld16u(TCGv ret, TCGv addr, int mem_index) |
c896fe29 FB |
2018 | { |
2019 | #if TARGET_LONG_BITS == 32 | |
a7812ae4 | 2020 | tcg_gen_op3i_i32(INDEX_op_qemu_ld16u, ret, addr, mem_index); |
c896fe29 | 2021 | #else |
a7812ae4 PB |
2022 | tcg_gen_op4i_i32(INDEX_op_qemu_ld16u, TCGV_LOW(ret), TCGV_LOW(addr), |
2023 | TCGV_HIGH(addr), mem_index); | |
ac56dd48 | 2024 | tcg_gen_movi_i32(TCGV_HIGH(ret), 0); |
c896fe29 FB |
2025 | #endif |
2026 | } | |
2027 | ||
ac56dd48 | 2028 | static inline void tcg_gen_qemu_ld16s(TCGv ret, TCGv addr, int mem_index) |
c896fe29 FB |
2029 | { |
2030 | #if TARGET_LONG_BITS == 32 | |
a7812ae4 | 2031 | tcg_gen_op3i_i32(INDEX_op_qemu_ld16s, ret, addr, mem_index); |
c896fe29 | 2032 | #else |
a7812ae4 PB |
2033 | tcg_gen_op4i_i32(INDEX_op_qemu_ld16s, TCGV_LOW(ret), TCGV_LOW(addr), |
2034 | TCGV_HIGH(addr), mem_index); | |
2035 | tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31); | |
c896fe29 FB |
2036 | #endif |
2037 | } | |
2038 | ||
ac56dd48 | 2039 | static inline void tcg_gen_qemu_ld32u(TCGv ret, TCGv addr, int mem_index) |
c896fe29 FB |
2040 | { |
2041 | #if TARGET_LONG_BITS == 32 | |
a7812ae4 | 2042 | tcg_gen_op3i_i32(INDEX_op_qemu_ld32u, ret, addr, mem_index); |
c896fe29 | 2043 | #else |
a7812ae4 PB |
2044 | tcg_gen_op4i_i32(INDEX_op_qemu_ld32u, TCGV_LOW(ret), TCGV_LOW(addr), |
2045 | TCGV_HIGH(addr), mem_index); | |
ac56dd48 | 2046 | tcg_gen_movi_i32(TCGV_HIGH(ret), 0); |
c896fe29 FB |
2047 | #endif |
2048 | } | |
2049 | ||
ac56dd48 | 2050 | static inline void tcg_gen_qemu_ld32s(TCGv ret, TCGv addr, int mem_index) |
c896fe29 FB |
2051 | { |
2052 | #if TARGET_LONG_BITS == 32 | |
a7812ae4 | 2053 | tcg_gen_op3i_i32(INDEX_op_qemu_ld32u, ret, addr, mem_index); |
c896fe29 | 2054 | #else |
a7812ae4 PB |
2055 | tcg_gen_op4i_i32(INDEX_op_qemu_ld32u, TCGV_LOW(ret), TCGV_LOW(addr), |
2056 | TCGV_HIGH(addr), mem_index); | |
2057 | tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31); | |
c896fe29 FB |
2058 | #endif |
2059 | } | |
2060 | ||
a7812ae4 | 2061 | static inline void tcg_gen_qemu_ld64(TCGv_i64 ret, TCGv addr, int mem_index) |
c896fe29 FB |
2062 | { |
2063 | #if TARGET_LONG_BITS == 32 | |
a7812ae4 | 2064 | tcg_gen_op4i_i32(INDEX_op_qemu_ld64, TCGV_LOW(ret), TCGV_HIGH(ret), addr, mem_index); |
c896fe29 | 2065 | #else |
a7812ae4 PB |
2066 | tcg_gen_op5i_i32(INDEX_op_qemu_ld64, TCGV_LOW(ret), TCGV_HIGH(ret), |
2067 | TCGV_LOW(addr), TCGV_HIGH(addr), mem_index); | |
c896fe29 FB |
2068 | #endif |
2069 | } | |
2070 | ||
ac56dd48 | 2071 | static inline void tcg_gen_qemu_st8(TCGv arg, TCGv addr, int mem_index) |
c896fe29 FB |
2072 | { |
2073 | #if TARGET_LONG_BITS == 32 | |
a7812ae4 | 2074 | tcg_gen_op3i_i32(INDEX_op_qemu_st8, arg, addr, mem_index); |
c896fe29 | 2075 | #else |
a7812ae4 PB |
2076 | tcg_gen_op4i_i32(INDEX_op_qemu_st8, TCGV_LOW(arg), TCGV_LOW(addr), |
2077 | TCGV_HIGH(addr), mem_index); | |
c896fe29 FB |
2078 | #endif |
2079 | } | |
2080 | ||
ac56dd48 | 2081 | static inline void tcg_gen_qemu_st16(TCGv arg, TCGv addr, int mem_index) |
c896fe29 FB |
2082 | { |
2083 | #if TARGET_LONG_BITS == 32 | |
a7812ae4 | 2084 | tcg_gen_op3i_i32(INDEX_op_qemu_st16, arg, addr, mem_index); |
c896fe29 | 2085 | #else |
a7812ae4 PB |
2086 | tcg_gen_op4i_i32(INDEX_op_qemu_st16, TCGV_LOW(arg), TCGV_LOW(addr), |
2087 | TCGV_HIGH(addr), mem_index); | |
c896fe29 FB |
2088 | #endif |
2089 | } | |
2090 | ||
ac56dd48 | 2091 | static inline void tcg_gen_qemu_st32(TCGv arg, TCGv addr, int mem_index) |
c896fe29 FB |
2092 | { |
2093 | #if TARGET_LONG_BITS == 32 | |
a7812ae4 | 2094 | tcg_gen_op3i_i32(INDEX_op_qemu_st32, arg, addr, mem_index); |
c896fe29 | 2095 | #else |
a7812ae4 PB |
2096 | tcg_gen_op4i_i32(INDEX_op_qemu_st32, TCGV_LOW(arg), TCGV_LOW(addr), |
2097 | TCGV_HIGH(addr), mem_index); | |
c896fe29 FB |
2098 | #endif |
2099 | } | |
2100 | ||
a7812ae4 | 2101 | static inline void tcg_gen_qemu_st64(TCGv_i64 arg, TCGv addr, int mem_index) |
c896fe29 FB |
2102 | { |
2103 | #if TARGET_LONG_BITS == 32 | |
a7812ae4 PB |
2104 | tcg_gen_op4i_i32(INDEX_op_qemu_st64, TCGV_LOW(arg), TCGV_HIGH(arg), addr, |
2105 | mem_index); | |
c896fe29 | 2106 | #else |
a7812ae4 PB |
2107 | tcg_gen_op5i_i32(INDEX_op_qemu_st64, TCGV_LOW(arg), TCGV_HIGH(arg), |
2108 | TCGV_LOW(addr), TCGV_HIGH(addr), mem_index); | |
c896fe29 FB |
2109 | #endif |
2110 | } | |
2111 | ||
56b8f567 | 2112 | #define tcg_gen_ld_ptr tcg_gen_ld_i32 |
a768e4b2 | 2113 | #define tcg_gen_discard_ptr tcg_gen_discard_i32 |
f8422f52 | 2114 | |
c896fe29 FB |
2115 | #else /* TCG_TARGET_REG_BITS == 32 */ |
2116 | ||
ac56dd48 | 2117 | static inline void tcg_gen_qemu_ld8u(TCGv ret, TCGv addr, int mem_index) |
c896fe29 | 2118 | { |
a7812ae4 | 2119 | tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld8u, ret, addr, mem_index); |
c896fe29 FB |
2120 | } |
2121 | ||
ac56dd48 | 2122 | static inline void tcg_gen_qemu_ld8s(TCGv ret, TCGv addr, int mem_index) |
c896fe29 | 2123 | { |
a7812ae4 | 2124 | tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld8s, ret, addr, mem_index); |
c896fe29 FB |
2125 | } |
2126 | ||
ac56dd48 | 2127 | static inline void tcg_gen_qemu_ld16u(TCGv ret, TCGv addr, int mem_index) |
c896fe29 | 2128 | { |
a7812ae4 | 2129 | tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld16u, ret, addr, mem_index); |
c896fe29 FB |
2130 | } |
2131 | ||
ac56dd48 | 2132 | static inline void tcg_gen_qemu_ld16s(TCGv ret, TCGv addr, int mem_index) |
c896fe29 | 2133 | { |
a7812ae4 | 2134 | tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld16s, ret, addr, mem_index); |
c896fe29 FB |
2135 | } |
2136 | ||
ac56dd48 | 2137 | static inline void tcg_gen_qemu_ld32u(TCGv ret, TCGv addr, int mem_index) |
c896fe29 | 2138 | { |
a7812ae4 | 2139 | tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld32u, ret, addr, mem_index); |
c896fe29 FB |
2140 | } |
2141 | ||
ac56dd48 | 2142 | static inline void tcg_gen_qemu_ld32s(TCGv ret, TCGv addr, int mem_index) |
c896fe29 | 2143 | { |
a7812ae4 | 2144 | tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld32s, ret, addr, mem_index); |
c896fe29 FB |
2145 | } |
2146 | ||
a7812ae4 | 2147 | static inline void tcg_gen_qemu_ld64(TCGv_i64 ret, TCGv addr, int mem_index) |
c896fe29 | 2148 | { |
a7812ae4 | 2149 | tcg_gen_qemu_ldst_op_i64(INDEX_op_qemu_ld64, ret, addr, mem_index); |
c896fe29 FB |
2150 | } |
2151 | ||
ac56dd48 | 2152 | static inline void tcg_gen_qemu_st8(TCGv arg, TCGv addr, int mem_index) |
c896fe29 | 2153 | { |
a7812ae4 | 2154 | tcg_gen_qemu_ldst_op(INDEX_op_qemu_st8, arg, addr, mem_index); |
c896fe29 FB |
2155 | } |
2156 | ||
ac56dd48 | 2157 | static inline void tcg_gen_qemu_st16(TCGv arg, TCGv addr, int mem_index) |
c896fe29 | 2158 | { |
a7812ae4 | 2159 | tcg_gen_qemu_ldst_op(INDEX_op_qemu_st16, arg, addr, mem_index); |
c896fe29 FB |
2160 | } |
2161 | ||
ac56dd48 | 2162 | static inline void tcg_gen_qemu_st32(TCGv arg, TCGv addr, int mem_index) |
c896fe29 | 2163 | { |
a7812ae4 | 2164 | tcg_gen_qemu_ldst_op(INDEX_op_qemu_st32, arg, addr, mem_index); |
c896fe29 FB |
2165 | } |
2166 | ||
a7812ae4 | 2167 | static inline void tcg_gen_qemu_st64(TCGv_i64 arg, TCGv addr, int mem_index) |
c896fe29 | 2168 | { |
a7812ae4 | 2169 | tcg_gen_qemu_ldst_op_i64(INDEX_op_qemu_st64, arg, addr, mem_index); |
c896fe29 FB |
2170 | } |
2171 | ||
56b8f567 | 2172 | #define tcg_gen_ld_ptr tcg_gen_ld_i64 |
a768e4b2 | 2173 | #define tcg_gen_discard_ptr tcg_gen_discard_i64 |
f8422f52 | 2174 | |
c896fe29 | 2175 | #endif /* TCG_TARGET_REG_BITS != 32 */ |
f8422f52 BS |
2176 | |
2177 | #if TARGET_LONG_BITS == 64 | |
2178 | #define TCG_TYPE_TL TCG_TYPE_I64 | |
2179 | #define tcg_gen_movi_tl tcg_gen_movi_i64 | |
2180 | #define tcg_gen_mov_tl tcg_gen_mov_i64 | |
2181 | #define tcg_gen_ld8u_tl tcg_gen_ld8u_i64 | |
2182 | #define tcg_gen_ld8s_tl tcg_gen_ld8s_i64 | |
2183 | #define tcg_gen_ld16u_tl tcg_gen_ld16u_i64 | |
2184 | #define tcg_gen_ld16s_tl tcg_gen_ld16s_i64 | |
2185 | #define tcg_gen_ld32u_tl tcg_gen_ld32u_i64 | |
2186 | #define tcg_gen_ld32s_tl tcg_gen_ld32s_i64 | |
2187 | #define tcg_gen_ld_tl tcg_gen_ld_i64 | |
2188 | #define tcg_gen_st8_tl tcg_gen_st8_i64 | |
2189 | #define tcg_gen_st16_tl tcg_gen_st16_i64 | |
2190 | #define tcg_gen_st32_tl tcg_gen_st32_i64 | |
2191 | #define tcg_gen_st_tl tcg_gen_st_i64 | |
2192 | #define tcg_gen_add_tl tcg_gen_add_i64 | |
2193 | #define tcg_gen_addi_tl tcg_gen_addi_i64 | |
2194 | #define tcg_gen_sub_tl tcg_gen_sub_i64 | |
390efc54 | 2195 | #define tcg_gen_neg_tl tcg_gen_neg_i64 |
10460c8a | 2196 | #define tcg_gen_subfi_tl tcg_gen_subfi_i64 |
f8422f52 BS |
2197 | #define tcg_gen_subi_tl tcg_gen_subi_i64 |
2198 | #define tcg_gen_and_tl tcg_gen_and_i64 | |
2199 | #define tcg_gen_andi_tl tcg_gen_andi_i64 | |
2200 | #define tcg_gen_or_tl tcg_gen_or_i64 | |
2201 | #define tcg_gen_ori_tl tcg_gen_ori_i64 | |
2202 | #define tcg_gen_xor_tl tcg_gen_xor_i64 | |
2203 | #define tcg_gen_xori_tl tcg_gen_xori_i64 | |
0b6ce4cf | 2204 | #define tcg_gen_not_tl tcg_gen_not_i64 |
f8422f52 BS |
2205 | #define tcg_gen_shl_tl tcg_gen_shl_i64 |
2206 | #define tcg_gen_shli_tl tcg_gen_shli_i64 | |
2207 | #define tcg_gen_shr_tl tcg_gen_shr_i64 | |
2208 | #define tcg_gen_shri_tl tcg_gen_shri_i64 | |
2209 | #define tcg_gen_sar_tl tcg_gen_sar_i64 | |
2210 | #define tcg_gen_sari_tl tcg_gen_sari_i64 | |
0cf767d6 | 2211 | #define tcg_gen_brcond_tl tcg_gen_brcond_i64 |
cb63669a | 2212 | #define tcg_gen_brcondi_tl tcg_gen_brcondi_i64 |
be210acb | 2213 | #define tcg_gen_setcond_tl tcg_gen_setcond_i64 |
add1e7ea | 2214 | #define tcg_gen_setcondi_tl tcg_gen_setcondi_i64 |
f730fd27 TS |
2215 | #define tcg_gen_mul_tl tcg_gen_mul_i64 |
2216 | #define tcg_gen_muli_tl tcg_gen_muli_i64 | |
ab36421e AJ |
2217 | #define tcg_gen_div_tl tcg_gen_div_i64 |
2218 | #define tcg_gen_rem_tl tcg_gen_rem_i64 | |
864951af AJ |
2219 | #define tcg_gen_divu_tl tcg_gen_divu_i64 |
2220 | #define tcg_gen_remu_tl tcg_gen_remu_i64 | |
a768e4b2 | 2221 | #define tcg_gen_discard_tl tcg_gen_discard_i64 |
e429073d BS |
2222 | #define tcg_gen_trunc_tl_i32 tcg_gen_trunc_i64_i32 |
2223 | #define tcg_gen_trunc_i64_tl tcg_gen_mov_i64 | |
2224 | #define tcg_gen_extu_i32_tl tcg_gen_extu_i32_i64 | |
2225 | #define tcg_gen_ext_i32_tl tcg_gen_ext_i32_i64 | |
2226 | #define tcg_gen_extu_tl_i64 tcg_gen_mov_i64 | |
2227 | #define tcg_gen_ext_tl_i64 tcg_gen_mov_i64 | |
0b6ce4cf FB |
2228 | #define tcg_gen_ext8u_tl tcg_gen_ext8u_i64 |
2229 | #define tcg_gen_ext8s_tl tcg_gen_ext8s_i64 | |
2230 | #define tcg_gen_ext16u_tl tcg_gen_ext16u_i64 | |
2231 | #define tcg_gen_ext16s_tl tcg_gen_ext16s_i64 | |
2232 | #define tcg_gen_ext32u_tl tcg_gen_ext32u_i64 | |
2233 | #define tcg_gen_ext32s_tl tcg_gen_ext32s_i64 | |
911d79ba AJ |
2234 | #define tcg_gen_bswap16_tl tcg_gen_bswap16_i64 |
2235 | #define tcg_gen_bswap32_tl tcg_gen_bswap32_i64 | |
2236 | #define tcg_gen_bswap64_tl tcg_gen_bswap64_i64 | |
945ca823 | 2237 | #define tcg_gen_concat_tl_i64 tcg_gen_concat32_i64 |
f24cb33e AJ |
2238 | #define tcg_gen_andc_tl tcg_gen_andc_i64 |
2239 | #define tcg_gen_eqv_tl tcg_gen_eqv_i64 | |
2240 | #define tcg_gen_nand_tl tcg_gen_nand_i64 | |
2241 | #define tcg_gen_nor_tl tcg_gen_nor_i64 | |
2242 | #define tcg_gen_orc_tl tcg_gen_orc_i64 | |
15824571 AJ |
2243 | #define tcg_gen_rotl_tl tcg_gen_rotl_i64 |
2244 | #define tcg_gen_rotli_tl tcg_gen_rotli_i64 | |
2245 | #define tcg_gen_rotr_tl tcg_gen_rotr_i64 | |
2246 | #define tcg_gen_rotri_tl tcg_gen_rotri_i64 | |
a98824ac | 2247 | #define tcg_const_tl tcg_const_i64 |
bdffd4a9 | 2248 | #define tcg_const_local_tl tcg_const_local_i64 |
f8422f52 BS |
2249 | #else |
2250 | #define TCG_TYPE_TL TCG_TYPE_I32 | |
2251 | #define tcg_gen_movi_tl tcg_gen_movi_i32 | |
2252 | #define tcg_gen_mov_tl tcg_gen_mov_i32 | |
2253 | #define tcg_gen_ld8u_tl tcg_gen_ld8u_i32 | |
2254 | #define tcg_gen_ld8s_tl tcg_gen_ld8s_i32 | |
2255 | #define tcg_gen_ld16u_tl tcg_gen_ld16u_i32 | |
2256 | #define tcg_gen_ld16s_tl tcg_gen_ld16s_i32 | |
2257 | #define tcg_gen_ld32u_tl tcg_gen_ld_i32 | |
2258 | #define tcg_gen_ld32s_tl tcg_gen_ld_i32 | |
2259 | #define tcg_gen_ld_tl tcg_gen_ld_i32 | |
2260 | #define tcg_gen_st8_tl tcg_gen_st8_i32 | |
2261 | #define tcg_gen_st16_tl tcg_gen_st16_i32 | |
2262 | #define tcg_gen_st32_tl tcg_gen_st_i32 | |
2263 | #define tcg_gen_st_tl tcg_gen_st_i32 | |
2264 | #define tcg_gen_add_tl tcg_gen_add_i32 | |
2265 | #define tcg_gen_addi_tl tcg_gen_addi_i32 | |
2266 | #define tcg_gen_sub_tl tcg_gen_sub_i32 | |
390efc54 | 2267 | #define tcg_gen_neg_tl tcg_gen_neg_i32 |
0045734a | 2268 | #define tcg_gen_subfi_tl tcg_gen_subfi_i32 |
f8422f52 BS |
2269 | #define tcg_gen_subi_tl tcg_gen_subi_i32 |
2270 | #define tcg_gen_and_tl tcg_gen_and_i32 | |
2271 | #define tcg_gen_andi_tl tcg_gen_andi_i32 | |
2272 | #define tcg_gen_or_tl tcg_gen_or_i32 | |
2273 | #define tcg_gen_ori_tl tcg_gen_ori_i32 | |
2274 | #define tcg_gen_xor_tl tcg_gen_xor_i32 | |
2275 | #define tcg_gen_xori_tl tcg_gen_xori_i32 | |
0b6ce4cf | 2276 | #define tcg_gen_not_tl tcg_gen_not_i32 |
f8422f52 BS |
2277 | #define tcg_gen_shl_tl tcg_gen_shl_i32 |
2278 | #define tcg_gen_shli_tl tcg_gen_shli_i32 | |
2279 | #define tcg_gen_shr_tl tcg_gen_shr_i32 | |
2280 | #define tcg_gen_shri_tl tcg_gen_shri_i32 | |
2281 | #define tcg_gen_sar_tl tcg_gen_sar_i32 | |
2282 | #define tcg_gen_sari_tl tcg_gen_sari_i32 | |
0cf767d6 | 2283 | #define tcg_gen_brcond_tl tcg_gen_brcond_i32 |
cb63669a | 2284 | #define tcg_gen_brcondi_tl tcg_gen_brcondi_i32 |
be210acb | 2285 | #define tcg_gen_setcond_tl tcg_gen_setcond_i32 |
add1e7ea | 2286 | #define tcg_gen_setcondi_tl tcg_gen_setcondi_i32 |
f730fd27 TS |
2287 | #define tcg_gen_mul_tl tcg_gen_mul_i32 |
2288 | #define tcg_gen_muli_tl tcg_gen_muli_i32 | |
ab36421e AJ |
2289 | #define tcg_gen_div_tl tcg_gen_div_i32 |
2290 | #define tcg_gen_rem_tl tcg_gen_rem_i32 | |
864951af AJ |
2291 | #define tcg_gen_divu_tl tcg_gen_divu_i32 |
2292 | #define tcg_gen_remu_tl tcg_gen_remu_i32 | |
a768e4b2 | 2293 | #define tcg_gen_discard_tl tcg_gen_discard_i32 |
e429073d BS |
2294 | #define tcg_gen_trunc_tl_i32 tcg_gen_mov_i32 |
2295 | #define tcg_gen_trunc_i64_tl tcg_gen_trunc_i64_i32 | |
2296 | #define tcg_gen_extu_i32_tl tcg_gen_mov_i32 | |
2297 | #define tcg_gen_ext_i32_tl tcg_gen_mov_i32 | |
2298 | #define tcg_gen_extu_tl_i64 tcg_gen_extu_i32_i64 | |
2299 | #define tcg_gen_ext_tl_i64 tcg_gen_ext_i32_i64 | |
0b6ce4cf FB |
2300 | #define tcg_gen_ext8u_tl tcg_gen_ext8u_i32 |
2301 | #define tcg_gen_ext8s_tl tcg_gen_ext8s_i32 | |
2302 | #define tcg_gen_ext16u_tl tcg_gen_ext16u_i32 | |
2303 | #define tcg_gen_ext16s_tl tcg_gen_ext16s_i32 | |
2304 | #define tcg_gen_ext32u_tl tcg_gen_mov_i32 | |
2305 | #define tcg_gen_ext32s_tl tcg_gen_mov_i32 | |
911d79ba AJ |
2306 | #define tcg_gen_bswap16_tl tcg_gen_bswap16_i32 |
2307 | #define tcg_gen_bswap32_tl tcg_gen_bswap32_i32 | |
945ca823 | 2308 | #define tcg_gen_concat_tl_i64 tcg_gen_concat_i32_i64 |
f24cb33e AJ |
2309 | #define tcg_gen_andc_tl tcg_gen_andc_i32 |
2310 | #define tcg_gen_eqv_tl tcg_gen_eqv_i32 | |
2311 | #define tcg_gen_nand_tl tcg_gen_nand_i32 | |
2312 | #define tcg_gen_nor_tl tcg_gen_nor_i32 | |
2313 | #define tcg_gen_orc_tl tcg_gen_orc_i32 | |
15824571 AJ |
2314 | #define tcg_gen_rotl_tl tcg_gen_rotl_i32 |
2315 | #define tcg_gen_rotli_tl tcg_gen_rotli_i32 | |
2316 | #define tcg_gen_rotr_tl tcg_gen_rotr_i32 | |
2317 | #define tcg_gen_rotri_tl tcg_gen_rotri_i32 | |
a98824ac | 2318 | #define tcg_const_tl tcg_const_i32 |
bdffd4a9 | 2319 | #define tcg_const_local_tl tcg_const_local_i32 |
f8422f52 | 2320 | #endif |
6ddbc6e4 PB |
2321 | |
2322 | #if TCG_TARGET_REG_BITS == 32 | |
48d38ca5 | 2323 | #define tcg_gen_add_ptr tcg_gen_add_i32 |
6ddbc6e4 | 2324 | #define tcg_gen_addi_ptr tcg_gen_addi_i32 |
48d38ca5 | 2325 | #define tcg_gen_ext_i32_ptr tcg_gen_mov_i32 |
6ddbc6e4 | 2326 | #else /* TCG_TARGET_REG_BITS == 32 */ |
48d38ca5 | 2327 | #define tcg_gen_add_ptr tcg_gen_add_i64 |
6ddbc6e4 | 2328 | #define tcg_gen_addi_ptr tcg_gen_addi_i64 |
48d38ca5 | 2329 | #define tcg_gen_ext_i32_ptr tcg_gen_ext_i32_i64 |
6ddbc6e4 | 2330 | #endif /* TCG_TARGET_REG_BITS != 32 */ |