]>
Commit | Line | Data |
---|---|---|
c896fe29 FB |
1 | /* |
2 | * Tiny Code Generator for QEMU | |
3 | * | |
4 | * Copyright (c) 2008 Fabrice Bellard | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
24 | #include "tcg.h" | |
25 | ||
c896fe29 FB |
26 | int gen_new_label(void); |
27 | ||
a7812ae4 | 28 | static inline void tcg_gen_op1_i32(int opc, TCGv_i32 arg1) |
c896fe29 FB |
29 | { |
30 | *gen_opc_ptr++ = opc; | |
a7812ae4 PB |
31 | *gen_opparam_ptr++ = GET_TCGV_I32(arg1); |
32 | } | |
33 | ||
34 | static inline void tcg_gen_op1_i64(int opc, TCGv_i64 arg1) | |
35 | { | |
36 | *gen_opc_ptr++ = opc; | |
37 | *gen_opparam_ptr++ = GET_TCGV_I64(arg1); | |
c896fe29 FB |
38 | } |
39 | ||
ac56dd48 | 40 | static inline void tcg_gen_op1i(int opc, TCGArg arg1) |
c896fe29 FB |
41 | { |
42 | *gen_opc_ptr++ = opc; | |
43 | *gen_opparam_ptr++ = arg1; | |
c896fe29 FB |
44 | } |
45 | ||
a7812ae4 PB |
46 | static inline void tcg_gen_op2_i32(int opc, TCGv_i32 arg1, TCGv_i32 arg2) |
47 | { | |
48 | *gen_opc_ptr++ = opc; | |
49 | *gen_opparam_ptr++ = GET_TCGV_I32(arg1); | |
50 | *gen_opparam_ptr++ = GET_TCGV_I32(arg2); | |
51 | } | |
52 | ||
53 | static inline void tcg_gen_op2_i64(int opc, TCGv_i64 arg1, TCGv_i64 arg2) | |
54 | { | |
55 | *gen_opc_ptr++ = opc; | |
56 | *gen_opparam_ptr++ = GET_TCGV_I64(arg1); | |
57 | *gen_opparam_ptr++ = GET_TCGV_I64(arg2); | |
58 | } | |
59 | ||
60 | static inline void tcg_gen_op2i_i32(int opc, TCGv_i32 arg1, TCGArg arg2) | |
c896fe29 FB |
61 | { |
62 | *gen_opc_ptr++ = opc; | |
a7812ae4 PB |
63 | *gen_opparam_ptr++ = GET_TCGV_I32(arg1); |
64 | *gen_opparam_ptr++ = arg2; | |
c896fe29 FB |
65 | } |
66 | ||
a7812ae4 | 67 | static inline void tcg_gen_op2i_i64(int opc, TCGv_i64 arg1, TCGArg arg2) |
c896fe29 FB |
68 | { |
69 | *gen_opc_ptr++ = opc; | |
a7812ae4 | 70 | *gen_opparam_ptr++ = GET_TCGV_I64(arg1); |
c896fe29 | 71 | *gen_opparam_ptr++ = arg2; |
ac56dd48 PB |
72 | } |
73 | ||
bcb0126f PB |
74 | static inline void tcg_gen_op2ii(int opc, TCGArg arg1, TCGArg arg2) |
75 | { | |
76 | *gen_opc_ptr++ = opc; | |
77 | *gen_opparam_ptr++ = arg1; | |
78 | *gen_opparam_ptr++ = arg2; | |
79 | } | |
80 | ||
a7812ae4 PB |
81 | static inline void tcg_gen_op3_i32(int opc, TCGv_i32 arg1, TCGv_i32 arg2, |
82 | TCGv_i32 arg3) | |
83 | { | |
84 | *gen_opc_ptr++ = opc; | |
85 | *gen_opparam_ptr++ = GET_TCGV_I32(arg1); | |
86 | *gen_opparam_ptr++ = GET_TCGV_I32(arg2); | |
87 | *gen_opparam_ptr++ = GET_TCGV_I32(arg3); | |
88 | } | |
89 | ||
90 | static inline void tcg_gen_op3_i64(int opc, TCGv_i64 arg1, TCGv_i64 arg2, | |
91 | TCGv_i64 arg3) | |
92 | { | |
93 | *gen_opc_ptr++ = opc; | |
94 | *gen_opparam_ptr++ = GET_TCGV_I64(arg1); | |
95 | *gen_opparam_ptr++ = GET_TCGV_I64(arg2); | |
96 | *gen_opparam_ptr++ = GET_TCGV_I64(arg3); | |
97 | } | |
98 | ||
99 | static inline void tcg_gen_op3i_i32(int opc, TCGv_i32 arg1, TCGv_i32 arg2, | |
100 | TCGArg arg3) | |
ac56dd48 PB |
101 | { |
102 | *gen_opc_ptr++ = opc; | |
a7812ae4 PB |
103 | *gen_opparam_ptr++ = GET_TCGV_I32(arg1); |
104 | *gen_opparam_ptr++ = GET_TCGV_I32(arg2); | |
105 | *gen_opparam_ptr++ = arg3; | |
ac56dd48 PB |
106 | } |
107 | ||
a7812ae4 PB |
108 | static inline void tcg_gen_op3i_i64(int opc, TCGv_i64 arg1, TCGv_i64 arg2, |
109 | TCGArg arg3) | |
ac56dd48 PB |
110 | { |
111 | *gen_opc_ptr++ = opc; | |
a7812ae4 PB |
112 | *gen_opparam_ptr++ = GET_TCGV_I64(arg1); |
113 | *gen_opparam_ptr++ = GET_TCGV_I64(arg2); | |
c896fe29 | 114 | *gen_opparam_ptr++ = arg3; |
ac56dd48 PB |
115 | } |
116 | ||
a7812ae4 PB |
117 | static inline void tcg_gen_ldst_op_i32(int opc, TCGv_i32 val, TCGv_ptr base, |
118 | TCGArg offset) | |
119 | { | |
120 | *gen_opc_ptr++ = opc; | |
121 | *gen_opparam_ptr++ = GET_TCGV_I32(val); | |
122 | *gen_opparam_ptr++ = GET_TCGV_PTR(base); | |
123 | *gen_opparam_ptr++ = offset; | |
124 | } | |
125 | ||
126 | static inline void tcg_gen_ldst_op_i64(int opc, TCGv_i64 val, TCGv_ptr base, | |
127 | TCGArg offset) | |
128 | { | |
129 | *gen_opc_ptr++ = opc; | |
a810a2de | 130 | *gen_opparam_ptr++ = GET_TCGV_I64(val); |
a7812ae4 PB |
131 | *gen_opparam_ptr++ = GET_TCGV_PTR(base); |
132 | *gen_opparam_ptr++ = offset; | |
133 | } | |
134 | ||
135 | static inline void tcg_gen_qemu_ldst_op_i64_i32(int opc, TCGv_i64 val, TCGv_i32 addr, | |
136 | TCGArg mem_index) | |
137 | { | |
138 | *gen_opc_ptr++ = opc; | |
139 | *gen_opparam_ptr++ = GET_TCGV_I64(val); | |
140 | *gen_opparam_ptr++ = GET_TCGV_I32(addr); | |
141 | *gen_opparam_ptr++ = mem_index; | |
142 | } | |
143 | ||
144 | static inline void tcg_gen_qemu_ldst_op_i64_i64(int opc, TCGv_i64 val, TCGv_i64 addr, | |
145 | TCGArg mem_index) | |
146 | { | |
147 | *gen_opc_ptr++ = opc; | |
148 | *gen_opparam_ptr++ = GET_TCGV_I64(val); | |
149 | *gen_opparam_ptr++ = GET_TCGV_I64(addr); | |
150 | *gen_opparam_ptr++ = mem_index; | |
151 | } | |
152 | ||
153 | static inline void tcg_gen_op4_i32(int opc, TCGv_i32 arg1, TCGv_i32 arg2, | |
154 | TCGv_i32 arg3, TCGv_i32 arg4) | |
155 | { | |
156 | *gen_opc_ptr++ = opc; | |
157 | *gen_opparam_ptr++ = GET_TCGV_I32(arg1); | |
158 | *gen_opparam_ptr++ = GET_TCGV_I32(arg2); | |
159 | *gen_opparam_ptr++ = GET_TCGV_I32(arg3); | |
160 | *gen_opparam_ptr++ = GET_TCGV_I32(arg4); | |
161 | } | |
162 | ||
163 | static inline void tcg_gen_op4_i64(int opc, TCGv_i64 arg1, TCGv_i64 arg2, | |
a810a2de | 164 | TCGv_i64 arg3, TCGv_i64 arg4) |
a7812ae4 PB |
165 | { |
166 | *gen_opc_ptr++ = opc; | |
167 | *gen_opparam_ptr++ = GET_TCGV_I64(arg1); | |
168 | *gen_opparam_ptr++ = GET_TCGV_I64(arg2); | |
169 | *gen_opparam_ptr++ = GET_TCGV_I64(arg3); | |
170 | *gen_opparam_ptr++ = GET_TCGV_I64(arg4); | |
171 | } | |
172 | ||
173 | static inline void tcg_gen_op4i_i32(int opc, TCGv_i32 arg1, TCGv_i32 arg2, | |
174 | TCGv_i32 arg3, TCGArg arg4) | |
175 | { | |
176 | *gen_opc_ptr++ = opc; | |
177 | *gen_opparam_ptr++ = GET_TCGV_I32(arg1); | |
178 | *gen_opparam_ptr++ = GET_TCGV_I32(arg2); | |
179 | *gen_opparam_ptr++ = GET_TCGV_I32(arg3); | |
180 | *gen_opparam_ptr++ = arg4; | |
181 | } | |
182 | ||
183 | static inline void tcg_gen_op4i_i64(int opc, TCGv_i64 arg1, TCGv_i64 arg2, | |
184 | TCGv_i64 arg3, TCGArg arg4) | |
ac56dd48 PB |
185 | { |
186 | *gen_opc_ptr++ = opc; | |
a7812ae4 PB |
187 | *gen_opparam_ptr++ = GET_TCGV_I64(arg1); |
188 | *gen_opparam_ptr++ = GET_TCGV_I64(arg2); | |
189 | *gen_opparam_ptr++ = GET_TCGV_I64(arg3); | |
190 | *gen_opparam_ptr++ = arg4; | |
ac56dd48 PB |
191 | } |
192 | ||
a7812ae4 PB |
193 | static inline void tcg_gen_op4ii_i32(int opc, TCGv_i32 arg1, TCGv_i32 arg2, |
194 | TCGArg arg3, TCGArg arg4) | |
ac56dd48 PB |
195 | { |
196 | *gen_opc_ptr++ = opc; | |
a7812ae4 PB |
197 | *gen_opparam_ptr++ = GET_TCGV_I32(arg1); |
198 | *gen_opparam_ptr++ = GET_TCGV_I32(arg2); | |
199 | *gen_opparam_ptr++ = arg3; | |
c896fe29 FB |
200 | *gen_opparam_ptr++ = arg4; |
201 | } | |
202 | ||
a7812ae4 PB |
203 | static inline void tcg_gen_op4ii_i64(int opc, TCGv_i64 arg1, TCGv_i64 arg2, |
204 | TCGArg arg3, TCGArg arg4) | |
c896fe29 FB |
205 | { |
206 | *gen_opc_ptr++ = opc; | |
a7812ae4 PB |
207 | *gen_opparam_ptr++ = GET_TCGV_I64(arg1); |
208 | *gen_opparam_ptr++ = GET_TCGV_I64(arg2); | |
c896fe29 FB |
209 | *gen_opparam_ptr++ = arg3; |
210 | *gen_opparam_ptr++ = arg4; | |
ac56dd48 PB |
211 | } |
212 | ||
a7812ae4 PB |
213 | static inline void tcg_gen_op5_i32(int opc, TCGv_i32 arg1, TCGv_i32 arg2, |
214 | TCGv_i32 arg3, TCGv_i32 arg4, TCGv_i32 arg5) | |
215 | { | |
216 | *gen_opc_ptr++ = opc; | |
217 | *gen_opparam_ptr++ = GET_TCGV_I32(arg1); | |
218 | *gen_opparam_ptr++ = GET_TCGV_I32(arg2); | |
219 | *gen_opparam_ptr++ = GET_TCGV_I32(arg3); | |
220 | *gen_opparam_ptr++ = GET_TCGV_I32(arg4); | |
221 | *gen_opparam_ptr++ = GET_TCGV_I32(arg5); | |
222 | } | |
223 | ||
224 | static inline void tcg_gen_op5_i64(int opc, TCGv_i64 arg1, TCGv_i64 arg2, | |
225 | TCGv_i64 arg3, TCGv_i64 arg4, TCGv_i64 arg5) | |
226 | { | |
227 | *gen_opc_ptr++ = opc; | |
228 | *gen_opparam_ptr++ = GET_TCGV_I64(arg1); | |
229 | *gen_opparam_ptr++ = GET_TCGV_I64(arg2); | |
230 | *gen_opparam_ptr++ = GET_TCGV_I64(arg3); | |
231 | *gen_opparam_ptr++ = GET_TCGV_I64(arg4); | |
232 | *gen_opparam_ptr++ = GET_TCGV_I64(arg5); | |
233 | } | |
234 | ||
235 | static inline void tcg_gen_op5i_i32(int opc, TCGv_i32 arg1, TCGv_i32 arg2, | |
236 | TCGv_i32 arg3, TCGv_i32 arg4, TCGArg arg5) | |
ac56dd48 PB |
237 | { |
238 | *gen_opc_ptr++ = opc; | |
a7812ae4 PB |
239 | *gen_opparam_ptr++ = GET_TCGV_I32(arg1); |
240 | *gen_opparam_ptr++ = GET_TCGV_I32(arg2); | |
241 | *gen_opparam_ptr++ = GET_TCGV_I32(arg3); | |
242 | *gen_opparam_ptr++ = GET_TCGV_I32(arg4); | |
243 | *gen_opparam_ptr++ = arg5; | |
ac56dd48 PB |
244 | } |
245 | ||
a7812ae4 PB |
246 | static inline void tcg_gen_op5i_i64(int opc, TCGv_i64 arg1, TCGv_i64 arg2, |
247 | TCGv_i64 arg3, TCGv_i64 arg4, TCGArg arg5) | |
ac56dd48 PB |
248 | { |
249 | *gen_opc_ptr++ = opc; | |
a7812ae4 PB |
250 | *gen_opparam_ptr++ = GET_TCGV_I64(arg1); |
251 | *gen_opparam_ptr++ = GET_TCGV_I64(arg2); | |
252 | *gen_opparam_ptr++ = GET_TCGV_I64(arg3); | |
253 | *gen_opparam_ptr++ = GET_TCGV_I64(arg4); | |
c896fe29 FB |
254 | *gen_opparam_ptr++ = arg5; |
255 | } | |
256 | ||
a7812ae4 PB |
257 | static inline void tcg_gen_op6_i32(int opc, TCGv_i32 arg1, TCGv_i32 arg2, |
258 | TCGv_i32 arg3, TCGv_i32 arg4, TCGv_i32 arg5, | |
259 | TCGv_i32 arg6) | |
260 | { | |
261 | *gen_opc_ptr++ = opc; | |
262 | *gen_opparam_ptr++ = GET_TCGV_I32(arg1); | |
263 | *gen_opparam_ptr++ = GET_TCGV_I32(arg2); | |
264 | *gen_opparam_ptr++ = GET_TCGV_I32(arg3); | |
265 | *gen_opparam_ptr++ = GET_TCGV_I32(arg4); | |
266 | *gen_opparam_ptr++ = GET_TCGV_I32(arg5); | |
267 | *gen_opparam_ptr++ = GET_TCGV_I32(arg6); | |
268 | } | |
269 | ||
270 | static inline void tcg_gen_op6_i64(int opc, TCGv_i64 arg1, TCGv_i64 arg2, | |
271 | TCGv_i64 arg3, TCGv_i64 arg4, TCGv_i64 arg5, | |
272 | TCGv_i64 arg6) | |
c896fe29 FB |
273 | { |
274 | *gen_opc_ptr++ = opc; | |
a7812ae4 PB |
275 | *gen_opparam_ptr++ = GET_TCGV_I64(arg1); |
276 | *gen_opparam_ptr++ = GET_TCGV_I64(arg2); | |
277 | *gen_opparam_ptr++ = GET_TCGV_I64(arg3); | |
278 | *gen_opparam_ptr++ = GET_TCGV_I64(arg4); | |
279 | *gen_opparam_ptr++ = GET_TCGV_I64(arg5); | |
280 | *gen_opparam_ptr++ = GET_TCGV_I64(arg6); | |
ac56dd48 PB |
281 | } |
282 | ||
a7812ae4 PB |
283 | static inline void tcg_gen_op6ii_i32(int opc, TCGv_i32 arg1, TCGv_i32 arg2, |
284 | TCGv_i32 arg3, TCGv_i32 arg4, TCGArg arg5, | |
285 | TCGArg arg6) | |
ac56dd48 PB |
286 | { |
287 | *gen_opc_ptr++ = opc; | |
a7812ae4 PB |
288 | *gen_opparam_ptr++ = GET_TCGV_I32(arg1); |
289 | *gen_opparam_ptr++ = GET_TCGV_I32(arg2); | |
290 | *gen_opparam_ptr++ = GET_TCGV_I32(arg3); | |
291 | *gen_opparam_ptr++ = GET_TCGV_I32(arg4); | |
292 | *gen_opparam_ptr++ = arg5; | |
293 | *gen_opparam_ptr++ = arg6; | |
294 | } | |
295 | ||
296 | static inline void tcg_gen_op6ii_i64(int opc, TCGv_i64 arg1, TCGv_i64 arg2, | |
297 | TCGv_i64 arg3, TCGv_i64 arg4, TCGArg arg5, | |
298 | TCGArg arg6) | |
299 | { | |
300 | *gen_opc_ptr++ = opc; | |
301 | *gen_opparam_ptr++ = GET_TCGV_I64(arg1); | |
302 | *gen_opparam_ptr++ = GET_TCGV_I64(arg2); | |
303 | *gen_opparam_ptr++ = GET_TCGV_I64(arg3); | |
304 | *gen_opparam_ptr++ = GET_TCGV_I64(arg4); | |
c896fe29 FB |
305 | *gen_opparam_ptr++ = arg5; |
306 | *gen_opparam_ptr++ = arg6; | |
307 | } | |
308 | ||
309 | static inline void gen_set_label(int n) | |
310 | { | |
ac56dd48 | 311 | tcg_gen_op1i(INDEX_op_set_label, n); |
c896fe29 FB |
312 | } |
313 | ||
fb50d413 BS |
314 | static inline void tcg_gen_br(int label) |
315 | { | |
316 | tcg_gen_op1i(INDEX_op_br, label); | |
317 | } | |
318 | ||
a7812ae4 | 319 | static inline void tcg_gen_mov_i32(TCGv_i32 ret, TCGv_i32 arg) |
c896fe29 | 320 | { |
fe75bcf7 | 321 | if (!TCGV_EQUAL_I32(ret, arg)) |
a7812ae4 | 322 | tcg_gen_op2_i32(INDEX_op_mov_i32, ret, arg); |
c896fe29 FB |
323 | } |
324 | ||
a7812ae4 | 325 | static inline void tcg_gen_movi_i32(TCGv_i32 ret, int32_t arg) |
c896fe29 | 326 | { |
a7812ae4 | 327 | tcg_gen_op2i_i32(INDEX_op_movi_i32, ret, arg); |
c896fe29 FB |
328 | } |
329 | ||
330 | /* helper calls */ | |
a7812ae4 PB |
331 | static inline void tcg_gen_helperN(void *func, int flags, int sizemask, |
332 | TCGArg ret, int nargs, TCGArg *args) | |
333 | { | |
334 | TCGv_ptr fn; | |
335 | fn = tcg_const_ptr((tcg_target_long)func); | |
336 | tcg_gen_callN(&tcg_ctx, fn, flags, sizemask, ret, | |
337 | nargs, args); | |
338 | tcg_temp_free_ptr(fn); | |
339 | } | |
c896fe29 | 340 | |
a7812ae4 PB |
341 | /* FIXME: Should this be pure? */ |
342 | static inline void tcg_gen_helper64(void *func, TCGv_i64 ret, | |
343 | TCGv_i64 a, TCGv_i64 b) | |
c896fe29 | 344 | { |
a7812ae4 PB |
345 | TCGv_ptr fn; |
346 | TCGArg args[2]; | |
347 | fn = tcg_const_ptr((tcg_target_long)func); | |
348 | args[0] = GET_TCGV_I64(a); | |
349 | args[1] = GET_TCGV_I64(b); | |
350 | tcg_gen_callN(&tcg_ctx, fn, 0, 7, GET_TCGV_I64(ret), 2, args); | |
351 | tcg_temp_free_ptr(fn); | |
f8422f52 BS |
352 | } |
353 | ||
c896fe29 FB |
354 | /* 32 bit ops */ |
355 | ||
a7812ae4 | 356 | static inline void tcg_gen_ld8u_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset) |
c896fe29 | 357 | { |
a7812ae4 | 358 | tcg_gen_ldst_op_i32(INDEX_op_ld8u_i32, ret, arg2, offset); |
c896fe29 FB |
359 | } |
360 | ||
a7812ae4 | 361 | static inline void tcg_gen_ld8s_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset) |
c896fe29 | 362 | { |
a7812ae4 | 363 | tcg_gen_ldst_op_i32(INDEX_op_ld8s_i32, ret, arg2, offset); |
c896fe29 FB |
364 | } |
365 | ||
a7812ae4 | 366 | static inline void tcg_gen_ld16u_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset) |
c896fe29 | 367 | { |
a7812ae4 | 368 | tcg_gen_ldst_op_i32(INDEX_op_ld16u_i32, ret, arg2, offset); |
c896fe29 FB |
369 | } |
370 | ||
a7812ae4 | 371 | static inline void tcg_gen_ld16s_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset) |
c896fe29 | 372 | { |
a7812ae4 | 373 | tcg_gen_ldst_op_i32(INDEX_op_ld16s_i32, ret, arg2, offset); |
c896fe29 FB |
374 | } |
375 | ||
a7812ae4 | 376 | static inline void tcg_gen_ld_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset) |
c896fe29 | 377 | { |
a7812ae4 | 378 | tcg_gen_ldst_op_i32(INDEX_op_ld_i32, ret, arg2, offset); |
c896fe29 FB |
379 | } |
380 | ||
a7812ae4 | 381 | static inline void tcg_gen_st8_i32(TCGv_i32 arg1, TCGv_ptr arg2, tcg_target_long offset) |
c896fe29 | 382 | { |
a7812ae4 | 383 | tcg_gen_ldst_op_i32(INDEX_op_st8_i32, arg1, arg2, offset); |
c896fe29 FB |
384 | } |
385 | ||
a7812ae4 | 386 | static inline void tcg_gen_st16_i32(TCGv_i32 arg1, TCGv_ptr arg2, tcg_target_long offset) |
c896fe29 | 387 | { |
a7812ae4 | 388 | tcg_gen_ldst_op_i32(INDEX_op_st16_i32, arg1, arg2, offset); |
c896fe29 FB |
389 | } |
390 | ||
a7812ae4 | 391 | static inline void tcg_gen_st_i32(TCGv_i32 arg1, TCGv_ptr arg2, tcg_target_long offset) |
c896fe29 | 392 | { |
a7812ae4 | 393 | tcg_gen_ldst_op_i32(INDEX_op_st_i32, arg1, arg2, offset); |
c896fe29 FB |
394 | } |
395 | ||
a7812ae4 | 396 | static inline void tcg_gen_add_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
c896fe29 | 397 | { |
a7812ae4 | 398 | tcg_gen_op3_i32(INDEX_op_add_i32, ret, arg1, arg2); |
c896fe29 FB |
399 | } |
400 | ||
a7812ae4 | 401 | static inline void tcg_gen_addi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) |
c896fe29 | 402 | { |
7089442c BS |
403 | /* some cases can be optimized here */ |
404 | if (arg2 == 0) { | |
405 | tcg_gen_mov_i32(ret, arg1); | |
406 | } else { | |
a7812ae4 | 407 | TCGv_i32 t0 = tcg_const_i32(arg2); |
e8996ee0 | 408 | tcg_gen_add_i32(ret, arg1, t0); |
a7812ae4 | 409 | tcg_temp_free_i32(t0); |
7089442c | 410 | } |
c896fe29 FB |
411 | } |
412 | ||
a7812ae4 | 413 | static inline void tcg_gen_sub_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
c896fe29 | 414 | { |
a7812ae4 | 415 | tcg_gen_op3_i32(INDEX_op_sub_i32, ret, arg1, arg2); |
c896fe29 FB |
416 | } |
417 | ||
a7812ae4 | 418 | static inline void tcg_gen_subfi_i32(TCGv_i32 ret, int32_t arg1, TCGv_i32 arg2) |
0045734a | 419 | { |
a7812ae4 | 420 | TCGv_i32 t0 = tcg_const_i32(arg1); |
0045734a | 421 | tcg_gen_sub_i32(ret, t0, arg2); |
a7812ae4 | 422 | tcg_temp_free_i32(t0); |
0045734a AJ |
423 | } |
424 | ||
a7812ae4 | 425 | static inline void tcg_gen_subi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) |
c896fe29 | 426 | { |
7089442c BS |
427 | /* some cases can be optimized here */ |
428 | if (arg2 == 0) { | |
429 | tcg_gen_mov_i32(ret, arg1); | |
430 | } else { | |
a7812ae4 | 431 | TCGv_i32 t0 = tcg_const_i32(arg2); |
e8996ee0 | 432 | tcg_gen_sub_i32(ret, arg1, t0); |
a7812ae4 | 433 | tcg_temp_free_i32(t0); |
7089442c | 434 | } |
c896fe29 FB |
435 | } |
436 | ||
a7812ae4 | 437 | static inline void tcg_gen_and_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
c896fe29 | 438 | { |
7fc81051 AJ |
439 | if (TCGV_EQUAL_I32(arg1, arg2)) { |
440 | tcg_gen_mov_i32(ret, arg1); | |
441 | } else { | |
442 | tcg_gen_op3_i32(INDEX_op_and_i32, ret, arg1, arg2); | |
443 | } | |
c896fe29 FB |
444 | } |
445 | ||
a7812ae4 | 446 | static inline void tcg_gen_andi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) |
c896fe29 FB |
447 | { |
448 | /* some cases can be optimized here */ | |
449 | if (arg2 == 0) { | |
450 | tcg_gen_movi_i32(ret, 0); | |
451 | } else if (arg2 == 0xffffffff) { | |
452 | tcg_gen_mov_i32(ret, arg1); | |
453 | } else { | |
a7812ae4 | 454 | TCGv_i32 t0 = tcg_const_i32(arg2); |
e8996ee0 | 455 | tcg_gen_and_i32(ret, arg1, t0); |
a7812ae4 | 456 | tcg_temp_free_i32(t0); |
c896fe29 FB |
457 | } |
458 | } | |
459 | ||
a7812ae4 | 460 | static inline void tcg_gen_or_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
c896fe29 | 461 | { |
7fc81051 AJ |
462 | if (TCGV_EQUAL_I32(arg1, arg2)) { |
463 | tcg_gen_mov_i32(ret, arg1); | |
464 | } else { | |
465 | tcg_gen_op3_i32(INDEX_op_or_i32, ret, arg1, arg2); | |
466 | } | |
c896fe29 FB |
467 | } |
468 | ||
a7812ae4 | 469 | static inline void tcg_gen_ori_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) |
c896fe29 FB |
470 | { |
471 | /* some cases can be optimized here */ | |
472 | if (arg2 == 0xffffffff) { | |
7089442c | 473 | tcg_gen_movi_i32(ret, 0xffffffff); |
c896fe29 FB |
474 | } else if (arg2 == 0) { |
475 | tcg_gen_mov_i32(ret, arg1); | |
476 | } else { | |
a7812ae4 | 477 | TCGv_i32 t0 = tcg_const_i32(arg2); |
e8996ee0 | 478 | tcg_gen_or_i32(ret, arg1, t0); |
a7812ae4 | 479 | tcg_temp_free_i32(t0); |
c896fe29 FB |
480 | } |
481 | } | |
482 | ||
a7812ae4 | 483 | static inline void tcg_gen_xor_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
c896fe29 | 484 | { |
7fc81051 AJ |
485 | if (TCGV_EQUAL_I32(arg1, arg2)) { |
486 | tcg_gen_movi_i32(ret, 0); | |
487 | } else { | |
488 | tcg_gen_op3_i32(INDEX_op_xor_i32, ret, arg1, arg2); | |
489 | } | |
c896fe29 FB |
490 | } |
491 | ||
a7812ae4 | 492 | static inline void tcg_gen_xori_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) |
c896fe29 FB |
493 | { |
494 | /* some cases can be optimized here */ | |
495 | if (arg2 == 0) { | |
496 | tcg_gen_mov_i32(ret, arg1); | |
497 | } else { | |
a7812ae4 | 498 | TCGv_i32 t0 = tcg_const_i32(arg2); |
e8996ee0 | 499 | tcg_gen_xor_i32(ret, arg1, t0); |
a7812ae4 | 500 | tcg_temp_free_i32(t0); |
c896fe29 FB |
501 | } |
502 | } | |
503 | ||
a7812ae4 | 504 | static inline void tcg_gen_shl_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
c896fe29 | 505 | { |
a7812ae4 | 506 | tcg_gen_op3_i32(INDEX_op_shl_i32, ret, arg1, arg2); |
c896fe29 FB |
507 | } |
508 | ||
a7812ae4 | 509 | static inline void tcg_gen_shli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) |
c896fe29 | 510 | { |
34151a20 FB |
511 | if (arg2 == 0) { |
512 | tcg_gen_mov_i32(ret, arg1); | |
513 | } else { | |
a7812ae4 | 514 | TCGv_i32 t0 = tcg_const_i32(arg2); |
e8996ee0 | 515 | tcg_gen_shl_i32(ret, arg1, t0); |
a7812ae4 | 516 | tcg_temp_free_i32(t0); |
34151a20 | 517 | } |
c896fe29 FB |
518 | } |
519 | ||
a7812ae4 | 520 | static inline void tcg_gen_shr_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
c896fe29 | 521 | { |
a7812ae4 | 522 | tcg_gen_op3_i32(INDEX_op_shr_i32, ret, arg1, arg2); |
c896fe29 FB |
523 | } |
524 | ||
a7812ae4 | 525 | static inline void tcg_gen_shri_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) |
c896fe29 | 526 | { |
34151a20 FB |
527 | if (arg2 == 0) { |
528 | tcg_gen_mov_i32(ret, arg1); | |
529 | } else { | |
a7812ae4 | 530 | TCGv_i32 t0 = tcg_const_i32(arg2); |
e8996ee0 | 531 | tcg_gen_shr_i32(ret, arg1, t0); |
a7812ae4 | 532 | tcg_temp_free_i32(t0); |
34151a20 | 533 | } |
c896fe29 FB |
534 | } |
535 | ||
a7812ae4 | 536 | static inline void tcg_gen_sar_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
c896fe29 | 537 | { |
a7812ae4 | 538 | tcg_gen_op3_i32(INDEX_op_sar_i32, ret, arg1, arg2); |
c896fe29 FB |
539 | } |
540 | ||
a7812ae4 | 541 | static inline void tcg_gen_sari_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) |
c896fe29 | 542 | { |
34151a20 FB |
543 | if (arg2 == 0) { |
544 | tcg_gen_mov_i32(ret, arg1); | |
545 | } else { | |
a7812ae4 | 546 | TCGv_i32 t0 = tcg_const_i32(arg2); |
e8996ee0 | 547 | tcg_gen_sar_i32(ret, arg1, t0); |
a7812ae4 | 548 | tcg_temp_free_i32(t0); |
34151a20 | 549 | } |
c896fe29 FB |
550 | } |
551 | ||
a7812ae4 | 552 | static inline void tcg_gen_brcond_i32(int cond, TCGv_i32 arg1, TCGv_i32 arg2, |
c896fe29 FB |
553 | int label_index) |
554 | { | |
a7812ae4 | 555 | tcg_gen_op4ii_i32(INDEX_op_brcond_i32, arg1, arg2, cond, label_index); |
c896fe29 FB |
556 | } |
557 | ||
a7812ae4 | 558 | static inline void tcg_gen_brcondi_i32(int cond, TCGv_i32 arg1, int32_t arg2, |
cb63669a PB |
559 | int label_index) |
560 | { | |
a7812ae4 | 561 | TCGv_i32 t0 = tcg_const_i32(arg2); |
cb63669a | 562 | tcg_gen_brcond_i32(cond, arg1, t0, label_index); |
a7812ae4 | 563 | tcg_temp_free_i32(t0); |
cb63669a PB |
564 | } |
565 | ||
a7812ae4 | 566 | static inline void tcg_gen_mul_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
c896fe29 | 567 | { |
a7812ae4 | 568 | tcg_gen_op3_i32(INDEX_op_mul_i32, ret, arg1, arg2); |
c896fe29 FB |
569 | } |
570 | ||
a7812ae4 | 571 | static inline void tcg_gen_muli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) |
f730fd27 | 572 | { |
a7812ae4 | 573 | TCGv_i32 t0 = tcg_const_i32(arg2); |
e8996ee0 | 574 | tcg_gen_mul_i32(ret, arg1, t0); |
a7812ae4 | 575 | tcg_temp_free_i32(t0); |
f730fd27 TS |
576 | } |
577 | ||
c896fe29 | 578 | #ifdef TCG_TARGET_HAS_div_i32 |
a7812ae4 | 579 | static inline void tcg_gen_div_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
c896fe29 | 580 | { |
a7812ae4 | 581 | tcg_gen_op3_i32(INDEX_op_div_i32, ret, arg1, arg2); |
c896fe29 FB |
582 | } |
583 | ||
a7812ae4 | 584 | static inline void tcg_gen_rem_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
c896fe29 | 585 | { |
a7812ae4 | 586 | tcg_gen_op3_i32(INDEX_op_rem_i32, ret, arg1, arg2); |
c896fe29 FB |
587 | } |
588 | ||
a7812ae4 | 589 | static inline void tcg_gen_divu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
c896fe29 | 590 | { |
a7812ae4 | 591 | tcg_gen_op3_i32(INDEX_op_divu_i32, ret, arg1, arg2); |
c896fe29 FB |
592 | } |
593 | ||
a7812ae4 | 594 | static inline void tcg_gen_remu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
c896fe29 | 595 | { |
a7812ae4 | 596 | tcg_gen_op3_i32(INDEX_op_remu_i32, ret, arg1, arg2); |
c896fe29 FB |
597 | } |
598 | #else | |
a7812ae4 | 599 | static inline void tcg_gen_div_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
c896fe29 | 600 | { |
a7812ae4 PB |
601 | TCGv_i32 t0; |
602 | t0 = tcg_temp_new_i32(); | |
c896fe29 | 603 | tcg_gen_sari_i32(t0, arg1, 31); |
a7812ae4 PB |
604 | tcg_gen_op5_i32(INDEX_op_div2_i32, ret, t0, arg1, t0, arg2); |
605 | tcg_temp_free_i32(t0); | |
c896fe29 FB |
606 | } |
607 | ||
a7812ae4 | 608 | static inline void tcg_gen_rem_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
c896fe29 | 609 | { |
a7812ae4 PB |
610 | TCGv_i32 t0; |
611 | t0 = tcg_temp_new_i32(); | |
c896fe29 | 612 | tcg_gen_sari_i32(t0, arg1, 31); |
a7812ae4 PB |
613 | tcg_gen_op5_i32(INDEX_op_div2_i32, t0, ret, arg1, t0, arg2); |
614 | tcg_temp_free_i32(t0); | |
c896fe29 FB |
615 | } |
616 | ||
a7812ae4 | 617 | static inline void tcg_gen_divu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
c896fe29 | 618 | { |
a7812ae4 PB |
619 | TCGv_i32 t0; |
620 | t0 = tcg_temp_new_i32(); | |
c896fe29 | 621 | tcg_gen_movi_i32(t0, 0); |
a7812ae4 PB |
622 | tcg_gen_op5_i32(INDEX_op_divu2_i32, ret, t0, arg1, t0, arg2); |
623 | tcg_temp_free_i32(t0); | |
c896fe29 FB |
624 | } |
625 | ||
a7812ae4 | 626 | static inline void tcg_gen_remu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
c896fe29 | 627 | { |
a7812ae4 PB |
628 | TCGv_i32 t0; |
629 | t0 = tcg_temp_new_i32(); | |
c896fe29 | 630 | tcg_gen_movi_i32(t0, 0); |
a7812ae4 PB |
631 | tcg_gen_op5_i32(INDEX_op_divu2_i32, t0, ret, arg1, t0, arg2); |
632 | tcg_temp_free_i32(t0); | |
c896fe29 FB |
633 | } |
634 | #endif | |
635 | ||
636 | #if TCG_TARGET_REG_BITS == 32 | |
637 | ||
a7812ae4 | 638 | static inline void tcg_gen_mov_i64(TCGv_i64 ret, TCGv_i64 arg) |
c896fe29 | 639 | { |
fe75bcf7 | 640 | if (!TCGV_EQUAL_I64(ret, arg)) { |
a7812ae4 | 641 | tcg_gen_mov_i32(TCGV_LOW(ret), TCGV_LOW(arg)); |
4d07272d BS |
642 | tcg_gen_mov_i32(TCGV_HIGH(ret), TCGV_HIGH(arg)); |
643 | } | |
c896fe29 FB |
644 | } |
645 | ||
a7812ae4 | 646 | static inline void tcg_gen_movi_i64(TCGv_i64 ret, int64_t arg) |
c896fe29 | 647 | { |
a7812ae4 | 648 | tcg_gen_movi_i32(TCGV_LOW(ret), arg); |
ac56dd48 | 649 | tcg_gen_movi_i32(TCGV_HIGH(ret), arg >> 32); |
c896fe29 FB |
650 | } |
651 | ||
a7812ae4 PB |
652 | static inline void tcg_gen_ld8u_i64(TCGv_i64 ret, TCGv_ptr arg2, |
653 | tcg_target_long offset) | |
c896fe29 | 654 | { |
a7812ae4 | 655 | tcg_gen_ld8u_i32(TCGV_LOW(ret), arg2, offset); |
ac56dd48 | 656 | tcg_gen_movi_i32(TCGV_HIGH(ret), 0); |
c896fe29 FB |
657 | } |
658 | ||
a7812ae4 PB |
659 | static inline void tcg_gen_ld8s_i64(TCGv_i64 ret, TCGv_ptr arg2, |
660 | tcg_target_long offset) | |
c896fe29 | 661 | { |
a7812ae4 PB |
662 | tcg_gen_ld8s_i32(TCGV_LOW(ret), arg2, offset); |
663 | tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_HIGH(ret), 31); | |
c896fe29 FB |
664 | } |
665 | ||
a7812ae4 PB |
666 | static inline void tcg_gen_ld16u_i64(TCGv_i64 ret, TCGv_ptr arg2, |
667 | tcg_target_long offset) | |
c896fe29 | 668 | { |
a747723b | 669 | tcg_gen_ld16u_i32(TCGV_LOW(ret), arg2, offset); |
ac56dd48 | 670 | tcg_gen_movi_i32(TCGV_HIGH(ret), 0); |
c896fe29 FB |
671 | } |
672 | ||
a7812ae4 PB |
673 | static inline void tcg_gen_ld16s_i64(TCGv_i64 ret, TCGv_ptr arg2, |
674 | tcg_target_long offset) | |
c896fe29 | 675 | { |
a7812ae4 PB |
676 | tcg_gen_ld16s_i32(TCGV_LOW(ret), arg2, offset); |
677 | tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31); | |
c896fe29 FB |
678 | } |
679 | ||
a7812ae4 PB |
680 | static inline void tcg_gen_ld32u_i64(TCGv_i64 ret, TCGv_ptr arg2, |
681 | tcg_target_long offset) | |
c896fe29 | 682 | { |
a7812ae4 | 683 | tcg_gen_ld_i32(TCGV_LOW(ret), arg2, offset); |
ac56dd48 | 684 | tcg_gen_movi_i32(TCGV_HIGH(ret), 0); |
c896fe29 FB |
685 | } |
686 | ||
a7812ae4 PB |
687 | static inline void tcg_gen_ld32s_i64(TCGv_i64 ret, TCGv_ptr arg2, |
688 | tcg_target_long offset) | |
c896fe29 | 689 | { |
a7812ae4 PB |
690 | tcg_gen_ld_i32(TCGV_LOW(ret), arg2, offset); |
691 | tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31); | |
c896fe29 FB |
692 | } |
693 | ||
a7812ae4 PB |
694 | static inline void tcg_gen_ld_i64(TCGv_i64 ret, TCGv_ptr arg2, |
695 | tcg_target_long offset) | |
c896fe29 FB |
696 | { |
697 | /* since arg2 and ret have different types, they cannot be the | |
698 | same temporary */ | |
699 | #ifdef TCG_TARGET_WORDS_BIGENDIAN | |
ac56dd48 | 700 | tcg_gen_ld_i32(TCGV_HIGH(ret), arg2, offset); |
a7812ae4 | 701 | tcg_gen_ld_i32(TCGV_LOW(ret), arg2, offset + 4); |
c896fe29 | 702 | #else |
a7812ae4 | 703 | tcg_gen_ld_i32(TCGV_LOW(ret), arg2, offset); |
ac56dd48 | 704 | tcg_gen_ld_i32(TCGV_HIGH(ret), arg2, offset + 4); |
c896fe29 FB |
705 | #endif |
706 | } | |
707 | ||
a7812ae4 PB |
708 | static inline void tcg_gen_st8_i64(TCGv_i64 arg1, TCGv_ptr arg2, |
709 | tcg_target_long offset) | |
c896fe29 | 710 | { |
a7812ae4 | 711 | tcg_gen_st8_i32(TCGV_LOW(arg1), arg2, offset); |
c896fe29 FB |
712 | } |
713 | ||
a7812ae4 PB |
714 | static inline void tcg_gen_st16_i64(TCGv_i64 arg1, TCGv_ptr arg2, |
715 | tcg_target_long offset) | |
c896fe29 | 716 | { |
a7812ae4 | 717 | tcg_gen_st16_i32(TCGV_LOW(arg1), arg2, offset); |
c896fe29 FB |
718 | } |
719 | ||
a7812ae4 PB |
720 | static inline void tcg_gen_st32_i64(TCGv_i64 arg1, TCGv_ptr arg2, |
721 | tcg_target_long offset) | |
c896fe29 | 722 | { |
a7812ae4 | 723 | tcg_gen_st_i32(TCGV_LOW(arg1), arg2, offset); |
c896fe29 FB |
724 | } |
725 | ||
a7812ae4 PB |
726 | static inline void tcg_gen_st_i64(TCGv_i64 arg1, TCGv_ptr arg2, |
727 | tcg_target_long offset) | |
c896fe29 FB |
728 | { |
729 | #ifdef TCG_TARGET_WORDS_BIGENDIAN | |
ac56dd48 | 730 | tcg_gen_st_i32(TCGV_HIGH(arg1), arg2, offset); |
a7812ae4 | 731 | tcg_gen_st_i32(TCGV_LOW(arg1), arg2, offset + 4); |
c896fe29 | 732 | #else |
a7812ae4 | 733 | tcg_gen_st_i32(TCGV_LOW(arg1), arg2, offset); |
ac56dd48 | 734 | tcg_gen_st_i32(TCGV_HIGH(arg1), arg2, offset + 4); |
c896fe29 FB |
735 | #endif |
736 | } | |
737 | ||
a7812ae4 | 738 | static inline void tcg_gen_add_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
c896fe29 | 739 | { |
a7812ae4 PB |
740 | tcg_gen_op6_i32(INDEX_op_add2_i32, TCGV_LOW(ret), TCGV_HIGH(ret), |
741 | TCGV_LOW(arg1), TCGV_HIGH(arg1), TCGV_LOW(arg2), | |
742 | TCGV_HIGH(arg2)); | |
c896fe29 FB |
743 | } |
744 | ||
a7812ae4 | 745 | static inline void tcg_gen_sub_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
c896fe29 | 746 | { |
a7812ae4 PB |
747 | tcg_gen_op6_i32(INDEX_op_sub2_i32, TCGV_LOW(ret), TCGV_HIGH(ret), |
748 | TCGV_LOW(arg1), TCGV_HIGH(arg1), TCGV_LOW(arg2), | |
749 | TCGV_HIGH(arg2)); | |
c896fe29 FB |
750 | } |
751 | ||
a7812ae4 | 752 | static inline void tcg_gen_and_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
c896fe29 | 753 | { |
a7812ae4 | 754 | tcg_gen_and_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2)); |
ac56dd48 | 755 | tcg_gen_and_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2)); |
c896fe29 FB |
756 | } |
757 | ||
a7812ae4 | 758 | static inline void tcg_gen_andi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
c896fe29 | 759 | { |
e5105083 AJ |
760 | tcg_gen_andi_i32(TCGV_LOW(ret), TCGV_LOW(arg1), arg2); |
761 | tcg_gen_andi_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), arg2 >> 32); | |
c896fe29 FB |
762 | } |
763 | ||
a7812ae4 | 764 | static inline void tcg_gen_or_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
c896fe29 | 765 | { |
e5105083 AJ |
766 | tcg_gen_or_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2)); |
767 | tcg_gen_or_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2)); | |
c896fe29 FB |
768 | } |
769 | ||
a7812ae4 | 770 | static inline void tcg_gen_ori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
c896fe29 | 771 | { |
a7812ae4 | 772 | tcg_gen_ori_i32(TCGV_LOW(ret), TCGV_LOW(arg1), arg2); |
ac56dd48 | 773 | tcg_gen_ori_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), arg2 >> 32); |
c896fe29 FB |
774 | } |
775 | ||
a7812ae4 | 776 | static inline void tcg_gen_xor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
c896fe29 | 777 | { |
e5105083 AJ |
778 | tcg_gen_xor_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2)); |
779 | tcg_gen_xor_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2)); | |
c896fe29 FB |
780 | } |
781 | ||
a7812ae4 | 782 | static inline void tcg_gen_xori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
c896fe29 | 783 | { |
a7812ae4 | 784 | tcg_gen_xori_i32(TCGV_LOW(ret), TCGV_LOW(arg1), arg2); |
ac56dd48 | 785 | tcg_gen_xori_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), arg2 >> 32); |
c896fe29 FB |
786 | } |
787 | ||
788 | /* XXX: use generic code when basic block handling is OK or CPU | |
789 | specific code (x86) */ | |
a7812ae4 | 790 | static inline void tcg_gen_shl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
c896fe29 | 791 | { |
a7812ae4 | 792 | tcg_gen_helper64(tcg_helper_shl_i64, ret, arg1, arg2); |
c896fe29 FB |
793 | } |
794 | ||
a7812ae4 | 795 | static inline void tcg_gen_shli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
c896fe29 FB |
796 | { |
797 | tcg_gen_shifti_i64(ret, arg1, arg2, 0, 0); | |
798 | } | |
799 | ||
a7812ae4 | 800 | static inline void tcg_gen_shr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
c896fe29 | 801 | { |
a7812ae4 | 802 | tcg_gen_helper64(tcg_helper_shr_i64, ret, arg1, arg2); |
c896fe29 FB |
803 | } |
804 | ||
a7812ae4 | 805 | static inline void tcg_gen_shri_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
c896fe29 FB |
806 | { |
807 | tcg_gen_shifti_i64(ret, arg1, arg2, 1, 0); | |
808 | } | |
809 | ||
a7812ae4 | 810 | static inline void tcg_gen_sar_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
c896fe29 | 811 | { |
a7812ae4 | 812 | tcg_gen_helper64(tcg_helper_sar_i64, ret, arg1, arg2); |
c896fe29 FB |
813 | } |
814 | ||
a7812ae4 | 815 | static inline void tcg_gen_sari_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
c896fe29 FB |
816 | { |
817 | tcg_gen_shifti_i64(ret, arg1, arg2, 1, 1); | |
818 | } | |
819 | ||
a7812ae4 | 820 | static inline void tcg_gen_brcond_i64(int cond, TCGv_i64 arg1, TCGv_i64 arg2, |
c896fe29 FB |
821 | int label_index) |
822 | { | |
a7812ae4 PB |
823 | tcg_gen_op6ii_i32(INDEX_op_brcond2_i32, |
824 | TCGV_LOW(arg1), TCGV_HIGH(arg1), TCGV_LOW(arg2), | |
825 | TCGV_HIGH(arg2), cond, label_index); | |
c896fe29 FB |
826 | } |
827 | ||
a7812ae4 | 828 | static inline void tcg_gen_mul_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
c896fe29 | 829 | { |
a7812ae4 PB |
830 | TCGv_i64 t0; |
831 | TCGv_i32 t1; | |
c896fe29 | 832 | |
a7812ae4 PB |
833 | t0 = tcg_temp_new_i64(); |
834 | t1 = tcg_temp_new_i32(); | |
835 | ||
836 | tcg_gen_op4_i32(INDEX_op_mulu2_i32, TCGV_LOW(t0), TCGV_HIGH(t0), | |
837 | TCGV_LOW(arg1), TCGV_LOW(arg2)); | |
838 | ||
839 | tcg_gen_mul_i32(t1, TCGV_LOW(arg1), TCGV_HIGH(arg2)); | |
ac56dd48 | 840 | tcg_gen_add_i32(TCGV_HIGH(t0), TCGV_HIGH(t0), t1); |
a7812ae4 | 841 | tcg_gen_mul_i32(t1, TCGV_HIGH(arg1), TCGV_LOW(arg2)); |
ac56dd48 | 842 | tcg_gen_add_i32(TCGV_HIGH(t0), TCGV_HIGH(t0), t1); |
a7812ae4 | 843 | |
c896fe29 | 844 | tcg_gen_mov_i64(ret, t0); |
a7812ae4 PB |
845 | tcg_temp_free_i64(t0); |
846 | tcg_temp_free_i32(t1); | |
c896fe29 FB |
847 | } |
848 | ||
a7812ae4 | 849 | static inline void tcg_gen_div_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
c896fe29 | 850 | { |
a7812ae4 | 851 | tcg_gen_helper64(tcg_helper_div_i64, ret, arg1, arg2); |
c896fe29 FB |
852 | } |
853 | ||
a7812ae4 | 854 | static inline void tcg_gen_rem_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
c896fe29 | 855 | { |
a7812ae4 | 856 | tcg_gen_helper64(tcg_helper_rem_i64, ret, arg1, arg2); |
c896fe29 FB |
857 | } |
858 | ||
a7812ae4 | 859 | static inline void tcg_gen_divu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
c896fe29 | 860 | { |
a7812ae4 | 861 | tcg_gen_helper64(tcg_helper_divu_i64, ret, arg1, arg2); |
c896fe29 FB |
862 | } |
863 | ||
a7812ae4 | 864 | static inline void tcg_gen_remu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
c896fe29 | 865 | { |
a7812ae4 | 866 | tcg_gen_helper64(tcg_helper_remu_i64, ret, arg1, arg2); |
c896fe29 FB |
867 | } |
868 | ||
869 | #else | |
870 | ||
a7812ae4 | 871 | static inline void tcg_gen_mov_i64(TCGv_i64 ret, TCGv_i64 arg) |
c896fe29 | 872 | { |
fe75bcf7 | 873 | if (!TCGV_EQUAL_I64(ret, arg)) |
a7812ae4 | 874 | tcg_gen_op2_i64(INDEX_op_mov_i64, ret, arg); |
c896fe29 FB |
875 | } |
876 | ||
a7812ae4 | 877 | static inline void tcg_gen_movi_i64(TCGv_i64 ret, int64_t arg) |
c896fe29 | 878 | { |
a7812ae4 | 879 | tcg_gen_op2i_i64(INDEX_op_movi_i64, ret, arg); |
c896fe29 FB |
880 | } |
881 | ||
a7812ae4 | 882 | static inline void tcg_gen_ld8u_i64(TCGv_i64 ret, TCGv_i64 arg2, |
ac56dd48 | 883 | tcg_target_long offset) |
c896fe29 | 884 | { |
a7812ae4 | 885 | tcg_gen_ldst_op_i64(INDEX_op_ld8u_i64, ret, arg2, offset); |
c896fe29 FB |
886 | } |
887 | ||
a7812ae4 | 888 | static inline void tcg_gen_ld8s_i64(TCGv_i64 ret, TCGv_i64 arg2, |
ac56dd48 | 889 | tcg_target_long offset) |
c896fe29 | 890 | { |
a7812ae4 | 891 | tcg_gen_ldst_op_i64(INDEX_op_ld8s_i64, ret, arg2, offset); |
c896fe29 FB |
892 | } |
893 | ||
a7812ae4 | 894 | static inline void tcg_gen_ld16u_i64(TCGv_i64 ret, TCGv_i64 arg2, |
ac56dd48 | 895 | tcg_target_long offset) |
c896fe29 | 896 | { |
a7812ae4 | 897 | tcg_gen_ldst_op_i64(INDEX_op_ld16u_i64, ret, arg2, offset); |
c896fe29 FB |
898 | } |
899 | ||
a7812ae4 | 900 | static inline void tcg_gen_ld16s_i64(TCGv_i64 ret, TCGv_i64 arg2, |
ac56dd48 | 901 | tcg_target_long offset) |
c896fe29 | 902 | { |
a7812ae4 | 903 | tcg_gen_ldst_op_i64(INDEX_op_ld16s_i64, ret, arg2, offset); |
c896fe29 FB |
904 | } |
905 | ||
a7812ae4 | 906 | static inline void tcg_gen_ld32u_i64(TCGv_i64 ret, TCGv_i64 arg2, |
ac56dd48 | 907 | tcg_target_long offset) |
c896fe29 | 908 | { |
a7812ae4 | 909 | tcg_gen_ldst_op_i64(INDEX_op_ld32u_i64, ret, arg2, offset); |
c896fe29 FB |
910 | } |
911 | ||
a7812ae4 | 912 | static inline void tcg_gen_ld32s_i64(TCGv_i64 ret, TCGv_i64 arg2, |
ac56dd48 | 913 | tcg_target_long offset) |
c896fe29 | 914 | { |
a7812ae4 | 915 | tcg_gen_ldst_op_i64(INDEX_op_ld32s_i64, ret, arg2, offset); |
c896fe29 FB |
916 | } |
917 | ||
a7812ae4 | 918 | static inline void tcg_gen_ld_i64(TCGv_i64 ret, TCGv_i64 arg2, tcg_target_long offset) |
c896fe29 | 919 | { |
a7812ae4 | 920 | tcg_gen_ldst_op_i64(INDEX_op_ld_i64, ret, arg2, offset); |
c896fe29 FB |
921 | } |
922 | ||
a7812ae4 | 923 | static inline void tcg_gen_st8_i64(TCGv_i64 arg1, TCGv_i64 arg2, |
ac56dd48 | 924 | tcg_target_long offset) |
c896fe29 | 925 | { |
a7812ae4 | 926 | tcg_gen_ldst_op_i64(INDEX_op_st8_i64, arg1, arg2, offset); |
c896fe29 FB |
927 | } |
928 | ||
a7812ae4 | 929 | static inline void tcg_gen_st16_i64(TCGv_i64 arg1, TCGv_i64 arg2, |
ac56dd48 | 930 | tcg_target_long offset) |
c896fe29 | 931 | { |
a7812ae4 | 932 | tcg_gen_ldst_op_i64(INDEX_op_st16_i64, arg1, arg2, offset); |
c896fe29 FB |
933 | } |
934 | ||
a7812ae4 | 935 | static inline void tcg_gen_st32_i64(TCGv_i64 arg1, TCGv_i64 arg2, |
ac56dd48 | 936 | tcg_target_long offset) |
c896fe29 | 937 | { |
a7812ae4 | 938 | tcg_gen_ldst_op_i64(INDEX_op_st32_i64, arg1, arg2, offset); |
c896fe29 FB |
939 | } |
940 | ||
a7812ae4 | 941 | static inline void tcg_gen_st_i64(TCGv_i64 arg1, TCGv_i64 arg2, tcg_target_long offset) |
c896fe29 | 942 | { |
a7812ae4 | 943 | tcg_gen_ldst_op_i64(INDEX_op_st_i64, arg1, arg2, offset); |
c896fe29 FB |
944 | } |
945 | ||
a7812ae4 | 946 | static inline void tcg_gen_add_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
c896fe29 | 947 | { |
a7812ae4 | 948 | tcg_gen_op3_i64(INDEX_op_add_i64, ret, arg1, arg2); |
c896fe29 FB |
949 | } |
950 | ||
a7812ae4 | 951 | static inline void tcg_gen_sub_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
c896fe29 | 952 | { |
a7812ae4 | 953 | tcg_gen_op3_i64(INDEX_op_sub_i64, ret, arg1, arg2); |
c896fe29 FB |
954 | } |
955 | ||
a7812ae4 | 956 | static inline void tcg_gen_and_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
c896fe29 | 957 | { |
7fc81051 AJ |
958 | if (TCGV_EQUAL_I64(arg1, arg2)) { |
959 | tcg_gen_mov_i64(ret, arg1); | |
960 | } else { | |
961 | tcg_gen_op3_i64(INDEX_op_and_i64, ret, arg1, arg2); | |
962 | } | |
c896fe29 FB |
963 | } |
964 | ||
a7812ae4 | 965 | static inline void tcg_gen_andi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
c896fe29 | 966 | { |
a7812ae4 | 967 | TCGv_i64 t0 = tcg_const_i64(arg2); |
e8996ee0 | 968 | tcg_gen_and_i64(ret, arg1, t0); |
a7812ae4 | 969 | tcg_temp_free_i64(t0); |
c896fe29 FB |
970 | } |
971 | ||
a7812ae4 | 972 | static inline void tcg_gen_or_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
c896fe29 | 973 | { |
7fc81051 AJ |
974 | if (TCGV_EQUAL_I64(arg1, arg2)) { |
975 | tcg_gen_mov_i64(ret, arg1); | |
976 | } else { | |
977 | tcg_gen_op3_i64(INDEX_op_or_i64, ret, arg1, arg2); | |
978 | } | |
c896fe29 FB |
979 | } |
980 | ||
a7812ae4 | 981 | static inline void tcg_gen_ori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
c896fe29 | 982 | { |
a7812ae4 | 983 | TCGv_i64 t0 = tcg_const_i64(arg2); |
e8996ee0 | 984 | tcg_gen_or_i64(ret, arg1, t0); |
a7812ae4 | 985 | tcg_temp_free_i64(t0); |
c896fe29 FB |
986 | } |
987 | ||
a7812ae4 | 988 | static inline void tcg_gen_xor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
c896fe29 | 989 | { |
7fc81051 AJ |
990 | if (TCGV_EQUAL_I64(arg1, arg2)) { |
991 | tcg_gen_movi_i64(ret, 0); | |
992 | } else { | |
993 | tcg_gen_op3_i64(INDEX_op_xor_i64, ret, arg1, arg2); | |
994 | } | |
c896fe29 FB |
995 | } |
996 | ||
a7812ae4 | 997 | static inline void tcg_gen_xori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
c896fe29 | 998 | { |
a7812ae4 | 999 | TCGv_i64 t0 = tcg_const_i64(arg2); |
e8996ee0 | 1000 | tcg_gen_xor_i64(ret, arg1, t0); |
a7812ae4 | 1001 | tcg_temp_free_i64(t0); |
c896fe29 FB |
1002 | } |
1003 | ||
a7812ae4 | 1004 | static inline void tcg_gen_shl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
c896fe29 | 1005 | { |
a7812ae4 | 1006 | tcg_gen_op3_i64(INDEX_op_shl_i64, ret, arg1, arg2); |
c896fe29 FB |
1007 | } |
1008 | ||
a7812ae4 | 1009 | static inline void tcg_gen_shli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
c896fe29 | 1010 | { |
34151a20 FB |
1011 | if (arg2 == 0) { |
1012 | tcg_gen_mov_i64(ret, arg1); | |
1013 | } else { | |
a7812ae4 | 1014 | TCGv_i64 t0 = tcg_const_i64(arg2); |
e8996ee0 | 1015 | tcg_gen_shl_i64(ret, arg1, t0); |
a7812ae4 | 1016 | tcg_temp_free_i64(t0); |
34151a20 | 1017 | } |
c896fe29 FB |
1018 | } |
1019 | ||
a7812ae4 | 1020 | static inline void tcg_gen_shr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
c896fe29 | 1021 | { |
a7812ae4 | 1022 | tcg_gen_op3_i64(INDEX_op_shr_i64, ret, arg1, arg2); |
c896fe29 FB |
1023 | } |
1024 | ||
a7812ae4 | 1025 | static inline void tcg_gen_shri_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
c896fe29 | 1026 | { |
34151a20 FB |
1027 | if (arg2 == 0) { |
1028 | tcg_gen_mov_i64(ret, arg1); | |
1029 | } else { | |
a7812ae4 | 1030 | TCGv_i64 t0 = tcg_const_i64(arg2); |
e8996ee0 | 1031 | tcg_gen_shr_i64(ret, arg1, t0); |
a7812ae4 | 1032 | tcg_temp_free_i64(t0); |
34151a20 | 1033 | } |
c896fe29 FB |
1034 | } |
1035 | ||
a7812ae4 | 1036 | static inline void tcg_gen_sar_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
c896fe29 | 1037 | { |
a7812ae4 | 1038 | tcg_gen_op3_i64(INDEX_op_sar_i64, ret, arg1, arg2); |
c896fe29 FB |
1039 | } |
1040 | ||
a7812ae4 | 1041 | static inline void tcg_gen_sari_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
c896fe29 | 1042 | { |
34151a20 FB |
1043 | if (arg2 == 0) { |
1044 | tcg_gen_mov_i64(ret, arg1); | |
1045 | } else { | |
a7812ae4 | 1046 | TCGv_i64 t0 = tcg_const_i64(arg2); |
e8996ee0 | 1047 | tcg_gen_sar_i64(ret, arg1, t0); |
a7812ae4 | 1048 | tcg_temp_free_i64(t0); |
34151a20 | 1049 | } |
c896fe29 FB |
1050 | } |
1051 | ||
a7812ae4 | 1052 | static inline void tcg_gen_brcond_i64(int cond, TCGv_i64 arg1, TCGv_i64 arg2, |
c896fe29 FB |
1053 | int label_index) |
1054 | { | |
a7812ae4 | 1055 | tcg_gen_op4ii_i64(INDEX_op_brcond_i64, arg1, arg2, cond, label_index); |
c896fe29 FB |
1056 | } |
1057 | ||
a7812ae4 | 1058 | static inline void tcg_gen_mul_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
c896fe29 | 1059 | { |
a7812ae4 | 1060 | tcg_gen_op3_i64(INDEX_op_mul_i64, ret, arg1, arg2); |
c896fe29 FB |
1061 | } |
1062 | ||
1063 | #ifdef TCG_TARGET_HAS_div_i64 | |
a7812ae4 | 1064 | static inline void tcg_gen_div_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
c896fe29 | 1065 | { |
a7812ae4 | 1066 | tcg_gen_op3_i64(INDEX_op_div_i64, ret, arg1, arg2); |
c896fe29 FB |
1067 | } |
1068 | ||
a7812ae4 | 1069 | static inline void tcg_gen_rem_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
c896fe29 | 1070 | { |
a7812ae4 | 1071 | tcg_gen_op3_i64(INDEX_op_rem_i64, ret, arg1, arg2); |
c896fe29 FB |
1072 | } |
1073 | ||
a7812ae4 | 1074 | static inline void tcg_gen_divu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
c896fe29 | 1075 | { |
a7812ae4 | 1076 | tcg_gen_op3_i64(INDEX_op_divu_i64, ret, arg1, arg2); |
c896fe29 FB |
1077 | } |
1078 | ||
a7812ae4 | 1079 | static inline void tcg_gen_remu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
c896fe29 | 1080 | { |
a7812ae4 | 1081 | tcg_gen_op3_i64(INDEX_op_remu_i64, ret, arg1, arg2); |
c896fe29 FB |
1082 | } |
1083 | #else | |
a7812ae4 | 1084 | static inline void tcg_gen_div_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
c896fe29 | 1085 | { |
a7812ae4 PB |
1086 | TCGv_i64 t0; |
1087 | t0 = tcg_temp_new_i64(); | |
c896fe29 | 1088 | tcg_gen_sari_i64(t0, arg1, 63); |
a7812ae4 PB |
1089 | tcg_gen_op5_i64(INDEX_op_div2_i64, ret, t0, arg1, t0, arg2); |
1090 | tcg_temp_free_i64(t0); | |
c896fe29 FB |
1091 | } |
1092 | ||
a7812ae4 | 1093 | static inline void tcg_gen_rem_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
c896fe29 | 1094 | { |
a7812ae4 PB |
1095 | TCGv_i64 t0; |
1096 | t0 = tcg_temp_new_i64(); | |
c896fe29 | 1097 | tcg_gen_sari_i64(t0, arg1, 63); |
a7812ae4 PB |
1098 | tcg_gen_op5_i64(INDEX_op_div2_i64, t0, ret, arg1, t0, arg2); |
1099 | tcg_temp_free_i64(t0); | |
c896fe29 FB |
1100 | } |
1101 | ||
a7812ae4 | 1102 | static inline void tcg_gen_divu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
c896fe29 | 1103 | { |
a7812ae4 PB |
1104 | TCGv_i64 t0; |
1105 | t0 = tcg_temp_new_i64(); | |
c896fe29 | 1106 | tcg_gen_movi_i64(t0, 0); |
a7812ae4 PB |
1107 | tcg_gen_op5_i64(INDEX_op_divu2_i64, ret, t0, arg1, t0, arg2); |
1108 | tcg_temp_free_i64(t0); | |
c896fe29 FB |
1109 | } |
1110 | ||
a7812ae4 | 1111 | static inline void tcg_gen_remu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
c896fe29 | 1112 | { |
a7812ae4 PB |
1113 | TCGv_i64 t0; |
1114 | t0 = tcg_temp_new_i64(); | |
c896fe29 | 1115 | tcg_gen_movi_i64(t0, 0); |
a7812ae4 PB |
1116 | tcg_gen_op5_i64(INDEX_op_divu2_i64, t0, ret, arg1, t0, arg2); |
1117 | tcg_temp_free_i64(t0); | |
c896fe29 FB |
1118 | } |
1119 | #endif | |
1120 | ||
1121 | #endif | |
1122 | ||
a7812ae4 | 1123 | static inline void tcg_gen_addi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
6359706f AJ |
1124 | { |
1125 | /* some cases can be optimized here */ | |
1126 | if (arg2 == 0) { | |
1127 | tcg_gen_mov_i64(ret, arg1); | |
1128 | } else { | |
a7812ae4 | 1129 | TCGv_i64 t0 = tcg_const_i64(arg2); |
6359706f | 1130 | tcg_gen_add_i64(ret, arg1, t0); |
a7812ae4 | 1131 | tcg_temp_free_i64(t0); |
6359706f AJ |
1132 | } |
1133 | } | |
1134 | ||
a7812ae4 | 1135 | static inline void tcg_gen_subfi_i64(TCGv_i64 ret, int64_t arg1, TCGv_i64 arg2) |
0045734a | 1136 | { |
a7812ae4 | 1137 | TCGv_i64 t0 = tcg_const_i64(arg1); |
0045734a | 1138 | tcg_gen_sub_i64(ret, t0, arg2); |
a7812ae4 | 1139 | tcg_temp_free_i64(t0); |
0045734a AJ |
1140 | } |
1141 | ||
a7812ae4 | 1142 | static inline void tcg_gen_subi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
6359706f AJ |
1143 | { |
1144 | /* some cases can be optimized here */ | |
1145 | if (arg2 == 0) { | |
1146 | tcg_gen_mov_i64(ret, arg1); | |
1147 | } else { | |
a7812ae4 | 1148 | TCGv_i64 t0 = tcg_const_i64(arg2); |
6359706f | 1149 | tcg_gen_sub_i64(ret, arg1, t0); |
a7812ae4 | 1150 | tcg_temp_free_i64(t0); |
6359706f AJ |
1151 | } |
1152 | } | |
a7812ae4 | 1153 | static inline void tcg_gen_brcondi_i64(int cond, TCGv_i64 arg1, int64_t arg2, |
f02bb954 AJ |
1154 | int label_index) |
1155 | { | |
a7812ae4 | 1156 | TCGv_i64 t0 = tcg_const_i64(arg2); |
f02bb954 | 1157 | tcg_gen_brcond_i64(cond, arg1, t0, label_index); |
a7812ae4 | 1158 | tcg_temp_free_i64(t0); |
f02bb954 AJ |
1159 | } |
1160 | ||
a7812ae4 | 1161 | static inline void tcg_gen_muli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
f02bb954 | 1162 | { |
a7812ae4 | 1163 | TCGv_i64 t0 = tcg_const_i64(arg2); |
f02bb954 | 1164 | tcg_gen_mul_i64(ret, arg1, t0); |
a7812ae4 | 1165 | tcg_temp_free_i64(t0); |
f02bb954 AJ |
1166 | } |
1167 | ||
6359706f | 1168 | |
c896fe29 FB |
1169 | /***************************************/ |
1170 | /* optional operations */ | |
1171 | ||
a7812ae4 | 1172 | static inline void tcg_gen_ext8s_i32(TCGv_i32 ret, TCGv_i32 arg) |
c896fe29 FB |
1173 | { |
1174 | #ifdef TCG_TARGET_HAS_ext8s_i32 | |
a7812ae4 | 1175 | tcg_gen_op2_i32(INDEX_op_ext8s_i32, ret, arg); |
c896fe29 FB |
1176 | #else |
1177 | tcg_gen_shli_i32(ret, arg, 24); | |
5ff9d6a4 | 1178 | tcg_gen_sari_i32(ret, ret, 24); |
c896fe29 FB |
1179 | #endif |
1180 | } | |
1181 | ||
a7812ae4 | 1182 | static inline void tcg_gen_ext16s_i32(TCGv_i32 ret, TCGv_i32 arg) |
c896fe29 FB |
1183 | { |
1184 | #ifdef TCG_TARGET_HAS_ext16s_i32 | |
a7812ae4 | 1185 | tcg_gen_op2_i32(INDEX_op_ext16s_i32, ret, arg); |
c896fe29 FB |
1186 | #else |
1187 | tcg_gen_shli_i32(ret, arg, 16); | |
5ff9d6a4 | 1188 | tcg_gen_sari_i32(ret, ret, 16); |
c896fe29 FB |
1189 | #endif |
1190 | } | |
1191 | ||
86831435 PB |
1192 | /* These are currently just for convenience. |
1193 | We assume a target will recognise these automatically . */ | |
a7812ae4 | 1194 | static inline void tcg_gen_ext8u_i32(TCGv_i32 ret, TCGv_i32 arg) |
86831435 PB |
1195 | { |
1196 | tcg_gen_andi_i32(ret, arg, 0xffu); | |
1197 | } | |
1198 | ||
a7812ae4 | 1199 | static inline void tcg_gen_ext16u_i32(TCGv_i32 ret, TCGv_i32 arg) |
86831435 PB |
1200 | { |
1201 | tcg_gen_andi_i32(ret, arg, 0xffffu); | |
1202 | } | |
1203 | ||
c896fe29 | 1204 | /* Note: we assume the two high bytes are set to zero */ |
a7812ae4 | 1205 | static inline void tcg_gen_bswap16_i32(TCGv_i32 ret, TCGv_i32 arg) |
c896fe29 FB |
1206 | { |
1207 | #ifdef TCG_TARGET_HAS_bswap16_i32 | |
a7812ae4 | 1208 | tcg_gen_op2_i32(INDEX_op_bswap16_i32, ret, arg); |
c896fe29 | 1209 | #else |
dfa1a3f1 | 1210 | TCGv_i32 t0 = tcg_temp_new_i32(); |
c896fe29 | 1211 | |
dfa1a3f1 AJ |
1212 | tcg_gen_ext8u_i32(t0, arg); |
1213 | tcg_gen_shli_i32(t0, t0, 8); | |
1214 | tcg_gen_shri_i32(ret, arg, 8); | |
1215 | tcg_gen_or_i32(ret, ret, t0); | |
a7812ae4 | 1216 | tcg_temp_free_i32(t0); |
c896fe29 FB |
1217 | #endif |
1218 | } | |
1219 | ||
66896cb8 | 1220 | static inline void tcg_gen_bswap32_i32(TCGv_i32 ret, TCGv_i32 arg) |
c896fe29 | 1221 | { |
66896cb8 AJ |
1222 | #ifdef TCG_TARGET_HAS_bswap32_i32 |
1223 | tcg_gen_op2_i32(INDEX_op_bswap32_i32, ret, arg); | |
c896fe29 | 1224 | #else |
a7812ae4 PB |
1225 | TCGv_i32 t0, t1; |
1226 | t0 = tcg_temp_new_i32(); | |
1227 | t1 = tcg_temp_new_i32(); | |
c896fe29 FB |
1228 | |
1229 | tcg_gen_shli_i32(t0, arg, 24); | |
1230 | ||
1231 | tcg_gen_andi_i32(t1, arg, 0x0000ff00); | |
1232 | tcg_gen_shli_i32(t1, t1, 8); | |
1233 | tcg_gen_or_i32(t0, t0, t1); | |
1234 | ||
1235 | tcg_gen_shri_i32(t1, arg, 8); | |
1236 | tcg_gen_andi_i32(t1, t1, 0x0000ff00); | |
1237 | tcg_gen_or_i32(t0, t0, t1); | |
1238 | ||
1239 | tcg_gen_shri_i32(t1, arg, 24); | |
1240 | tcg_gen_or_i32(ret, t0, t1); | |
a7812ae4 PB |
1241 | tcg_temp_free_i32(t0); |
1242 | tcg_temp_free_i32(t1); | |
c896fe29 FB |
1243 | #endif |
1244 | } | |
1245 | ||
1246 | #if TCG_TARGET_REG_BITS == 32 | |
a7812ae4 | 1247 | static inline void tcg_gen_ext8s_i64(TCGv_i64 ret, TCGv_i64 arg) |
c896fe29 | 1248 | { |
a7812ae4 PB |
1249 | tcg_gen_ext8s_i32(TCGV_LOW(ret), TCGV_LOW(arg)); |
1250 | tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31); | |
c896fe29 FB |
1251 | } |
1252 | ||
a7812ae4 | 1253 | static inline void tcg_gen_ext16s_i64(TCGv_i64 ret, TCGv_i64 arg) |
c896fe29 | 1254 | { |
a7812ae4 PB |
1255 | tcg_gen_ext16s_i32(TCGV_LOW(ret), TCGV_LOW(arg)); |
1256 | tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31); | |
c896fe29 FB |
1257 | } |
1258 | ||
a7812ae4 | 1259 | static inline void tcg_gen_ext32s_i64(TCGv_i64 ret, TCGv_i64 arg) |
c896fe29 | 1260 | { |
a7812ae4 PB |
1261 | tcg_gen_mov_i32(TCGV_LOW(ret), TCGV_LOW(arg)); |
1262 | tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31); | |
c896fe29 FB |
1263 | } |
1264 | ||
a7812ae4 | 1265 | static inline void tcg_gen_ext8u_i64(TCGv_i64 ret, TCGv_i64 arg) |
86831435 | 1266 | { |
a7812ae4 | 1267 | tcg_gen_ext8u_i32(TCGV_LOW(ret), TCGV_LOW(arg)); |
86831435 PB |
1268 | tcg_gen_movi_i32(TCGV_HIGH(ret), 0); |
1269 | } | |
1270 | ||
a7812ae4 | 1271 | static inline void tcg_gen_ext16u_i64(TCGv_i64 ret, TCGv_i64 arg) |
86831435 | 1272 | { |
a7812ae4 | 1273 | tcg_gen_ext16u_i32(TCGV_LOW(ret), TCGV_LOW(arg)); |
86831435 PB |
1274 | tcg_gen_movi_i32(TCGV_HIGH(ret), 0); |
1275 | } | |
1276 | ||
a7812ae4 | 1277 | static inline void tcg_gen_ext32u_i64(TCGv_i64 ret, TCGv_i64 arg) |
86831435 | 1278 | { |
a7812ae4 | 1279 | tcg_gen_mov_i32(TCGV_LOW(ret), TCGV_LOW(arg)); |
86831435 PB |
1280 | tcg_gen_movi_i32(TCGV_HIGH(ret), 0); |
1281 | } | |
1282 | ||
a7812ae4 | 1283 | static inline void tcg_gen_trunc_i64_i32(TCGv_i32 ret, TCGv_i64 arg) |
c896fe29 | 1284 | { |
a7812ae4 | 1285 | tcg_gen_mov_i32(ret, TCGV_LOW(arg)); |
c896fe29 FB |
1286 | } |
1287 | ||
a7812ae4 | 1288 | static inline void tcg_gen_extu_i32_i64(TCGv_i64 ret, TCGv_i32 arg) |
c896fe29 | 1289 | { |
a7812ae4 | 1290 | tcg_gen_mov_i32(TCGV_LOW(ret), arg); |
ac56dd48 | 1291 | tcg_gen_movi_i32(TCGV_HIGH(ret), 0); |
c896fe29 FB |
1292 | } |
1293 | ||
a7812ae4 | 1294 | static inline void tcg_gen_ext_i32_i64(TCGv_i64 ret, TCGv_i32 arg) |
c896fe29 | 1295 | { |
a7812ae4 PB |
1296 | tcg_gen_mov_i32(TCGV_LOW(ret), arg); |
1297 | tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31); | |
c896fe29 FB |
1298 | } |
1299 | ||
9a5c57fd AJ |
1300 | /* Note: we assume the six high bytes are set to zero */ |
1301 | static inline void tcg_gen_bswap16_i64(TCGv_i64 ret, TCGv_i64 arg) | |
1302 | { | |
1303 | tcg_gen_mov_i32(TCGV_HIGH(ret), TCGV_HIGH(arg)); | |
1304 | tcg_gen_bswap16_i32(TCGV_LOW(ret), TCGV_LOW(arg)); | |
1305 | } | |
1306 | ||
1307 | /* Note: we assume the four high bytes are set to zero */ | |
1308 | static inline void tcg_gen_bswap32_i64(TCGv_i64 ret, TCGv_i64 arg) | |
1309 | { | |
1310 | tcg_gen_mov_i32(TCGV_HIGH(ret), TCGV_HIGH(arg)); | |
1311 | tcg_gen_bswap32_i32(TCGV_LOW(ret), TCGV_LOW(arg)); | |
1312 | } | |
1313 | ||
66896cb8 | 1314 | static inline void tcg_gen_bswap64_i64(TCGv_i64 ret, TCGv_i64 arg) |
c896fe29 | 1315 | { |
a7812ae4 PB |
1316 | TCGv_i32 t0, t1; |
1317 | t0 = tcg_temp_new_i32(); | |
1318 | t1 = tcg_temp_new_i32(); | |
c896fe29 | 1319 | |
66896cb8 AJ |
1320 | tcg_gen_bswap32_i32(t0, TCGV_LOW(arg)); |
1321 | tcg_gen_bswap32_i32(t1, TCGV_HIGH(arg)); | |
a7812ae4 | 1322 | tcg_gen_mov_i32(TCGV_LOW(ret), t1); |
ac56dd48 | 1323 | tcg_gen_mov_i32(TCGV_HIGH(ret), t0); |
a7812ae4 PB |
1324 | tcg_temp_free_i32(t0); |
1325 | tcg_temp_free_i32(t1); | |
c896fe29 FB |
1326 | } |
1327 | #else | |
1328 | ||
a7812ae4 | 1329 | static inline void tcg_gen_ext8s_i64(TCGv_i64 ret, TCGv_i64 arg) |
c896fe29 FB |
1330 | { |
1331 | #ifdef TCG_TARGET_HAS_ext8s_i64 | |
a7812ae4 | 1332 | tcg_gen_op2_i64(INDEX_op_ext8s_i64, ret, arg); |
c896fe29 FB |
1333 | #else |
1334 | tcg_gen_shli_i64(ret, arg, 56); | |
5ff9d6a4 | 1335 | tcg_gen_sari_i64(ret, ret, 56); |
c896fe29 FB |
1336 | #endif |
1337 | } | |
1338 | ||
a7812ae4 | 1339 | static inline void tcg_gen_ext16s_i64(TCGv_i64 ret, TCGv_i64 arg) |
c896fe29 FB |
1340 | { |
1341 | #ifdef TCG_TARGET_HAS_ext16s_i64 | |
a7812ae4 | 1342 | tcg_gen_op2_i64(INDEX_op_ext16s_i64, ret, arg); |
c896fe29 FB |
1343 | #else |
1344 | tcg_gen_shli_i64(ret, arg, 48); | |
5ff9d6a4 | 1345 | tcg_gen_sari_i64(ret, ret, 48); |
c896fe29 FB |
1346 | #endif |
1347 | } | |
1348 | ||
a7812ae4 | 1349 | static inline void tcg_gen_ext32s_i64(TCGv_i64 ret, TCGv_i64 arg) |
c896fe29 FB |
1350 | { |
1351 | #ifdef TCG_TARGET_HAS_ext32s_i64 | |
a7812ae4 | 1352 | tcg_gen_op2_i64(INDEX_op_ext32s_i64, ret, arg); |
c896fe29 FB |
1353 | #else |
1354 | tcg_gen_shli_i64(ret, arg, 32); | |
5ff9d6a4 | 1355 | tcg_gen_sari_i64(ret, ret, 32); |
c896fe29 FB |
1356 | #endif |
1357 | } | |
1358 | ||
a7812ae4 | 1359 | static inline void tcg_gen_ext8u_i64(TCGv_i64 ret, TCGv_i64 arg) |
86831435 PB |
1360 | { |
1361 | tcg_gen_andi_i64(ret, arg, 0xffu); | |
1362 | } | |
1363 | ||
a7812ae4 | 1364 | static inline void tcg_gen_ext16u_i64(TCGv_i64 ret, TCGv_i64 arg) |
86831435 PB |
1365 | { |
1366 | tcg_gen_andi_i64(ret, arg, 0xffffu); | |
1367 | } | |
1368 | ||
a7812ae4 | 1369 | static inline void tcg_gen_ext32u_i64(TCGv_i64 ret, TCGv_i64 arg) |
86831435 PB |
1370 | { |
1371 | tcg_gen_andi_i64(ret, arg, 0xffffffffu); | |
1372 | } | |
1373 | ||
c896fe29 | 1374 | /* Note: we assume the target supports move between 32 and 64 bit |
ac56dd48 | 1375 | registers. This will probably break MIPS64 targets. */ |
a7812ae4 | 1376 | static inline void tcg_gen_trunc_i64_i32(TCGv_i32 ret, TCGv_i64 arg) |
c896fe29 | 1377 | { |
a7812ae4 | 1378 | tcg_gen_mov_i32(ret, MAKE_TCGV_I32(GET_TCGV_I64(arg))); |
c896fe29 FB |
1379 | } |
1380 | ||
1381 | /* Note: we assume the target supports move between 32 and 64 bit | |
1382 | registers */ | |
a7812ae4 | 1383 | static inline void tcg_gen_extu_i32_i64(TCGv_i64 ret, TCGv_i32 arg) |
c896fe29 | 1384 | { |
a7812ae4 | 1385 | tcg_gen_andi_i64(ret, MAKE_TCGV_I64(GET_TCGV_I32(arg)), 0xffffffffu); |
c896fe29 FB |
1386 | } |
1387 | ||
1388 | /* Note: we assume the target supports move between 32 and 64 bit | |
1389 | registers */ | |
a7812ae4 | 1390 | static inline void tcg_gen_ext_i32_i64(TCGv_i64 ret, TCGv_i32 arg) |
c896fe29 | 1391 | { |
a7812ae4 | 1392 | tcg_gen_ext32s_i64(ret, MAKE_TCGV_I64(GET_TCGV_I32(arg))); |
c896fe29 FB |
1393 | } |
1394 | ||
9a5c57fd AJ |
1395 | /* Note: we assume the six high bytes are set to zero */ |
1396 | static inline void tcg_gen_bswap16_i64(TCGv_i64 ret, TCGv_i64 arg) | |
1397 | { | |
1398 | #ifdef TCG_TARGET_HAS_bswap16_i64 | |
1399 | tcg_gen_op2_i64(INDEX_op_bswap16_i64, ret, arg); | |
1400 | #else | |
1401 | TCGv_i64 t0 = tcg_temp_new_i64(); | |
1402 | ||
1403 | tcg_gen_ext8u_i64(t0, arg); | |
1404 | tcg_gen_shli_i64(t0, t0, 8); | |
1405 | tcg_gen_shri_i64(ret, arg, 8); | |
1406 | tcg_gen_or_i64(ret, ret, t0); | |
1407 | tcg_temp_free_i64(t0); | |
1408 | #endif | |
1409 | } | |
1410 | ||
1411 | /* Note: we assume the four high bytes are set to zero */ | |
1412 | static inline void tcg_gen_bswap32_i64(TCGv_i64 ret, TCGv_i64 arg) | |
1413 | { | |
1414 | #ifdef TCG_TARGET_HAS_bswap32_i64 | |
1415 | tcg_gen_op2_i64(INDEX_op_bswap32_i64, ret, arg); | |
1416 | #else | |
1417 | TCGv_i64 t0, t1; | |
1418 | t0 = tcg_temp_new_i64(); | |
1419 | t1 = tcg_temp_new_i64(); | |
1420 | ||
1421 | tcg_gen_shli_i64(t0, arg, 24); | |
1422 | tcg_gen_ext32u_i64(t0, t0); | |
1423 | ||
1424 | tcg_gen_andi_i64(t1, arg, 0x0000ff00); | |
1425 | tcg_gen_shli_i64(t1, t1, 8); | |
1426 | tcg_gen_or_i64(t0, t0, t1); | |
1427 | ||
1428 | tcg_gen_shri_i64(t1, arg, 8); | |
1429 | tcg_gen_andi_i64(t1, t1, 0x0000ff00); | |
1430 | tcg_gen_or_i64(t0, t0, t1); | |
1431 | ||
1432 | tcg_gen_shri_i64(t1, arg, 24); | |
1433 | tcg_gen_or_i64(ret, t0, t1); | |
1434 | tcg_temp_free_i64(t0); | |
1435 | tcg_temp_free_i64(t1); | |
1436 | #endif | |
1437 | } | |
1438 | ||
66896cb8 | 1439 | static inline void tcg_gen_bswap64_i64(TCGv_i64 ret, TCGv_i64 arg) |
c896fe29 | 1440 | { |
66896cb8 AJ |
1441 | #ifdef TCG_TARGET_HAS_bswap64_i64 |
1442 | tcg_gen_op2_i64(INDEX_op_bswap64_i64, ret, arg); | |
c896fe29 | 1443 | #else |
a7812ae4 PB |
1444 | TCGv_i32 t0, t1; |
1445 | t0 = tcg_temp_new_i32(); | |
1446 | t1 = tcg_temp_new_i32(); | |
c896fe29 FB |
1447 | |
1448 | tcg_gen_shli_i64(t0, arg, 56); | |
1449 | ||
1450 | tcg_gen_andi_i64(t1, arg, 0x0000ff00); | |
1451 | tcg_gen_shli_i64(t1, t1, 40); | |
1452 | tcg_gen_or_i64(t0, t0, t1); | |
1453 | ||
1454 | tcg_gen_andi_i64(t1, arg, 0x00ff0000); | |
1455 | tcg_gen_shli_i64(t1, t1, 24); | |
1456 | tcg_gen_or_i64(t0, t0, t1); | |
1457 | ||
1458 | tcg_gen_andi_i64(t1, arg, 0xff000000); | |
1459 | tcg_gen_shli_i64(t1, t1, 8); | |
1460 | tcg_gen_or_i64(t0, t0, t1); | |
1461 | ||
1462 | tcg_gen_shri_i64(t1, arg, 8); | |
1463 | tcg_gen_andi_i64(t1, t1, 0xff000000); | |
1464 | tcg_gen_or_i64(t0, t0, t1); | |
1465 | ||
1466 | tcg_gen_shri_i64(t1, arg, 24); | |
1467 | tcg_gen_andi_i64(t1, t1, 0x00ff0000); | |
1468 | tcg_gen_or_i64(t0, t0, t1); | |
1469 | ||
1470 | tcg_gen_shri_i64(t1, arg, 40); | |
1471 | tcg_gen_andi_i64(t1, t1, 0x0000ff00); | |
1472 | tcg_gen_or_i64(t0, t0, t1); | |
1473 | ||
1474 | tcg_gen_shri_i64(t1, arg, 56); | |
1475 | tcg_gen_or_i64(ret, t0, t1); | |
a7812ae4 PB |
1476 | tcg_temp_free_i32(t0); |
1477 | tcg_temp_free_i32(t1); | |
c896fe29 FB |
1478 | #endif |
1479 | } | |
1480 | ||
1481 | #endif | |
1482 | ||
a7812ae4 | 1483 | static inline void tcg_gen_neg_i32(TCGv_i32 ret, TCGv_i32 arg) |
390efc54 PB |
1484 | { |
1485 | #ifdef TCG_TARGET_HAS_neg_i32 | |
a7812ae4 | 1486 | tcg_gen_op2_i32(INDEX_op_neg_i32, ret, arg); |
390efc54 | 1487 | #else |
a7812ae4 | 1488 | TCGv_i32 t0 = tcg_const_i32(0); |
e8996ee0 | 1489 | tcg_gen_sub_i32(ret, t0, arg); |
a7812ae4 | 1490 | tcg_temp_free_i32(t0); |
390efc54 PB |
1491 | #endif |
1492 | } | |
1493 | ||
a7812ae4 | 1494 | static inline void tcg_gen_neg_i64(TCGv_i64 ret, TCGv_i64 arg) |
390efc54 PB |
1495 | { |
1496 | #ifdef TCG_TARGET_HAS_neg_i64 | |
a7812ae4 | 1497 | tcg_gen_op2_i64(INDEX_op_neg_i64, ret, arg); |
390efc54 | 1498 | #else |
a7812ae4 | 1499 | TCGv_i64 t0 = tcg_const_i64(0); |
e8996ee0 | 1500 | tcg_gen_sub_i64(ret, t0, arg); |
a7812ae4 | 1501 | tcg_temp_free_i64(t0); |
390efc54 PB |
1502 | #endif |
1503 | } | |
1504 | ||
a7812ae4 | 1505 | static inline void tcg_gen_not_i32(TCGv_i32 ret, TCGv_i32 arg) |
0b6ce4cf | 1506 | { |
d2604285 AJ |
1507 | #ifdef TCG_TARGET_HAS_not_i32 |
1508 | tcg_gen_op2_i32(INDEX_op_not_i32, ret, arg); | |
1509 | #else | |
e8996ee0 | 1510 | tcg_gen_xori_i32(ret, arg, -1); |
d2604285 | 1511 | #endif |
0b6ce4cf FB |
1512 | } |
1513 | ||
a7812ae4 | 1514 | static inline void tcg_gen_not_i64(TCGv_i64 ret, TCGv_i64 arg) |
0b6ce4cf | 1515 | { |
d2604285 | 1516 | #ifdef TCG_TARGET_HAS_not_i64 |
43e860ef | 1517 | tcg_gen_op2_i64(INDEX_op_not_i64, ret, arg); |
d2604285 | 1518 | #else |
e8996ee0 | 1519 | tcg_gen_xori_i64(ret, arg, -1); |
d2604285 | 1520 | #endif |
0b6ce4cf | 1521 | } |
5ff9d6a4 | 1522 | |
a7812ae4 | 1523 | static inline void tcg_gen_discard_i32(TCGv_i32 arg) |
5ff9d6a4 | 1524 | { |
a7812ae4 | 1525 | tcg_gen_op1_i32(INDEX_op_discard, arg); |
5ff9d6a4 FB |
1526 | } |
1527 | ||
1528 | #if TCG_TARGET_REG_BITS == 32 | |
a7812ae4 | 1529 | static inline void tcg_gen_discard_i64(TCGv_i64 arg) |
5ff9d6a4 | 1530 | { |
a7812ae4 | 1531 | tcg_gen_discard_i32(TCGV_LOW(arg)); |
5ff9d6a4 FB |
1532 | tcg_gen_discard_i32(TCGV_HIGH(arg)); |
1533 | } | |
1534 | #else | |
a7812ae4 | 1535 | static inline void tcg_gen_discard_i64(TCGv_i64 arg) |
5ff9d6a4 | 1536 | { |
a7812ae4 | 1537 | tcg_gen_op1_i64(INDEX_op_discard, arg); |
5ff9d6a4 FB |
1538 | } |
1539 | #endif | |
1540 | ||
a7812ae4 | 1541 | static inline void tcg_gen_concat_i32_i64(TCGv_i64 dest, TCGv_i32 low, TCGv_i32 high) |
36aa55dc PB |
1542 | { |
1543 | #if TCG_TARGET_REG_BITS == 32 | |
a7812ae4 | 1544 | tcg_gen_mov_i32(TCGV_LOW(dest), low); |
36aa55dc PB |
1545 | tcg_gen_mov_i32(TCGV_HIGH(dest), high); |
1546 | #else | |
a7812ae4 | 1547 | TCGv_i64 tmp = tcg_temp_new_i64(); |
36aa55dc PB |
1548 | /* This extension is only needed for type correctness. |
1549 | We may be able to do better given target specific information. */ | |
1550 | tcg_gen_extu_i32_i64(tmp, high); | |
1551 | tcg_gen_shli_i64(tmp, tmp, 32); | |
1552 | tcg_gen_extu_i32_i64(dest, low); | |
1553 | tcg_gen_or_i64(dest, dest, tmp); | |
a7812ae4 | 1554 | tcg_temp_free_i64(tmp); |
36aa55dc PB |
1555 | #endif |
1556 | } | |
1557 | ||
a7812ae4 | 1558 | static inline void tcg_gen_concat32_i64(TCGv_i64 dest, TCGv_i64 low, TCGv_i64 high) |
945ca823 BS |
1559 | { |
1560 | #if TCG_TARGET_REG_BITS == 32 | |
a7812ae4 | 1561 | tcg_gen_concat_i32_i64(dest, TCGV_LOW(low), TCGV_LOW(high)); |
945ca823 | 1562 | #else |
a7812ae4 | 1563 | TCGv_i64 tmp = tcg_temp_new_i64(); |
88422e2e | 1564 | tcg_gen_ext32u_i64(dest, low); |
945ca823 | 1565 | tcg_gen_shli_i64(tmp, high, 32); |
88422e2e | 1566 | tcg_gen_or_i64(dest, dest, tmp); |
a7812ae4 | 1567 | tcg_temp_free_i64(tmp); |
945ca823 BS |
1568 | #endif |
1569 | } | |
1570 | ||
a7812ae4 | 1571 | static inline void tcg_gen_andc_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
f24cb33e | 1572 | { |
a7812ae4 PB |
1573 | TCGv_i32 t0; |
1574 | t0 = tcg_temp_new_i32(); | |
f24cb33e AJ |
1575 | tcg_gen_not_i32(t0, arg2); |
1576 | tcg_gen_and_i32(ret, arg1, t0); | |
a7812ae4 | 1577 | tcg_temp_free_i32(t0); |
f24cb33e AJ |
1578 | } |
1579 | ||
a7812ae4 | 1580 | static inline void tcg_gen_andc_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
f24cb33e | 1581 | { |
a7812ae4 PB |
1582 | TCGv_i64 t0; |
1583 | t0 = tcg_temp_new_i64(); | |
f24cb33e AJ |
1584 | tcg_gen_not_i64(t0, arg2); |
1585 | tcg_gen_and_i64(ret, arg1, t0); | |
a7812ae4 | 1586 | tcg_temp_free_i64(t0); |
f24cb33e AJ |
1587 | } |
1588 | ||
a7812ae4 | 1589 | static inline void tcg_gen_eqv_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
f24cb33e | 1590 | { |
7fc81051 AJ |
1591 | tcg_gen_xor_i32(ret, arg1, arg2); |
1592 | tcg_gen_not_i32(ret, ret); | |
f24cb33e AJ |
1593 | } |
1594 | ||
a7812ae4 | 1595 | static inline void tcg_gen_eqv_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
f24cb33e | 1596 | { |
7fc81051 AJ |
1597 | tcg_gen_xor_i64(ret, arg1, arg2); |
1598 | tcg_gen_not_i64(ret, ret); | |
f24cb33e AJ |
1599 | } |
1600 | ||
a7812ae4 | 1601 | static inline void tcg_gen_nand_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
f24cb33e | 1602 | { |
7fc81051 AJ |
1603 | tcg_gen_and_i32(ret, arg1, arg2); |
1604 | tcg_gen_not_i32(ret, ret); | |
f24cb33e AJ |
1605 | } |
1606 | ||
a7812ae4 | 1607 | static inline void tcg_gen_nand_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
f24cb33e | 1608 | { |
7fc81051 AJ |
1609 | tcg_gen_and_i64(ret, arg1, arg2); |
1610 | tcg_gen_not_i64(ret, ret); | |
f24cb33e AJ |
1611 | } |
1612 | ||
a7812ae4 | 1613 | static inline void tcg_gen_nor_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
f24cb33e | 1614 | { |
7fc81051 AJ |
1615 | tcg_gen_or_i32(ret, arg1, arg2); |
1616 | tcg_gen_not_i32(ret, ret); | |
f24cb33e AJ |
1617 | } |
1618 | ||
a7812ae4 | 1619 | static inline void tcg_gen_nor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
f24cb33e | 1620 | { |
7fc81051 AJ |
1621 | tcg_gen_or_i64(ret, arg1, arg2); |
1622 | tcg_gen_not_i64(ret, ret); | |
f24cb33e AJ |
1623 | } |
1624 | ||
a7812ae4 | 1625 | static inline void tcg_gen_orc_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
f24cb33e | 1626 | { |
a7812ae4 PB |
1627 | TCGv_i32 t0; |
1628 | t0 = tcg_temp_new_i32(); | |
f24cb33e AJ |
1629 | tcg_gen_not_i32(t0, arg2); |
1630 | tcg_gen_or_i32(ret, arg1, t0); | |
a7812ae4 | 1631 | tcg_temp_free_i32(t0); |
f24cb33e AJ |
1632 | } |
1633 | ||
a7812ae4 | 1634 | static inline void tcg_gen_orc_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
f24cb33e | 1635 | { |
a7812ae4 PB |
1636 | TCGv_i64 t0; |
1637 | t0 = tcg_temp_new_i64(); | |
f24cb33e AJ |
1638 | tcg_gen_not_i64(t0, arg2); |
1639 | tcg_gen_or_i64(ret, arg1, t0); | |
a7812ae4 | 1640 | tcg_temp_free_i64(t0); |
f24cb33e AJ |
1641 | } |
1642 | ||
a7812ae4 | 1643 | static inline void tcg_gen_rotl_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
15824571 | 1644 | { |
d42f183c AJ |
1645 | #ifdef TCG_TARGET_HAS_rot_i32 |
1646 | tcg_gen_op3_i32(INDEX_op_rotl_i32, ret, arg1, arg2); | |
1647 | #else | |
a7812ae4 | 1648 | TCGv_i32 t0, t1; |
15824571 | 1649 | |
a7812ae4 PB |
1650 | t0 = tcg_temp_new_i32(); |
1651 | t1 = tcg_temp_new_i32(); | |
15824571 AJ |
1652 | tcg_gen_shl_i32(t0, arg1, arg2); |
1653 | tcg_gen_subfi_i32(t1, 32, arg2); | |
1654 | tcg_gen_shr_i32(t1, arg1, t1); | |
1655 | tcg_gen_or_i32(ret, t0, t1); | |
a7812ae4 PB |
1656 | tcg_temp_free_i32(t0); |
1657 | tcg_temp_free_i32(t1); | |
d42f183c | 1658 | #endif |
15824571 AJ |
1659 | } |
1660 | ||
a7812ae4 | 1661 | static inline void tcg_gen_rotl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
15824571 | 1662 | { |
d42f183c AJ |
1663 | #ifdef TCG_TARGET_HAS_rot_i64 |
1664 | tcg_gen_op3_i64(INDEX_op_rotl_i64, ret, arg1, arg2); | |
1665 | #else | |
a7812ae4 | 1666 | TCGv_i64 t0, t1; |
15824571 | 1667 | |
a7812ae4 PB |
1668 | t0 = tcg_temp_new_i64(); |
1669 | t1 = tcg_temp_new_i64(); | |
15824571 AJ |
1670 | tcg_gen_shl_i64(t0, arg1, arg2); |
1671 | tcg_gen_subfi_i64(t1, 64, arg2); | |
1672 | tcg_gen_shr_i64(t1, arg1, t1); | |
1673 | tcg_gen_or_i64(ret, t0, t1); | |
a7812ae4 PB |
1674 | tcg_temp_free_i64(t0); |
1675 | tcg_temp_free_i64(t1); | |
d42f183c | 1676 | #endif |
15824571 AJ |
1677 | } |
1678 | ||
a7812ae4 | 1679 | static inline void tcg_gen_rotli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) |
15824571 AJ |
1680 | { |
1681 | /* some cases can be optimized here */ | |
1682 | if (arg2 == 0) { | |
1683 | tcg_gen_mov_i32(ret, arg1); | |
1684 | } else { | |
d42f183c AJ |
1685 | #ifdef TCG_TARGET_HAS_rot_i32 |
1686 | TCGv_i32 t0 = tcg_const_i32(arg2); | |
1687 | tcg_gen_rotl_i32(ret, arg1, t0); | |
1688 | tcg_temp_free_i32(t0); | |
1689 | #else | |
a7812ae4 PB |
1690 | TCGv_i32 t0, t1; |
1691 | t0 = tcg_temp_new_i32(); | |
1692 | t1 = tcg_temp_new_i32(); | |
15824571 AJ |
1693 | tcg_gen_shli_i32(t0, arg1, arg2); |
1694 | tcg_gen_shri_i32(t1, arg1, 32 - arg2); | |
1695 | tcg_gen_or_i32(ret, t0, t1); | |
a7812ae4 PB |
1696 | tcg_temp_free_i32(t0); |
1697 | tcg_temp_free_i32(t1); | |
d42f183c | 1698 | #endif |
15824571 AJ |
1699 | } |
1700 | } | |
1701 | ||
a7812ae4 | 1702 | static inline void tcg_gen_rotli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
15824571 AJ |
1703 | { |
1704 | /* some cases can be optimized here */ | |
1705 | if (arg2 == 0) { | |
1706 | tcg_gen_mov_i64(ret, arg1); | |
1707 | } else { | |
d42f183c AJ |
1708 | #ifdef TCG_TARGET_HAS_rot_i64 |
1709 | TCGv_i64 t0 = tcg_const_i64(arg2); | |
1710 | tcg_gen_rotl_i64(ret, arg1, t0); | |
1711 | tcg_temp_free_i64(t0); | |
1712 | #else | |
a7812ae4 PB |
1713 | TCGv_i64 t0, t1; |
1714 | t0 = tcg_temp_new_i64(); | |
1715 | t1 = tcg_temp_new_i64(); | |
15824571 AJ |
1716 | tcg_gen_shli_i64(t0, arg1, arg2); |
1717 | tcg_gen_shri_i64(t1, arg1, 64 - arg2); | |
1718 | tcg_gen_or_i64(ret, t0, t1); | |
a7812ae4 PB |
1719 | tcg_temp_free_i64(t0); |
1720 | tcg_temp_free_i64(t1); | |
d42f183c | 1721 | #endif |
15824571 AJ |
1722 | } |
1723 | } | |
1724 | ||
a7812ae4 | 1725 | static inline void tcg_gen_rotr_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
15824571 | 1726 | { |
d42f183c AJ |
1727 | #ifdef TCG_TARGET_HAS_rot_i32 |
1728 | tcg_gen_op3_i32(INDEX_op_rotr_i32, ret, arg1, arg2); | |
1729 | #else | |
a7812ae4 | 1730 | TCGv_i32 t0, t1; |
15824571 | 1731 | |
a7812ae4 PB |
1732 | t0 = tcg_temp_new_i32(); |
1733 | t1 = tcg_temp_new_i32(); | |
15824571 AJ |
1734 | tcg_gen_shr_i32(t0, arg1, arg2); |
1735 | tcg_gen_subfi_i32(t1, 32, arg2); | |
1736 | tcg_gen_shl_i32(t1, arg1, t1); | |
1737 | tcg_gen_or_i32(ret, t0, t1); | |
a7812ae4 PB |
1738 | tcg_temp_free_i32(t0); |
1739 | tcg_temp_free_i32(t1); | |
d42f183c | 1740 | #endif |
15824571 AJ |
1741 | } |
1742 | ||
a7812ae4 | 1743 | static inline void tcg_gen_rotr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
15824571 | 1744 | { |
d42f183c AJ |
1745 | #ifdef TCG_TARGET_HAS_rot_i64 |
1746 | tcg_gen_op3_i64(INDEX_op_rotr_i64, ret, arg1, arg2); | |
1747 | #else | |
a7812ae4 | 1748 | TCGv_i64 t0, t1; |
15824571 | 1749 | |
a7812ae4 PB |
1750 | t0 = tcg_temp_new_i64(); |
1751 | t1 = tcg_temp_new_i64(); | |
d9885a0b | 1752 | tcg_gen_shr_i64(t0, arg1, arg2); |
15824571 AJ |
1753 | tcg_gen_subfi_i64(t1, 64, arg2); |
1754 | tcg_gen_shl_i64(t1, arg1, t1); | |
1755 | tcg_gen_or_i64(ret, t0, t1); | |
a7812ae4 PB |
1756 | tcg_temp_free_i64(t0); |
1757 | tcg_temp_free_i64(t1); | |
d42f183c | 1758 | #endif |
15824571 AJ |
1759 | } |
1760 | ||
a7812ae4 | 1761 | static inline void tcg_gen_rotri_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) |
15824571 AJ |
1762 | { |
1763 | /* some cases can be optimized here */ | |
1764 | if (arg2 == 0) { | |
1765 | tcg_gen_mov_i32(ret, arg1); | |
1766 | } else { | |
1767 | tcg_gen_rotli_i32(ret, arg1, 32 - arg2); | |
1768 | } | |
1769 | } | |
1770 | ||
a7812ae4 | 1771 | static inline void tcg_gen_rotri_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
15824571 AJ |
1772 | { |
1773 | /* some cases can be optimized here */ | |
1774 | if (arg2 == 0) { | |
de3526b2 | 1775 | tcg_gen_mov_i64(ret, arg1); |
15824571 AJ |
1776 | } else { |
1777 | tcg_gen_rotli_i64(ret, arg1, 64 - arg2); | |
1778 | } | |
1779 | } | |
1780 | ||
c896fe29 FB |
1781 | /***************************************/ |
1782 | /* QEMU specific operations. Their type depend on the QEMU CPU | |
1783 | type. */ | |
1784 | #ifndef TARGET_LONG_BITS | |
1785 | #error must include QEMU headers | |
1786 | #endif | |
1787 | ||
a7812ae4 PB |
1788 | #if TARGET_LONG_BITS == 32 |
1789 | #define TCGv TCGv_i32 | |
1790 | #define tcg_temp_new() tcg_temp_new_i32() | |
1791 | #define tcg_global_reg_new tcg_global_reg_new_i32 | |
1792 | #define tcg_global_mem_new tcg_global_mem_new_i32 | |
df9247b2 | 1793 | #define tcg_temp_local_new() tcg_temp_local_new_i32() |
a7812ae4 PB |
1794 | #define tcg_temp_free tcg_temp_free_i32 |
1795 | #define tcg_gen_qemu_ldst_op tcg_gen_op3i_i32 | |
1796 | #define tcg_gen_qemu_ldst_op_i64 tcg_gen_qemu_ldst_op_i64_i32 | |
1797 | #define TCGV_UNUSED(x) TCGV_UNUSED_I32(x) | |
fe75bcf7 | 1798 | #define TCGV_EQUAL(a, b) TCGV_EQUAL_I32(a, b) |
a7812ae4 PB |
1799 | #else |
1800 | #define TCGv TCGv_i64 | |
1801 | #define tcg_temp_new() tcg_temp_new_i64() | |
1802 | #define tcg_global_reg_new tcg_global_reg_new_i64 | |
1803 | #define tcg_global_mem_new tcg_global_mem_new_i64 | |
df9247b2 | 1804 | #define tcg_temp_local_new() tcg_temp_local_new_i64() |
a7812ae4 PB |
1805 | #define tcg_temp_free tcg_temp_free_i64 |
1806 | #define tcg_gen_qemu_ldst_op tcg_gen_op3i_i64 | |
1807 | #define tcg_gen_qemu_ldst_op_i64 tcg_gen_qemu_ldst_op_i64_i64 | |
1808 | #define TCGV_UNUSED(x) TCGV_UNUSED_I64(x) | |
fe75bcf7 | 1809 | #define TCGV_EQUAL(a, b) TCGV_EQUAL_I64(a, b) |
a7812ae4 PB |
1810 | #endif |
1811 | ||
7e4597d7 FB |
1812 | /* debug info: write the PC of the corresponding QEMU CPU instruction */ |
1813 | static inline void tcg_gen_debug_insn_start(uint64_t pc) | |
1814 | { | |
1815 | /* XXX: must really use a 32 bit size for TCGArg in all cases */ | |
1816 | #if TARGET_LONG_BITS > TCG_TARGET_REG_BITS | |
bcb0126f PB |
1817 | tcg_gen_op2ii(INDEX_op_debug_insn_start, |
1818 | (uint32_t)(pc), (uint32_t)(pc >> 32)); | |
7e4597d7 FB |
1819 | #else |
1820 | tcg_gen_op1i(INDEX_op_debug_insn_start, pc); | |
1821 | #endif | |
1822 | } | |
1823 | ||
c896fe29 FB |
1824 | static inline void tcg_gen_exit_tb(tcg_target_long val) |
1825 | { | |
ac56dd48 | 1826 | tcg_gen_op1i(INDEX_op_exit_tb, val); |
c896fe29 FB |
1827 | } |
1828 | ||
1829 | static inline void tcg_gen_goto_tb(int idx) | |
1830 | { | |
ac56dd48 | 1831 | tcg_gen_op1i(INDEX_op_goto_tb, idx); |
c896fe29 FB |
1832 | } |
1833 | ||
1834 | #if TCG_TARGET_REG_BITS == 32 | |
ac56dd48 | 1835 | static inline void tcg_gen_qemu_ld8u(TCGv ret, TCGv addr, int mem_index) |
c896fe29 FB |
1836 | { |
1837 | #if TARGET_LONG_BITS == 32 | |
a7812ae4 | 1838 | tcg_gen_op3i_i32(INDEX_op_qemu_ld8u, ret, addr, mem_index); |
c896fe29 | 1839 | #else |
a7812ae4 PB |
1840 | tcg_gen_op4i_i32(INDEX_op_qemu_ld8u, TCGV_LOW(ret), TCGV_LOW(addr), |
1841 | TCGV_HIGH(addr), mem_index); | |
ac56dd48 | 1842 | tcg_gen_movi_i32(TCGV_HIGH(ret), 0); |
c896fe29 FB |
1843 | #endif |
1844 | } | |
1845 | ||
ac56dd48 | 1846 | static inline void tcg_gen_qemu_ld8s(TCGv ret, TCGv addr, int mem_index) |
c896fe29 FB |
1847 | { |
1848 | #if TARGET_LONG_BITS == 32 | |
a7812ae4 | 1849 | tcg_gen_op3i_i32(INDEX_op_qemu_ld8s, ret, addr, mem_index); |
c896fe29 | 1850 | #else |
a7812ae4 PB |
1851 | tcg_gen_op4i_i32(INDEX_op_qemu_ld8s, TCGV_LOW(ret), TCGV_LOW(addr), |
1852 | TCGV_HIGH(addr), mem_index); | |
1853 | tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31); | |
c896fe29 FB |
1854 | #endif |
1855 | } | |
1856 | ||
ac56dd48 | 1857 | static inline void tcg_gen_qemu_ld16u(TCGv ret, TCGv addr, int mem_index) |
c896fe29 FB |
1858 | { |
1859 | #if TARGET_LONG_BITS == 32 | |
a7812ae4 | 1860 | tcg_gen_op3i_i32(INDEX_op_qemu_ld16u, ret, addr, mem_index); |
c896fe29 | 1861 | #else |
a7812ae4 PB |
1862 | tcg_gen_op4i_i32(INDEX_op_qemu_ld16u, TCGV_LOW(ret), TCGV_LOW(addr), |
1863 | TCGV_HIGH(addr), mem_index); | |
ac56dd48 | 1864 | tcg_gen_movi_i32(TCGV_HIGH(ret), 0); |
c896fe29 FB |
1865 | #endif |
1866 | } | |
1867 | ||
ac56dd48 | 1868 | static inline void tcg_gen_qemu_ld16s(TCGv ret, TCGv addr, int mem_index) |
c896fe29 FB |
1869 | { |
1870 | #if TARGET_LONG_BITS == 32 | |
a7812ae4 | 1871 | tcg_gen_op3i_i32(INDEX_op_qemu_ld16s, ret, addr, mem_index); |
c896fe29 | 1872 | #else |
a7812ae4 PB |
1873 | tcg_gen_op4i_i32(INDEX_op_qemu_ld16s, TCGV_LOW(ret), TCGV_LOW(addr), |
1874 | TCGV_HIGH(addr), mem_index); | |
1875 | tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31); | |
c896fe29 FB |
1876 | #endif |
1877 | } | |
1878 | ||
ac56dd48 | 1879 | static inline void tcg_gen_qemu_ld32u(TCGv ret, TCGv addr, int mem_index) |
c896fe29 FB |
1880 | { |
1881 | #if TARGET_LONG_BITS == 32 | |
a7812ae4 | 1882 | tcg_gen_op3i_i32(INDEX_op_qemu_ld32u, ret, addr, mem_index); |
c896fe29 | 1883 | #else |
a7812ae4 PB |
1884 | tcg_gen_op4i_i32(INDEX_op_qemu_ld32u, TCGV_LOW(ret), TCGV_LOW(addr), |
1885 | TCGV_HIGH(addr), mem_index); | |
ac56dd48 | 1886 | tcg_gen_movi_i32(TCGV_HIGH(ret), 0); |
c896fe29 FB |
1887 | #endif |
1888 | } | |
1889 | ||
ac56dd48 | 1890 | static inline void tcg_gen_qemu_ld32s(TCGv ret, TCGv addr, int mem_index) |
c896fe29 FB |
1891 | { |
1892 | #if TARGET_LONG_BITS == 32 | |
a7812ae4 | 1893 | tcg_gen_op3i_i32(INDEX_op_qemu_ld32u, ret, addr, mem_index); |
c896fe29 | 1894 | #else |
a7812ae4 PB |
1895 | tcg_gen_op4i_i32(INDEX_op_qemu_ld32u, TCGV_LOW(ret), TCGV_LOW(addr), |
1896 | TCGV_HIGH(addr), mem_index); | |
1897 | tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31); | |
c896fe29 FB |
1898 | #endif |
1899 | } | |
1900 | ||
a7812ae4 | 1901 | static inline void tcg_gen_qemu_ld64(TCGv_i64 ret, TCGv addr, int mem_index) |
c896fe29 FB |
1902 | { |
1903 | #if TARGET_LONG_BITS == 32 | |
a7812ae4 | 1904 | tcg_gen_op4i_i32(INDEX_op_qemu_ld64, TCGV_LOW(ret), TCGV_HIGH(ret), addr, mem_index); |
c896fe29 | 1905 | #else |
a7812ae4 PB |
1906 | tcg_gen_op5i_i32(INDEX_op_qemu_ld64, TCGV_LOW(ret), TCGV_HIGH(ret), |
1907 | TCGV_LOW(addr), TCGV_HIGH(addr), mem_index); | |
c896fe29 FB |
1908 | #endif |
1909 | } | |
1910 | ||
ac56dd48 | 1911 | static inline void tcg_gen_qemu_st8(TCGv arg, TCGv addr, int mem_index) |
c896fe29 FB |
1912 | { |
1913 | #if TARGET_LONG_BITS == 32 | |
a7812ae4 | 1914 | tcg_gen_op3i_i32(INDEX_op_qemu_st8, arg, addr, mem_index); |
c896fe29 | 1915 | #else |
a7812ae4 PB |
1916 | tcg_gen_op4i_i32(INDEX_op_qemu_st8, TCGV_LOW(arg), TCGV_LOW(addr), |
1917 | TCGV_HIGH(addr), mem_index); | |
c896fe29 FB |
1918 | #endif |
1919 | } | |
1920 | ||
ac56dd48 | 1921 | static inline void tcg_gen_qemu_st16(TCGv arg, TCGv addr, int mem_index) |
c896fe29 FB |
1922 | { |
1923 | #if TARGET_LONG_BITS == 32 | |
a7812ae4 | 1924 | tcg_gen_op3i_i32(INDEX_op_qemu_st16, arg, addr, mem_index); |
c896fe29 | 1925 | #else |
a7812ae4 PB |
1926 | tcg_gen_op4i_i32(INDEX_op_qemu_st16, TCGV_LOW(arg), TCGV_LOW(addr), |
1927 | TCGV_HIGH(addr), mem_index); | |
c896fe29 FB |
1928 | #endif |
1929 | } | |
1930 | ||
ac56dd48 | 1931 | static inline void tcg_gen_qemu_st32(TCGv arg, TCGv addr, int mem_index) |
c896fe29 FB |
1932 | { |
1933 | #if TARGET_LONG_BITS == 32 | |
a7812ae4 | 1934 | tcg_gen_op3i_i32(INDEX_op_qemu_st32, arg, addr, mem_index); |
c896fe29 | 1935 | #else |
a7812ae4 PB |
1936 | tcg_gen_op4i_i32(INDEX_op_qemu_st32, TCGV_LOW(arg), TCGV_LOW(addr), |
1937 | TCGV_HIGH(addr), mem_index); | |
c896fe29 FB |
1938 | #endif |
1939 | } | |
1940 | ||
a7812ae4 | 1941 | static inline void tcg_gen_qemu_st64(TCGv_i64 arg, TCGv addr, int mem_index) |
c896fe29 FB |
1942 | { |
1943 | #if TARGET_LONG_BITS == 32 | |
a7812ae4 PB |
1944 | tcg_gen_op4i_i32(INDEX_op_qemu_st64, TCGV_LOW(arg), TCGV_HIGH(arg), addr, |
1945 | mem_index); | |
c896fe29 | 1946 | #else |
a7812ae4 PB |
1947 | tcg_gen_op5i_i32(INDEX_op_qemu_st64, TCGV_LOW(arg), TCGV_HIGH(arg), |
1948 | TCGV_LOW(addr), TCGV_HIGH(addr), mem_index); | |
c896fe29 FB |
1949 | #endif |
1950 | } | |
1951 | ||
56b8f567 | 1952 | #define tcg_gen_ld_ptr tcg_gen_ld_i32 |
a768e4b2 | 1953 | #define tcg_gen_discard_ptr tcg_gen_discard_i32 |
f8422f52 | 1954 | |
c896fe29 FB |
1955 | #else /* TCG_TARGET_REG_BITS == 32 */ |
1956 | ||
ac56dd48 | 1957 | static inline void tcg_gen_qemu_ld8u(TCGv ret, TCGv addr, int mem_index) |
c896fe29 | 1958 | { |
a7812ae4 | 1959 | tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld8u, ret, addr, mem_index); |
c896fe29 FB |
1960 | } |
1961 | ||
ac56dd48 | 1962 | static inline void tcg_gen_qemu_ld8s(TCGv ret, TCGv addr, int mem_index) |
c896fe29 | 1963 | { |
a7812ae4 | 1964 | tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld8s, ret, addr, mem_index); |
c896fe29 FB |
1965 | } |
1966 | ||
ac56dd48 | 1967 | static inline void tcg_gen_qemu_ld16u(TCGv ret, TCGv addr, int mem_index) |
c896fe29 | 1968 | { |
a7812ae4 | 1969 | tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld16u, ret, addr, mem_index); |
c896fe29 FB |
1970 | } |
1971 | ||
ac56dd48 | 1972 | static inline void tcg_gen_qemu_ld16s(TCGv ret, TCGv addr, int mem_index) |
c896fe29 | 1973 | { |
a7812ae4 | 1974 | tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld16s, ret, addr, mem_index); |
c896fe29 FB |
1975 | } |
1976 | ||
ac56dd48 | 1977 | static inline void tcg_gen_qemu_ld32u(TCGv ret, TCGv addr, int mem_index) |
c896fe29 | 1978 | { |
a7812ae4 | 1979 | tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld32u, ret, addr, mem_index); |
c896fe29 FB |
1980 | } |
1981 | ||
ac56dd48 | 1982 | static inline void tcg_gen_qemu_ld32s(TCGv ret, TCGv addr, int mem_index) |
c896fe29 | 1983 | { |
a7812ae4 | 1984 | tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld32s, ret, addr, mem_index); |
c896fe29 FB |
1985 | } |
1986 | ||
a7812ae4 | 1987 | static inline void tcg_gen_qemu_ld64(TCGv_i64 ret, TCGv addr, int mem_index) |
c896fe29 | 1988 | { |
a7812ae4 | 1989 | tcg_gen_qemu_ldst_op_i64(INDEX_op_qemu_ld64, ret, addr, mem_index); |
c896fe29 FB |
1990 | } |
1991 | ||
ac56dd48 | 1992 | static inline void tcg_gen_qemu_st8(TCGv arg, TCGv addr, int mem_index) |
c896fe29 | 1993 | { |
a7812ae4 | 1994 | tcg_gen_qemu_ldst_op(INDEX_op_qemu_st8, arg, addr, mem_index); |
c896fe29 FB |
1995 | } |
1996 | ||
ac56dd48 | 1997 | static inline void tcg_gen_qemu_st16(TCGv arg, TCGv addr, int mem_index) |
c896fe29 | 1998 | { |
a7812ae4 | 1999 | tcg_gen_qemu_ldst_op(INDEX_op_qemu_st16, arg, addr, mem_index); |
c896fe29 FB |
2000 | } |
2001 | ||
ac56dd48 | 2002 | static inline void tcg_gen_qemu_st32(TCGv arg, TCGv addr, int mem_index) |
c896fe29 | 2003 | { |
a7812ae4 | 2004 | tcg_gen_qemu_ldst_op(INDEX_op_qemu_st32, arg, addr, mem_index); |
c896fe29 FB |
2005 | } |
2006 | ||
a7812ae4 | 2007 | static inline void tcg_gen_qemu_st64(TCGv_i64 arg, TCGv addr, int mem_index) |
c896fe29 | 2008 | { |
a7812ae4 | 2009 | tcg_gen_qemu_ldst_op_i64(INDEX_op_qemu_st64, arg, addr, mem_index); |
c896fe29 FB |
2010 | } |
2011 | ||
56b8f567 | 2012 | #define tcg_gen_ld_ptr tcg_gen_ld_i64 |
a768e4b2 | 2013 | #define tcg_gen_discard_ptr tcg_gen_discard_i64 |
f8422f52 | 2014 | |
c896fe29 | 2015 | #endif /* TCG_TARGET_REG_BITS != 32 */ |
f8422f52 BS |
2016 | |
2017 | #if TARGET_LONG_BITS == 64 | |
2018 | #define TCG_TYPE_TL TCG_TYPE_I64 | |
2019 | #define tcg_gen_movi_tl tcg_gen_movi_i64 | |
2020 | #define tcg_gen_mov_tl tcg_gen_mov_i64 | |
2021 | #define tcg_gen_ld8u_tl tcg_gen_ld8u_i64 | |
2022 | #define tcg_gen_ld8s_tl tcg_gen_ld8s_i64 | |
2023 | #define tcg_gen_ld16u_tl tcg_gen_ld16u_i64 | |
2024 | #define tcg_gen_ld16s_tl tcg_gen_ld16s_i64 | |
2025 | #define tcg_gen_ld32u_tl tcg_gen_ld32u_i64 | |
2026 | #define tcg_gen_ld32s_tl tcg_gen_ld32s_i64 | |
2027 | #define tcg_gen_ld_tl tcg_gen_ld_i64 | |
2028 | #define tcg_gen_st8_tl tcg_gen_st8_i64 | |
2029 | #define tcg_gen_st16_tl tcg_gen_st16_i64 | |
2030 | #define tcg_gen_st32_tl tcg_gen_st32_i64 | |
2031 | #define tcg_gen_st_tl tcg_gen_st_i64 | |
2032 | #define tcg_gen_add_tl tcg_gen_add_i64 | |
2033 | #define tcg_gen_addi_tl tcg_gen_addi_i64 | |
2034 | #define tcg_gen_sub_tl tcg_gen_sub_i64 | |
390efc54 | 2035 | #define tcg_gen_neg_tl tcg_gen_neg_i64 |
10460c8a | 2036 | #define tcg_gen_subfi_tl tcg_gen_subfi_i64 |
f8422f52 BS |
2037 | #define tcg_gen_subi_tl tcg_gen_subi_i64 |
2038 | #define tcg_gen_and_tl tcg_gen_and_i64 | |
2039 | #define tcg_gen_andi_tl tcg_gen_andi_i64 | |
2040 | #define tcg_gen_or_tl tcg_gen_or_i64 | |
2041 | #define tcg_gen_ori_tl tcg_gen_ori_i64 | |
2042 | #define tcg_gen_xor_tl tcg_gen_xor_i64 | |
2043 | #define tcg_gen_xori_tl tcg_gen_xori_i64 | |
0b6ce4cf | 2044 | #define tcg_gen_not_tl tcg_gen_not_i64 |
f8422f52 BS |
2045 | #define tcg_gen_shl_tl tcg_gen_shl_i64 |
2046 | #define tcg_gen_shli_tl tcg_gen_shli_i64 | |
2047 | #define tcg_gen_shr_tl tcg_gen_shr_i64 | |
2048 | #define tcg_gen_shri_tl tcg_gen_shri_i64 | |
2049 | #define tcg_gen_sar_tl tcg_gen_sar_i64 | |
2050 | #define tcg_gen_sari_tl tcg_gen_sari_i64 | |
0cf767d6 | 2051 | #define tcg_gen_brcond_tl tcg_gen_brcond_i64 |
cb63669a | 2052 | #define tcg_gen_brcondi_tl tcg_gen_brcondi_i64 |
f730fd27 TS |
2053 | #define tcg_gen_mul_tl tcg_gen_mul_i64 |
2054 | #define tcg_gen_muli_tl tcg_gen_muli_i64 | |
ab36421e AJ |
2055 | #define tcg_gen_div_tl tcg_gen_div_i64 |
2056 | #define tcg_gen_rem_tl tcg_gen_rem_i64 | |
864951af AJ |
2057 | #define tcg_gen_divu_tl tcg_gen_divu_i64 |
2058 | #define tcg_gen_remu_tl tcg_gen_remu_i64 | |
a768e4b2 | 2059 | #define tcg_gen_discard_tl tcg_gen_discard_i64 |
e429073d BS |
2060 | #define tcg_gen_trunc_tl_i32 tcg_gen_trunc_i64_i32 |
2061 | #define tcg_gen_trunc_i64_tl tcg_gen_mov_i64 | |
2062 | #define tcg_gen_extu_i32_tl tcg_gen_extu_i32_i64 | |
2063 | #define tcg_gen_ext_i32_tl tcg_gen_ext_i32_i64 | |
2064 | #define tcg_gen_extu_tl_i64 tcg_gen_mov_i64 | |
2065 | #define tcg_gen_ext_tl_i64 tcg_gen_mov_i64 | |
0b6ce4cf FB |
2066 | #define tcg_gen_ext8u_tl tcg_gen_ext8u_i64 |
2067 | #define tcg_gen_ext8s_tl tcg_gen_ext8s_i64 | |
2068 | #define tcg_gen_ext16u_tl tcg_gen_ext16u_i64 | |
2069 | #define tcg_gen_ext16s_tl tcg_gen_ext16s_i64 | |
2070 | #define tcg_gen_ext32u_tl tcg_gen_ext32u_i64 | |
2071 | #define tcg_gen_ext32s_tl tcg_gen_ext32s_i64 | |
911d79ba AJ |
2072 | #define tcg_gen_bswap16_tl tcg_gen_bswap16_i64 |
2073 | #define tcg_gen_bswap32_tl tcg_gen_bswap32_i64 | |
2074 | #define tcg_gen_bswap64_tl tcg_gen_bswap64_i64 | |
945ca823 | 2075 | #define tcg_gen_concat_tl_i64 tcg_gen_concat32_i64 |
f24cb33e AJ |
2076 | #define tcg_gen_andc_tl tcg_gen_andc_i64 |
2077 | #define tcg_gen_eqv_tl tcg_gen_eqv_i64 | |
2078 | #define tcg_gen_nand_tl tcg_gen_nand_i64 | |
2079 | #define tcg_gen_nor_tl tcg_gen_nor_i64 | |
2080 | #define tcg_gen_orc_tl tcg_gen_orc_i64 | |
15824571 AJ |
2081 | #define tcg_gen_rotl_tl tcg_gen_rotl_i64 |
2082 | #define tcg_gen_rotli_tl tcg_gen_rotli_i64 | |
2083 | #define tcg_gen_rotr_tl tcg_gen_rotr_i64 | |
2084 | #define tcg_gen_rotri_tl tcg_gen_rotri_i64 | |
a98824ac | 2085 | #define tcg_const_tl tcg_const_i64 |
bdffd4a9 | 2086 | #define tcg_const_local_tl tcg_const_local_i64 |
f8422f52 BS |
2087 | #else |
2088 | #define TCG_TYPE_TL TCG_TYPE_I32 | |
2089 | #define tcg_gen_movi_tl tcg_gen_movi_i32 | |
2090 | #define tcg_gen_mov_tl tcg_gen_mov_i32 | |
2091 | #define tcg_gen_ld8u_tl tcg_gen_ld8u_i32 | |
2092 | #define tcg_gen_ld8s_tl tcg_gen_ld8s_i32 | |
2093 | #define tcg_gen_ld16u_tl tcg_gen_ld16u_i32 | |
2094 | #define tcg_gen_ld16s_tl tcg_gen_ld16s_i32 | |
2095 | #define tcg_gen_ld32u_tl tcg_gen_ld_i32 | |
2096 | #define tcg_gen_ld32s_tl tcg_gen_ld_i32 | |
2097 | #define tcg_gen_ld_tl tcg_gen_ld_i32 | |
2098 | #define tcg_gen_st8_tl tcg_gen_st8_i32 | |
2099 | #define tcg_gen_st16_tl tcg_gen_st16_i32 | |
2100 | #define tcg_gen_st32_tl tcg_gen_st_i32 | |
2101 | #define tcg_gen_st_tl tcg_gen_st_i32 | |
2102 | #define tcg_gen_add_tl tcg_gen_add_i32 | |
2103 | #define tcg_gen_addi_tl tcg_gen_addi_i32 | |
2104 | #define tcg_gen_sub_tl tcg_gen_sub_i32 | |
390efc54 | 2105 | #define tcg_gen_neg_tl tcg_gen_neg_i32 |
0045734a | 2106 | #define tcg_gen_subfi_tl tcg_gen_subfi_i32 |
f8422f52 BS |
2107 | #define tcg_gen_subi_tl tcg_gen_subi_i32 |
2108 | #define tcg_gen_and_tl tcg_gen_and_i32 | |
2109 | #define tcg_gen_andi_tl tcg_gen_andi_i32 | |
2110 | #define tcg_gen_or_tl tcg_gen_or_i32 | |
2111 | #define tcg_gen_ori_tl tcg_gen_ori_i32 | |
2112 | #define tcg_gen_xor_tl tcg_gen_xor_i32 | |
2113 | #define tcg_gen_xori_tl tcg_gen_xori_i32 | |
0b6ce4cf | 2114 | #define tcg_gen_not_tl tcg_gen_not_i32 |
f8422f52 BS |
2115 | #define tcg_gen_shl_tl tcg_gen_shl_i32 |
2116 | #define tcg_gen_shli_tl tcg_gen_shli_i32 | |
2117 | #define tcg_gen_shr_tl tcg_gen_shr_i32 | |
2118 | #define tcg_gen_shri_tl tcg_gen_shri_i32 | |
2119 | #define tcg_gen_sar_tl tcg_gen_sar_i32 | |
2120 | #define tcg_gen_sari_tl tcg_gen_sari_i32 | |
0cf767d6 | 2121 | #define tcg_gen_brcond_tl tcg_gen_brcond_i32 |
cb63669a | 2122 | #define tcg_gen_brcondi_tl tcg_gen_brcondi_i32 |
f730fd27 TS |
2123 | #define tcg_gen_mul_tl tcg_gen_mul_i32 |
2124 | #define tcg_gen_muli_tl tcg_gen_muli_i32 | |
ab36421e AJ |
2125 | #define tcg_gen_div_tl tcg_gen_div_i32 |
2126 | #define tcg_gen_rem_tl tcg_gen_rem_i32 | |
864951af AJ |
2127 | #define tcg_gen_divu_tl tcg_gen_divu_i32 |
2128 | #define tcg_gen_remu_tl tcg_gen_remu_i32 | |
a768e4b2 | 2129 | #define tcg_gen_discard_tl tcg_gen_discard_i32 |
e429073d BS |
2130 | #define tcg_gen_trunc_tl_i32 tcg_gen_mov_i32 |
2131 | #define tcg_gen_trunc_i64_tl tcg_gen_trunc_i64_i32 | |
2132 | #define tcg_gen_extu_i32_tl tcg_gen_mov_i32 | |
2133 | #define tcg_gen_ext_i32_tl tcg_gen_mov_i32 | |
2134 | #define tcg_gen_extu_tl_i64 tcg_gen_extu_i32_i64 | |
2135 | #define tcg_gen_ext_tl_i64 tcg_gen_ext_i32_i64 | |
0b6ce4cf FB |
2136 | #define tcg_gen_ext8u_tl tcg_gen_ext8u_i32 |
2137 | #define tcg_gen_ext8s_tl tcg_gen_ext8s_i32 | |
2138 | #define tcg_gen_ext16u_tl tcg_gen_ext16u_i32 | |
2139 | #define tcg_gen_ext16s_tl tcg_gen_ext16s_i32 | |
2140 | #define tcg_gen_ext32u_tl tcg_gen_mov_i32 | |
2141 | #define tcg_gen_ext32s_tl tcg_gen_mov_i32 | |
911d79ba AJ |
2142 | #define tcg_gen_bswap16_tl tcg_gen_bswap16_i32 |
2143 | #define tcg_gen_bswap32_tl tcg_gen_bswap32_i32 | |
945ca823 | 2144 | #define tcg_gen_concat_tl_i64 tcg_gen_concat_i32_i64 |
f24cb33e AJ |
2145 | #define tcg_gen_andc_tl tcg_gen_andc_i32 |
2146 | #define tcg_gen_eqv_tl tcg_gen_eqv_i32 | |
2147 | #define tcg_gen_nand_tl tcg_gen_nand_i32 | |
2148 | #define tcg_gen_nor_tl tcg_gen_nor_i32 | |
2149 | #define tcg_gen_orc_tl tcg_gen_orc_i32 | |
15824571 AJ |
2150 | #define tcg_gen_rotl_tl tcg_gen_rotl_i32 |
2151 | #define tcg_gen_rotli_tl tcg_gen_rotli_i32 | |
2152 | #define tcg_gen_rotr_tl tcg_gen_rotr_i32 | |
2153 | #define tcg_gen_rotri_tl tcg_gen_rotri_i32 | |
a98824ac | 2154 | #define tcg_const_tl tcg_const_i32 |
bdffd4a9 | 2155 | #define tcg_const_local_tl tcg_const_local_i32 |
f8422f52 | 2156 | #endif |
6ddbc6e4 PB |
2157 | |
2158 | #if TCG_TARGET_REG_BITS == 32 | |
48d38ca5 | 2159 | #define tcg_gen_add_ptr tcg_gen_add_i32 |
6ddbc6e4 | 2160 | #define tcg_gen_addi_ptr tcg_gen_addi_i32 |
48d38ca5 | 2161 | #define tcg_gen_ext_i32_ptr tcg_gen_mov_i32 |
6ddbc6e4 | 2162 | #else /* TCG_TARGET_REG_BITS == 32 */ |
48d38ca5 | 2163 | #define tcg_gen_add_ptr tcg_gen_add_i64 |
6ddbc6e4 | 2164 | #define tcg_gen_addi_ptr tcg_gen_addi_i64 |
48d38ca5 | 2165 | #define tcg_gen_ext_i32_ptr tcg_gen_ext_i32_i64 |
6ddbc6e4 | 2166 | #endif /* TCG_TARGET_REG_BITS != 32 */ |