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c896fe29 FB |
1 | /* |
2 | * Tiny Code Generator for QEMU | |
3 | * | |
4 | * Copyright (c) 2008 Fabrice Bellard | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
c61aaf7a AJ |
24 | |
25 | /* | |
26 | * DEF(name, oargs, iargs, cargs, flags) | |
27 | */ | |
c896fe29 FB |
28 | |
29 | /* predefined ops */ | |
c61aaf7a AJ |
30 | DEF(end, 0, 0, 0, 0) /* must be kept first */ |
31 | DEF(nop, 0, 0, 0, 0) | |
32 | DEF(nop1, 0, 0, 1, 0) | |
33 | DEF(nop2, 0, 0, 2, 0) | |
34 | DEF(nop3, 0, 0, 3, 0) | |
35 | DEF(nopn, 0, 0, 1, 0) /* variable number of parameters */ | |
c896fe29 | 36 | |
c61aaf7a | 37 | DEF(discard, 1, 0, 0, 0) |
5ff9d6a4 | 38 | |
c61aaf7a AJ |
39 | DEF(set_label, 0, 0, 1, 0) |
40 | DEF(call, 0, 1, 2, TCG_OPF_SIDE_EFFECTS) /* variable number of parameters */ | |
41 | DEF(jmp, 0, 1, 0, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS) | |
42 | DEF(br, 0, 0, 1, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS) | |
c896fe29 | 43 | |
c61aaf7a AJ |
44 | DEF(mov_i32, 1, 1, 0, 0) |
45 | DEF(movi_i32, 1, 0, 1, 0) | |
46 | DEF(setcond_i32, 1, 2, 1, 0) | |
c896fe29 | 47 | /* load/store */ |
c61aaf7a AJ |
48 | DEF(ld8u_i32, 1, 1, 1, 0) |
49 | DEF(ld8s_i32, 1, 1, 1, 0) | |
50 | DEF(ld16u_i32, 1, 1, 1, 0) | |
51 | DEF(ld16s_i32, 1, 1, 1, 0) | |
52 | DEF(ld_i32, 1, 1, 1, 0) | |
53 | DEF(st8_i32, 0, 2, 1, TCG_OPF_SIDE_EFFECTS) | |
54 | DEF(st16_i32, 0, 2, 1, TCG_OPF_SIDE_EFFECTS) | |
55 | DEF(st_i32, 0, 2, 1, TCG_OPF_SIDE_EFFECTS) | |
c896fe29 | 56 | /* arith */ |
c61aaf7a AJ |
57 | DEF(add_i32, 1, 2, 0, 0) |
58 | DEF(sub_i32, 1, 2, 0, 0) | |
59 | DEF(mul_i32, 1, 2, 0, 0) | |
c896fe29 | 60 | #ifdef TCG_TARGET_HAS_div_i32 |
c61aaf7a AJ |
61 | DEF(div_i32, 1, 2, 0, 0) |
62 | DEF(divu_i32, 1, 2, 0, 0) | |
63 | DEF(rem_i32, 1, 2, 0, 0) | |
64 | DEF(remu_i32, 1, 2, 0, 0) | |
30138f28 AJ |
65 | #endif |
66 | #ifdef TCG_TARGET_HAS_div2_i32 | |
c61aaf7a AJ |
67 | DEF(div2_i32, 2, 3, 0, 0) |
68 | DEF(divu2_i32, 2, 3, 0, 0) | |
c896fe29 | 69 | #endif |
c61aaf7a AJ |
70 | DEF(and_i32, 1, 2, 0, 0) |
71 | DEF(or_i32, 1, 2, 0, 0) | |
72 | DEF(xor_i32, 1, 2, 0, 0) | |
d42f183c | 73 | /* shifts/rotates */ |
c61aaf7a AJ |
74 | DEF(shl_i32, 1, 2, 0, 0) |
75 | DEF(shr_i32, 1, 2, 0, 0) | |
76 | DEF(sar_i32, 1, 2, 0, 0) | |
f31e9370 | 77 | #ifdef TCG_TARGET_HAS_rot_i32 |
c61aaf7a AJ |
78 | DEF(rotl_i32, 1, 2, 0, 0) |
79 | DEF(rotr_i32, 1, 2, 0, 0) | |
f31e9370 | 80 | #endif |
c896fe29 | 81 | |
c61aaf7a | 82 | DEF(brcond_i32, 0, 2, 2, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS) |
c896fe29 | 83 | #if TCG_TARGET_REG_BITS == 32 |
c61aaf7a AJ |
84 | DEF(add2_i32, 2, 4, 0, 0) |
85 | DEF(sub2_i32, 2, 4, 0, 0) | |
86 | DEF(brcond2_i32, 0, 4, 2, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS) | |
87 | DEF(mulu2_i32, 2, 2, 0, 0) | |
88 | DEF(setcond2_i32, 1, 4, 1, 0) | |
c896fe29 FB |
89 | #endif |
90 | #ifdef TCG_TARGET_HAS_ext8s_i32 | |
c61aaf7a | 91 | DEF(ext8s_i32, 1, 1, 0, 0) |
c896fe29 FB |
92 | #endif |
93 | #ifdef TCG_TARGET_HAS_ext16s_i32 | |
c61aaf7a | 94 | DEF(ext16s_i32, 1, 1, 0, 0) |
c896fe29 | 95 | #endif |
cfc86988 | 96 | #ifdef TCG_TARGET_HAS_ext8u_i32 |
c61aaf7a | 97 | DEF(ext8u_i32, 1, 1, 0, 0) |
cfc86988 AJ |
98 | #endif |
99 | #ifdef TCG_TARGET_HAS_ext16u_i32 | |
c61aaf7a | 100 | DEF(ext16u_i32, 1, 1, 0, 0) |
cfc86988 | 101 | #endif |
84aafb06 | 102 | #ifdef TCG_TARGET_HAS_bswap16_i32 |
c61aaf7a | 103 | DEF(bswap16_i32, 1, 1, 0, 0) |
84aafb06 | 104 | #endif |
66896cb8 | 105 | #ifdef TCG_TARGET_HAS_bswap32_i32 |
c61aaf7a | 106 | DEF(bswap32_i32, 1, 1, 0, 0) |
c896fe29 | 107 | #endif |
0dd0dd55 | 108 | #ifdef TCG_TARGET_HAS_not_i32 |
c61aaf7a | 109 | DEF(not_i32, 1, 1, 0, 0) |
0dd0dd55 AJ |
110 | #endif |
111 | #ifdef TCG_TARGET_HAS_neg_i32 | |
c61aaf7a | 112 | DEF(neg_i32, 1, 1, 0, 0) |
0dd0dd55 | 113 | #endif |
241cbed4 | 114 | #ifdef TCG_TARGET_HAS_andc_i32 |
c61aaf7a | 115 | DEF(andc_i32, 1, 2, 0, 0) |
241cbed4 | 116 | #endif |
791d1262 | 117 | #ifdef TCG_TARGET_HAS_orc_i32 |
c61aaf7a | 118 | DEF(orc_i32, 1, 2, 0, 0) |
791d1262 | 119 | #endif |
8d625cf1 | 120 | #ifdef TCG_TARGET_HAS_eqv_i32 |
c61aaf7a | 121 | DEF(eqv_i32, 1, 2, 0, 0) |
8d625cf1 | 122 | #endif |
9940a96b | 123 | #ifdef TCG_TARGET_HAS_nand_i32 |
c61aaf7a | 124 | DEF(nand_i32, 1, 2, 0, 0) |
9940a96b | 125 | #endif |
32d98fbd | 126 | #ifdef TCG_TARGET_HAS_nor_i32 |
c61aaf7a | 127 | DEF(nor_i32, 1, 2, 0, 0) |
32d98fbd | 128 | #endif |
c896fe29 FB |
129 | |
130 | #if TCG_TARGET_REG_BITS == 64 | |
c61aaf7a AJ |
131 | DEF(mov_i64, 1, 1, 0, 0) |
132 | DEF(movi_i64, 1, 0, 1, 0) | |
133 | DEF(setcond_i64, 1, 2, 1, 0) | |
c896fe29 | 134 | /* load/store */ |
c61aaf7a AJ |
135 | DEF(ld8u_i64, 1, 1, 1, 0) |
136 | DEF(ld8s_i64, 1, 1, 1, 0) | |
137 | DEF(ld16u_i64, 1, 1, 1, 0) | |
138 | DEF(ld16s_i64, 1, 1, 1, 0) | |
139 | DEF(ld32u_i64, 1, 1, 1, 0) | |
140 | DEF(ld32s_i64, 1, 1, 1, 0) | |
141 | DEF(ld_i64, 1, 1, 1, 0) | |
142 | DEF(st8_i64, 0, 2, 1, TCG_OPF_SIDE_EFFECTS) | |
143 | DEF(st16_i64, 0, 2, 1, TCG_OPF_SIDE_EFFECTS) | |
144 | DEF(st32_i64, 0, 2, 1, TCG_OPF_SIDE_EFFECTS) | |
145 | DEF(st_i64, 0, 2, 1, TCG_OPF_SIDE_EFFECTS) | |
c896fe29 | 146 | /* arith */ |
c61aaf7a AJ |
147 | DEF(add_i64, 1, 2, 0, 0) |
148 | DEF(sub_i64, 1, 2, 0, 0) | |
149 | DEF(mul_i64, 1, 2, 0, 0) | |
c896fe29 | 150 | #ifdef TCG_TARGET_HAS_div_i64 |
c61aaf7a AJ |
151 | DEF(div_i64, 1, 2, 0, 0) |
152 | DEF(divu_i64, 1, 2, 0, 0) | |
153 | DEF(rem_i64, 1, 2, 0, 0) | |
154 | DEF(remu_i64, 1, 2, 0, 0) | |
30138f28 AJ |
155 | #endif |
156 | #ifdef TCG_TARGET_HAS_div2_i64 | |
c61aaf7a AJ |
157 | DEF(div2_i64, 2, 3, 0, 0) |
158 | DEF(divu2_i64, 2, 3, 0, 0) | |
c896fe29 | 159 | #endif |
c61aaf7a AJ |
160 | DEF(and_i64, 1, 2, 0, 0) |
161 | DEF(or_i64, 1, 2, 0, 0) | |
162 | DEF(xor_i64, 1, 2, 0, 0) | |
d42f183c | 163 | /* shifts/rotates */ |
c61aaf7a AJ |
164 | DEF(shl_i64, 1, 2, 0, 0) |
165 | DEF(shr_i64, 1, 2, 0, 0) | |
166 | DEF(sar_i64, 1, 2, 0, 0) | |
f31e9370 | 167 | #ifdef TCG_TARGET_HAS_rot_i64 |
c61aaf7a AJ |
168 | DEF(rotl_i64, 1, 2, 0, 0) |
169 | DEF(rotr_i64, 1, 2, 0, 0) | |
f31e9370 | 170 | #endif |
c896fe29 | 171 | |
c61aaf7a | 172 | DEF(brcond_i64, 0, 2, 2, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS) |
c896fe29 | 173 | #ifdef TCG_TARGET_HAS_ext8s_i64 |
c61aaf7a | 174 | DEF(ext8s_i64, 1, 1, 0, 0) |
c896fe29 FB |
175 | #endif |
176 | #ifdef TCG_TARGET_HAS_ext16s_i64 | |
c61aaf7a | 177 | DEF(ext16s_i64, 1, 1, 0, 0) |
c896fe29 FB |
178 | #endif |
179 | #ifdef TCG_TARGET_HAS_ext32s_i64 | |
c61aaf7a | 180 | DEF(ext32s_i64, 1, 1, 0, 0) |
c896fe29 | 181 | #endif |
cfc86988 | 182 | #ifdef TCG_TARGET_HAS_ext8u_i64 |
c61aaf7a | 183 | DEF(ext8u_i64, 1, 1, 0, 0) |
cfc86988 AJ |
184 | #endif |
185 | #ifdef TCG_TARGET_HAS_ext16u_i64 | |
c61aaf7a | 186 | DEF(ext16u_i64, 1, 1, 0, 0) |
cfc86988 AJ |
187 | #endif |
188 | #ifdef TCG_TARGET_HAS_ext32u_i64 | |
c61aaf7a | 189 | DEF(ext32u_i64, 1, 1, 0, 0) |
cfc86988 | 190 | #endif |
9a5c57fd | 191 | #ifdef TCG_TARGET_HAS_bswap16_i64 |
c61aaf7a | 192 | DEF(bswap16_i64, 1, 1, 0, 0) |
9a5c57fd AJ |
193 | #endif |
194 | #ifdef TCG_TARGET_HAS_bswap32_i64 | |
c61aaf7a | 195 | DEF(bswap32_i64, 1, 1, 0, 0) |
9a5c57fd | 196 | #endif |
66896cb8 | 197 | #ifdef TCG_TARGET_HAS_bswap64_i64 |
c61aaf7a | 198 | DEF(bswap64_i64, 1, 1, 0, 0) |
c896fe29 | 199 | #endif |
d2604285 | 200 | #ifdef TCG_TARGET_HAS_not_i64 |
c61aaf7a | 201 | DEF(not_i64, 1, 1, 0, 0) |
d2604285 | 202 | #endif |
390efc54 | 203 | #ifdef TCG_TARGET_HAS_neg_i64 |
c61aaf7a | 204 | DEF(neg_i64, 1, 1, 0, 0) |
390efc54 | 205 | #endif |
241cbed4 | 206 | #ifdef TCG_TARGET_HAS_andc_i64 |
c61aaf7a | 207 | DEF(andc_i64, 1, 2, 0, 0) |
241cbed4 | 208 | #endif |
791d1262 | 209 | #ifdef TCG_TARGET_HAS_orc_i64 |
c61aaf7a | 210 | DEF(orc_i64, 1, 2, 0, 0) |
791d1262 | 211 | #endif |
8d625cf1 | 212 | #ifdef TCG_TARGET_HAS_eqv_i64 |
c61aaf7a | 213 | DEF(eqv_i64, 1, 2, 0, 0) |
8d625cf1 | 214 | #endif |
9940a96b | 215 | #ifdef TCG_TARGET_HAS_nand_i64 |
c61aaf7a | 216 | DEF(nand_i64, 1, 2, 0, 0) |
9940a96b | 217 | #endif |
32d98fbd | 218 | #ifdef TCG_TARGET_HAS_nor_i64 |
c61aaf7a | 219 | DEF(nor_i64, 1, 2, 0, 0) |
32d98fbd | 220 | #endif |
0dd0dd55 | 221 | #endif |
c896fe29 FB |
222 | |
223 | /* QEMU specific */ | |
7e4597d7 | 224 | #if TARGET_LONG_BITS > TCG_TARGET_REG_BITS |
c61aaf7a | 225 | DEF(debug_insn_start, 0, 0, 2, 0) |
7e4597d7 | 226 | #else |
c61aaf7a | 227 | DEF(debug_insn_start, 0, 0, 1, 0) |
7e4597d7 | 228 | #endif |
c61aaf7a AJ |
229 | DEF(exit_tb, 0, 0, 1, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS) |
230 | DEF(goto_tb, 0, 0, 1, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS) | |
c896fe29 FB |
231 | /* Note: even if TARGET_LONG_BITS is not defined, the INDEX_op |
232 | constants must be defined */ | |
233 | #if TCG_TARGET_REG_BITS == 32 | |
234 | #if TARGET_LONG_BITS == 32 | |
c61aaf7a | 235 | DEF(qemu_ld8u, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
c896fe29 | 236 | #else |
c61aaf7a | 237 | DEF(qemu_ld8u, 1, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
c896fe29 FB |
238 | #endif |
239 | #if TARGET_LONG_BITS == 32 | |
c61aaf7a | 240 | DEF(qemu_ld8s, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
c896fe29 | 241 | #else |
c61aaf7a | 242 | DEF(qemu_ld8s, 1, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
c896fe29 FB |
243 | #endif |
244 | #if TARGET_LONG_BITS == 32 | |
c61aaf7a | 245 | DEF(qemu_ld16u, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
c896fe29 | 246 | #else |
c61aaf7a | 247 | DEF(qemu_ld16u, 1, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
c896fe29 FB |
248 | #endif |
249 | #if TARGET_LONG_BITS == 32 | |
c61aaf7a | 250 | DEF(qemu_ld16s, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
c896fe29 | 251 | #else |
c61aaf7a | 252 | DEF(qemu_ld16s, 1, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
c896fe29 FB |
253 | #endif |
254 | #if TARGET_LONG_BITS == 32 | |
c61aaf7a | 255 | DEF(qemu_ld32, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
c896fe29 | 256 | #else |
c61aaf7a | 257 | DEF(qemu_ld32, 1, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
c896fe29 FB |
258 | #endif |
259 | #if TARGET_LONG_BITS == 32 | |
c61aaf7a | 260 | DEF(qemu_ld64, 2, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
c896fe29 | 261 | #else |
c61aaf7a | 262 | DEF(qemu_ld64, 2, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
c896fe29 FB |
263 | #endif |
264 | ||
265 | #if TARGET_LONG_BITS == 32 | |
c61aaf7a | 266 | DEF(qemu_st8, 0, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
c896fe29 | 267 | #else |
c61aaf7a | 268 | DEF(qemu_st8, 0, 3, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
c896fe29 FB |
269 | #endif |
270 | #if TARGET_LONG_BITS == 32 | |
c61aaf7a | 271 | DEF(qemu_st16, 0, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
c896fe29 | 272 | #else |
c61aaf7a | 273 | DEF(qemu_st16, 0, 3, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
c896fe29 FB |
274 | #endif |
275 | #if TARGET_LONG_BITS == 32 | |
c61aaf7a | 276 | DEF(qemu_st32, 0, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
c896fe29 | 277 | #else |
c61aaf7a | 278 | DEF(qemu_st32, 0, 3, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
c896fe29 FB |
279 | #endif |
280 | #if TARGET_LONG_BITS == 32 | |
c61aaf7a | 281 | DEF(qemu_st64, 0, 3, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
c896fe29 | 282 | #else |
c61aaf7a | 283 | DEF(qemu_st64, 0, 4, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
c896fe29 FB |
284 | #endif |
285 | ||
286 | #else /* TCG_TARGET_REG_BITS == 32 */ | |
287 | ||
c61aaf7a AJ |
288 | DEF(qemu_ld8u, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
289 | DEF(qemu_ld8s, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) | |
290 | DEF(qemu_ld16u, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) | |
291 | DEF(qemu_ld16s, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) | |
292 | DEF(qemu_ld32, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) | |
293 | DEF(qemu_ld32u, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) | |
294 | DEF(qemu_ld32s, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) | |
295 | DEF(qemu_ld64, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) | |
c896fe29 | 296 | |
c61aaf7a AJ |
297 | DEF(qemu_st8, 0, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
298 | DEF(qemu_st16, 0, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) | |
299 | DEF(qemu_st32, 0, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) | |
300 | DEF(qemu_st64, 0, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) | |
c896fe29 FB |
301 | |
302 | #endif /* TCG_TARGET_REG_BITS != 32 */ | |
303 | ||
c61aaf7a | 304 | #undef DEF |