projects / qemu.git / blame
| Commit | Line | Data |
|---|---|---|
| c896fe29 FB |
1 | /* |
| 2 | * Tiny Code Generator for QEMU | |
| 3 | * | |
| 4 | * Copyright (c) 2008 Fabrice Bellard | |
| 5 | * | |
| 6 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
| 7 | * of this software and associated documentation files (the "Software"), to deal | |
| 8 | * in the Software without restriction, including without limitation the rights | |
| 9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
| 10 | * copies of the Software, and to permit persons to whom the Software is | |
| 11 | * furnished to do so, subject to the following conditions: | |
| 12 | * | |
| 13 | * The above copyright notice and this permission notice shall be included in | |
| 14 | * all copies or substantial portions of the Software. | |
| 15 | * | |
| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
| 19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
| 20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
| 21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
| 22 | * THE SOFTWARE. | |
| 23 | */ | |
| c896fe29 FB |
24 | #ifndef DEF2 |
| 25 | #define DEF2(name, oargs, iargs, cargs, flags) DEF(name, oargs + iargs + cargs, 0) | |
| 26 | #endif | |
| 27 | ||
| 28 | /* predefined ops */ | |
| 29 | DEF2(end, 0, 0, 0, 0) /* must be kept first */ | |
| 30 | DEF2(nop, 0, 0, 0, 0) | |
| 31 | DEF2(nop1, 0, 0, 1, 0) | |
| 32 | DEF2(nop2, 0, 0, 2, 0) | |
| 33 | DEF2(nop3, 0, 0, 3, 0) | |
| 34 | DEF2(nopn, 0, 0, 1, 0) /* variable number of parameters */ | |
| c896fe29 | 35 | |
| 5ff9d6a4 FB |
36 | DEF2(discard, 1, 0, 0, 0) |
| 37 | ||
| c896fe29 | 38 | DEF2(set_label, 0, 0, 1, 0) |
| 5ff9d6a4 FB |
39 | DEF2(call, 0, 1, 2, TCG_OPF_SIDE_EFFECTS) /* variable number of parameters */ |
| 40 | DEF2(jmp, 0, 1, 0, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS) | |
| 41 | DEF2(br, 0, 0, 1, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS) | |
| c896fe29 FB |
42 | |
| 43 | DEF2(mov_i32, 1, 1, 0, 0) | |
| 44 | DEF2(movi_i32, 1, 0, 1, 0) | |
| be210acb | 45 | DEF2(setcond_i32, 1, 2, 1, 0) |
| c896fe29 FB |
46 | /* load/store */ |
| 47 | DEF2(ld8u_i32, 1, 1, 1, 0) | |
| 48 | DEF2(ld8s_i32, 1, 1, 1, 0) | |
| 49 | DEF2(ld16u_i32, 1, 1, 1, 0) | |
| 50 | DEF2(ld16s_i32, 1, 1, 1, 0) | |
| 51 | DEF2(ld_i32, 1, 1, 1, 0) | |
| 5ff9d6a4 FB |
52 | DEF2(st8_i32, 0, 2, 1, TCG_OPF_SIDE_EFFECTS) |
| 53 | DEF2(st16_i32, 0, 2, 1, TCG_OPF_SIDE_EFFECTS) | |
| 54 | DEF2(st_i32, 0, 2, 1, TCG_OPF_SIDE_EFFECTS) | |
| c896fe29 FB |
55 | /* arith */ |
| 56 | DEF2(add_i32, 1, 2, 0, 0) | |
| 57 | DEF2(sub_i32, 1, 2, 0, 0) | |
| 58 | DEF2(mul_i32, 1, 2, 0, 0) | |
| 59 | #ifdef TCG_TARGET_HAS_div_i32 | |
| 60 | DEF2(div_i32, 1, 2, 0, 0) | |
| 61 | DEF2(divu_i32, 1, 2, 0, 0) | |
| 62 | DEF2(rem_i32, 1, 2, 0, 0) | |
| 63 | DEF2(remu_i32, 1, 2, 0, 0) | |
| 30138f28 AJ |
64 | #endif |
| 65 | #ifdef TCG_TARGET_HAS_div2_i32 | |
| c896fe29 FB |
66 | DEF2(div2_i32, 2, 3, 0, 0) |
| 67 | DEF2(divu2_i32, 2, 3, 0, 0) | |
| 68 | #endif | |
| 69 | DEF2(and_i32, 1, 2, 0, 0) | |
| 70 | DEF2(or_i32, 1, 2, 0, 0) | |
| 71 | DEF2(xor_i32, 1, 2, 0, 0) | |
| d42f183c | 72 | /* shifts/rotates */ |
| c896fe29 FB |
73 | DEF2(shl_i32, 1, 2, 0, 0) |
| 74 | DEF2(shr_i32, 1, 2, 0, 0) | |
| 75 | DEF2(sar_i32, 1, 2, 0, 0) | |
| f31e9370 | 76 | #ifdef TCG_TARGET_HAS_rot_i32 |
| d42f183c AJ |
77 | DEF2(rotl_i32, 1, 2, 0, 0) |
| 78 | DEF2(rotr_i32, 1, 2, 0, 0) | |
| f31e9370 | 79 | #endif |
| c896fe29 | 80 | |
| 5ff9d6a4 | 81 | DEF2(brcond_i32, 0, 2, 2, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS) |
| c896fe29 FB |
82 | #if TCG_TARGET_REG_BITS == 32 |
| 83 | DEF2(add2_i32, 2, 4, 0, 0) | |
| 84 | DEF2(sub2_i32, 2, 4, 0, 0) | |
| 5ff9d6a4 | 85 | DEF2(brcond2_i32, 0, 4, 2, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS) |
| c896fe29 | 86 | DEF2(mulu2_i32, 2, 2, 0, 0) |
| be210acb | 87 | DEF2(setcond2_i32, 1, 4, 1, 0) |
| c896fe29 FB |
88 | #endif |
| 89 | #ifdef TCG_TARGET_HAS_ext8s_i32 | |
| 90 | DEF2(ext8s_i32, 1, 1, 0, 0) | |
| 91 | #endif | |
| 92 | #ifdef TCG_TARGET_HAS_ext16s_i32 | |
| 93 | DEF2(ext16s_i32, 1, 1, 0, 0) | |
| 94 | #endif | |
| cfc86988 AJ |
95 | #ifdef TCG_TARGET_HAS_ext8u_i32 |
| 96 | DEF2(ext8u_i32, 1, 1, 0, 0) | |
| 97 | #endif | |
| 98 | #ifdef TCG_TARGET_HAS_ext16u_i32 | |
| 99 | DEF2(ext16u_i32, 1, 1, 0, 0) | |
| 100 | #endif | |
| 84aafb06 AJ |
101 | #ifdef TCG_TARGET_HAS_bswap16_i32 |
| 102 | DEF2(bswap16_i32, 1, 1, 0, 0) | |
| 103 | #endif | |
| 66896cb8 AJ |
104 | #ifdef TCG_TARGET_HAS_bswap32_i32 |
| 105 | DEF2(bswap32_i32, 1, 1, 0, 0) | |
| c896fe29 | 106 | #endif |
| 0dd0dd55 AJ |
107 | #ifdef TCG_TARGET_HAS_not_i32 |
| 108 | DEF2(not_i32, 1, 1, 0, 0) | |
| 109 | #endif | |
| 110 | #ifdef TCG_TARGET_HAS_neg_i32 | |
| 111 | DEF2(neg_i32, 1, 1, 0, 0) | |
| 112 | #endif | |
| 241cbed4 RH |
113 | #ifdef TCG_TARGET_HAS_andc_i32 |
| 114 | DEF2(andc_i32, 1, 2, 0, 0) | |
| 115 | #endif | |
| 791d1262 RH |
116 | #ifdef TCG_TARGET_HAS_orc_i32 |
| 117 | DEF2(orc_i32, 1, 2, 0, 0) | |
| 118 | #endif | |
| 8d625cf1 RH |
119 | #ifdef TCG_TARGET_HAS_eqv_i32 |
| 120 | DEF2(eqv_i32, 1, 2, 0, 0) | |
| 121 | #endif | |
| c896fe29 FB |
122 | |
| 123 | #if TCG_TARGET_REG_BITS == 64 | |
| 124 | DEF2(mov_i64, 1, 1, 0, 0) | |
| 125 | DEF2(movi_i64, 1, 0, 1, 0) | |
| be210acb | 126 | DEF2(setcond_i64, 1, 2, 1, 0) |
| c896fe29 FB |
127 | /* load/store */ |
| 128 | DEF2(ld8u_i64, 1, 1, 1, 0) | |
| 129 | DEF2(ld8s_i64, 1, 1, 1, 0) | |
| 130 | DEF2(ld16u_i64, 1, 1, 1, 0) | |
| 131 | DEF2(ld16s_i64, 1, 1, 1, 0) | |
| 132 | DEF2(ld32u_i64, 1, 1, 1, 0) | |
| 133 | DEF2(ld32s_i64, 1, 1, 1, 0) | |
| 134 | DEF2(ld_i64, 1, 1, 1, 0) | |
| 5ff9d6a4 FB |
135 | DEF2(st8_i64, 0, 2, 1, TCG_OPF_SIDE_EFFECTS) |
| 136 | DEF2(st16_i64, 0, 2, 1, TCG_OPF_SIDE_EFFECTS) | |
| 137 | DEF2(st32_i64, 0, 2, 1, TCG_OPF_SIDE_EFFECTS) | |
| 138 | DEF2(st_i64, 0, 2, 1, TCG_OPF_SIDE_EFFECTS) | |
| c896fe29 FB |
139 | /* arith */ |
| 140 | DEF2(add_i64, 1, 2, 0, 0) | |
| 141 | DEF2(sub_i64, 1, 2, 0, 0) | |
| 142 | DEF2(mul_i64, 1, 2, 0, 0) | |
| 143 | #ifdef TCG_TARGET_HAS_div_i64 | |
| 144 | DEF2(div_i64, 1, 2, 0, 0) | |
| 145 | DEF2(divu_i64, 1, 2, 0, 0) | |
| 146 | DEF2(rem_i64, 1, 2, 0, 0) | |
| 147 | DEF2(remu_i64, 1, 2, 0, 0) | |
| 30138f28 AJ |
148 | #endif |
| 149 | #ifdef TCG_TARGET_HAS_div2_i64 | |
| c896fe29 FB |
150 | DEF2(div2_i64, 2, 3, 0, 0) |
| 151 | DEF2(divu2_i64, 2, 3, 0, 0) | |
| 152 | #endif | |
| 153 | DEF2(and_i64, 1, 2, 0, 0) | |
| 154 | DEF2(or_i64, 1, 2, 0, 0) | |
| 155 | DEF2(xor_i64, 1, 2, 0, 0) | |
| d42f183c | 156 | /* shifts/rotates */ |
| c896fe29 FB |
157 | DEF2(shl_i64, 1, 2, 0, 0) |
| 158 | DEF2(shr_i64, 1, 2, 0, 0) | |
| 159 | DEF2(sar_i64, 1, 2, 0, 0) | |
| f31e9370 | 160 | #ifdef TCG_TARGET_HAS_rot_i64 |
| d42f183c AJ |
161 | DEF2(rotl_i64, 1, 2, 0, 0) |
| 162 | DEF2(rotr_i64, 1, 2, 0, 0) | |
| f31e9370 | 163 | #endif |
| c896fe29 | 164 | |
| 5ff9d6a4 | 165 | DEF2(brcond_i64, 0, 2, 2, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS) |
| c896fe29 FB |
166 | #ifdef TCG_TARGET_HAS_ext8s_i64 |
| 167 | DEF2(ext8s_i64, 1, 1, 0, 0) | |
| 168 | #endif | |
| 169 | #ifdef TCG_TARGET_HAS_ext16s_i64 | |
| 170 | DEF2(ext16s_i64, 1, 1, 0, 0) | |
| 171 | #endif | |
| 172 | #ifdef TCG_TARGET_HAS_ext32s_i64 | |
| 173 | DEF2(ext32s_i64, 1, 1, 0, 0) | |
| 174 | #endif | |
| cfc86988 AJ |
175 | #ifdef TCG_TARGET_HAS_ext8u_i64 |
| 176 | DEF2(ext8u_i64, 1, 1, 0, 0) | |
| 177 | #endif | |
| 178 | #ifdef TCG_TARGET_HAS_ext16u_i64 | |
| 179 | DEF2(ext16u_i64, 1, 1, 0, 0) | |
| 180 | #endif | |
| 181 | #ifdef TCG_TARGET_HAS_ext32u_i64 | |
| 182 | DEF2(ext32u_i64, 1, 1, 0, 0) | |
| 183 | #endif | |
| 9a5c57fd AJ |
184 | #ifdef TCG_TARGET_HAS_bswap16_i64 |
| 185 | DEF2(bswap16_i64, 1, 1, 0, 0) | |
| 186 | #endif | |
| 187 | #ifdef TCG_TARGET_HAS_bswap32_i64 | |
| 188 | DEF2(bswap32_i64, 1, 1, 0, 0) | |
| 189 | #endif | |
| 66896cb8 AJ |
190 | #ifdef TCG_TARGET_HAS_bswap64_i64 |
| 191 | DEF2(bswap64_i64, 1, 1, 0, 0) | |
| c896fe29 | 192 | #endif |
| d2604285 AJ |
193 | #ifdef TCG_TARGET_HAS_not_i64 |
| 194 | DEF2(not_i64, 1, 1, 0, 0) | |
| 195 | #endif | |
| 390efc54 PB |
196 | #ifdef TCG_TARGET_HAS_neg_i64 |
| 197 | DEF2(neg_i64, 1, 1, 0, 0) | |
| 198 | #endif | |
| 241cbed4 RH |
199 | #ifdef TCG_TARGET_HAS_andc_i64 |
| 200 | DEF2(andc_i64, 1, 2, 0, 0) | |
| 201 | #endif | |
| 791d1262 RH |
202 | #ifdef TCG_TARGET_HAS_orc_i64 |
| 203 | DEF2(orc_i64, 1, 2, 0, 0) | |
| 204 | #endif | |
| 8d625cf1 RH |
205 | #ifdef TCG_TARGET_HAS_eqv_i64 |
| 206 | DEF2(eqv_i64, 1, 2, 0, 0) | |
| 207 | #endif | |
| 0dd0dd55 | 208 | #endif |
| c896fe29 FB |
209 | |
| 210 | /* QEMU specific */ | |
| 7e4597d7 FB |
211 | #if TARGET_LONG_BITS > TCG_TARGET_REG_BITS |
| 212 | DEF2(debug_insn_start, 0, 0, 2, 0) | |
| 213 | #else | |
| 214 | DEF2(debug_insn_start, 0, 0, 1, 0) | |
| 215 | #endif | |
| 5ff9d6a4 FB |
216 | DEF2(exit_tb, 0, 0, 1, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS) |
| 217 | DEF2(goto_tb, 0, 0, 1, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS) | |
| c896fe29 FB |
218 | /* Note: even if TARGET_LONG_BITS is not defined, the INDEX_op |
| 219 | constants must be defined */ | |
| 220 | #if TCG_TARGET_REG_BITS == 32 | |
| 221 | #if TARGET_LONG_BITS == 32 | |
| 5ff9d6a4 | 222 | DEF2(qemu_ld8u, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
| c896fe29 | 223 | #else |
| 5ff9d6a4 | 224 | DEF2(qemu_ld8u, 1, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
| c896fe29 FB |
225 | #endif |
| 226 | #if TARGET_LONG_BITS == 32 | |
| 5ff9d6a4 | 227 | DEF2(qemu_ld8s, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
| c896fe29 | 228 | #else |
| 5ff9d6a4 | 229 | DEF2(qemu_ld8s, 1, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
| c896fe29 FB |
230 | #endif |
| 231 | #if TARGET_LONG_BITS == 32 | |
| 5ff9d6a4 | 232 | DEF2(qemu_ld16u, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
| c896fe29 | 233 | #else |
| 5ff9d6a4 | 234 | DEF2(qemu_ld16u, 1, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
| c896fe29 FB |
235 | #endif |
| 236 | #if TARGET_LONG_BITS == 32 | |
| 5ff9d6a4 | 237 | DEF2(qemu_ld16s, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
| c896fe29 | 238 | #else |
| 5ff9d6a4 | 239 | DEF2(qemu_ld16s, 1, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
| c896fe29 FB |
240 | #endif |
| 241 | #if TARGET_LONG_BITS == 32 | |
| 5ff9d6a4 | 242 | DEF2(qemu_ld32u, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
| c896fe29 | 243 | #else |
| 5ff9d6a4 | 244 | DEF2(qemu_ld32u, 1, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
| c896fe29 FB |
245 | #endif |
| 246 | #if TARGET_LONG_BITS == 32 | |
| 5ff9d6a4 | 247 | DEF2(qemu_ld64, 2, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
| c896fe29 | 248 | #else |
| 5ff9d6a4 | 249 | DEF2(qemu_ld64, 2, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
| c896fe29 FB |
250 | #endif |
| 251 | ||
| 252 | #if TARGET_LONG_BITS == 32 | |
| 5ff9d6a4 | 253 | DEF2(qemu_st8, 0, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
| c896fe29 | 254 | #else |
| 5ff9d6a4 | 255 | DEF2(qemu_st8, 0, 3, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
| c896fe29 FB |
256 | #endif |
| 257 | #if TARGET_LONG_BITS == 32 | |
| 5ff9d6a4 | 258 | DEF2(qemu_st16, 0, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
| c896fe29 | 259 | #else |
| 5ff9d6a4 | 260 | DEF2(qemu_st16, 0, 3, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
| c896fe29 FB |
261 | #endif |
| 262 | #if TARGET_LONG_BITS == 32 | |
| 5ff9d6a4 | 263 | DEF2(qemu_st32, 0, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
| c896fe29 | 264 | #else |
| 5ff9d6a4 | 265 | DEF2(qemu_st32, 0, 3, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
| c896fe29 FB |
266 | #endif |
| 267 | #if TARGET_LONG_BITS == 32 | |
| 5ff9d6a4 | 268 | DEF2(qemu_st64, 0, 3, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
| c896fe29 | 269 | #else |
| 5ff9d6a4 | 270 | DEF2(qemu_st64, 0, 4, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
| c896fe29 FB |
271 | #endif |
| 272 | ||
| 273 | #else /* TCG_TARGET_REG_BITS == 32 */ | |
| 274 | ||
| 5ff9d6a4 FB |
275 | DEF2(qemu_ld8u, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
| 276 | DEF2(qemu_ld8s, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) | |
| 277 | DEF2(qemu_ld16u, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) | |
| 278 | DEF2(qemu_ld16s, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) | |
| 279 | DEF2(qemu_ld32u, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) | |
| 280 | DEF2(qemu_ld32s, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) | |
| 281 | DEF2(qemu_ld64, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) | |
| c896fe29 | 282 | |
| 5ff9d6a4 FB |
283 | DEF2(qemu_st8, 0, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
| 284 | DEF2(qemu_st16, 0, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) | |
| 285 | DEF2(qemu_st32, 0, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) | |
| 286 | DEF2(qemu_st64, 0, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) | |
| c896fe29 FB |
287 | |
| 288 | #endif /* TCG_TARGET_REG_BITS != 32 */ | |
| 289 | ||
| 290 | #undef DEF2 |