]> git.proxmox.com Git - qemu.git/blame - tests/test-i386.c
projects / qemu.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Increase the odds for the movei test to pass in system simulation.
[qemu.git] / tests / test-i386.c
CommitLineData
78d6da97
FB		 1/*
2 * x86 CPU test
5fafdf24 3 *
78d6da97
FB		 4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
19 */
3a27ad0b 20#define _GNU_SOURCE
4d1135e4
FB		 21#include <stdlib.h>
22#include <stdio.h>
e3e86d56 23#include <string.h>
6dbad63e 24#include <inttypes.h>
4d1135e4 25#include <math.h>
3a27ad0b
FB		 26#include <signal.h>
27#include <setjmp.h>
070893f4 28#include <errno.h>
3a27ad0b
FB		 29#include <sys/ucontext.h>
30#include <sys/mman.h>
4d1135e4 31
776f2227 32#if !defined(__x86_64__)
a5973fbf 33//#define TEST_VM86
776f2227
FB		 34#define TEST_SEGS
35#endif
3ff0631e 36//#define LINUX_VM86_IOPL_FIX
791c2261 37//#define TEST_P4_FLAGS
a5973fbf 38#ifdef __SSE__
776f2227
FB		 39#define TEST_SSE
40#define TEST_CMOV 1
41#define TEST_FCOMI 1
42#else
a5973fbf
FB		 43#undef TEST_SSE
44#define TEST_CMOV 1
45#define TEST_FCOMI 1
776f2227
FB		 46#endif
47
48#if defined(__x86_64__)
49#define FMT64X "%016lx"
50#define FMTLX "%016lx"
51#define X86_64_ONLY(x) x
52#else
26a76461 53#define FMT64X "%016" PRIx64
776f2227
FB		 54#define FMTLX "%08lx"
55#define X86_64_ONLY(x)
56#endif
57
58#ifdef TEST_VM86
59#include <asm/vm86.h>
60#endif
5dd9488c 61
4d1135e4
FB		 62#define xglue(x, y) x ## y
63#define glue(x, y) xglue(x, y)
64#define stringify(s) tostring(s)
65#define tostring(s) #s
66
67#define CC_C 0x0001
68#define CC_P 0x0004
69#define CC_A 0x0010
70#define CC_Z 0x0040
71#define CC_S 0x0080
72#define CC_O 0x0800
73
776f2227 74#define __init_call __attribute__ ((unused,__section__ ("initcall")))
4d1135e4 75
4b74fe1f
FB		 76#define CC_MASK (CC_C | CC_P | CC_Z | CC_S | CC_O | CC_A)
77
776f2227
FB		 78#if defined(__x86_64__)
79static inline long i2l(long v)
80{
81 return v | ((v ^ 0xabcd) << 32);
82}
83#else
84static inline long i2l(long v)
85{
86 return v;
87}
88#endif
89
4d1135e4
FB		 90#define OP add
91#include "test-i386.h"
92
93#define OP sub
94#include "test-i386.h"
95
96#define OP xor
97#include "test-i386.h"
98
99#define OP and
100#include "test-i386.h"
101
102#define OP or
103#include "test-i386.h"
104
105#define OP cmp
106#include "test-i386.h"
107
108#define OP adc
109#define OP_CC
110#include "test-i386.h"
111
112#define OP sbb
113#define OP_CC
114#include "test-i386.h"
115
116#define OP inc
117#define OP_CC
118#define OP1
119#include "test-i386.h"
120
121#define OP dec
122#define OP_CC
123#define OP1
124#include "test-i386.h"
125
126#define OP neg
127#define OP_CC
128#define OP1
129#include "test-i386.h"
130
131#define OP not
132#define OP_CC
133#define OP1
134#include "test-i386.h"
135
4b74fe1f
FB		 136#undef CC_MASK
137#define CC_MASK (CC_C | CC_P | CC_Z | CC_S | CC_O)
138
379ca80d
FB		 139#define OP shl
140#include "test-i386-shift.h"
141
142#define OP shr
143#include "test-i386-shift.h"
144
145#define OP sar
146#include "test-i386-shift.h"
147
148#define OP rol
149#include "test-i386-shift.h"
150
151#define OP ror
152#include "test-i386-shift.h"
153
154#define OP rcr
155#define OP_CC
156#include "test-i386-shift.h"
157
158#define OP rcl
159#define OP_CC
160#include "test-i386-shift.h"
161
d57c4e01
FB		 162#define OP shld
163#define OP_SHIFTD
164#define OP_NOBYTE
165#include "test-i386-shift.h"
166
167#define OP shrd
168#define OP_SHIFTD
169#define OP_NOBYTE
170#include "test-i386-shift.h"
171
172/* XXX: should be more precise ? */
173#undef CC_MASK
174#define CC_MASK (CC_C)
175
176#define OP bt
177#define OP_NOBYTE
178#include "test-i386-shift.h"
179
180#define OP bts
181#define OP_NOBYTE
182#include "test-i386-shift.h"
183
184#define OP btr
185#define OP_NOBYTE
186#include "test-i386-shift.h"
187
188#define OP btc
189#define OP_NOBYTE
190#include "test-i386-shift.h"
379ca80d 191
4d1135e4 192/* lea test (modrm support) */
776f2227
FB		 193#define TEST_LEAQ(STR)\
194{\
195 asm("lea " STR ", %0"\
196 : "=r" (res)\
197 : "a" (eax), "b" (ebx), "c" (ecx), "d" (edx), "S" (esi), "D" (edi));\
198 printf("lea %s = " FMTLX "\n", STR, res);\
199}
200
4d1135e4
FB		 201#define TEST_LEA(STR)\
202{\
776f2227 203 asm("lea " STR ", %0"\
4d1135e4
FB		 204 : "=r" (res)\
205 : "a" (eax), "b" (ebx), "c" (ecx), "d" (edx), "S" (esi), "D" (edi));\
776f2227 206 printf("lea %s = " FMTLX "\n", STR, res);\
4d1135e4
FB		 207}
208
209#define TEST_LEA16(STR)\
210{\
211 asm(".code16 ; .byte 0x67 ; leal " STR ", %0 ; .code32"\
212 : "=wq" (res)\
213 : "a" (eax), "b" (ebx), "c" (ecx), "d" (edx), "S" (esi), "D" (edi));\
776f2227 214 printf("lea %s = %08lx\n", STR, res);\
4d1135e4
FB		 215}
216
217
218void test_lea(void)
219{
776f2227
FB		 220 long eax, ebx, ecx, edx, esi, edi, res;
221 eax = i2l(0x0001);
222 ebx = i2l(0x0002);
223 ecx = i2l(0x0004);
224 edx = i2l(0x0008);
225 esi = i2l(0x0010);
226 edi = i2l(0x0020);
4d1135e4
FB		 227
228 TEST_LEA("0x4000");
229
230 TEST_LEA("(%%eax)");
231 TEST_LEA("(%%ebx)");
232 TEST_LEA("(%%ecx)");
233 TEST_LEA("(%%edx)");
234 TEST_LEA("(%%esi)");
235 TEST_LEA("(%%edi)");
236
237 TEST_LEA("0x40(%%eax)");
238 TEST_LEA("0x40(%%ebx)");
239 TEST_LEA("0x40(%%ecx)");
240 TEST_LEA("0x40(%%edx)");
241 TEST_LEA("0x40(%%esi)");
242 TEST_LEA("0x40(%%edi)");
243
244 TEST_LEA("0x4000(%%eax)");
245 TEST_LEA("0x4000(%%ebx)");
246 TEST_LEA("0x4000(%%ecx)");
247 TEST_LEA("0x4000(%%edx)");
248 TEST_LEA("0x4000(%%esi)");
249 TEST_LEA("0x4000(%%edi)");
250
251 TEST_LEA("(%%eax, %%ecx)");
252 TEST_LEA("(%%ebx, %%edx)");
253 TEST_LEA("(%%ecx, %%ecx)");
254 TEST_LEA("(%%edx, %%ecx)");
255 TEST_LEA("(%%esi, %%ecx)");
256 TEST_LEA("(%%edi, %%ecx)");
257
258 TEST_LEA("0x40(%%eax, %%ecx)");
259 TEST_LEA("0x4000(%%ebx, %%edx)");
260
261 TEST_LEA("(%%ecx, %%ecx, 2)");
262 TEST_LEA("(%%edx, %%ecx, 4)");
263 TEST_LEA("(%%esi, %%ecx, 8)");
264
265 TEST_LEA("(,%%eax, 2)");
266 TEST_LEA("(,%%ebx, 4)");
267 TEST_LEA("(,%%ecx, 8)");
268
269 TEST_LEA("0x40(,%%eax, 2)");
270 TEST_LEA("0x40(,%%ebx, 4)");
271 TEST_LEA("0x40(,%%ecx, 8)");
272
273
274 TEST_LEA("-10(%%ecx, %%ecx, 2)");
275 TEST_LEA("-10(%%edx, %%ecx, 4)");
276 TEST_LEA("-10(%%esi, %%ecx, 8)");
277
278 TEST_LEA("0x4000(%%ecx, %%ecx, 2)");
279 TEST_LEA("0x4000(%%edx, %%ecx, 4)");
280 TEST_LEA("0x4000(%%esi, %%ecx, 8)");
281
776f2227
FB		 282#if defined(__x86_64__)
283 TEST_LEAQ("0x4000");
284 TEST_LEAQ("0x4000(%%rip)");
285
286 TEST_LEAQ("(%%rax)");
287 TEST_LEAQ("(%%rbx)");
288 TEST_LEAQ("(%%rcx)");
289 TEST_LEAQ("(%%rdx)");
290 TEST_LEAQ("(%%rsi)");
291 TEST_LEAQ("(%%rdi)");
292
293 TEST_LEAQ("0x40(%%rax)");
294 TEST_LEAQ("0x40(%%rbx)");
295 TEST_LEAQ("0x40(%%rcx)");
296 TEST_LEAQ("0x40(%%rdx)");
297 TEST_LEAQ("0x40(%%rsi)");
298 TEST_LEAQ("0x40(%%rdi)");
299
300 TEST_LEAQ("0x4000(%%rax)");
301 TEST_LEAQ("0x4000(%%rbx)");
302 TEST_LEAQ("0x4000(%%rcx)");
303 TEST_LEAQ("0x4000(%%rdx)");
304 TEST_LEAQ("0x4000(%%rsi)");
305 TEST_LEAQ("0x4000(%%rdi)");
306
307 TEST_LEAQ("(%%rax, %%rcx)");
308 TEST_LEAQ("(%%rbx, %%rdx)");
309 TEST_LEAQ("(%%rcx, %%rcx)");
310 TEST_LEAQ("(%%rdx, %%rcx)");
311 TEST_LEAQ("(%%rsi, %%rcx)");
312 TEST_LEAQ("(%%rdi, %%rcx)");
313
314 TEST_LEAQ("0x40(%%rax, %%rcx)");
315 TEST_LEAQ("0x4000(%%rbx, %%rdx)");
316
317 TEST_LEAQ("(%%rcx, %%rcx, 2)");
318 TEST_LEAQ("(%%rdx, %%rcx, 4)");
319 TEST_LEAQ("(%%rsi, %%rcx, 8)");
320
321 TEST_LEAQ("(,%%rax, 2)");
322 TEST_LEAQ("(,%%rbx, 4)");
323 TEST_LEAQ("(,%%rcx, 8)");
324
325 TEST_LEAQ("0x40(,%%rax, 2)");
326 TEST_LEAQ("0x40(,%%rbx, 4)");
327 TEST_LEAQ("0x40(,%%rcx, 8)");
328
329
330 TEST_LEAQ("-10(%%rcx, %%rcx, 2)");
331 TEST_LEAQ("-10(%%rdx, %%rcx, 4)");
332 TEST_LEAQ("-10(%%rsi, %%rcx, 8)");
333
334 TEST_LEAQ("0x4000(%%rcx, %%rcx, 2)");
335 TEST_LEAQ("0x4000(%%rdx, %%rcx, 4)");
336 TEST_LEAQ("0x4000(%%rsi, %%rcx, 8)");
337#else
4d1135e4
FB		 338 /* limited 16 bit addressing test */
339 TEST_LEA16("0x4000");
340 TEST_LEA16("(%%bx)");
341 TEST_LEA16("(%%si)");
342 TEST_LEA16("(%%di)");
343 TEST_LEA16("0x40(%%bx)");
344 TEST_LEA16("0x40(%%si)");
345 TEST_LEA16("0x40(%%di)");
346 TEST_LEA16("0x4000(%%bx)");
347 TEST_LEA16("0x4000(%%si)");
348 TEST_LEA16("(%%bx,%%si)");
349 TEST_LEA16("(%%bx,%%di)");
350 TEST_LEA16("0x40(%%bx,%%si)");
351 TEST_LEA16("0x40(%%bx,%%di)");
352 TEST_LEA16("0x4000(%%bx,%%si)");
353 TEST_LEA16("0x4000(%%bx,%%di)");
776f2227 354#endif
4d1135e4
FB		 355}
356
357#define TEST_JCC(JCC, v1, v2)\
358{\
5dd9488c 359 int res;\
4d1135e4
FB		 360 asm("movl $1, %0\n\t"\
361 "cmpl %2, %1\n\t"\
5dd9488c 362 "j" JCC " 1f\n\t"\
4d1135e4
FB		 363 "movl $0, %0\n\t"\
364 "1:\n\t"\
365 : "=r" (res)\
366 : "r" (v1), "r" (v2));\
5dd9488c
FB		 367 printf("%-10s %d\n", "j" JCC, res);\
368\
369 asm("movl $0, %0\n\t"\
370 "cmpl %2, %1\n\t"\
371 "set" JCC " %b0\n\t"\
372 : "=r" (res)\
373 : "r" (v1), "r" (v2));\
374 printf("%-10s %d\n", "set" JCC, res);\
375 if (TEST_CMOV) {\
776f2227
FB		 376 long val = i2l(1);\
377 long res = i2l(0x12345678);\
378X86_64_ONLY(\
379 asm("cmpl %2, %1\n\t"\
380 "cmov" JCC "q %3, %0\n\t"\
5dd9488c 381 : "=r" (res)\
776f2227 382 : "r" (v1), "r" (v2), "m" (val), "0" (res));\
d057099a 383 printf("%-10s R=" FMTLX "\n", "cmov" JCC "q", res);)\
776f2227
FB		 384 asm("cmpl %2, %1\n\t"\
385 "cmov" JCC "l %k3, %k0\n\t"\
386 : "=r" (res)\
387 : "r" (v1), "r" (v2), "m" (val), "0" (res));\
388 printf("%-10s R=" FMTLX "\n", "cmov" JCC "l", res);\
389 asm("cmpl %2, %1\n\t"\
5dd9488c
FB		 390 "cmov" JCC "w %w3, %w0\n\t"\
391 : "=r" (res)\
776f2227
FB		 392 : "r" (v1), "r" (v2), "r" (1), "0" (res));\
393 printf("%-10s R=" FMTLX "\n", "cmov" JCC "w", res);\
5dd9488c 394 } \
4d1135e4
FB		 395}
396
397/* various jump tests */
398void test_jcc(void)
399{
5dd9488c
FB		 400 TEST_JCC("ne", 1, 1);
401 TEST_JCC("ne", 1, 0);
4d1135e4 402
5dd9488c
FB		 403 TEST_JCC("e", 1, 1);
404 TEST_JCC("e", 1, 0);
4d1135e4 405
5dd9488c
FB		 406 TEST_JCC("l", 1, 1);
407 TEST_JCC("l", 1, 0);
408 TEST_JCC("l", 1, -1);
4d1135e4 409
5dd9488c
FB		 410 TEST_JCC("le", 1, 1);
411 TEST_JCC("le", 1, 0);
412 TEST_JCC("le", 1, -1);
4d1135e4 413
5dd9488c
FB		 414 TEST_JCC("ge", 1, 1);
415 TEST_JCC("ge", 1, 0);
416 TEST_JCC("ge", -1, 1);
4d1135e4 417
5dd9488c
FB		 418 TEST_JCC("g", 1, 1);
419 TEST_JCC("g", 1, 0);
420 TEST_JCC("g", 1, -1);
4d1135e4 421
5dd9488c
FB		 422 TEST_JCC("b", 1, 1);
423 TEST_JCC("b", 1, 0);
424 TEST_JCC("b", 1, -1);
4d1135e4 425
5dd9488c
FB		 426 TEST_JCC("be", 1, 1);
427 TEST_JCC("be", 1, 0);
428 TEST_JCC("be", 1, -1);
4d1135e4 429
5dd9488c
FB		 430 TEST_JCC("ae", 1, 1);
431 TEST_JCC("ae", 1, 0);
432 TEST_JCC("ae", 1, -1);
4d1135e4 433
5dd9488c
FB		 434 TEST_JCC("a", 1, 1);
435 TEST_JCC("a", 1, 0);
436 TEST_JCC("a", 1, -1);
4d1135e4
FB		 437
438
5dd9488c
FB		 439 TEST_JCC("p", 1, 1);
440 TEST_JCC("p", 1, 0);
4d1135e4 441
5dd9488c
FB		 442 TEST_JCC("np", 1, 1);
443 TEST_JCC("np", 1, 0);
4d1135e4 444
5dd9488c
FB		 445 TEST_JCC("o", 0x7fffffff, 0);
446 TEST_JCC("o", 0x7fffffff, -1);
4d1135e4 447
5dd9488c
FB		 448 TEST_JCC("no", 0x7fffffff, 0);
449 TEST_JCC("no", 0x7fffffff, -1);
4d1135e4 450
5dd9488c
FB		 451 TEST_JCC("s", 0, 1);
452 TEST_JCC("s", 0, -1);
453 TEST_JCC("s", 0, 0);
4d1135e4 454
5dd9488c
FB		 455 TEST_JCC("ns", 0, 1);
456 TEST_JCC("ns", 0, -1);
457 TEST_JCC("ns", 0, 0);
4d1135e4
FB		 458}
459
a5973fbf
FB		 460#define TEST_LOOP(insn) \
461{\
462 for(i = 0; i < sizeof(ecx_vals) / sizeof(long); i++) {\
463 ecx = ecx_vals[i];\
464 for(zf = 0; zf < 2; zf++) {\
465 asm("test %2, %2\n\t"\
466 "movl $1, %0\n\t"\
467 insn " 1f\n\t" \
468 "movl $0, %0\n\t"\
469 "1:\n\t"\
470 : "=a" (res)\
471 : "c" (ecx), "b" (!zf)); \
472 printf("%-10s ECX=" FMTLX " ZF=%ld r=%d\n", insn, ecx, zf, res); \
473 }\
474 }\
475}
476
477void test_loop(void)
478{
479 long ecx, zf;
480 const long ecx_vals[] = {
481 0,
482 1,
483 0x10000,
484 0x10001,
485#if defined(__x86_64__)
486 0x100000000L,
487 0x100000001L,
488#endif
489 };
490 int i, res;
491
492 TEST_LOOP("jcxz");
493 TEST_LOOP("loopw");
494 TEST_LOOP("loopzw");
495 TEST_LOOP("loopnzw");
496
497 TEST_LOOP("jecxz");
498 TEST_LOOP("loopl");
499 TEST_LOOP("loopzl");
500 TEST_LOOP("loopnzl");
501}
502
4b74fe1f 503#undef CC_MASK
791c2261
FB		 504#ifdef TEST_P4_FLAGS
505#define CC_MASK (CC_C | CC_P | CC_Z | CC_S | CC_O | CC_A)
506#else
4b74fe1f 507#define CC_MASK (CC_O | CC_C)
791c2261 508#endif
4b74fe1f
FB		 509
510#define OP mul
511#include "test-i386-muldiv.h"
512
513#define OP imul
514#include "test-i386-muldiv.h"
515
5fafdf24 516void test_imulw2(long op0, long op1)
4b74fe1f 517{
776f2227 518 long res, s1, s0, flags;
4b74fe1f
FB		 519 s0 = op0;
520 s1 = op1;
521 res = s0;
522 flags = 0;
acae4681 523 asm volatile ("push %4\n\t"
4b74fe1f 524 "popf\n\t"
5fafdf24 525 "imulw %w2, %w0\n\t"
4b74fe1f 526 "pushf\n\t"
776f2227 527 "pop %1\n\t"
4b74fe1f
FB		 528 : "=q" (res), "=g" (flags)
529 : "q" (s1), "0" (res), "1" (flags));
776f2227 530 printf("%-10s A=" FMTLX " B=" FMTLX " R=" FMTLX " CC=%04lx\n",
4b74fe1f
FB		 531 "imulw", s0, s1, res, flags & CC_MASK);
532}
533
5fafdf24 534void test_imull2(long op0, long op1)
4b74fe1f 535{
776f2227 536 long res, s1, s0, flags;
4b74fe1f
FB		 537 s0 = op0;
538 s1 = op1;
539 res = s0;
540 flags = 0;
acae4681 541 asm volatile ("push %4\n\t"
4b74fe1f 542 "popf\n\t"
5fafdf24 543 "imull %k2, %k0\n\t"
4b74fe1f 544 "pushf\n\t"
776f2227 545 "pop %1\n\t"
4b74fe1f
FB		 546 : "=q" (res), "=g" (flags)
547 : "q" (s1), "0" (res), "1" (flags));
776f2227 548 printf("%-10s A=" FMTLX " B=" FMTLX " R=" FMTLX " CC=%04lx\n",
4b74fe1f
FB		 549 "imull", s0, s1, res, flags & CC_MASK);
550}
551
776f2227 552#if defined(__x86_64__)
5fafdf24 553void test_imulq2(long op0, long op1)
776f2227
FB		 554{
555 long res, s1, s0, flags;
556 s0 = op0;
557 s1 = op1;
558 res = s0;
559 flags = 0;
560 asm volatile ("push %4\n\t"
561 "popf\n\t"
5fafdf24 562 "imulq %2, %0\n\t"
776f2227
FB		 563 "pushf\n\t"
564 "pop %1\n\t"
565 : "=q" (res), "=g" (flags)
566 : "q" (s1), "0" (res), "1" (flags));
567 printf("%-10s A=" FMTLX " B=" FMTLX " R=" FMTLX " CC=%04lx\n",
568 "imulq", s0, s1, res, flags & CC_MASK);
569}
570#endif
571
572#define TEST_IMUL_IM(size, rsize, op0, op1)\
b5075d29 573{\
776f2227 574 long res, flags, s1;\
b5075d29
FB		 575 flags = 0;\
576 res = 0;\
776f2227 577 s1 = op1;\
acae4681 578 asm volatile ("push %3\n\t"\
b5075d29 579 "popf\n\t"\
776f2227 580 "imul" size " $" #op0 ", %" rsize "2, %" rsize "0\n\t" \
b5075d29 581 "pushf\n\t"\
776f2227 582 "pop %1\n\t"\
b5075d29 583 : "=r" (res), "=g" (flags)\
776f2227
FB		 584 : "r" (s1), "1" (flags), "0" (res));\
585 printf("%-10s A=" FMTLX " B=" FMTLX " R=" FMTLX " CC=%04lx\n",\
586 "imul" size " im", (long)op0, (long)op1, res, flags & CC_MASK);\
b5075d29
FB		 587}
588
589
791c2261
FB		 590#undef CC_MASK
591#define CC_MASK (0)
592
593#define OP div
594#include "test-i386-muldiv.h"
595
596#define OP idiv
597#include "test-i386-muldiv.h"
598
4b74fe1f
FB		 599void test_mul(void)
600{
601 test_imulb(0x1234561d, 4);
602 test_imulb(3, -4);
603 test_imulb(0x80, 0x80);
604 test_imulb(0x10, 0x10);
605
606 test_imulw(0, 0x1234001d, 45);
607 test_imulw(0, 23, -45);
608 test_imulw(0, 0x8000, 0x8000);
609 test_imulw(0, 0x100, 0x100);
610
611 test_imull(0, 0x1234001d, 45);
612 test_imull(0, 23, -45);
613 test_imull(0, 0x80000000, 0x80000000);
614 test_imull(0, 0x10000, 0x10000);
615
616 test_mulb(0x1234561d, 4);
617 test_mulb(3, -4);
618 test_mulb(0x80, 0x80);
619 test_mulb(0x10, 0x10);
620
621 test_mulw(0, 0x1234001d, 45);
622 test_mulw(0, 23, -45);
623 test_mulw(0, 0x8000, 0x8000);
624 test_mulw(0, 0x100, 0x100);
625
626 test_mull(0, 0x1234001d, 45);
627 test_mull(0, 23, -45);
628 test_mull(0, 0x80000000, 0x80000000);
629 test_mull(0, 0x10000, 0x10000);
630
631 test_imulw2(0x1234001d, 45);
632 test_imulw2(23, -45);
633 test_imulw2(0x8000, 0x8000);
634 test_imulw2(0x100, 0x100);
635
636 test_imull2(0x1234001d, 45);
637 test_imull2(23, -45);
638 test_imull2(0x80000000, 0x80000000);
639 test_imull2(0x10000, 0x10000);
640
b5075d29
FB		 641 TEST_IMUL_IM("w", "w", 45, 0x1234);
642 TEST_IMUL_IM("w", "w", -45, 23);
643 TEST_IMUL_IM("w", "w", 0x8000, 0x80000000);
644 TEST_IMUL_IM("w", "w", 0x7fff, 0x1000);
645
776f2227
FB		 646 TEST_IMUL_IM("l", "k", 45, 0x1234);
647 TEST_IMUL_IM("l", "k", -45, 23);
648 TEST_IMUL_IM("l", "k", 0x8000, 0x80000000);
649 TEST_IMUL_IM("l", "k", 0x7fff, 0x1000);
b5075d29 650
4b74fe1f
FB		 651 test_idivb(0x12341678, 0x127e);
652 test_idivb(0x43210123, -5);
653 test_idivb(0x12340004, -1);
654
655 test_idivw(0, 0x12345678, 12347);
656 test_idivw(0, -23223, -45);
657 test_idivw(0, 0x12348000, -1);
658 test_idivw(0x12343, 0x12345678, 0x81238567);
659
660 test_idivl(0, 0x12345678, 12347);
661 test_idivl(0, -233223, -45);
662 test_idivl(0, 0x80000000, -1);
663 test_idivl(0x12343, 0x12345678, 0x81234567);
664
665 test_divb(0x12341678, 0x127e);
666 test_divb(0x43210123, -5);
667 test_divb(0x12340004, -1);
668
669 test_divw(0, 0x12345678, 12347);
670 test_divw(0, -23223, -45);
671 test_divw(0, 0x12348000, -1);
672 test_divw(0x12343, 0x12345678, 0x81238567);
673
674 test_divl(0, 0x12345678, 12347);
675 test_divl(0, -233223, -45);
676 test_divl(0, 0x80000000, -1);
677 test_divl(0x12343, 0x12345678, 0x81234567);
776f2227
FB		 678
679#if defined(__x86_64__)
680 test_imulq(0, 0x1234001d1234001d, 45);
681 test_imulq(0, 23, -45);
682 test_imulq(0, 0x8000000000000000, 0x8000000000000000);
683 test_imulq(0, 0x100000000, 0x100000000);
684
685 test_mulq(0, 0x1234001d1234001d, 45);
686 test_mulq(0, 23, -45);
687 test_mulq(0, 0x8000000000000000, 0x8000000000000000);
688 test_mulq(0, 0x100000000, 0x100000000);
689
690 test_imulq2(0x1234001d1234001d, 45);
691 test_imulq2(23, -45);
692 test_imulq2(0x8000000000000000, 0x8000000000000000);
693 test_imulq2(0x100000000, 0x100000000);
694
695 TEST_IMUL_IM("q", "", 45, 0x12341234);
696 TEST_IMUL_IM("q", "", -45, 23);
697 TEST_IMUL_IM("q", "", 0x8000, 0x8000000000000000);
698 TEST_IMUL_IM("q", "", 0x7fff, 0x10000000);
699
700 test_idivq(0, 0x12345678abcdef, 12347);
701 test_idivq(0, -233223, -45);
702 test_idivq(0, 0x8000000000000000, -1);
703 test_idivq(0x12343, 0x12345678, 0x81234567);
704
705 test_divq(0, 0x12345678abcdef, 12347);
706 test_divq(0, -233223, -45);
707 test_divq(0, 0x8000000000000000, -1);
708 test_divq(0x12343, 0x12345678, 0x81234567);
709#endif
4b74fe1f
FB		 710}
711
9d8e9c09
FB		 712#define TEST_BSX(op, size, op0)\
713{\
776f2227 714 long res, val, resz;\
9d8e9c09 715 val = op0;\
776f2227
FB		 716 asm("xor %1, %1\n"\
717 "mov $0x12345678, %0\n"\
7f5e1452 718 #op " %" size "2, %" size "0 ; setz %b1" \
9d8e9c09
FB		 719 : "=r" (res), "=q" (resz)\
720 : "g" (val));\
776f2227 721 printf("%-10s A=" FMTLX " R=" FMTLX " %ld\n", #op, val, res, resz);\
9d8e9c09
FB		 722}
723
724void test_bsx(void)
725{
726 TEST_BSX(bsrw, "w", 0);
727 TEST_BSX(bsrw, "w", 0x12340128);
9d8e9c09
FB		 728 TEST_BSX(bsfw, "w", 0);
729 TEST_BSX(bsfw, "w", 0x12340128);
776f2227
FB		 730 TEST_BSX(bsrl, "k", 0);
731 TEST_BSX(bsrl, "k", 0x00340128);
732 TEST_BSX(bsfl, "k", 0);
733 TEST_BSX(bsfl, "k", 0x00340128);
734#if defined(__x86_64__)
735 TEST_BSX(bsrq, "", 0);
736 TEST_BSX(bsrq, "", 0x003401281234);
737 TEST_BSX(bsfq, "", 0);
738 TEST_BSX(bsfq, "", 0x003401281234);
739#endif
9d8e9c09
FB		 740}
741
55480af8
FB		 742/**********************************************/
743
86bd2ca5
FB		 744union float64u {
745 double d;
746 uint64_t l;
747};
748
be98f1f8
FB		 749union float64u q_nan = { .l = 0xFFF8000000000000LL };
750union float64u s_nan = { .l = 0xFFF0000000000000LL };
86bd2ca5 751
9d8e9c09
FB		 752void test_fops(double a, double b)
753{
754 printf("a=%f b=%f a+b=%f\n", a, b, a + b);
755 printf("a=%f b=%f a-b=%f\n", a, b, a - b);
756 printf("a=%f b=%f a*b=%f\n", a, b, a * b);
757 printf("a=%f b=%f a/b=%f\n", a, b, a / b);
758 printf("a=%f b=%f fmod(a, b)=%f\n", a, b, fmod(a, b));
759 printf("a=%f sqrt(a)=%f\n", a, sqrt(a));
760 printf("a=%f sin(a)=%f\n", a, sin(a));
761 printf("a=%f cos(a)=%f\n", a, cos(a));
762 printf("a=%f tan(a)=%f\n", a, tan(a));
763 printf("a=%f log(a)=%f\n", a, log(a));
764 printf("a=%f exp(a)=%f\n", a, exp(a));
765 printf("a=%f b=%f atan2(a, b)=%f\n", a, b, atan2(a, b));
766 /* just to test some op combining */
767 printf("a=%f asin(sin(a))=%f\n", a, asin(sin(a)));
768 printf("a=%f acos(cos(a))=%f\n", a, acos(cos(a)));
769 printf("a=%f atan(tan(a))=%f\n", a, atan(tan(a)));
770
771}
772
86bd2ca5
FB		 773void fpu_clear_exceptions(void)
774{
775 struct __attribute__((packed)) {
776 uint16_t fpuc;
777 uint16_t dummy1;
778 uint16_t fpus;
779 uint16_t dummy2;
780 uint16_t fptag;
781 uint16_t dummy3;
782 uint32_t ignored[4];
783 long double fpregs[8];
784 } float_env32;
3b46e624 785
86bd2ca5
FB		 786 asm volatile ("fnstenv %0\n" : : "m" (float_env32));
787 float_env32.fpus &= ~0x7f;
788 asm volatile ("fldenv %0\n" : : "m" (float_env32));
789}
790
791/* XXX: display exception bits when supported */
792#define FPUS_EMASK 0x0000
793//#define FPUS_EMASK 0x007f
794
9d8e9c09
FB		 795void test_fcmp(double a, double b)
796{
86bd2ca5
FB		 797 long eflags, fpus;
798
799 fpu_clear_exceptions();
800 asm("fcom %2\n"
801 "fstsw %%ax\n"
802 : "=a" (fpus)
803 : "t" (a), "u" (b));
5fafdf24 804 printf("fcom(%f %f)=%04lx \n",
86bd2ca5
FB		 805 a, b, fpus & (0x4500 | FPUS_EMASK));
806 fpu_clear_exceptions();
807 asm("fucom %2\n"
808 "fstsw %%ax\n"
809 : "=a" (fpus)
810 : "t" (a), "u" (b));
5fafdf24 811 printf("fucom(%f %f)=%04lx\n",
86bd2ca5 812 a, b, fpus & (0x4500 | FPUS_EMASK));
03bfca94 813 if (TEST_FCOMI) {
03bfca94 814 /* test f(u)comi instruction */
86bd2ca5
FB		 815 fpu_clear_exceptions();
816 asm("fcomi %3, %2\n"
817 "fstsw %%ax\n"
03bfca94
FB		 818 "pushf\n"
819 "pop %0\n"
86bd2ca5 820 : "=r" (eflags), "=a" (fpus)
03bfca94 821 : "t" (a), "u" (b));
5fafdf24 822 printf("fcomi(%f %f)=%04lx %02lx\n",
86bd2ca5
FB		 823 a, b, fpus & FPUS_EMASK, eflags & (CC_Z | CC_P | CC_C));
824 fpu_clear_exceptions();
825 asm("fucomi %3, %2\n"
826 "fstsw %%ax\n"
827 "pushf\n"
828 "pop %0\n"
829 : "=r" (eflags), "=a" (fpus)
830 : "t" (a), "u" (b));
5fafdf24 831 printf("fucomi(%f %f)=%04lx %02lx\n",
86bd2ca5 832 a, b, fpus & FPUS_EMASK, eflags & (CC_Z | CC_P | CC_C));
03bfca94 833 }
86bd2ca5 834 fpu_clear_exceptions();
b2a8e592
FB		 835 asm volatile("fxam\n"
836 "fstsw %%ax\n"
837 : "=a" (fpus)
838 : "t" (a));
839 printf("fxam(%f)=%04lx\n", a, fpus & 0x4700);
840 fpu_clear_exceptions();
9d8e9c09
FB		 841}
842
843void test_fcvt(double a)
844{
845 float fa;
846 long double la;
ea768640
FB		 847 int16_t fpuc;
848 int i;
849 int64_t lla;
850 int ia;
851 int16_t wa;
852 double ra;
9d8e9c09
FB		 853
854 fa = a;
855 la = a;
856 printf("(float)%f = %f\n", a, fa);
857 printf("(long double)%f = %Lf\n", a, la);
776f2227 858 printf("a=" FMT64X "\n", *(uint64_t *)&a);
5fafdf24 859 printf("la=" FMT64X " %04x\n", *(uint64_t *)&la,
c5e9815d 860 *(unsigned short *)((char *)(&la) + 8));
ea768640
FB		 861
862 /* test all roundings */
863 asm volatile ("fstcw %0" : "=m" (fpuc));
864 for(i=0;i<4;i++) {
be98f1f8
FB		 865 uint16_t val16;
866 val16 = (fpuc & ~0x0c00) | (i << 10);
867 asm volatile ("fldcw %0" : : "m" (val16));
ea768640
FB		 868 asm volatile ("fist %0" : "=m" (wa) : "t" (a));
869 asm volatile ("fistl %0" : "=m" (ia) : "t" (a));
870 asm volatile ("fistpll %0" : "=m" (lla) : "t" (a) : "st");
871 asm volatile ("frndint ; fstl %0" : "=m" (ra) : "t" (a));
872 asm volatile ("fldcw %0" : : "m" (fpuc));
873 printf("(short)a = %d\n", wa);
874 printf("(int)a = %d\n", ia);
776f2227 875 printf("(int64_t)a = " FMT64X "\n", lla);
ea768640
FB		 876 printf("rint(a) = %f\n", ra);
877 }
9d8e9c09
FB		 878}
879
880#define TEST(N) \
881 asm("fld" #N : "=t" (a)); \
882 printf("fld" #N "= %f\n", a);
883
884void test_fconst(void)
885{
886 double a;
887 TEST(1);
888 TEST(l2t);
889 TEST(l2e);
890 TEST(pi);
891 TEST(lg2);
892 TEST(ln2);
893 TEST(z);
894}
895
c5e9815d
FB		 896void test_fbcd(double a)
897{
898 unsigned short bcd[5];
899 double b;
900
901 asm("fbstp %0" : "=m" (bcd[0]) : "t" (a) : "st");
902 asm("fbld %1" : "=t" (b) : "m" (bcd[0]));
5fafdf24 903 printf("a=%f bcd=%04x%04x%04x%04x%04x b=%f\n",
c5e9815d
FB		 904 a, bcd[4], bcd[3], bcd[2], bcd[1], bcd[0], b);
905}
906
6b2b6112 907#define TEST_ENV(env, save, restore)\
03bfca94
FB		 908{\
909 memset((env), 0xaa, sizeof(*(env)));\
6b2b6112
FB		 910 for(i=0;i<5;i++)\
911 asm volatile ("fldl %0" : : "m" (dtab[i]));\
085339a1
FB		 912 asm volatile (save " %0\n" : : "m" (*(env)));\
913 asm volatile (restore " %0\n": : "m" (*(env)));\
6b2b6112
FB		 914 for(i=0;i<5;i++)\
915 asm volatile ("fstpl %0" : "=m" (rtab[i]));\
916 for(i=0;i<5;i++)\
917 printf("res[%d]=%f\n", i, rtab[i]);\
03bfca94
FB		 918 printf("fpuc=%04x fpus=%04x fptag=%04x\n",\
919 (env)->fpuc,\
920 (env)->fpus & 0xff00,\
921 (env)->fptag);\
03bfca94
FB		 922}
923
924void test_fenv(void)
925{
926 struct __attribute__((packed)) {
927 uint16_t fpuc;
928 uint16_t dummy1;
929 uint16_t fpus;
930 uint16_t dummy2;
931 uint16_t fptag;
932 uint16_t dummy3;
933 uint32_t ignored[4];
934 long double fpregs[8];
935 } float_env32;
936 struct __attribute__((packed)) {
937 uint16_t fpuc;
938 uint16_t fpus;
939 uint16_t fptag;
940 uint16_t ignored[4];
941 long double fpregs[8];
942 } float_env16;
6b2b6112
FB		 943 double dtab[8];
944 double rtab[8];
945 int i;
946
947 for(i=0;i<8;i++)
948 dtab[i] = i + 1;
03bfca94 949
6b2b6112
FB		 950 TEST_ENV(&float_env16, "data16 fnstenv", "data16 fldenv");
951 TEST_ENV(&float_env16, "data16 fnsave", "data16 frstor");
952 TEST_ENV(&float_env32, "fnstenv", "fldenv");
953 TEST_ENV(&float_env32, "fnsave", "frstor");
665656a9
FB		 954
955 /* test for ffree */
956 for(i=0;i<5;i++)
957 asm volatile ("fldl %0" : : "m" (dtab[i]));
958 asm volatile("ffree %st(2)");
959 asm volatile ("fnstenv %0\n" : : "m" (float_env32));
960 asm volatile ("fninit");
961 printf("fptag=%04x\n", float_env32.fptag);
03bfca94
FB		 962}
963
75175024
FB		 964
965#define TEST_FCMOV(a, b, eflags, CC)\
966{\
967 double res;\
968 asm("push %3\n"\
969 "popf\n"\
970 "fcmov" CC " %2, %0\n"\
971 : "=t" (res)\
972 : "0" (a), "u" (b), "g" (eflags));\
776f2227
FB		 973 printf("fcmov%s eflags=0x%04lx-> %f\n", \
974 CC, (long)eflags, res);\
75175024
FB		 975}
976
977void test_fcmov(void)
978{
979 double a, b;
776f2227 980 long eflags, i;
75175024
FB		 981
982 a = 1.0;
983 b = 2.0;
984 for(i = 0; i < 4; i++) {
985 eflags = 0;
986 if (i & 1)
987 eflags |= CC_C;
988 if (i & 2)
989 eflags |= CC_Z;
990 TEST_FCMOV(a, b, eflags, "b");
991 TEST_FCMOV(a, b, eflags, "e");
992 TEST_FCMOV(a, b, eflags, "be");
993 TEST_FCMOV(a, b, eflags, "nb");
994 TEST_FCMOV(a, b, eflags, "ne");
995 TEST_FCMOV(a, b, eflags, "nbe");
996 }
997 TEST_FCMOV(a, b, 0, "u");
9cdf757f
FB		 998 TEST_FCMOV(a, b, CC_P, "u");
999 TEST_FCMOV(a, b, 0, "nu");
75175024
FB		 1000 TEST_FCMOV(a, b, CC_P, "nu");
1001}
1002
9d8e9c09
FB		 1003void test_floats(void)
1004{
1005 test_fops(2, 3);
1006 test_fops(1.4, -5);
1007 test_fcmp(2, -1);
1008 test_fcmp(2, 2);
1009 test_fcmp(2, 3);
86bd2ca5
FB		 1010 test_fcmp(2, q_nan.d);
1011 test_fcmp(q_nan.d, -1);
b2a8e592
FB		 1012 test_fcmp(-1.0/0.0, -1);
1013 test_fcmp(1.0/0.0, -1);
ea768640
FB		 1014 test_fcvt(0.5);
1015 test_fcvt(-0.5);
9d8e9c09
FB		 1016 test_fcvt(1.0/7.0);
1017 test_fcvt(-1.0/9.0);
ea768640
FB		 1018 test_fcvt(32768);
1019 test_fcvt(-1e20);
b2a8e592
FB		 1020 test_fcvt(-1.0/0.0);
1021 test_fcvt(1.0/0.0);
1022 test_fcvt(q_nan.d);
9d8e9c09 1023 test_fconst();
be98f1f8
FB		 1024 test_fbcd(1234567890123456.0);
1025 test_fbcd(-123451234567890.0);
03bfca94 1026 test_fenv();
75175024
FB		 1027 if (TEST_CMOV) {
1028 test_fcmov();
1029 }
9d8e9c09 1030}
4b74fe1f 1031
55480af8 1032/**********************************************/
776f2227 1033#if !defined(__x86_64__)
55480af8
FB		 1034
1035#define TEST_BCD(op, op0, cc_in, cc_mask)\
1036{\
1037 int res, flags;\
1038 res = op0;\
1039 flags = cc_in;\
1040 asm ("push %3\n\t"\
1041 "popf\n\t"\
1042 #op "\n\t"\
1043 "pushf\n\t"\
776f2227 1044 "pop %1\n\t"\
55480af8
FB		 1045 : "=a" (res), "=g" (flags)\
1046 : "0" (res), "1" (flags));\
1047 printf("%-10s A=%08x R=%08x CCIN=%04x CC=%04x\n",\
1048 #op, op0, res, cc_in, flags & cc_mask);\
1049}
1050
1051void test_bcd(void)
1052{
1053 TEST_BCD(daa, 0x12340503, CC_A, (CC_C | CC_P | CC_Z | CC_S | CC_A));
1054 TEST_BCD(daa, 0x12340506, CC_A, (CC_C | CC_P | CC_Z | CC_S | CC_A));
1055 TEST_BCD(daa, 0x12340507, CC_A, (CC_C | CC_P | CC_Z | CC_S | CC_A));
1056 TEST_BCD(daa, 0x12340559, CC_A, (CC_C | CC_P | CC_Z | CC_S | CC_A));
1057 TEST_BCD(daa, 0x12340560, CC_A, (CC_C | CC_P | CC_Z | CC_S | CC_A));
1058 TEST_BCD(daa, 0x1234059f, CC_A, (CC_C | CC_P | CC_Z | CC_S | CC_A));
1059 TEST_BCD(daa, 0x123405a0, CC_A, (CC_C | CC_P | CC_Z | CC_S | CC_A));
1060 TEST_BCD(daa, 0x12340503, 0, (CC_C | CC_P | CC_Z | CC_S | CC_A));
1061 TEST_BCD(daa, 0x12340506, 0, (CC_C | CC_P | CC_Z | CC_S | CC_A));
1062 TEST_BCD(daa, 0x12340503, CC_C, (CC_C | CC_P | CC_Z | CC_S | CC_A));
1063 TEST_BCD(daa, 0x12340506, CC_C, (CC_C | CC_P | CC_Z | CC_S | CC_A));
1064 TEST_BCD(daa, 0x12340503, CC_C | CC_A, (CC_C | CC_P | CC_Z | CC_S | CC_A));
1065 TEST_BCD(daa, 0x12340506, CC_C | CC_A, (CC_C | CC_P | CC_Z | CC_S | CC_A));
1066
1067 TEST_BCD(das, 0x12340503, CC_A, (CC_C | CC_P | CC_Z | CC_S | CC_A));
1068 TEST_BCD(das, 0x12340506, CC_A, (CC_C | CC_P | CC_Z | CC_S | CC_A));
1069 TEST_BCD(das, 0x12340507, CC_A, (CC_C | CC_P | CC_Z | CC_S | CC_A));
1070 TEST_BCD(das, 0x12340559, CC_A, (CC_C | CC_P | CC_Z | CC_S | CC_A));
1071 TEST_BCD(das, 0x12340560, CC_A, (CC_C | CC_P | CC_Z | CC_S | CC_A));
1072 TEST_BCD(das, 0x1234059f, CC_A, (CC_C | CC_P | CC_Z | CC_S | CC_A));
1073 TEST_BCD(das, 0x123405a0, CC_A, (CC_C | CC_P | CC_Z | CC_S | CC_A));
1074 TEST_BCD(das, 0x12340503, 0, (CC_C | CC_P | CC_Z | CC_S | CC_A));
1075 TEST_BCD(das, 0x12340506, 0, (CC_C | CC_P | CC_Z | CC_S | CC_A));
1076 TEST_BCD(das, 0x12340503, CC_C, (CC_C | CC_P | CC_Z | CC_S | CC_A));
1077 TEST_BCD(das, 0x12340506, CC_C, (CC_C | CC_P | CC_Z | CC_S | CC_A));
1078 TEST_BCD(das, 0x12340503, CC_C | CC_A, (CC_C | CC_P | CC_Z | CC_S | CC_A));
1079 TEST_BCD(das, 0x12340506, CC_C | CC_A, (CC_C | CC_P | CC_Z | CC_S | CC_A));
1080
1081 TEST_BCD(aaa, 0x12340205, CC_A, (CC_C | CC_A));
1082 TEST_BCD(aaa, 0x12340306, CC_A, (CC_C | CC_A));
1083 TEST_BCD(aaa, 0x1234040a, CC_A, (CC_C | CC_A));
1084 TEST_BCD(aaa, 0x123405fa, CC_A, (CC_C | CC_A));
1085 TEST_BCD(aaa, 0x12340205, 0, (CC_C | CC_A));
1086 TEST_BCD(aaa, 0x12340306, 0, (CC_C | CC_A));
1087 TEST_BCD(aaa, 0x1234040a, 0, (CC_C | CC_A));
1088 TEST_BCD(aaa, 0x123405fa, 0, (CC_C | CC_A));
3b46e624 1089
55480af8
FB		 1090 TEST_BCD(aas, 0x12340205, CC_A, (CC_C | CC_A));
1091 TEST_BCD(aas, 0x12340306, CC_A, (CC_C | CC_A));
1092 TEST_BCD(aas, 0x1234040a, CC_A, (CC_C | CC_A));
1093 TEST_BCD(aas, 0x123405fa, CC_A, (CC_C | CC_A));
1094 TEST_BCD(aas, 0x12340205, 0, (CC_C | CC_A));
1095 TEST_BCD(aas, 0x12340306, 0, (CC_C | CC_A));
1096 TEST_BCD(aas, 0x1234040a, 0, (CC_C | CC_A));
1097 TEST_BCD(aas, 0x123405fa, 0, (CC_C | CC_A));
1098
1099 TEST_BCD(aam, 0x12340547, CC_A, (CC_C | CC_P | CC_Z | CC_S | CC_O | CC_A));
1100 TEST_BCD(aad, 0x12340407, CC_A, (CC_C | CC_P | CC_Z | CC_S | CC_O | CC_A));
1101}
776f2227 1102#endif
55480af8 1103
e5918247
FB		 1104#define TEST_XCHG(op, size, opconst)\
1105{\
776f2227
FB		 1106 long op0, op1;\
1107 op0 = i2l(0x12345678);\
1108 op1 = i2l(0xfbca7654);\
e5918247
FB		 1109 asm(#op " %" size "0, %" size "1" \
1110 : "=q" (op0), opconst (op1) \
8aadfbf0 1111 : "0" (op0));\
776f2227 1112 printf("%-10s A=" FMTLX " B=" FMTLX "\n",\
e5918247
FB		 1113 #op, op0, op1);\
1114}
1115
1116#define TEST_CMPXCHG(op, size, opconst, eax)\
1117{\
776f2227
FB		 1118 long op0, op1, op2;\
1119 op0 = i2l(0x12345678);\
1120 op1 = i2l(0xfbca7654);\
1121 op2 = i2l(eax);\
e5918247
FB		 1122 asm(#op " %" size "0, %" size "1" \
1123 : "=q" (op0), opconst (op1) \
8aadfbf0 1124 : "0" (op0), "a" (op2));\
776f2227
FB		 1125 printf("%-10s EAX=" FMTLX " A=" FMTLX " C=" FMTLX "\n",\
1126 #op, op2, op0, op1);\
e5918247
FB		 1127}
1128
1129void test_xchg(void)
1130{
776f2227 1131#if defined(__x86_64__)
8aadfbf0 1132 TEST_XCHG(xchgq, "", "+q");
776f2227 1133#endif
8aadfbf0
FB		 1134 TEST_XCHG(xchgl, "k", "+q");
1135 TEST_XCHG(xchgw, "w", "+q");
1136 TEST_XCHG(xchgb, "b", "+q");
e5918247 1137
776f2227
FB		 1138#if defined(__x86_64__)
1139 TEST_XCHG(xchgq, "", "=m");
1140#endif
8aadfbf0
FB		 1141 TEST_XCHG(xchgl, "k", "+m");
1142 TEST_XCHG(xchgw, "w", "+m");
1143 TEST_XCHG(xchgb, "b", "+m");
e5918247 1144
776f2227 1145#if defined(__x86_64__)
8aadfbf0 1146 TEST_XCHG(xaddq, "", "+q");
776f2227 1147#endif
8aadfbf0
FB		 1148 TEST_XCHG(xaddl, "k", "+q");
1149 TEST_XCHG(xaddw, "w", "+q");
1150 TEST_XCHG(xaddb, "b", "+q");
e5918247 1151
d575b78a
FB		 1152 {
1153 int res;
1154 res = 0x12345678;
1155 asm("xaddl %1, %0" : "=r" (res) : "0" (res));
1156 printf("xaddl same res=%08x\n", res);
1157 }
1158
776f2227 1159#if defined(__x86_64__)
8aadfbf0 1160 TEST_XCHG(xaddq, "", "+m");
776f2227 1161#endif
8aadfbf0
FB		 1162 TEST_XCHG(xaddl, "k", "+m");
1163 TEST_XCHG(xaddw, "w", "+m");
1164 TEST_XCHG(xaddb, "b", "+m");
e5918247 1165
776f2227 1166#if defined(__x86_64__)
8aadfbf0 1167 TEST_CMPXCHG(cmpxchgq, "", "+q", 0xfbca7654);
776f2227 1168#endif
8aadfbf0
FB		 1169 TEST_CMPXCHG(cmpxchgl, "k", "+q", 0xfbca7654);
1170 TEST_CMPXCHG(cmpxchgw, "w", "+q", 0xfbca7654);
1171 TEST_CMPXCHG(cmpxchgb, "b", "+q", 0xfbca7654);
e5918247 1172
776f2227 1173#if defined(__x86_64__)
8aadfbf0 1174 TEST_CMPXCHG(cmpxchgq, "", "+q", 0xfffefdfc);
776f2227 1175#endif
8aadfbf0
FB		 1176 TEST_CMPXCHG(cmpxchgl, "k", "+q", 0xfffefdfc);
1177 TEST_CMPXCHG(cmpxchgw, "w", "+q", 0xfffefdfc);
1178 TEST_CMPXCHG(cmpxchgb, "b", "+q", 0xfffefdfc);
e5918247 1179
776f2227 1180#if defined(__x86_64__)
8aadfbf0 1181 TEST_CMPXCHG(cmpxchgq, "", "+m", 0xfbca7654);
776f2227 1182#endif
8aadfbf0
FB		 1183 TEST_CMPXCHG(cmpxchgl, "k", "+m", 0xfbca7654);
1184 TEST_CMPXCHG(cmpxchgw, "w", "+m", 0xfbca7654);
1185 TEST_CMPXCHG(cmpxchgb, "b", "+m", 0xfbca7654);
e5918247 1186
776f2227 1187#if defined(__x86_64__)
8aadfbf0 1188 TEST_CMPXCHG(cmpxchgq, "", "+m", 0xfffefdfc);
776f2227 1189#endif
8aadfbf0
FB		 1190 TEST_CMPXCHG(cmpxchgl, "k", "+m", 0xfffefdfc);
1191 TEST_CMPXCHG(cmpxchgw, "w", "+m", 0xfffefdfc);
1192 TEST_CMPXCHG(cmpxchgb, "b", "+m", 0xfffefdfc);
d575b78a
FB		 1193
1194 {
1195 uint64_t op0, op1, op2;
a5973fbf 1196 long eax, edx;
776f2227 1197 long i, eflags;
d575b78a
FB		 1198
1199 for(i = 0; i < 2; i++) {
be98f1f8 1200 op0 = 0x123456789abcdLL;
a5973fbf
FB		 1201 eax = i2l(op0 & 0xffffffff);
1202 edx = i2l(op0 >> 32);
d575b78a 1203 if (i == 0)
be98f1f8 1204 op1 = 0xfbca765423456LL;
d575b78a
FB		 1205 else
1206 op1 = op0;
be98f1f8 1207 op2 = 0x6532432432434LL;
a5973fbf 1208 asm("cmpxchg8b %2\n"
d575b78a 1209 "pushf\n"
a5973fbf
FB		 1210 "pop %3\n"
1211 : "=a" (eax), "=d" (edx), "=m" (op1), "=g" (eflags)
1212 : "0" (eax), "1" (edx), "m" (op1), "b" ((int)op2), "c" ((int)(op2 >> 32)));
1213 printf("cmpxchg8b: eax=" FMTLX " edx=" FMTLX " op1=" FMT64X " CC=%02lx\n",
1214 eax, edx, op1, eflags & CC_Z);
d575b78a
FB		 1215 }
1216 }
e5918247
FB		 1217}
1218
776f2227 1219#ifdef TEST_SEGS
6dbad63e
FB		 1220/**********************************************/
1221/* segmentation tests */
1222
be98f1f8
FB		 1223#include <sys/syscall.h>
1224#include <unistd.h>
6dbad63e 1225#include <asm/ldt.h>
73bdea19 1226#include <linux/version.h>
6dbad63e 1227
be98f1f8
FB		 1228static inline int modify_ldt(int func, void * ptr, unsigned long bytecount)
1229{
1230 return syscall(__NR_modify_ldt, func, ptr, bytecount);
1231}
6dbad63e 1232
73bdea19
FB		 1233#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 5, 66)
1234#define modify_ldt_ldt_s user_desc
1235#endif
1236
776f2227
FB		 1237#define MK_SEL(n) (((n) << 3) | 7)
1238
6dbad63e
FB		 1239uint8_t seg_data1[4096];
1240uint8_t seg_data2[4096];
1241
288426fe
FB		 1242#define TEST_LR(op, size, seg, mask)\
1243{\
1244 int res, res2;\
a5973fbf 1245 uint16_t mseg = seg;\
288426fe
FB		 1246 res = 0x12345678;\
1247 asm (op " %" size "2, %" size "0\n" \
1248 "movl $0, %1\n"\
1249 "jnz 1f\n"\
1250 "movl $1, %1\n"\
1251 "1:\n"\
a5973fbf 1252 : "=r" (res), "=r" (res2) : "m" (mseg), "0" (res));\
288426fe
FB		 1253 printf(op ": Z=%d %08x\n", res2, res & ~(mask));\
1254}
1255
a5973fbf
FB		 1256#define TEST_ARPL(op, size, op1, op2)\
1257{\
1258 long a, b, c; \
1259 a = (op1); \
1260 b = (op2); \
1261 asm volatile(op " %" size "3, %" size "0\n"\
1262 "movl $0,%1\n"\
1263 "jnz 1f\n"\
1264 "movl $1,%1\n"\
1265 "1:\n"\
1266 : "=r" (a), "=r" (c) : "0" (a), "r" (b)); \
1267 printf(op size " A=" FMTLX " B=" FMTLX " R=" FMTLX " z=%ld\n",\
1268 (long)(op1), (long)(op2), a, c);\
1269}
1270
6dbad63e
FB		 1271/* NOTE: we use Linux modify_ldt syscall */
1272void test_segs(void)
1273{
1274 struct modify_ldt_ldt_s ldt;
1275 long long ldt_table[3];
04369ff2 1276 int res, res2;
6dbad63e 1277 char tmp;
e1d4294a
FB		 1278 struct {
1279 uint32_t offset;
1280 uint16_t seg;
1281 } __attribute__((packed)) segoff;
6dbad63e
FB		 1282
1283 ldt.entry_number = 1;
1284 ldt.base_addr = (unsigned long)&seg_data1;
1285 ldt.limit = (sizeof(seg_data1) + 0xfff) >> 12;
1286 ldt.seg_32bit = 1;
1287 ldt.contents = MODIFY_LDT_CONTENTS_DATA;
1288 ldt.read_exec_only = 0;
1289 ldt.limit_in_pages = 1;
1290 ldt.seg_not_present = 0;
1291 ldt.useable = 1;
1292 modify_ldt(1, &ldt, sizeof(ldt)); /* write ldt entry */
1293
1294 ldt.entry_number = 2;
1295 ldt.base_addr = (unsigned long)&seg_data2;
1296 ldt.limit = (sizeof(seg_data2) + 0xfff) >> 12;
1297 ldt.seg_32bit = 1;
1298 ldt.contents = MODIFY_LDT_CONTENTS_DATA;
1299 ldt.read_exec_only = 0;
1300 ldt.limit_in_pages = 1;
1301 ldt.seg_not_present = 0;
1302 ldt.useable = 1;
1303 modify_ldt(1, &ldt, sizeof(ldt)); /* write ldt entry */
1304
1305 modify_ldt(0, &ldt_table, sizeof(ldt_table)); /* read ldt entries */
04369ff2
FB		 1306#if 0
1307 {
1308 int i;
1309 for(i=0;i<3;i++)
1310 printf("%d: %016Lx\n", i, ldt_table[i]);
1311 }
1312#endif
6dbad63e
FB		 1313 /* do some tests with fs or gs */
1314 asm volatile ("movl %0, %%fs" : : "r" (MK_SEL(1)));
6dbad63e
FB		 1315
1316 seg_data1[1] = 0xaa;
1317 seg_data2[1] = 0x55;
1318
1319 asm volatile ("fs movzbl 0x1, %0" : "=r" (res));
1320 printf("FS[1] = %02x\n", res);
1321
070893f4
FB		 1322 asm volatile ("pushl %%gs\n"
1323 "movl %1, %%gs\n"
1324 "gs movzbl 0x1, %0\n"
1325 "popl %%gs\n"
1326 : "=r" (res)
1327 : "r" (MK_SEL(2)));
6dbad63e
FB		 1328 printf("GS[1] = %02x\n", res);
1329
1330 /* tests with ds/ss (implicit segment case) */
1331 tmp = 0xa5;
1332 asm volatile ("pushl %%ebp\n\t"
1333 "pushl %%ds\n\t"
1334 "movl %2, %%ds\n\t"
1335 "movl %3, %%ebp\n\t"
1336 "movzbl 0x1, %0\n\t"
1337 "movzbl (%%ebp), %1\n\t"
1338 "popl %%ds\n\t"
1339 "popl %%ebp\n\t"
1340 : "=r" (res), "=r" (res2)
1341 : "r" (MK_SEL(1)), "r" (&tmp));
1342 printf("DS[1] = %02x\n", res);
1343 printf("SS[tmp] = %02x\n", res2);
e1d4294a
FB		 1344
1345 segoff.seg = MK_SEL(2);
1346 segoff.offset = 0xabcdef12;
5fafdf24 1347 asm volatile("lfs %2, %0\n\t"
e1d4294a 1348 "movl %%fs, %1\n\t"
5fafdf24 1349 : "=r" (res), "=g" (res2)
e1d4294a
FB		 1350 : "m" (segoff));
1351 printf("FS:reg = %04x:%08x\n", res2, res);
288426fe
FB		 1352
1353 TEST_LR("larw", "w", MK_SEL(2), 0x0100);
1354 TEST_LR("larl", "", MK_SEL(2), 0x0100);
1355 TEST_LR("lslw", "w", MK_SEL(2), 0);
1356 TEST_LR("lsll", "", MK_SEL(2), 0);
1357
1358 TEST_LR("larw", "w", 0xfff8, 0);
1359 TEST_LR("larl", "", 0xfff8, 0);
1360 TEST_LR("lslw", "w", 0xfff8, 0);
1361 TEST_LR("lsll", "", 0xfff8, 0);
a5973fbf
FB		 1362
1363 TEST_ARPL("arpl", "w", 0x12345678 | 3, 0x762123c | 1);
1364 TEST_ARPL("arpl", "w", 0x12345678 | 1, 0x762123c | 3);
1365 TEST_ARPL("arpl", "w", 0x12345678 | 1, 0x762123c | 1);
6dbad63e 1366}
55480af8 1367
e5918247
FB		 1368/* 16 bit code test */
1369extern char code16_start, code16_end;
1370extern char code16_func1;
1371extern char code16_func2;
1372extern char code16_func3;
a300e691 1373
e5918247 1374void test_code16(void)
1a9353d2 1375{
e5918247
FB		 1376 struct modify_ldt_ldt_s ldt;
1377 int res, res2;
a300e691 1378
e5918247
FB		 1379 /* build a code segment */
1380 ldt.entry_number = 1;
1381 ldt.base_addr = (unsigned long)&code16_start;
1382 ldt.limit = &code16_end - &code16_start;
1383 ldt.seg_32bit = 0;
1384 ldt.contents = MODIFY_LDT_CONTENTS_CODE;
1385 ldt.read_exec_only = 0;
1386 ldt.limit_in_pages = 0;
1387 ldt.seg_not_present = 0;
1388 ldt.useable = 1;
1389 modify_ldt(1, &ldt, sizeof(ldt)); /* write ldt entry */
a300e691 1390
e5918247 1391 /* call the first function */
5fafdf24 1392 asm volatile ("lcall %1, %2"
e5918247
FB		 1393 : "=a" (res)
1394 : "i" (MK_SEL(1)), "i" (&code16_func1): "memory", "cc");
1395 printf("func1() = 0x%08x\n", res);
5fafdf24 1396 asm volatile ("lcall %2, %3"
e5918247
FB		 1397 : "=a" (res), "=c" (res2)
1398 : "i" (MK_SEL(1)), "i" (&code16_func2): "memory", "cc");
1399 printf("func2() = 0x%08x spdec=%d\n", res, res2);
5fafdf24 1400 asm volatile ("lcall %1, %2"
e5918247
FB		 1401 : "=a" (res)
1402 : "i" (MK_SEL(1)), "i" (&code16_func3): "memory", "cc");
1403 printf("func3() = 0x%08x\n", res);
1a9353d2 1404}
776f2227 1405#endif
1a9353d2 1406
e06e5259
FB		 1407#if defined(__x86_64__)
1408asm(".globl func_lret\n"
1409 "func_lret:\n"
1410 "movl $0x87654641, %eax\n"
1411 "lretq\n");
1412#else
1413asm(".globl func_lret\n"
1414 "func_lret:\n"
1415 "movl $0x87654321, %eax\n"
1416 "lret\n"
1417
1418 ".globl func_iret\n"
1419 "func_iret:\n"
1420 "movl $0xabcd4321, %eax\n"
1421 "iret\n");
1422#endif
1423
1424extern char func_lret;
1425extern char func_iret;
dd3587f3 1426
e1d4294a
FB		 1427void test_misc(void)
1428{
1429 char table[256];
776f2227 1430 long res, i;
e1d4294a
FB		 1431
1432 for(i=0;i<256;i++) table[i] = 256 - i;
1433 res = 0x12345678;
1434 asm ("xlat" : "=a" (res) : "b" (table), "0" (res));
776f2227 1435 printf("xlat: EAX=" FMTLX "\n", res);
dd3587f3 1436
e06e5259 1437#if defined(__x86_64__)
8aadfbf0 1438#if 0
e06e5259 1439 {
8aadfbf0
FB		 1440 /* XXX: see if Intel Core2 and AMD64 behavior really
1441 differ. Here we implemented the Intel way which is not
1442 compatible yet with QEMU. */
e06e5259 1443 static struct __attribute__((packed)) {
8aadfbf0 1444 uint64_t offset;
e06e5259
FB		 1445 uint16_t seg;
1446 } desc;
1447 long cs_sel;
1448
1449 asm volatile ("mov %%cs, %0" : "=r" (cs_sel));
1450
1451 asm volatile ("push %1\n"
5fafdf24 1452 "call func_lret\n"
e06e5259
FB		 1453 : "=a" (res)
1454 : "r" (cs_sel) : "memory", "cc");
1455 printf("func_lret=" FMTLX "\n", res);
1456
e06e5259
FB		 1457 desc.offset = (long)&func_lret;
1458 desc.seg = cs_sel;
3b46e624 1459
e06e5259 1460 asm volatile ("xor %%rax, %%rax\n"
8aadfbf0 1461 "rex64 lcall *(%%rcx)\n"
e06e5259 1462 : "=a" (res)
8aadfbf0 1463 : "c" (&desc)
e06e5259
FB		 1464 : "memory", "cc");
1465 printf("func_lret2=" FMTLX "\n", res);
1466
1467 asm volatile ("push %2\n"
1468 "mov $ 1f, %%rax\n"
1469 "push %%rax\n"
8aadfbf0 1470 "rex64 ljmp *(%%rcx)\n"
e06e5259
FB		 1471 "1:\n"
1472 : "=a" (res)
8aadfbf0 1473 : "c" (&desc), "b" (cs_sel)
e06e5259
FB		 1474 : "memory", "cc");
1475 printf("func_lret3=" FMTLX "\n", res);
1476 }
8aadfbf0 1477#endif
e06e5259 1478#else
5fafdf24 1479 asm volatile ("push %%cs ; call %1"
dd3587f3 1480 : "=a" (res)
e06e5259
FB		 1481 : "m" (func_lret): "memory", "cc");
1482 printf("func_lret=" FMTLX "\n", res);
dd3587f3 1483
5fafdf24 1484 asm volatile ("pushf ; push %%cs ; call %1"
dd3587f3 1485 : "=a" (res)
e06e5259
FB		 1486 : "m" (func_iret): "memory", "cc");
1487 printf("func_iret=" FMTLX "\n", res);
776f2227 1488#endif
dd3587f3 1489
776f2227
FB		 1490#if defined(__x86_64__)
1491 /* specific popl test */
1492 asm volatile ("push $12345432 ; push $0x9abcdef ; pop (%%rsp) ; pop %0"
1493 : "=g" (res));
1494 printf("popl esp=" FMTLX "\n", res);
1495#else
dd3587f3
FB		 1496 /* specific popl test */
1497 asm volatile ("pushl $12345432 ; pushl $0x9abcdef ; popl (%%esp) ; popl %0"
1498 : "=g" (res));
776f2227 1499 printf("popl esp=" FMTLX "\n", res);
b2b5fb22
FB		 1500
1501 /* specific popw test */
1502 asm volatile ("pushl $12345432 ; pushl $0x9abcdef ; popw (%%esp) ; addl $2, %%esp ; popl %0"
1503 : "=g" (res));
776f2227
FB		 1504 printf("popw esp=" FMTLX "\n", res);
1505#endif
e1d4294a
FB		 1506}
1507
1508uint8_t str_buffer[4096];
1509
1510#define TEST_STRING1(OP, size, DF, REP)\
1511{\
776f2227 1512 long esi, edi, eax, ecx, eflags;\
e1d4294a
FB		 1513\
1514 esi = (long)(str_buffer + sizeof(str_buffer) / 2);\
1515 edi = (long)(str_buffer + sizeof(str_buffer) / 2) + 16;\
776f2227 1516 eax = i2l(0x12345678);\
e1d4294a
FB		 1517 ecx = 17;\
1518\
776f2227 1519 asm volatile ("push $0\n\t"\
e1d4294a
FB		 1520 "popf\n\t"\
1521 DF "\n\t"\
1522 REP #OP size "\n\t"\
1523 "cld\n\t"\
1524 "pushf\n\t"\
776f2227 1525 "pop %4\n\t"\
e1d4294a
FB		 1526 : "=S" (esi), "=D" (edi), "=a" (eax), "=c" (ecx), "=g" (eflags)\
1527 : "0" (esi), "1" (edi), "2" (eax), "3" (ecx));\
776f2227 1528 printf("%-10s ESI=" FMTLX " EDI=" FMTLX " EAX=" FMTLX " ECX=" FMTLX " EFL=%04x\n",\
e1d4294a 1529 REP #OP size, esi, edi, eax, ecx,\
776f2227 1530 (int)(eflags & (CC_C | CC_P | CC_Z | CC_S | CC_O | CC_A)));\
e1d4294a
FB		 1531}
1532
1533#define TEST_STRING(OP, REP)\
1534 TEST_STRING1(OP, "b", "", REP);\
1535 TEST_STRING1(OP, "w", "", REP);\
1536 TEST_STRING1(OP, "l", "", REP);\
776f2227 1537 X86_64_ONLY(TEST_STRING1(OP, "q", "", REP));\
e1d4294a
FB		 1538 TEST_STRING1(OP, "b", "std", REP);\
1539 TEST_STRING1(OP, "w", "std", REP);\
776f2227
FB		 1540 TEST_STRING1(OP, "l", "std", REP);\
1541 X86_64_ONLY(TEST_STRING1(OP, "q", "std", REP))
e1d4294a
FB		 1542
1543void test_string(void)
1544{
1545 int i;
1546 for(i = 0;i < sizeof(str_buffer); i++)
1547 str_buffer[i] = i + 0x56;
1548 TEST_STRING(stos, "");
1549 TEST_STRING(stos, "rep ");
1550 TEST_STRING(lods, ""); /* to verify stos */
5fafdf24 1551 TEST_STRING(lods, "rep ");
e1d4294a
FB		 1552 TEST_STRING(movs, "");
1553 TEST_STRING(movs, "rep ");
1554 TEST_STRING(lods, ""); /* to verify stos */
1555
1556 /* XXX: better tests */
1557 TEST_STRING(scas, "");
1558 TEST_STRING(scas, "repz ");
1559 TEST_STRING(scas, "repnz ");
1560 TEST_STRING(cmps, "");
1561 TEST_STRING(cmps, "repz ");
1562 TEST_STRING(cmps, "repnz ");
1563}
e5918247 1564
776f2227 1565#ifdef TEST_VM86
3a27ad0b
FB		 1566/* VM86 test */
1567
1568static inline void set_bit(uint8_t *a, unsigned int bit)
1569{
1570 a[bit / 8] |= (1 << (bit % 8));
1571}
1572
1573static inline uint8_t *seg_to_linear(unsigned int seg, unsigned int reg)
1574{
1575 return (uint8_t *)((seg << 4) + (reg & 0xffff));
1576}
1577
1578static inline void pushw(struct vm86_regs *r, int val)
1579{
1580 r->esp = (r->esp & ~0xffff) | ((r->esp - 2) & 0xffff);
1581 *(uint16_t *)seg_to_linear(r->ss, r->esp) = val;
1582}
1583
be98f1f8
FB		 1584static inline int vm86(int func, struct vm86plus_struct *v86)
1585{
1586 return syscall(__NR_vm86, func, v86);
1587}
3a27ad0b
FB		 1588
1589extern char vm86_code_start;
1590extern char vm86_code_end;
1591
1592#define VM86_CODE_CS 0x100
1593#define VM86_CODE_IP 0x100
1594
1595void test_vm86(void)
1596{
1597 struct vm86plus_struct ctx;
1598 struct vm86_regs *r;
1599 uint8_t *vm86_mem;
1600 int seg, ret;
1601
5fafdf24
TS		 1602 vm86_mem = mmap((void *)0x00000000, 0x110000,
1603 PROT_WRITE | PROT_READ | PROT_EXEC,
3a27ad0b
FB		 1604 MAP_FIXED | MAP_ANON | MAP_PRIVATE, -1, 0);
1605 if (vm86_mem == MAP_FAILED) {
1606 printf("ERROR: could not map vm86 memory");
1607 return;
1608 }
1609 memset(&ctx, 0, sizeof(ctx));
1610
1611 /* init basic registers */
1612 r = &ctx.regs;
1613 r->eip = VM86_CODE_IP;
1614 r->esp = 0xfffe;
1615 seg = VM86_CODE_CS;
1616 r->cs = seg;
1617 r->ss = seg;
1618 r->ds = seg;
1619 r->es = seg;
1620 r->fs = seg;
1621 r->gs = seg;
1622 r->eflags = VIF_MASK;
1623
1624 /* move code to proper address. We use the same layout as a .com
1625 dos program. */
5fafdf24 1626 memcpy(vm86_mem + (VM86_CODE_CS << 4) + VM86_CODE_IP,
3a27ad0b
FB		 1627 &vm86_code_start, &vm86_code_end - &vm86_code_start);
1628
1629 /* mark int 0x21 as being emulated */
1630 set_bit((uint8_t *)&ctx.int_revectored, 0x21);
1631
1632 for(;;) {
1633 ret = vm86(VM86_ENTER, &ctx);
1634 switch(VM86_TYPE(ret)) {
1635 case VM86_INTx:
1636 {
3ff0631e 1637 int int_num, ah, v;
3b46e624 1638
3a27ad0b
FB		 1639 int_num = VM86_ARG(ret);
1640 if (int_num != 0x21)
1641 goto unknown_int;
1642 ah = (r->eax >> 8) & 0xff;
1643 switch(ah) {
1644 case 0x00: /* exit */
1645 goto the_end;
1646 case 0x02: /* write char */
1647 {
1648 uint8_t c = r->edx;
1649 putchar(c);
1650 }
1651 break;
1652 case 0x09: /* write string */
1653 {
1654 uint8_t c, *ptr;
1655 ptr = seg_to_linear(r->ds, r->edx);
1656 for(;;) {
1657 c = *ptr++;
1658 if (c == '$')
1659 break;
1660 putchar(c);
1661 }
1662 r->eax = (r->eax & ~0xff) | '$';
1663 }
1664 break;
3ff0631e
FB		 1665 case 0xff: /* extension: write eflags number in edx */
1666 v = (int)r->edx;
1667#ifndef LINUX_VM86_IOPL_FIX
1668 v &= ~0x3000;
1669#endif
1670 printf("%08x\n", v);
3a27ad0b
FB		 1671 break;
1672 default:
1673 unknown_int:
1674 printf("unsupported int 0x%02x\n", int_num);
1675 goto the_end;
1676 }
1677 }
1678 break;
1679 case VM86_SIGNAL:
1680 /* a signal came, we just ignore that */
1681 break;
1682 case VM86_STI:
1683 break;
1684 default:
1685 printf("ERROR: unhandled vm86 return code (0x%x)\n", ret);
1686 goto the_end;
1687 }
1688 }
1689 the_end:
1690 printf("VM86 end\n");
1691 munmap(vm86_mem, 0x110000);
1692}
776f2227 1693#endif
3a27ad0b
FB		 1694
1695/* exception tests */
776f2227 1696#if defined(__i386__) && !defined(REG_EAX)
3a27ad0b
FB		 1697#define REG_EAX EAX
1698#define REG_EBX EBX
1699#define REG_ECX ECX
1700#define REG_EDX EDX
1701#define REG_ESI ESI
1702#define REG_EDI EDI
1703#define REG_EBP EBP
1704#define REG_ESP ESP
1705#define REG_EIP EIP
1706#define REG_EFL EFL
1707#define REG_TRAPNO TRAPNO
1708#define REG_ERR ERR
1709#endif
1710
776f2227
FB		 1711#if defined(__x86_64__)
1712#define REG_EIP REG_RIP
1713#endif
1714
3a27ad0b 1715jmp_buf jmp_env;
3a27ad0b
FB		 1716int v1;
1717int tab[2];
1718
1719void sig_handler(int sig, siginfo_t *info, void *puc)
1720{
1721 struct ucontext *uc = puc;
1722
1723 printf("si_signo=%d si_errno=%d si_code=%d",
1724 info->si_signo, info->si_errno, info->si_code);
e3b32540
FB		 1725 printf(" si_addr=0x%08lx",
1726 (unsigned long)info->si_addr);
3a27ad0b
FB		 1727 printf("\n");
1728
776f2227
FB		 1729 printf("trapno=" FMTLX " err=" FMTLX,
1730 (long)uc->uc_mcontext.gregs[REG_TRAPNO],
1731 (long)uc->uc_mcontext.gregs[REG_ERR]);
1732 printf(" EIP=" FMTLX, (long)uc->uc_mcontext.gregs[REG_EIP]);
3a27ad0b
FB		 1733 printf("\n");
1734 longjmp(jmp_env, 1);
1735}
1736
1737void test_exceptions(void)
1738{
1739 struct sigaction act;
1740 volatile int val;
3b46e624 1741
3a27ad0b
FB		 1742 act.sa_sigaction = sig_handler;
1743 sigemptyset(&act.sa_mask);
776f2227 1744 act.sa_flags = SA_SIGINFO | SA_NODEFER;
3a27ad0b
FB		 1745 sigaction(SIGFPE, &act, NULL);
1746 sigaction(SIGILL, &act, NULL);
1747 sigaction(SIGSEGV, &act, NULL);
e3b32540 1748 sigaction(SIGBUS, &act, NULL);
3a27ad0b
FB		 1749 sigaction(SIGTRAP, &act, NULL);
1750
1751 /* test division by zero reporting */
e3b32540 1752 printf("DIVZ exception:\n");
3a27ad0b
FB		 1753 if (setjmp(jmp_env) == 0) {
1754 /* now divide by zero */
1755 v1 = 0;
1756 v1 = 2 / v1;
1757 }
1758
776f2227 1759#if !defined(__x86_64__)
e3b32540 1760 printf("BOUND exception:\n");
3a27ad0b
FB		 1761 if (setjmp(jmp_env) == 0) {
1762 /* bound exception */
1763 tab[0] = 1;
1764 tab[1] = 10;
e82d8ade 1765 asm volatile ("bound %0, %1" : : "r" (11), "m" (tab[0]));
3a27ad0b 1766 }
776f2227 1767#endif
3a27ad0b 1768
776f2227 1769#ifdef TEST_SEGS
e3b32540
FB		 1770 printf("segment exceptions:\n");
1771 if (setjmp(jmp_env) == 0) {
1772 /* load an invalid segment */
1773 asm volatile ("movl %0, %%fs" : : "r" ((0x1234 << 3) | 1));
1774 }
1775 if (setjmp(jmp_env) == 0) {
1776 /* null data segment is valid */
1777 asm volatile ("movl %0, %%fs" : : "r" (3));
1778 /* null stack segment */
1779 asm volatile ("movl %0, %%ss" : : "r" (3));
1780 }
1781
776f2227
FB		 1782 {
1783 struct modify_ldt_ldt_s ldt;
1784 ldt.entry_number = 1;
1785 ldt.base_addr = (unsigned long)&seg_data1;
1786 ldt.limit = (sizeof(seg_data1) + 0xfff) >> 12;
1787 ldt.seg_32bit = 1;
1788 ldt.contents = MODIFY_LDT_CONTENTS_DATA;
1789 ldt.read_exec_only = 0;
1790 ldt.limit_in_pages = 1;
1791 ldt.seg_not_present = 1;
1792 ldt.useable = 1;
1793 modify_ldt(1, &ldt, sizeof(ldt)); /* write ldt entry */
3b46e624 1794
776f2227
FB		 1795 if (setjmp(jmp_env) == 0) {
1796 /* segment not present */
1797 asm volatile ("movl %0, %%fs" : : "r" (MK_SEL(1)));
1798 }
e3b32540 1799 }
776f2227 1800#endif
e3b32540 1801
3a27ad0b 1802 /* test SEGV reporting */
e3b32540 1803 printf("PF exception:\n");
3a27ad0b 1804 if (setjmp(jmp_env) == 0) {
e3b32540 1805 val = 1;
ede28208
FB		 1806 /* we add a nop to test a weird PC retrieval case */
1807 asm volatile ("nop");
3a27ad0b
FB		 1808 /* now store in an invalid address */
1809 *(char *)0x1234 = 1;
1810 }
1811
1812 /* test SEGV reporting */
e3b32540 1813 printf("PF exception:\n");
3a27ad0b 1814 if (setjmp(jmp_env) == 0) {
e3b32540 1815 val = 1;
3a27ad0b
FB		 1816 /* read from an invalid address */
1817 v1 = *(char *)0x1234;
1818 }
3b46e624 1819
3a27ad0b
FB		 1820 /* test illegal instruction reporting */
1821 printf("UD2 exception:\n");
1822 if (setjmp(jmp_env) == 0) {
1823 /* now execute an invalid instruction */
1824 asm volatile("ud2");
1825 }
4120b61d
FB		 1826 printf("lock nop exception:\n");
1827 if (setjmp(jmp_env) == 0) {
1828 /* now execute an invalid instruction */
1829 asm volatile("lock nop");
1830 }
3b46e624 1831
3a27ad0b
FB		 1832 printf("INT exception:\n");
1833 if (setjmp(jmp_env) == 0) {
1834 asm volatile ("int $0xfd");
1835 }
e3b32540
FB		 1836 if (setjmp(jmp_env) == 0) {
1837 asm volatile ("int $0x01");
1838 }
1839 if (setjmp(jmp_env) == 0) {
1840 asm volatile (".byte 0xcd, 0x03");
1841 }
1842 if (setjmp(jmp_env) == 0) {
1843 asm volatile ("int $0x04");
1844 }
1845 if (setjmp(jmp_env) == 0) {
1846 asm volatile ("int $0x05");
1847 }
3a27ad0b
FB		 1848
1849 printf("INT3 exception:\n");
1850 if (setjmp(jmp_env) == 0) {
1851 asm volatile ("int3");
1852 }
1853
1854 printf("CLI exception:\n");
1855 if (setjmp(jmp_env) == 0) {
1856 asm volatile ("cli");
1857 }
1858
1859 printf("STI exception:\n");
1860 if (setjmp(jmp_env) == 0) {
1861 asm volatile ("cli");
1862 }
1863
776f2227 1864#if !defined(__x86_64__)
3a27ad0b
FB		 1865 printf("INTO exception:\n");
1866 if (setjmp(jmp_env) == 0) {
1867 /* overflow exception */
1868 asm volatile ("addl $1, %0 ; into" : : "r" (0x7fffffff));
1869 }
776f2227 1870#endif
3a27ad0b
FB		 1871
1872 printf("OUTB exception:\n");
1873 if (setjmp(jmp_env) == 0) {
1874 asm volatile ("outb %%al, %%dx" : : "d" (0x4321), "a" (0));
1875 }
1876
1877 printf("INB exception:\n");
1878 if (setjmp(jmp_env) == 0) {
1879 asm volatile ("inb %%dx, %%al" : "=a" (val) : "d" (0x4321));
1880 }
1881
1882 printf("REP OUTSB exception:\n");
1883 if (setjmp(jmp_env) == 0) {
1884 asm volatile ("rep outsb" : : "d" (0x4321), "S" (tab), "c" (1));
1885 }
1886
1887 printf("REP INSB exception:\n");
1888 if (setjmp(jmp_env) == 0) {
1889 asm volatile ("rep insb" : : "d" (0x4321), "D" (tab), "c" (1));
1890 }
1891
1892 printf("HLT exception:\n");
1893 if (setjmp(jmp_env) == 0) {
1894 asm volatile ("hlt");
1895 }
1896
1897 printf("single step exception:\n");
1898 val = 0;
1899 if (setjmp(jmp_env) == 0) {
1900 asm volatile ("pushf\n"
1901 "orl $0x00100, (%%esp)\n"
1902 "popf\n"
5fafdf24 1903 "movl $0xabcd, %0\n"
3a27ad0b
FB		 1904 "movl $0x0, %0\n" : "=m" (val) : : "cc", "memory");
1905 }
1906 printf("val=0x%x\n", val);
1907}
1908
776f2227 1909#if !defined(__x86_64__)
3ff0631e
FB		 1910/* specific precise single step test */
1911void sig_trap_handler(int sig, siginfo_t *info, void *puc)
1912{
1913 struct ucontext *uc = puc;
776f2227 1914 printf("EIP=" FMTLX "\n", (long)uc->uc_mcontext.gregs[REG_EIP]);
3ff0631e
FB		 1915}
1916
1917const uint8_t sstep_buf1[4] = { 1, 2, 3, 4};
1918uint8_t sstep_buf2[4];
1919
1920void test_single_step(void)
1921{
1922 struct sigaction act;
1923 volatile int val;
1924 int i;
1925
1926 val = 0;
1927 act.sa_sigaction = sig_trap_handler;
1928 sigemptyset(&act.sa_mask);
1929 act.sa_flags = SA_SIGINFO;
1930 sigaction(SIGTRAP, &act, NULL);
1931 asm volatile ("pushf\n"
1932 "orl $0x00100, (%%esp)\n"
1933 "popf\n"
5fafdf24 1934 "movl $0xabcd, %0\n"
3ff0631e
FB		 1935
1936 /* jmp test */
1937 "movl $3, %%ecx\n"
1938 "1:\n"
1939 "addl $1, %0\n"
1940 "decl %%ecx\n"
1941 "jnz 1b\n"
1942
1943 /* movsb: the single step should stop at each movsb iteration */
1944 "movl $sstep_buf1, %%esi\n"
1945 "movl $sstep_buf2, %%edi\n"
1946 "movl $0, %%ecx\n"
1947 "rep movsb\n"
1948 "movl $3, %%ecx\n"
1949 "rep movsb\n"
1950 "movl $1, %%ecx\n"
1951 "rep movsb\n"
1952
1953 /* cmpsb: the single step should stop at each cmpsb iteration */
1954 "movl $sstep_buf1, %%esi\n"
1955 "movl $sstep_buf2, %%edi\n"
1956 "movl $0, %%ecx\n"
1957 "rep cmpsb\n"
1958 "movl $4, %%ecx\n"
1959 "rep cmpsb\n"
3b46e624 1960
3ff0631e
FB		 1961 /* getpid() syscall: single step should skip one
1962 instruction */
1963 "movl $20, %%eax\n"
1964 "int $0x80\n"
1965 "movl $0, %%eax\n"
3b46e624 1966
3ff0631e
FB		 1967 /* when modifying SS, trace is not done on the next
1968 instruction */
1969 "movl %%ss, %%ecx\n"
1970 "movl %%ecx, %%ss\n"
1971 "addl $1, %0\n"
1972 "movl $1, %%eax\n"
1973 "movl %%ecx, %%ss\n"
1974 "jmp 1f\n"
1975 "addl $1, %0\n"
1976 "1:\n"
1977 "movl $1, %%eax\n"
1978 "pushl %%ecx\n"
1979 "popl %%ss\n"
1980 "addl $1, %0\n"
1981 "movl $1, %%eax\n"
3b46e624 1982
3ff0631e
FB		 1983 "pushf\n"
1984 "andl $~0x00100, (%%esp)\n"
1985 "popf\n"
5fafdf24
TS		 1986 : "=m" (val)
1987 :
3ff0631e
FB		 1988 : "cc", "memory", "eax", "ecx", "esi", "edi");
1989 printf("val=%d\n", val);
1990 for(i = 0; i < 4; i++)
1991 printf("sstep_buf2[%d] = %d\n", i, sstep_buf2[i]);
1992}
1993
3a27ad0b
FB		 1994/* self modifying code test */
1995uint8_t code[] = {
1996 0xb8, 0x1, 0x00, 0x00, 0x00, /* movl $1, %eax */
1997 0xc3, /* ret */
1998};
1999
a5973fbf
FB		 2000asm(".section \".data\"\n"
2001 "smc_code2:\n"
1190935d
FB		 2002 "movl 4(%esp), %eax\n"
2003 "movl %eax, smc_patch_addr2 + 1\n"
2004 "nop\n"
2005 "nop\n"
2006 "nop\n"
2007 "nop\n"
2008 "nop\n"
2009 "nop\n"
2010 "nop\n"
2011 "nop\n"
2012 "smc_patch_addr2:\n"
2013 "movl $1, %eax\n"
a5973fbf
FB		 2014 "ret\n"
2015 ".previous\n"
2016 );
d1fe2b24 2017
1190935d
FB		 2018typedef int FuncType(void);
2019extern int smc_code2(int);
3a27ad0b
FB		 2020void test_self_modifying_code(void)
2021{
d1fe2b24 2022 int i;
3a27ad0b 2023 printf("self modifying code:\n");
d1fe2b24
FB		 2024 printf("func1 = 0x%x\n", ((FuncType *)code)());
2025 for(i = 2; i <= 4; i++) {
2026 code[1] = i;
2027 printf("func%d = 0x%x\n", i, ((FuncType *)code)());
2028 }
1190935d
FB		 2029
2030 /* more difficult test : the modified code is just after the
2031 modifying instruction. It is forbidden in Intel specs, but it
2032 is used by old DOS programs */
2033 for(i = 2; i <= 4; i++) {
2034 printf("smc_code2(%d) = %d\n", i, smc_code2(i));
2035 }
3a27ad0b 2036}
776f2227 2037#endif
61a8c4ec 2038
776f2227
FB		 2039long enter_stack[4096];
2040
2041#if defined(__x86_64__)
2042#define RSP "%%rsp"
2043#define RBP "%%rbp"
2044#else
2045#define RSP "%%esp"
2046#define RBP "%%ebp"
2047#endif
61a8c4ec
FB		 2048
2049#define TEST_ENTER(size, stack_type, level)\
2050{\
776f2227 2051 long esp_save, esp_val, ebp_val, ebp_save, i;\
61a8c4ec
FB		 2052 stack_type *ptr, *stack_end, *stack_ptr;\
2053 memset(enter_stack, 0, sizeof(enter_stack));\
2054 stack_end = stack_ptr = (stack_type *)(enter_stack + 4096);\
2055 ebp_val = (long)stack_ptr;\
2056 for(i=1;i<=32;i++)\
2057 *--stack_ptr = i;\
2058 esp_val = (long)stack_ptr;\
776f2227
FB		 2059 asm("mov " RSP ", %[esp_save]\n"\
2060 "mov " RBP ", %[ebp_save]\n"\
2061 "mov %[esp_val], " RSP "\n"\
2062 "mov %[ebp_val], " RBP "\n"\
2063 "enter" size " $8, $" #level "\n"\
2064 "mov " RSP ", %[esp_val]\n"\
2065 "mov " RBP ", %[ebp_val]\n"\
2066 "mov %[esp_save], " RSP "\n"\
2067 "mov %[ebp_save], " RBP "\n"\
61a8c4ec
FB		 2068 : [esp_save] "=r" (esp_save),\
2069 [ebp_save] "=r" (ebp_save),\
2070 [esp_val] "=r" (esp_val),\
2071 [ebp_val] "=r" (ebp_val)\
2072 : "[esp_val]" (esp_val),\
2073 "[ebp_val]" (ebp_val));\
2074 printf("level=%d:\n", level);\
776f2227
FB		 2075 printf("esp_val=" FMTLX "\n", esp_val - (long)stack_end);\
2076 printf("ebp_val=" FMTLX "\n", ebp_val - (long)stack_end);\
61a8c4ec 2077 for(ptr = (stack_type *)esp_val; ptr < stack_end; ptr++)\
776f2227 2078 printf(FMTLX "\n", (long)ptr[0]);\
61a8c4ec
FB		 2079}
2080
2081static void test_enter(void)
2082{
776f2227
FB		 2083#if defined(__x86_64__)
2084 TEST_ENTER("q", uint64_t, 0);
2085 TEST_ENTER("q", uint64_t, 1);
2086 TEST_ENTER("q", uint64_t, 2);
2087 TEST_ENTER("q", uint64_t, 31);
2088#else
61a8c4ec
FB		 2089 TEST_ENTER("l", uint32_t, 0);
2090 TEST_ENTER("l", uint32_t, 1);
2091 TEST_ENTER("l", uint32_t, 2);
2092 TEST_ENTER("l", uint32_t, 31);
776f2227 2093#endif
61a8c4ec
FB		 2094
2095 TEST_ENTER("w", uint16_t, 0);
2096 TEST_ENTER("w", uint16_t, 1);
2097 TEST_ENTER("w", uint16_t, 2);
2098 TEST_ENTER("w", uint16_t, 31);
2099}
2100
085339a1
FB		 2101#ifdef TEST_SSE
2102
2103typedef int __m64 __attribute__ ((__mode__ (__V2SI__)));
8aadfbf0 2104typedef float __m128 __attribute__ ((__mode__(__V4SF__)));
085339a1
FB		 2105
2106typedef union {
2107 double d[2];
2108 float s[4];
2109 uint32_t l[4];
2110 uint64_t q[2];
2111 __m128 dq;
2112} XMMReg;
2113
2114static uint64_t __attribute__((aligned(16))) test_values[4][2] = {
2115 { 0x456723c698694873, 0xdc515cff944a58ec },
2116 { 0x1f297ccd58bad7ab, 0x41f21efba9e3e146 },
2117 { 0x007c62c2085427f8, 0x231be9e8cde7438d },
2118 { 0x0f76255a085427f8, 0xc233e9e8c4c9439a },
2119};
2120
2121#define SSE_OP(op)\
2122{\
2123 asm volatile (#op " %2, %0" : "=x" (r.dq) : "0" (a.dq), "x" (b.dq));\
776f2227 2124 printf("%-9s: a=" FMT64X "" FMT64X " b=" FMT64X "" FMT64X " r=" FMT64X "" FMT64X "\n",\
085339a1
FB		 2125 #op,\
2126 a.q[1], a.q[0],\
2127 b.q[1], b.q[0],\
2128 r.q[1], r.q[0]);\
2129}
2130
2131#define SSE_OP2(op)\
2132{\
2133 int i;\
2134 for(i=0;i<2;i++) {\
2135 a.q[0] = test_values[2*i][0];\
2136 a.q[1] = test_values[2*i][1];\
2137 b.q[0] = test_values[2*i+1][0];\
2138 b.q[1] = test_values[2*i+1][1];\
2139 SSE_OP(op);\
2140 }\
2141}
2142
2143#define MMX_OP2(op)\
2144{\
2145 int i;\
2146 for(i=0;i<2;i++) {\
2147 a.q[0] = test_values[2*i][0];\
2148 b.q[0] = test_values[2*i+1][0];\
2149 asm volatile (#op " %2, %0" : "=y" (r.q[0]) : "0" (a.q[0]), "y" (b.q[0]));\
776f2227 2150 printf("%-9s: a=" FMT64X " b=" FMT64X " r=" FMT64X "\n",\
085339a1
FB		 2151 #op,\
2152 a.q[0],\
2153 b.q[0],\
2154 r.q[0]);\
2155 }\
2156 SSE_OP2(op);\
2157}
2158
97ed14ae
FB		 2159#define SHUF_OP(op, ib)\
2160{\
97ed14ae
FB		 2161 a.q[0] = test_values[0][0];\
2162 a.q[1] = test_values[0][1];\
2163 b.q[0] = test_values[1][0];\
2164 b.q[1] = test_values[1][1];\
2165 asm volatile (#op " $" #ib ", %2, %0" : "=x" (r.dq) : "0" (a.dq), "x" (b.dq));\
776f2227 2166 printf("%-9s: a=" FMT64X "" FMT64X " b=" FMT64X "" FMT64X " ib=%02x r=" FMT64X "" FMT64X "\n",\
97ed14ae
FB		 2167 #op,\
2168 a.q[1], a.q[0],\
2169 b.q[1], b.q[0],\
2170 ib,\
2171 r.q[1], r.q[0]);\
2172}
2173
085339a1
FB		 2174#define PSHUF_OP(op, ib)\
2175{\
2176 int i;\
2177 for(i=0;i<2;i++) {\
2178 a.q[0] = test_values[2*i][0];\
2179 a.q[1] = test_values[2*i][1];\
2180 asm volatile (#op " $" #ib ", %1, %0" : "=x" (r.dq) : "x" (a.dq));\
776f2227 2181 printf("%-9s: a=" FMT64X "" FMT64X " ib=%02x r=" FMT64X "" FMT64X "\n",\
085339a1
FB		 2182 #op,\
2183 a.q[1], a.q[0],\
2184 ib,\
2185 r.q[1], r.q[0]);\
2186 }\
2187}
2188
2189#define SHIFT_IM(op, ib)\
2190{\
2191 int i;\
2192 for(i=0;i<2;i++) {\
2193 a.q[0] = test_values[2*i][0];\
2194 a.q[1] = test_values[2*i][1];\
2195 asm volatile (#op " $" #ib ", %0" : "=x" (r.dq) : "0" (a.dq));\
776f2227 2196 printf("%-9s: a=" FMT64X "" FMT64X " ib=%02x r=" FMT64X "" FMT64X "\n",\
085339a1
FB		 2197 #op,\
2198 a.q[1], a.q[0],\
2199 ib,\
2200 r.q[1], r.q[0]);\
2201 }\
2202}
2203
2204#define SHIFT_OP(op, ib)\
2205{\
2206 int i;\
2207 SHIFT_IM(op, ib);\
2208 for(i=0;i<2;i++) {\
2209 a.q[0] = test_values[2*i][0];\
2210 a.q[1] = test_values[2*i][1];\
2211 b.q[0] = ib;\
2212 b.q[1] = 0;\
2213 asm volatile (#op " %2, %0" : "=x" (r.dq) : "0" (a.dq), "x" (b.dq));\
776f2227 2214 printf("%-9s: a=" FMT64X "" FMT64X " b=" FMT64X "" FMT64X " r=" FMT64X "" FMT64X "\n",\
085339a1
FB		 2215 #op,\
2216 a.q[1], a.q[0],\
2217 b.q[1], b.q[0],\
2218 r.q[1], r.q[0]);\
2219 }\
2220}
2221
2222#define MOVMSK(op)\
2223{\
2224 int i, reg;\
2225 for(i=0;i<2;i++) {\
2226 a.q[0] = test_values[2*i][0];\
2227 a.q[1] = test_values[2*i][1];\
2228 asm volatile (#op " %1, %0" : "=r" (reg) : "x" (a.dq));\
776f2227 2229 printf("%-9s: a=" FMT64X "" FMT64X " r=%08x\n",\
085339a1
FB		 2230 #op,\
2231 a.q[1], a.q[0],\
2232 reg);\
2233 }\
2234}
2235
2236#define SSE_OPS(a) \
2237SSE_OP(a ## ps);\
2238SSE_OP(a ## ss);
2239
2240#define SSE_OPD(a) \
2241SSE_OP(a ## pd);\
2242SSE_OP(a ## sd);
2243
2244#define SSE_COMI(op, field)\
2245{\
2246 unsigned int eflags;\
2247 XMMReg a, b;\
2248 a.field[0] = a1;\
2249 b.field[0] = b1;\
2250 asm volatile (#op " %2, %1\n"\
2251 "pushf\n"\
2252 "pop %0\n"\
2253 : "=m" (eflags)\
2254 : "x" (a.dq), "x" (b.dq));\
2255 printf("%-9s: a=%f b=%f cc=%04x\n",\
2256 #op, a1, b1,\
2257 eflags & (CC_C | CC_P | CC_Z | CC_S | CC_O | CC_A));\
2258}
2259
2260void test_sse_comi(double a1, double b1)
2261{
2262 SSE_COMI(ucomiss, s);
2263 SSE_COMI(ucomisd, d);
2264 SSE_COMI(comiss, s);
2265 SSE_COMI(comisd, d);
2266}
2267
2268#define CVT_OP_XMM(op)\
2269{\
2270 asm volatile (#op " %1, %0" : "=x" (r.dq) : "x" (a.dq));\
776f2227 2271 printf("%-9s: a=" FMT64X "" FMT64X " r=" FMT64X "" FMT64X "\n",\
085339a1
FB		 2272 #op,\
2273 a.q[1], a.q[0],\
2274 r.q[1], r.q[0]);\
2275}
2276
80e7d521
FB		 2277/* Force %xmm0 usage to avoid the case where both register index are 0
2278 to test intruction decoding more extensively */
085339a1
FB		 2279#define CVT_OP_XMM2MMX(op)\
2280{\
80e7d521 2281 asm volatile (#op " %1, %0" : "=y" (r.q[0]) : "x" (a.dq) \
a5973fbf
FB		 2282 : "%xmm0"); \
2283 asm volatile("emms\n"); \
776f2227 2284 printf("%-9s: a=" FMT64X "" FMT64X " r=" FMT64X "\n",\
085339a1
FB		 2285 #op,\
2286 a.q[1], a.q[0],\
2287 r.q[0]);\
2288}
2289
2290#define CVT_OP_MMX2XMM(op)\
2291{\
2292 asm volatile (#op " %1, %0" : "=x" (r.dq) : "y" (a.q[0]));\
a5973fbf 2293 asm volatile("emms\n"); \
776f2227 2294 printf("%-9s: a=" FMT64X " r=" FMT64X "" FMT64X "\n",\
085339a1
FB		 2295 #op,\
2296 a.q[0],\
2297 r.q[1], r.q[0]);\
2298}
2299
2300#define CVT_OP_REG2XMM(op)\
2301{\
2302 asm volatile (#op " %1, %0" : "=x" (r.dq) : "r" (a.l[0]));\
776f2227 2303 printf("%-9s: a=%08x r=" FMT64X "" FMT64X "\n",\
085339a1
FB		 2304 #op,\
2305 a.l[0],\
2306 r.q[1], r.q[0]);\
2307}
2308
2309#define CVT_OP_XMM2REG(op)\
2310{\
2311 asm volatile (#op " %1, %0" : "=r" (r.l[0]) : "x" (a.dq));\
776f2227 2312 printf("%-9s: a=" FMT64X "" FMT64X " r=%08x\n",\
085339a1
FB		 2313 #op,\
2314 a.q[1], a.q[0],\
2315 r.l[0]);\
2316}
2317
a4682cc2
FB		 2318struct fpxstate {
2319 uint16_t fpuc;
2320 uint16_t fpus;
2321 uint16_t fptag;
2322 uint16_t fop;
2323 uint32_t fpuip;
2324 uint16_t cs_sel;
2325 uint16_t dummy0;
2326 uint32_t fpudp;
2327 uint16_t ds_sel;
2328 uint16_t dummy1;
2329 uint32_t mxcsr;
2330 uint32_t mxcsr_mask;
2331 uint8_t fpregs1[8 * 16];
2332 uint8_t xmm_regs[8 * 16];
2333 uint8_t dummy2[224];
2334};
2335
2336static struct fpxstate fpx_state __attribute__((aligned(16)));
2337static struct fpxstate fpx_state2 __attribute__((aligned(16)));
2338
2339void test_fxsave(void)
2340{
2341 struct fpxstate *fp = &fpx_state;
2342 struct fpxstate *fp2 = &fpx_state2;
776f2227 2343 int i, nb_xmm;
a4682cc2
FB		 2344 XMMReg a, b;
2345 a.q[0] = test_values[0][0];
2346 a.q[1] = test_values[0][1];
2347 b.q[0] = test_values[1][0];
2348 b.q[1] = test_values[1][1];
2349
2350 asm("movdqa %2, %%xmm0\n"
2351 "movdqa %3, %%xmm7\n"
776f2227
FB		 2352#if defined(__x86_64__)
2353 "movdqa %2, %%xmm15\n"
2354#endif
a4682cc2
FB		 2355 " fld1\n"
2356 " fldpi\n"
2357 " fldln2\n"
2358 " fxsave %0\n"
2359 " fxrstor %0\n"
2360 " fxsave %1\n"
2361 " fninit\n"
5fafdf24 2362 : "=m" (*(uint32_t *)fp2), "=m" (*(uint32_t *)fp)
a4682cc2
FB		 2363 : "m" (a), "m" (b));
2364 printf("fpuc=%04x\n", fp->fpuc);
2365 printf("fpus=%04x\n", fp->fpus);
2366 printf("fptag=%04x\n", fp->fptag);
2367 for(i = 0; i < 3; i++) {
776f2227 2368 printf("ST%d: " FMT64X " %04x\n",
5fafdf24 2369 i,
a4682cc2
FB		 2370 *(uint64_t *)&fp->fpregs1[i * 16],
2371 *(uint16_t *)&fp->fpregs1[i * 16 + 8]);
2372 }
2373 printf("mxcsr=%08x\n", fp->mxcsr & 0x1f80);
776f2227
FB		 2374#if defined(__x86_64__)
2375 nb_xmm = 16;
2376#else
2377 nb_xmm = 8;
2378#endif
2379 for(i = 0; i < nb_xmm; i++) {
2380 printf("xmm%d: " FMT64X "" FMT64X "\n",
5fafdf24 2381 i,
a4682cc2
FB		 2382 *(uint64_t *)&fp->xmm_regs[i * 16],
2383 *(uint64_t *)&fp->xmm_regs[i * 16 + 8]);
2384 }
2385}
2386
085339a1
FB		 2387void test_sse(void)
2388{
2389 XMMReg r, a, b;
86bd2ca5 2390 int i;
085339a1
FB		 2391
2392 MMX_OP2(punpcklbw);
2393 MMX_OP2(punpcklwd);
2394 MMX_OP2(punpckldq);
2395 MMX_OP2(packsswb);
2396 MMX_OP2(pcmpgtb);
2397 MMX_OP2(pcmpgtw);
2398 MMX_OP2(pcmpgtd);
2399 MMX_OP2(packuswb);
2400 MMX_OP2(punpckhbw);
2401 MMX_OP2(punpckhwd);
2402 MMX_OP2(punpckhdq);
2403 MMX_OP2(packssdw);
2404 MMX_OP2(pcmpeqb);
2405 MMX_OP2(pcmpeqw);
2406 MMX_OP2(pcmpeqd);
2407
2408 MMX_OP2(paddq);
2409 MMX_OP2(pmullw);
2410 MMX_OP2(psubusb);
2411 MMX_OP2(psubusw);
2412 MMX_OP2(pminub);
2413 MMX_OP2(pand);
2414 MMX_OP2(paddusb);
2415 MMX_OP2(paddusw);
2416 MMX_OP2(pmaxub);
2417 MMX_OP2(pandn);
2418
2419 MMX_OP2(pmulhuw);
2420 MMX_OP2(pmulhw);
3b46e624 2421
085339a1
FB		 2422 MMX_OP2(psubsb);
2423 MMX_OP2(psubsw);
2424 MMX_OP2(pminsw);
2425 MMX_OP2(por);
2426 MMX_OP2(paddsb);
2427 MMX_OP2(paddsw);
2428 MMX_OP2(pmaxsw);
2429 MMX_OP2(pxor);
2430 MMX_OP2(pmuludq);
2431 MMX_OP2(pmaddwd);
2432 MMX_OP2(psadbw);
2433 MMX_OP2(psubb);
2434 MMX_OP2(psubw);
2435 MMX_OP2(psubd);
2436 MMX_OP2(psubq);
2437 MMX_OP2(paddb);
2438 MMX_OP2(paddw);
2439 MMX_OP2(paddd);
2440
2441 MMX_OP2(pavgb);
2442 MMX_OP2(pavgw);
2443
2444 asm volatile ("pinsrw $1, %1, %0" : "=y" (r.q[0]) : "r" (0x12345678));
776f2227 2445 printf("%-9s: r=" FMT64X "\n", "pinsrw", r.q[0]);
085339a1
FB		 2446
2447 asm volatile ("pinsrw $5, %1, %0" : "=x" (r.dq) : "r" (0x12345678));
776f2227 2448 printf("%-9s: r=" FMT64X "" FMT64X "\n", "pinsrw", r.q[1], r.q[0]);
085339a1
FB		 2449
2450 a.q[0] = test_values[0][0];
2451 a.q[1] = test_values[0][1];
2452 asm volatile ("pextrw $1, %1, %0" : "=r" (r.l[0]) : "y" (a.q[0]));
2453 printf("%-9s: r=%08x\n", "pextrw", r.l[0]);
2454
2455 asm volatile ("pextrw $5, %1, %0" : "=r" (r.l[0]) : "x" (a.dq));
2456 printf("%-9s: r=%08x\n", "pextrw", r.l[0]);
2457
2458 asm volatile ("pmovmskb %1, %0" : "=r" (r.l[0]) : "y" (a.q[0]));
2459 printf("%-9s: r=%08x\n", "pmovmskb", r.l[0]);
3b46e624 2460
085339a1
FB		 2461 asm volatile ("pmovmskb %1, %0" : "=r" (r.l[0]) : "x" (a.dq));
2462 printf("%-9s: r=%08x\n", "pmovmskb", r.l[0]);
2463
97ed14ae
FB		 2464 {
2465 r.q[0] = -1;
2466 r.q[1] = -1;
2467
2468 a.q[0] = test_values[0][0];
2469 a.q[1] = test_values[0][1];
2470 b.q[0] = test_values[1][0];
2471 b.q[1] = test_values[1][1];
5fafdf24 2472 asm volatile("maskmovq %1, %0" :
97ed14ae 2473 : "y" (a.q[0]), "y" (b.q[0]), "D" (&r)
5fafdf24
TS		 2474 : "memory");
2475 printf("%-9s: r=" FMT64X " a=" FMT64X " b=" FMT64X "\n",
2476 "maskmov",
2477 r.q[0],
2478 a.q[0],
97ed14ae 2479 b.q[0]);
5fafdf24 2480 asm volatile("maskmovdqu %1, %0" :
97ed14ae 2481 : "x" (a.dq), "x" (b.dq), "D" (&r)
5fafdf24
TS		 2482 : "memory");
2483 printf("%-9s: r=" FMT64X "" FMT64X " a=" FMT64X "" FMT64X " b=" FMT64X "" FMT64X "\n",
2484 "maskmov",
2485 r.q[1], r.q[0],
2486 a.q[1], a.q[0],
97ed14ae
FB		 2487 b.q[1], b.q[0]);
2488 }
2489
085339a1
FB		 2490 asm volatile ("emms");
2491
2492 SSE_OP2(punpcklqdq);
2493 SSE_OP2(punpckhqdq);
2494 SSE_OP2(andps);
2495 SSE_OP2(andpd);
2496 SSE_OP2(andnps);
2497 SSE_OP2(andnpd);
2498 SSE_OP2(orps);
2499 SSE_OP2(orpd);
2500 SSE_OP2(xorps);
2501 SSE_OP2(xorpd);
2502
2503 SSE_OP2(unpcklps);
2504 SSE_OP2(unpcklpd);
2505 SSE_OP2(unpckhps);
2506 SSE_OP2(unpckhpd);
2507
97ed14ae
FB		 2508 SHUF_OP(shufps, 0x78);
2509 SHUF_OP(shufpd, 0x02);
085339a1
FB		 2510
2511 PSHUF_OP(pshufd, 0x78);
2512 PSHUF_OP(pshuflw, 0x78);
2513 PSHUF_OP(pshufhw, 0x78);
2514
2515 SHIFT_OP(psrlw, 7);
2516 SHIFT_OP(psrlw, 16);
2517 SHIFT_OP(psraw, 7);
2518 SHIFT_OP(psraw, 16);
2519 SHIFT_OP(psllw, 7);
2520 SHIFT_OP(psllw, 16);
2521
2522 SHIFT_OP(psrld, 7);
2523 SHIFT_OP(psrld, 32);
2524 SHIFT_OP(psrad, 7);
2525 SHIFT_OP(psrad, 32);
2526 SHIFT_OP(pslld, 7);
2527 SHIFT_OP(pslld, 32);
2528
2529 SHIFT_OP(psrlq, 7);
2530 SHIFT_OP(psrlq, 32);
2531 SHIFT_OP(psllq, 7);
2532 SHIFT_OP(psllq, 32);
2533
2534 SHIFT_IM(psrldq, 16);
2535 SHIFT_IM(psrldq, 7);
2536 SHIFT_IM(pslldq, 16);
2537 SHIFT_IM(pslldq, 7);
2538
2539 MOVMSK(movmskps);
2540 MOVMSK(movmskpd);
2541
2542 /* FPU specific ops */
2543
2544 {
2545 uint32_t mxcsr;
2546 asm volatile("stmxcsr %0" : "=m" (mxcsr));
2547 printf("mxcsr=%08x\n", mxcsr & 0x1f80);
2548 asm volatile("ldmxcsr %0" : : "m" (mxcsr));
2549 }
2550
2551 test_sse_comi(2, -1);
2552 test_sse_comi(2, 2);
2553 test_sse_comi(2, 3);
86bd2ca5
FB		 2554 test_sse_comi(2, q_nan.d);
2555 test_sse_comi(q_nan.d, -1);
2556
2557 for(i = 0; i < 2; i++) {
2558 a.s[0] = 2.7;
2559 a.s[1] = 3.4;
2560 a.s[2] = 4;
2561 a.s[3] = -6.3;
2562 b.s[0] = 45.7;
2563 b.s[1] = 353.4;
2564 b.s[2] = 4;
2565 b.s[3] = 56.3;
2566 if (i == 1) {
2567 a.s[0] = q_nan.d;
2568 b.s[3] = q_nan.d;
2569 }
2570
2571 SSE_OPS(add);
2572 SSE_OPS(mul);
2573 SSE_OPS(sub);
2574 SSE_OPS(min);
2575 SSE_OPS(div);
2576 SSE_OPS(max);
2577 SSE_OPS(sqrt);
2578 SSE_OPS(cmpeq);
2579 SSE_OPS(cmplt);
2580 SSE_OPS(cmple);
2581 SSE_OPS(cmpunord);
2582 SSE_OPS(cmpneq);
2583 SSE_OPS(cmpnlt);
2584 SSE_OPS(cmpnle);
2585 SSE_OPS(cmpord);
3b46e624
TS		 2586
2587
86bd2ca5
FB		 2588 a.d[0] = 2.7;
2589 a.d[1] = -3.4;
2590 b.d[0] = 45.7;
2591 b.d[1] = -53.4;
2592 if (i == 1) {
2593 a.d[0] = q_nan.d;
2594 b.d[1] = q_nan.d;
2595 }
2596 SSE_OPD(add);
2597 SSE_OPD(mul);
2598 SSE_OPD(sub);
2599 SSE_OPD(min);
2600 SSE_OPD(div);
2601 SSE_OPD(max);
2602 SSE_OPD(sqrt);
2603 SSE_OPD(cmpeq);
2604 SSE_OPD(cmplt);
2605 SSE_OPD(cmple);
2606 SSE_OPD(cmpunord);
2607 SSE_OPD(cmpneq);
2608 SSE_OPD(cmpnlt);
2609 SSE_OPD(cmpnle);
2610 SSE_OPD(cmpord);
2611 }
085339a1 2612
085339a1
FB		 2613 /* float to float/int */
2614 a.s[0] = 2.7;
2615 a.s[1] = 3.4;
2616 a.s[2] = 4;
2617 a.s[3] = -6.3;
2618 CVT_OP_XMM(cvtps2pd);
2619 CVT_OP_XMM(cvtss2sd);
2620 CVT_OP_XMM2MMX(cvtps2pi);
2621 CVT_OP_XMM2MMX(cvttps2pi);
2622 CVT_OP_XMM2REG(cvtss2si);
2623 CVT_OP_XMM2REG(cvttss2si);
2624 CVT_OP_XMM(cvtps2dq);
2625 CVT_OP_XMM(cvttps2dq);
2626
2627 a.d[0] = 2.6;
2628 a.d[1] = -3.4;
2629 CVT_OP_XMM(cvtpd2ps);
2630 CVT_OP_XMM(cvtsd2ss);
2631 CVT_OP_XMM2MMX(cvtpd2pi);
2632 CVT_OP_XMM2MMX(cvttpd2pi);
2633 CVT_OP_XMM2REG(cvtsd2si);
2634 CVT_OP_XMM2REG(cvttsd2si);
2635 CVT_OP_XMM(cvtpd2dq);
2636 CVT_OP_XMM(cvttpd2dq);
2637
80e7d521
FB		 2638 /* sse/mmx moves */
2639 CVT_OP_XMM2MMX(movdq2q);
2640 CVT_OP_MMX2XMM(movq2dq);
2641
085339a1
FB		 2642 /* int to float */
2643 a.l[0] = -6;
2644 a.l[1] = 2;
2645 a.l[2] = 100;
2646 a.l[3] = -60000;
2647 CVT_OP_MMX2XMM(cvtpi2ps);
2648 CVT_OP_MMX2XMM(cvtpi2pd);
2649 CVT_OP_REG2XMM(cvtsi2ss);
2650 CVT_OP_REG2XMM(cvtsi2sd);
2651 CVT_OP_XMM(cvtdq2ps);
2652 CVT_OP_XMM(cvtdq2pd);
2653
2654 /* XXX: test PNI insns */
2655#if 0
2656 SSE_OP2(movshdup);
2657#endif
a4682cc2 2658 asm volatile ("emms");
085339a1
FB		 2659}
2660
2661#endif
2662
df517cec
FB		 2663#define TEST_CONV_RAX(op)\
2664{\
2665 unsigned long a, r;\
2666 a = i2l(0x8234a6f8);\
2667 r = a;\
2668 asm volatile(#op : "=a" (r) : "0" (r));\
2669 printf("%-10s A=" FMTLX " R=" FMTLX "\n", #op, a, r);\
2670}
2671
2672#define TEST_CONV_RAX_RDX(op)\
2673{\
2674 unsigned long a, d, r, rh; \
2675 a = i2l(0x8234a6f8);\
2676 d = i2l(0x8345a1f2);\
2677 r = a;\
2678 rh = d;\
2679 asm volatile(#op : "=a" (r), "=d" (rh) : "0" (r), "1" (rh)); \
2680 printf("%-10s A=" FMTLX " R=" FMTLX ":" FMTLX "\n", #op, a, r, rh); \
2681}
2682
2683void test_conv(void)
2684{
2685 TEST_CONV_RAX(cbw);
2686 TEST_CONV_RAX(cwde);
2687#if defined(__x86_64__)
2688 TEST_CONV_RAX(cdqe);
2689#endif
2690
2691 TEST_CONV_RAX_RDX(cwd);
2692 TEST_CONV_RAX_RDX(cdq);
2693#if defined(__x86_64__)
2694 TEST_CONV_RAX_RDX(cqo);
2695#endif
8aadfbf0
FB		 2696
2697 {
2698 unsigned long a, r;
2699 a = i2l(0x12345678);
2700 asm volatile("bswapl %k0" : "=r" (r) : "0" (a));
2701 printf("%-10s: A=" FMTLX " R=" FMTLX "\n", "bswapl", a, r);
2702 }
2703#if defined(__x86_64__)
2704 {
2705 unsigned long a, r;
2706 a = i2l(0x12345678);
2707 asm volatile("bswapq %0" : "=r" (r) : "0" (a));
2708 printf("%-10s: A=" FMTLX " R=" FMTLX "\n", "bswapq", a, r);
2709 }
2710#endif
df517cec
FB		 2711}
2712
776f2227
FB		 2713extern void *__start_initcall;
2714extern void *__stop_initcall;
2715
4d1135e4
FB		 2716
2717int main(int argc, char **argv)
2718{
2719 void **ptr;
2720 void (*func)(void);
4b74fe1f 2721
776f2227
FB		 2722 ptr = &__start_initcall;
2723 while (ptr != &__stop_initcall) {
4d1135e4
FB		 2724 func = *ptr++;
2725 func();
2726 }
9d8e9c09 2727 test_bsx();
d57c4e01 2728 test_mul();
4d1135e4 2729 test_jcc();
a5973fbf 2730 test_loop();
9d8e9c09 2731 test_floats();
776f2227 2732#if !defined(__x86_64__)
55480af8 2733 test_bcd();
776f2227 2734#endif
1a9353d2 2735 test_xchg();
e1d4294a
FB		 2736 test_string();
2737 test_misc();
6dbad63e 2738 test_lea();
776f2227 2739#ifdef TEST_SEGS
6dbad63e 2740 test_segs();
e5918247 2741 test_code16();
776f2227 2742#endif
acae4681 2743#ifdef TEST_VM86
3a27ad0b 2744 test_vm86();
acae4681 2745#endif
776f2227 2746#if !defined(__x86_64__)
8aadfbf0 2747 test_exceptions();
3a27ad0b 2748 test_self_modifying_code();
3ff0631e 2749 test_single_step();
776f2227 2750#endif
61a8c4ec 2751 test_enter();
df517cec 2752 test_conv();
085339a1
FB		 2753#ifdef TEST_SSE
2754 test_sse();
a4682cc2 2755 test_fxsave();
085339a1 2756#endif
4d1135e4
FB		 2757 return 0;
2758}
Qemu copy for testing