[qemu.git] / tests / xtensa / test_pipeline.S

.include "macros.inc"

.purgem test
.macro test name
    movi    a2, 1f
    movi    a3, 99f
0:
    ipf     a2, 0
    ipf     a2, 4
    ipf     a2, 8
    ipf     a2, 12
    addi    a2, a2, 16
    blt     a2, a3, 0b
    j       1f
    .align 4
1:
.endm

test_suite pipeline

test register_no_stall
    rsr     a3, ccount
    add     a5, a6, a6
    add     a6, a5, a5
    rsr     a4, ccount
    sub     a3, a4, a3
    assert  eqi, a3, 3
test_end

test register_stall
    l32i    a5, a1, 0   /* data cache preload */
    nop
    rsr     a3, ccount
    l32i    a5, a1, 0
    add     a6, a5, a5  /* M-to-E interlock */
    rsr     a4, ccount
    sub     a3, a4, a3
    assert  eqi, a3, 4
test_end

test j0_stall
    rsr     a3, ccount
    j       1f          /* E + 2-cycle penalty */
1:
    rsr     a4, ccount  /* E */
    sub     a3, a4, a3
    assert  eqi, a3, 4
test_end

test j1_stall
    rsr     a3, ccount
    j       1f
    nop
1:
    rsr     a4, ccount
    sub     a3, a4, a3
    assert  eqi, a3, 4
test_end

test j5_stall
    rsr     a3, ccount
    j       1f
    nop
    nop
    nop
    nop
    nop
1:
    rsr     a4, ccount
    sub     a3, a4, a3
    assert  eqi, a3, 4
test_end

test b_no_stall
    movi    a5, 1
    rsr     a3, ccount
    beqi    a5, 2, 1f
    rsr     a4, ccount
    sub     a3, a4, a3
    assert  eqi, a3, 2
1:
test_end

test b1_stall
    movi    a5, 1
    rsr     a3, ccount
    beqi    a5, 1, 1f
    nop
1:
    rsr     a4, ccount
    sub     a3, a4, a3
    assert  eqi, a3, 4
test_end

test b5_stall
    movi    a5, 1
    rsr     a3, ccount
    beqi    a5, 1, 1f
    nop
    nop
    nop
    nop
    nop
1:
    rsr     a4, ccount
    sub     a3, a4, a3
    assert  eqi, a3, 4
test_end

/* PS *SYNC */

test ps_dsync
    rsr     a5, ps
    isync
    rsr     a3, ccount
    wsr     a5, ps
    dsync
    rsr     a4, ccount
    sub     a3, a4, a3
    assert  eqi, a3, 5
test_end

test ps_esync
    rsr     a5, ps
    isync
    rsr     a3, ccount
    wsr     a5, ps
    esync
    rsr     a4, ccount
    sub     a3, a4, a3
    assert  eqi, a3, 5
test_end

test ps_rsync
    rsr     a5, ps
    isync
    rsr     a3, ccount
    wsr     a5, ps
    rsync
    rsr     a4, ccount
    sub     a3, a4, a3
    assert  eqi, a3, 5
test_end

test ps_isync
    rsr     a5, ps
    isync
    rsr     a3, ccount
    wsr     a5, ps
    isync
    rsr     a4, ccount
    sub     a3, a4, a3
    movi    a4, 9
    assert  eq, a3, a4
test_end

test_suite_end
Commit	Line	Data
7d890b40 MF	1	.include "macros.inc"
	2
	3	.purgem test
	4	.macro test name
	5	movi a2, 1f
	6	movi a3, 99f
	7	0:
	8	ipf a2, 0
	9	ipf a2, 4
	10	ipf a2, 8
	11	ipf a2, 12
	12	addi a2, a2, 16
	13	blt a2, a3, 0b
	14	j 1f
	15	.align 4
	16	1:
	17	.endm
	18
	19	test_suite pipeline
	20
	21	test register_no_stall
	22	rsr a3, ccount
	23	add a5, a6, a6
	24	add a6, a5, a5
	25	rsr a4, ccount
	26	sub a3, a4, a3
	27	assert eqi, a3, 3
	28	test_end
	29
	30	test register_stall
	31	l32i a5, a1, 0 /* data cache preload */
	32	nop
	33	rsr a3, ccount
	34	l32i a5, a1, 0
	35	add a6, a5, a5 /* M-to-E interlock */
	36	rsr a4, ccount
	37	sub a3, a4, a3
	38	assert eqi, a3, 4
	39	test_end
	40
	41	test j0_stall
	42	rsr a3, ccount
	43	j 1f /* E + 2-cycle penalty */
	44	1:
	45	rsr a4, ccount /* E */
	46	sub a3, a4, a3
	47	assert eqi, a3, 4
	48	test_end
	49
	50	test j1_stall
	51	rsr a3, ccount
	52	j 1f
	53	nop
	54	1:
	55	rsr a4, ccount
	56	sub a3, a4, a3
	57	assert eqi, a3, 4
	58	test_end
	59
	60	test j5_stall
	61	rsr a3, ccount
	62	j 1f
	63	nop
	64	nop
65	nop
66	nop
67	nop
68	1:
69	rsr a4, ccount
70	sub a3, a4, a3
71	assert eqi, a3, 4
72	test_end
73
74	test b_no_stall
75	movi a5, 1
76	rsr a3, ccount
77	beqi a5, 2, 1f
78	rsr a4, ccount
79	sub a3, a4, a3
80	assert eqi, a3, 2
81	1:
82	test_end
83
84	test b1_stall
85	movi a5, 1
86	rsr a3, ccount
87	beqi a5, 1, 1f
88	nop
89	1:
90	rsr a4, ccount
91	sub a3, a4, a3
92	assert eqi, a3, 4
93	test_end
94
95	test b5_stall
96	movi a5, 1
97	rsr a3, ccount
98	beqi a5, 1, 1f
99	nop
100	nop
101	nop
102	nop
103	nop
104	1:
105	rsr a4, ccount
106	sub a3, a4, a3
107	assert eqi, a3, 4
108	test_end
109
110	/* PS SYNC /
111
112	test ps_dsync
113	rsr a5, ps
114	isync
115	rsr a3, ccount
116	wsr a5, ps
117	dsync
118	rsr a4, ccount
119	sub a3, a4, a3
120	assert eqi, a3, 5
121	test_end
122
123	test ps_esync
124	rsr a5, ps
125	isync
126	rsr a3, ccount
127	wsr a5, ps
128	esync
129	rsr a4, ccount
130	sub a3, a4, a3
131	assert eqi, a3, 5
132	test_end
133
134	test ps_rsync
135	rsr a5, ps
136	isync
137	rsr a3, ccount
138	wsr a5, ps
139	rsync
140	rsr a4, ccount
141	sub a3, a4, a3
142	assert eqi, a3, 5
143	test_end
144
145	test ps_isync
146	rsr a5, ps
147	isync
148	rsr a3, ccount
149	wsr a5, ps
150	isync
151	rsr a4, ccount
152	sub a3, a4, a3
153	movi a4, 9
154	assert eq, a3, a4
155	test_end
156
157	test_suite_end