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Commit | Line | Data |
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d19893da FB |
1 | /* |
2 | * Host code generation | |
5fafdf24 | 3 | * |
d19893da FB |
4 | * Copyright (c) 2003 Fabrice Bellard |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
8167ee88 | 17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
d19893da | 18 | */ |
5b6dd868 BS |
19 | #ifdef _WIN32 |
20 | #include <windows.h> | |
21 | #else | |
22 | #include <sys/types.h> | |
23 | #include <sys/mman.h> | |
24 | #endif | |
d19893da FB |
25 | #include <stdarg.h> |
26 | #include <stdlib.h> | |
27 | #include <stdio.h> | |
28 | #include <string.h> | |
29 | #include <inttypes.h> | |
30 | ||
31 | #include "config.h" | |
2054396a | 32 | |
5b6dd868 | 33 | #include "qemu-common.h" |
af5ad107 | 34 | #define NO_CPU_IO_DEFS |
d3eead2e | 35 | #include "cpu.h" |
76cad711 | 36 | #include "disas/disas.h" |
57fec1fe | 37 | #include "tcg.h" |
1de7afc9 | 38 | #include "qemu/timer.h" |
022c62cb PB |
39 | #include "exec/memory.h" |
40 | #include "exec/address-spaces.h" | |
5b6dd868 BS |
41 | #if defined(CONFIG_USER_ONLY) |
42 | #include "qemu.h" | |
43 | #if defined(__FreeBSD__) || defined(__FreeBSD_kernel__) | |
44 | #include <sys/param.h> | |
45 | #if __FreeBSD_version >= 700104 | |
46 | #define HAVE_KINFO_GETVMMAP | |
47 | #define sigqueue sigqueue_freebsd /* avoid redefinition */ | |
48 | #include <sys/time.h> | |
49 | #include <sys/proc.h> | |
50 | #include <machine/profile.h> | |
51 | #define _KERNEL | |
52 | #include <sys/user.h> | |
53 | #undef _KERNEL | |
54 | #undef sigqueue | |
55 | #include <libutil.h> | |
56 | #endif | |
57 | #endif | |
58 | #endif | |
59 | ||
022c62cb | 60 | #include "exec/cputlb.h" |
5b6dd868 BS |
61 | #include "translate-all.h" |
62 | ||
63 | //#define DEBUG_TB_INVALIDATE | |
64 | //#define DEBUG_FLUSH | |
65 | /* make various TB consistency checks */ | |
66 | //#define DEBUG_TB_CHECK | |
67 | ||
68 | #if !defined(CONFIG_USER_ONLY) | |
69 | /* TB consistency checks only implemented for usermode emulation. */ | |
70 | #undef DEBUG_TB_CHECK | |
71 | #endif | |
72 | ||
73 | #define SMC_BITMAP_USE_THRESHOLD 10 | |
74 | ||
0b0d3320 | 75 | /* Translation blocks */ |
5b6dd868 | 76 | static TranslationBlock *tbs; |
5b6dd868 BS |
77 | TranslationBlock *tb_phys_hash[CODE_GEN_PHYS_HASH_SIZE]; |
78 | static int nb_tbs; | |
79 | /* any access to the tbs or the page table must use this lock */ | |
80 | spinlock_t tb_lock = SPIN_LOCK_UNLOCKED; | |
81 | ||
5b6dd868 BS |
82 | typedef struct PageDesc { |
83 | /* list of TBs intersecting this ram page */ | |
84 | TranslationBlock *first_tb; | |
85 | /* in order to optimize self modifying code, we count the number | |
86 | of lookups we do to a given page to use a bitmap */ | |
87 | unsigned int code_write_count; | |
88 | uint8_t *code_bitmap; | |
89 | #if defined(CONFIG_USER_ONLY) | |
90 | unsigned long flags; | |
91 | #endif | |
92 | } PageDesc; | |
93 | ||
94 | /* In system mode we want L1_MAP to be based on ram offsets, | |
95 | while in user mode we want it to be based on virtual addresses. */ | |
96 | #if !defined(CONFIG_USER_ONLY) | |
97 | #if HOST_LONG_BITS < TARGET_PHYS_ADDR_SPACE_BITS | |
98 | # define L1_MAP_ADDR_SPACE_BITS HOST_LONG_BITS | |
99 | #else | |
100 | # define L1_MAP_ADDR_SPACE_BITS TARGET_PHYS_ADDR_SPACE_BITS | |
101 | #endif | |
102 | #else | |
103 | # define L1_MAP_ADDR_SPACE_BITS TARGET_VIRT_ADDR_SPACE_BITS | |
104 | #endif | |
105 | ||
106 | /* The bits remaining after N lower levels of page tables. */ | |
107 | #define V_L1_BITS_REM \ | |
108 | ((L1_MAP_ADDR_SPACE_BITS - TARGET_PAGE_BITS) % L2_BITS) | |
109 | ||
110 | #if V_L1_BITS_REM < 4 | |
111 | #define V_L1_BITS (V_L1_BITS_REM + L2_BITS) | |
112 | #else | |
113 | #define V_L1_BITS V_L1_BITS_REM | |
114 | #endif | |
115 | ||
116 | #define V_L1_SIZE ((target_ulong)1 << V_L1_BITS) | |
117 | ||
118 | #define V_L1_SHIFT (L1_MAP_ADDR_SPACE_BITS - TARGET_PAGE_BITS - V_L1_BITS) | |
119 | ||
120 | uintptr_t qemu_real_host_page_size; | |
121 | uintptr_t qemu_host_page_size; | |
122 | uintptr_t qemu_host_page_mask; | |
123 | ||
124 | /* This is a multi-level map on the virtual address space. | |
125 | The bottom level has pointers to PageDesc. */ | |
126 | static void *l1_map[V_L1_SIZE]; | |
127 | ||
128 | /* statistics */ | |
129 | static int tb_flush_count; | |
130 | static int tb_phys_invalidate_count; | |
d19893da | 131 | |
57fec1fe FB |
132 | /* code generation context */ |
133 | TCGContext tcg_ctx; | |
d19893da | 134 | |
5b6dd868 BS |
135 | static void tb_link_page(TranslationBlock *tb, tb_page_addr_t phys_pc, |
136 | tb_page_addr_t phys_page2); | |
a8a826a3 | 137 | static TranslationBlock *tb_find_pc(uintptr_t tc_ptr); |
5b6dd868 | 138 | |
57fec1fe FB |
139 | void cpu_gen_init(void) |
140 | { | |
141 | tcg_context_init(&tcg_ctx); | |
57fec1fe FB |
142 | } |
143 | ||
d19893da | 144 | /* return non zero if the very first instruction is invalid so that |
5fafdf24 | 145 | the virtual CPU can trigger an exception. |
d19893da FB |
146 | |
147 | '*gen_code_size_ptr' contains the size of the generated code (host | |
148 | code). | |
149 | */ | |
9349b4f9 | 150 | int cpu_gen_code(CPUArchState *env, TranslationBlock *tb, int *gen_code_size_ptr) |
d19893da | 151 | { |
57fec1fe | 152 | TCGContext *s = &tcg_ctx; |
d19893da FB |
153 | uint8_t *gen_code_buf; |
154 | int gen_code_size; | |
57fec1fe FB |
155 | #ifdef CONFIG_PROFILER |
156 | int64_t ti; | |
157 | #endif | |
158 | ||
159 | #ifdef CONFIG_PROFILER | |
b67d9a52 FB |
160 | s->tb_count1++; /* includes aborted translations because of |
161 | exceptions */ | |
57fec1fe FB |
162 | ti = profile_getclock(); |
163 | #endif | |
164 | tcg_func_start(s); | |
d19893da | 165 | |
2cfc5f17 TS |
166 | gen_intermediate_code(env, tb); |
167 | ||
ec6338ba | 168 | /* generate machine code */ |
57fec1fe | 169 | gen_code_buf = tb->tc_ptr; |
ec6338ba FB |
170 | tb->tb_next_offset[0] = 0xffff; |
171 | tb->tb_next_offset[1] = 0xffff; | |
57fec1fe | 172 | s->tb_next_offset = tb->tb_next_offset; |
4cbb86e1 | 173 | #ifdef USE_DIRECT_JUMP |
57fec1fe FB |
174 | s->tb_jmp_offset = tb->tb_jmp_offset; |
175 | s->tb_next = NULL; | |
d19893da | 176 | #else |
57fec1fe FB |
177 | s->tb_jmp_offset = NULL; |
178 | s->tb_next = tb->tb_next; | |
d19893da | 179 | #endif |
57fec1fe FB |
180 | |
181 | #ifdef CONFIG_PROFILER | |
b67d9a52 FB |
182 | s->tb_count++; |
183 | s->interm_time += profile_getclock() - ti; | |
184 | s->code_time -= profile_getclock(); | |
57fec1fe | 185 | #endif |
54604f74 | 186 | gen_code_size = tcg_gen_code(s, gen_code_buf); |
d19893da | 187 | *gen_code_size_ptr = gen_code_size; |
57fec1fe | 188 | #ifdef CONFIG_PROFILER |
b67d9a52 FB |
189 | s->code_time += profile_getclock(); |
190 | s->code_in_len += tb->size; | |
191 | s->code_out_len += gen_code_size; | |
57fec1fe FB |
192 | #endif |
193 | ||
d19893da | 194 | #ifdef DEBUG_DISAS |
8fec2b8c | 195 | if (qemu_loglevel_mask(CPU_LOG_TB_OUT_ASM)) { |
93fcfe39 AL |
196 | qemu_log("OUT: [size=%d]\n", *gen_code_size_ptr); |
197 | log_disas(tb->tc_ptr, *gen_code_size_ptr); | |
198 | qemu_log("\n"); | |
31b1a7b4 | 199 | qemu_log_flush(); |
d19893da FB |
200 | } |
201 | #endif | |
202 | return 0; | |
203 | } | |
204 | ||
5fafdf24 | 205 | /* The cpu state corresponding to 'searched_pc' is restored. |
d19893da | 206 | */ |
a8a826a3 BS |
207 | static int cpu_restore_state_from_tb(TranslationBlock *tb, CPUArchState *env, |
208 | uintptr_t searched_pc) | |
d19893da | 209 | { |
57fec1fe FB |
210 | TCGContext *s = &tcg_ctx; |
211 | int j; | |
6375e09e | 212 | uintptr_t tc_ptr; |
57fec1fe FB |
213 | #ifdef CONFIG_PROFILER |
214 | int64_t ti; | |
215 | #endif | |
216 | ||
217 | #ifdef CONFIG_PROFILER | |
218 | ti = profile_getclock(); | |
219 | #endif | |
220 | tcg_func_start(s); | |
d19893da | 221 | |
2cfc5f17 | 222 | gen_intermediate_code_pc(env, tb); |
3b46e624 | 223 | |
2e70f6ef PB |
224 | if (use_icount) { |
225 | /* Reset the cycle counter to the start of the block. */ | |
226 | env->icount_decr.u16.low += tb->icount; | |
227 | /* Clear the IO flag. */ | |
228 | env->can_do_io = 0; | |
229 | } | |
230 | ||
d19893da | 231 | /* find opc index corresponding to search_pc */ |
6375e09e | 232 | tc_ptr = (uintptr_t)tb->tc_ptr; |
d19893da FB |
233 | if (searched_pc < tc_ptr) |
234 | return -1; | |
57fec1fe FB |
235 | |
236 | s->tb_next_offset = tb->tb_next_offset; | |
237 | #ifdef USE_DIRECT_JUMP | |
238 | s->tb_jmp_offset = tb->tb_jmp_offset; | |
239 | s->tb_next = NULL; | |
240 | #else | |
241 | s->tb_jmp_offset = NULL; | |
242 | s->tb_next = tb->tb_next; | |
243 | #endif | |
54604f74 | 244 | j = tcg_gen_code_search_pc(s, (uint8_t *)tc_ptr, searched_pc - tc_ptr); |
57fec1fe FB |
245 | if (j < 0) |
246 | return -1; | |
d19893da | 247 | /* now find start of instruction before */ |
ab1103de | 248 | while (s->gen_opc_instr_start[j] == 0) { |
d19893da | 249 | j--; |
ab1103de | 250 | } |
c9c99c22 | 251 | env->icount_decr.u16.low -= s->gen_opc_icount[j]; |
3b46e624 | 252 | |
e87b7cb0 | 253 | restore_state_to_opc(env, tb, j); |
57fec1fe FB |
254 | |
255 | #ifdef CONFIG_PROFILER | |
b67d9a52 FB |
256 | s->restore_time += profile_getclock() - ti; |
257 | s->restore_count++; | |
57fec1fe | 258 | #endif |
d19893da FB |
259 | return 0; |
260 | } | |
5b6dd868 | 261 | |
a8a826a3 BS |
262 | bool cpu_restore_state(CPUArchState *env, uintptr_t retaddr) |
263 | { | |
264 | TranslationBlock *tb; | |
265 | ||
266 | tb = tb_find_pc(retaddr); | |
267 | if (tb) { | |
268 | cpu_restore_state_from_tb(tb, env, retaddr); | |
269 | return true; | |
270 | } | |
271 | return false; | |
272 | } | |
273 | ||
5b6dd868 BS |
274 | #ifdef _WIN32 |
275 | static inline void map_exec(void *addr, long size) | |
276 | { | |
277 | DWORD old_protect; | |
278 | VirtualProtect(addr, size, | |
279 | PAGE_EXECUTE_READWRITE, &old_protect); | |
280 | } | |
281 | #else | |
282 | static inline void map_exec(void *addr, long size) | |
283 | { | |
284 | unsigned long start, end, page_size; | |
285 | ||
286 | page_size = getpagesize(); | |
287 | start = (unsigned long)addr; | |
288 | start &= ~(page_size - 1); | |
289 | ||
290 | end = (unsigned long)addr + size; | |
291 | end += page_size - 1; | |
292 | end &= ~(page_size - 1); | |
293 | ||
294 | mprotect((void *)start, end - start, | |
295 | PROT_READ | PROT_WRITE | PROT_EXEC); | |
296 | } | |
297 | #endif | |
298 | ||
299 | static void page_init(void) | |
300 | { | |
301 | /* NOTE: we can always suppose that qemu_host_page_size >= | |
302 | TARGET_PAGE_SIZE */ | |
303 | #ifdef _WIN32 | |
304 | { | |
305 | SYSTEM_INFO system_info; | |
306 | ||
307 | GetSystemInfo(&system_info); | |
308 | qemu_real_host_page_size = system_info.dwPageSize; | |
309 | } | |
310 | #else | |
311 | qemu_real_host_page_size = getpagesize(); | |
312 | #endif | |
313 | if (qemu_host_page_size == 0) { | |
314 | qemu_host_page_size = qemu_real_host_page_size; | |
315 | } | |
316 | if (qemu_host_page_size < TARGET_PAGE_SIZE) { | |
317 | qemu_host_page_size = TARGET_PAGE_SIZE; | |
318 | } | |
319 | qemu_host_page_mask = ~(qemu_host_page_size - 1); | |
320 | ||
321 | #if defined(CONFIG_BSD) && defined(CONFIG_USER_ONLY) | |
322 | { | |
323 | #ifdef HAVE_KINFO_GETVMMAP | |
324 | struct kinfo_vmentry *freep; | |
325 | int i, cnt; | |
326 | ||
327 | freep = kinfo_getvmmap(getpid(), &cnt); | |
328 | if (freep) { | |
329 | mmap_lock(); | |
330 | for (i = 0; i < cnt; i++) { | |
331 | unsigned long startaddr, endaddr; | |
332 | ||
333 | startaddr = freep[i].kve_start; | |
334 | endaddr = freep[i].kve_end; | |
335 | if (h2g_valid(startaddr)) { | |
336 | startaddr = h2g(startaddr) & TARGET_PAGE_MASK; | |
337 | ||
338 | if (h2g_valid(endaddr)) { | |
339 | endaddr = h2g(endaddr); | |
340 | page_set_flags(startaddr, endaddr, PAGE_RESERVED); | |
341 | } else { | |
342 | #if TARGET_ABI_BITS <= L1_MAP_ADDR_SPACE_BITS | |
343 | endaddr = ~0ul; | |
344 | page_set_flags(startaddr, endaddr, PAGE_RESERVED); | |
345 | #endif | |
346 | } | |
347 | } | |
348 | } | |
349 | free(freep); | |
350 | mmap_unlock(); | |
351 | } | |
352 | #else | |
353 | FILE *f; | |
354 | ||
355 | last_brk = (unsigned long)sbrk(0); | |
356 | ||
357 | f = fopen("/compat/linux/proc/self/maps", "r"); | |
358 | if (f) { | |
359 | mmap_lock(); | |
360 | ||
361 | do { | |
362 | unsigned long startaddr, endaddr; | |
363 | int n; | |
364 | ||
365 | n = fscanf(f, "%lx-%lx %*[^\n]\n", &startaddr, &endaddr); | |
366 | ||
367 | if (n == 2 && h2g_valid(startaddr)) { | |
368 | startaddr = h2g(startaddr) & TARGET_PAGE_MASK; | |
369 | ||
370 | if (h2g_valid(endaddr)) { | |
371 | endaddr = h2g(endaddr); | |
372 | } else { | |
373 | endaddr = ~0ul; | |
374 | } | |
375 | page_set_flags(startaddr, endaddr, PAGE_RESERVED); | |
376 | } | |
377 | } while (!feof(f)); | |
378 | ||
379 | fclose(f); | |
380 | mmap_unlock(); | |
381 | } | |
382 | #endif | |
383 | } | |
384 | #endif | |
385 | } | |
386 | ||
387 | static PageDesc *page_find_alloc(tb_page_addr_t index, int alloc) | |
388 | { | |
389 | PageDesc *pd; | |
390 | void **lp; | |
391 | int i; | |
392 | ||
393 | #if defined(CONFIG_USER_ONLY) | |
394 | /* We can't use g_malloc because it may recurse into a locked mutex. */ | |
395 | # define ALLOC(P, SIZE) \ | |
396 | do { \ | |
397 | P = mmap(NULL, SIZE, PROT_READ | PROT_WRITE, \ | |
398 | MAP_PRIVATE | MAP_ANONYMOUS, -1, 0); \ | |
399 | } while (0) | |
400 | #else | |
401 | # define ALLOC(P, SIZE) \ | |
402 | do { P = g_malloc0(SIZE); } while (0) | |
403 | #endif | |
404 | ||
405 | /* Level 1. Always allocated. */ | |
406 | lp = l1_map + ((index >> V_L1_SHIFT) & (V_L1_SIZE - 1)); | |
407 | ||
408 | /* Level 2..N-1. */ | |
409 | for (i = V_L1_SHIFT / L2_BITS - 1; i > 0; i--) { | |
410 | void **p = *lp; | |
411 | ||
412 | if (p == NULL) { | |
413 | if (!alloc) { | |
414 | return NULL; | |
415 | } | |
416 | ALLOC(p, sizeof(void *) * L2_SIZE); | |
417 | *lp = p; | |
418 | } | |
419 | ||
420 | lp = p + ((index >> (i * L2_BITS)) & (L2_SIZE - 1)); | |
421 | } | |
422 | ||
423 | pd = *lp; | |
424 | if (pd == NULL) { | |
425 | if (!alloc) { | |
426 | return NULL; | |
427 | } | |
428 | ALLOC(pd, sizeof(PageDesc) * L2_SIZE); | |
429 | *lp = pd; | |
430 | } | |
431 | ||
432 | #undef ALLOC | |
433 | ||
434 | return pd + (index & (L2_SIZE - 1)); | |
435 | } | |
436 | ||
437 | static inline PageDesc *page_find(tb_page_addr_t index) | |
438 | { | |
439 | return page_find_alloc(index, 0); | |
440 | } | |
441 | ||
442 | #if !defined(CONFIG_USER_ONLY) | |
443 | #define mmap_lock() do { } while (0) | |
444 | #define mmap_unlock() do { } while (0) | |
445 | #endif | |
446 | ||
447 | #if defined(CONFIG_USER_ONLY) | |
448 | /* Currently it is not recommended to allocate big chunks of data in | |
449 | user mode. It will change when a dedicated libc will be used. */ | |
450 | /* ??? 64-bit hosts ought to have no problem mmaping data outside the | |
451 | region in which the guest needs to run. Revisit this. */ | |
452 | #define USE_STATIC_CODE_GEN_BUFFER | |
453 | #endif | |
454 | ||
455 | /* ??? Should configure for this, not list operating systems here. */ | |
456 | #if (defined(__linux__) \ | |
457 | || defined(__FreeBSD__) || defined(__FreeBSD_kernel__) \ | |
458 | || defined(__DragonFly__) || defined(__OpenBSD__) \ | |
459 | || defined(__NetBSD__)) | |
460 | # define USE_MMAP | |
461 | #endif | |
462 | ||
463 | /* Minimum size of the code gen buffer. This number is randomly chosen, | |
464 | but not so small that we can't have a fair number of TB's live. */ | |
465 | #define MIN_CODE_GEN_BUFFER_SIZE (1024u * 1024) | |
466 | ||
467 | /* Maximum size of the code gen buffer we'd like to use. Unless otherwise | |
468 | indicated, this is constrained by the range of direct branches on the | |
469 | host cpu, as used by the TCG implementation of goto_tb. */ | |
470 | #if defined(__x86_64__) | |
471 | # define MAX_CODE_GEN_BUFFER_SIZE (2ul * 1024 * 1024 * 1024) | |
472 | #elif defined(__sparc__) | |
473 | # define MAX_CODE_GEN_BUFFER_SIZE (2ul * 1024 * 1024 * 1024) | |
474 | #elif defined(__arm__) | |
475 | # define MAX_CODE_GEN_BUFFER_SIZE (16u * 1024 * 1024) | |
476 | #elif defined(__s390x__) | |
477 | /* We have a +- 4GB range on the branches; leave some slop. */ | |
478 | # define MAX_CODE_GEN_BUFFER_SIZE (3ul * 1024 * 1024 * 1024) | |
479 | #else | |
480 | # define MAX_CODE_GEN_BUFFER_SIZE ((size_t)-1) | |
481 | #endif | |
482 | ||
483 | #define DEFAULT_CODE_GEN_BUFFER_SIZE_1 (32u * 1024 * 1024) | |
484 | ||
485 | #define DEFAULT_CODE_GEN_BUFFER_SIZE \ | |
486 | (DEFAULT_CODE_GEN_BUFFER_SIZE_1 < MAX_CODE_GEN_BUFFER_SIZE \ | |
487 | ? DEFAULT_CODE_GEN_BUFFER_SIZE_1 : MAX_CODE_GEN_BUFFER_SIZE) | |
488 | ||
489 | static inline size_t size_code_gen_buffer(size_t tb_size) | |
490 | { | |
491 | /* Size the buffer. */ | |
492 | if (tb_size == 0) { | |
493 | #ifdef USE_STATIC_CODE_GEN_BUFFER | |
494 | tb_size = DEFAULT_CODE_GEN_BUFFER_SIZE; | |
495 | #else | |
496 | /* ??? Needs adjustments. */ | |
497 | /* ??? If we relax the requirement that CONFIG_USER_ONLY use the | |
498 | static buffer, we could size this on RESERVED_VA, on the text | |
499 | segment size of the executable, or continue to use the default. */ | |
500 | tb_size = (unsigned long)(ram_size / 4); | |
501 | #endif | |
502 | } | |
503 | if (tb_size < MIN_CODE_GEN_BUFFER_SIZE) { | |
504 | tb_size = MIN_CODE_GEN_BUFFER_SIZE; | |
505 | } | |
506 | if (tb_size > MAX_CODE_GEN_BUFFER_SIZE) { | |
507 | tb_size = MAX_CODE_GEN_BUFFER_SIZE; | |
508 | } | |
0b0d3320 | 509 | tcg_ctx.code_gen_buffer_size = tb_size; |
5b6dd868 BS |
510 | return tb_size; |
511 | } | |
512 | ||
513 | #ifdef USE_STATIC_CODE_GEN_BUFFER | |
514 | static uint8_t static_code_gen_buffer[DEFAULT_CODE_GEN_BUFFER_SIZE] | |
515 | __attribute__((aligned(CODE_GEN_ALIGN))); | |
516 | ||
517 | static inline void *alloc_code_gen_buffer(void) | |
518 | { | |
0b0d3320 | 519 | map_exec(static_code_gen_buffer, tcg_ctx.code_gen_buffer_size); |
5b6dd868 BS |
520 | return static_code_gen_buffer; |
521 | } | |
522 | #elif defined(USE_MMAP) | |
523 | static inline void *alloc_code_gen_buffer(void) | |
524 | { | |
525 | int flags = MAP_PRIVATE | MAP_ANONYMOUS; | |
526 | uintptr_t start = 0; | |
527 | void *buf; | |
528 | ||
529 | /* Constrain the position of the buffer based on the host cpu. | |
530 | Note that these addresses are chosen in concert with the | |
531 | addresses assigned in the relevant linker script file. */ | |
532 | # if defined(__PIE__) || defined(__PIC__) | |
533 | /* Don't bother setting a preferred location if we're building | |
534 | a position-independent executable. We're more likely to get | |
535 | an address near the main executable if we let the kernel | |
536 | choose the address. */ | |
537 | # elif defined(__x86_64__) && defined(MAP_32BIT) | |
538 | /* Force the memory down into low memory with the executable. | |
539 | Leave the choice of exact location with the kernel. */ | |
540 | flags |= MAP_32BIT; | |
541 | /* Cannot expect to map more than 800MB in low memory. */ | |
0b0d3320 EV |
542 | if (tcg_ctx.code_gen_buffer_size > 800u * 1024 * 1024) { |
543 | tcg_ctx.code_gen_buffer_size = 800u * 1024 * 1024; | |
5b6dd868 BS |
544 | } |
545 | # elif defined(__sparc__) | |
546 | start = 0x40000000ul; | |
547 | # elif defined(__s390x__) | |
548 | start = 0x90000000ul; | |
549 | # endif | |
550 | ||
0b0d3320 | 551 | buf = mmap((void *)start, tcg_ctx.code_gen_buffer_size, |
5b6dd868 BS |
552 | PROT_WRITE | PROT_READ | PROT_EXEC, flags, -1, 0); |
553 | return buf == MAP_FAILED ? NULL : buf; | |
554 | } | |
555 | #else | |
556 | static inline void *alloc_code_gen_buffer(void) | |
557 | { | |
0b0d3320 | 558 | void *buf = g_malloc(tcg_ctx.code_gen_buffer_size); |
5b6dd868 BS |
559 | |
560 | if (buf) { | |
0b0d3320 | 561 | map_exec(buf, tcg_ctx.code_gen_buffer_size); |
5b6dd868 BS |
562 | } |
563 | return buf; | |
564 | } | |
565 | #endif /* USE_STATIC_CODE_GEN_BUFFER, USE_MMAP */ | |
566 | ||
567 | static inline void code_gen_alloc(size_t tb_size) | |
568 | { | |
0b0d3320 EV |
569 | tcg_ctx.code_gen_buffer_size = size_code_gen_buffer(tb_size); |
570 | tcg_ctx.code_gen_buffer = alloc_code_gen_buffer(); | |
571 | if (tcg_ctx.code_gen_buffer == NULL) { | |
5b6dd868 BS |
572 | fprintf(stderr, "Could not allocate dynamic translator buffer\n"); |
573 | exit(1); | |
574 | } | |
575 | ||
0b0d3320 EV |
576 | qemu_madvise(tcg_ctx.code_gen_buffer, tcg_ctx.code_gen_buffer_size, |
577 | QEMU_MADV_HUGEPAGE); | |
5b6dd868 BS |
578 | |
579 | /* Steal room for the prologue at the end of the buffer. This ensures | |
580 | (via the MAX_CODE_GEN_BUFFER_SIZE limits above) that direct branches | |
581 | from TB's to the prologue are going to be in range. It also means | |
582 | that we don't need to mark (additional) portions of the data segment | |
583 | as executable. */ | |
0b0d3320 EV |
584 | tcg_ctx.code_gen_prologue = tcg_ctx.code_gen_buffer + |
585 | tcg_ctx.code_gen_buffer_size - 1024; | |
586 | tcg_ctx.code_gen_buffer_size -= 1024; | |
5b6dd868 | 587 | |
0b0d3320 | 588 | tcg_ctx.code_gen_buffer_max_size = tcg_ctx.code_gen_buffer_size - |
5b6dd868 | 589 | (TCG_MAX_OP_SIZE * OPC_BUF_SIZE); |
0b0d3320 EV |
590 | tcg_ctx.code_gen_max_blocks = tcg_ctx.code_gen_buffer_size / |
591 | CODE_GEN_AVG_BLOCK_SIZE; | |
592 | tbs = g_malloc(tcg_ctx.code_gen_max_blocks * sizeof(TranslationBlock)); | |
5b6dd868 BS |
593 | } |
594 | ||
595 | /* Must be called before using the QEMU cpus. 'tb_size' is the size | |
596 | (in bytes) allocated to the translation buffer. Zero means default | |
597 | size. */ | |
598 | void tcg_exec_init(unsigned long tb_size) | |
599 | { | |
600 | cpu_gen_init(); | |
601 | code_gen_alloc(tb_size); | |
0b0d3320 EV |
602 | tcg_ctx.code_gen_ptr = tcg_ctx.code_gen_buffer; |
603 | tcg_register_jit(tcg_ctx.code_gen_buffer, tcg_ctx.code_gen_buffer_size); | |
5b6dd868 BS |
604 | page_init(); |
605 | #if !defined(CONFIG_USER_ONLY) || !defined(CONFIG_USE_GUEST_BASE) | |
606 | /* There's no guest base to take into account, so go ahead and | |
607 | initialize the prologue now. */ | |
608 | tcg_prologue_init(&tcg_ctx); | |
609 | #endif | |
610 | } | |
611 | ||
612 | bool tcg_enabled(void) | |
613 | { | |
0b0d3320 | 614 | return tcg_ctx.code_gen_buffer != NULL; |
5b6dd868 BS |
615 | } |
616 | ||
617 | /* Allocate a new translation block. Flush the translation buffer if | |
618 | too many translation blocks or too much generated code. */ | |
619 | static TranslationBlock *tb_alloc(target_ulong pc) | |
620 | { | |
621 | TranslationBlock *tb; | |
622 | ||
0b0d3320 EV |
623 | if (nb_tbs >= tcg_ctx.code_gen_max_blocks || |
624 | (tcg_ctx.code_gen_ptr - tcg_ctx.code_gen_buffer) >= | |
625 | tcg_ctx.code_gen_buffer_max_size) { | |
5b6dd868 BS |
626 | return NULL; |
627 | } | |
628 | tb = &tbs[nb_tbs++]; | |
629 | tb->pc = pc; | |
630 | tb->cflags = 0; | |
631 | return tb; | |
632 | } | |
633 | ||
634 | void tb_free(TranslationBlock *tb) | |
635 | { | |
636 | /* In practice this is mostly used for single use temporary TB | |
637 | Ignore the hard cases and just back up if this TB happens to | |
638 | be the last one generated. */ | |
639 | if (nb_tbs > 0 && tb == &tbs[nb_tbs - 1]) { | |
0b0d3320 | 640 | tcg_ctx.code_gen_ptr = tb->tc_ptr; |
5b6dd868 BS |
641 | nb_tbs--; |
642 | } | |
643 | } | |
644 | ||
645 | static inline void invalidate_page_bitmap(PageDesc *p) | |
646 | { | |
647 | if (p->code_bitmap) { | |
648 | g_free(p->code_bitmap); | |
649 | p->code_bitmap = NULL; | |
650 | } | |
651 | p->code_write_count = 0; | |
652 | } | |
653 | ||
654 | /* Set to NULL all the 'first_tb' fields in all PageDescs. */ | |
655 | static void page_flush_tb_1(int level, void **lp) | |
656 | { | |
657 | int i; | |
658 | ||
659 | if (*lp == NULL) { | |
660 | return; | |
661 | } | |
662 | if (level == 0) { | |
663 | PageDesc *pd = *lp; | |
664 | ||
665 | for (i = 0; i < L2_SIZE; ++i) { | |
666 | pd[i].first_tb = NULL; | |
667 | invalidate_page_bitmap(pd + i); | |
668 | } | |
669 | } else { | |
670 | void **pp = *lp; | |
671 | ||
672 | for (i = 0; i < L2_SIZE; ++i) { | |
673 | page_flush_tb_1(level - 1, pp + i); | |
674 | } | |
675 | } | |
676 | } | |
677 | ||
678 | static void page_flush_tb(void) | |
679 | { | |
680 | int i; | |
681 | ||
682 | for (i = 0; i < V_L1_SIZE; i++) { | |
683 | page_flush_tb_1(V_L1_SHIFT / L2_BITS - 1, l1_map + i); | |
684 | } | |
685 | } | |
686 | ||
687 | /* flush all the translation blocks */ | |
688 | /* XXX: tb_flush is currently not thread safe */ | |
689 | void tb_flush(CPUArchState *env1) | |
690 | { | |
691 | CPUArchState *env; | |
692 | ||
693 | #if defined(DEBUG_FLUSH) | |
694 | printf("qemu: flush code_size=%ld nb_tbs=%d avg_tb_size=%ld\n", | |
0b0d3320 | 695 | (unsigned long)(tcg_ctx.code_gen_ptr - tcg_ctx.code_gen_buffer), |
5b6dd868 | 696 | nb_tbs, nb_tbs > 0 ? |
0b0d3320 EV |
697 | ((unsigned long)(tcg_ctx.code_gen_ptr - tcg_ctx.code_gen_buffer)) / |
698 | nb_tbs : 0); | |
5b6dd868 | 699 | #endif |
0b0d3320 EV |
700 | if ((unsigned long)(tcg_ctx.code_gen_ptr - tcg_ctx.code_gen_buffer) |
701 | > tcg_ctx.code_gen_buffer_size) { | |
5b6dd868 BS |
702 | cpu_abort(env1, "Internal error: code buffer overflow\n"); |
703 | } | |
704 | nb_tbs = 0; | |
705 | ||
706 | for (env = first_cpu; env != NULL; env = env->next_cpu) { | |
707 | memset(env->tb_jmp_cache, 0, TB_JMP_CACHE_SIZE * sizeof(void *)); | |
708 | } | |
709 | ||
710 | memset(tb_phys_hash, 0, CODE_GEN_PHYS_HASH_SIZE * sizeof(void *)); | |
711 | page_flush_tb(); | |
712 | ||
0b0d3320 | 713 | tcg_ctx.code_gen_ptr = tcg_ctx.code_gen_buffer; |
5b6dd868 BS |
714 | /* XXX: flush processor icache at this point if cache flush is |
715 | expensive */ | |
716 | tb_flush_count++; | |
717 | } | |
718 | ||
719 | #ifdef DEBUG_TB_CHECK | |
720 | ||
721 | static void tb_invalidate_check(target_ulong address) | |
722 | { | |
723 | TranslationBlock *tb; | |
724 | int i; | |
725 | ||
726 | address &= TARGET_PAGE_MASK; | |
727 | for (i = 0; i < CODE_GEN_PHYS_HASH_SIZE; i++) { | |
728 | for (tb = tb_phys_hash[i]; tb != NULL; tb = tb->phys_hash_next) { | |
729 | if (!(address + TARGET_PAGE_SIZE <= tb->pc || | |
730 | address >= tb->pc + tb->size)) { | |
731 | printf("ERROR invalidate: address=" TARGET_FMT_lx | |
732 | " PC=%08lx size=%04x\n", | |
733 | address, (long)tb->pc, tb->size); | |
734 | } | |
735 | } | |
736 | } | |
737 | } | |
738 | ||
739 | /* verify that all the pages have correct rights for code */ | |
740 | static void tb_page_check(void) | |
741 | { | |
742 | TranslationBlock *tb; | |
743 | int i, flags1, flags2; | |
744 | ||
745 | for (i = 0; i < CODE_GEN_PHYS_HASH_SIZE; i++) { | |
746 | for (tb = tb_phys_hash[i]; tb != NULL; tb = tb->phys_hash_next) { | |
747 | flags1 = page_get_flags(tb->pc); | |
748 | flags2 = page_get_flags(tb->pc + tb->size - 1); | |
749 | if ((flags1 & PAGE_WRITE) || (flags2 & PAGE_WRITE)) { | |
750 | printf("ERROR page flags: PC=%08lx size=%04x f1=%x f2=%x\n", | |
751 | (long)tb->pc, tb->size, flags1, flags2); | |
752 | } | |
753 | } | |
754 | } | |
755 | } | |
756 | ||
757 | #endif | |
758 | ||
0c884d16 | 759 | static inline void tb_hash_remove(TranslationBlock **ptb, TranslationBlock *tb) |
5b6dd868 BS |
760 | { |
761 | TranslationBlock *tb1; | |
762 | ||
763 | for (;;) { | |
764 | tb1 = *ptb; | |
765 | if (tb1 == tb) { | |
0c884d16 | 766 | *ptb = tb1->phys_hash_next; |
5b6dd868 BS |
767 | break; |
768 | } | |
0c884d16 | 769 | ptb = &tb1->phys_hash_next; |
5b6dd868 BS |
770 | } |
771 | } | |
772 | ||
773 | static inline void tb_page_remove(TranslationBlock **ptb, TranslationBlock *tb) | |
774 | { | |
775 | TranslationBlock *tb1; | |
776 | unsigned int n1; | |
777 | ||
778 | for (;;) { | |
779 | tb1 = *ptb; | |
780 | n1 = (uintptr_t)tb1 & 3; | |
781 | tb1 = (TranslationBlock *)((uintptr_t)tb1 & ~3); | |
782 | if (tb1 == tb) { | |
783 | *ptb = tb1->page_next[n1]; | |
784 | break; | |
785 | } | |
786 | ptb = &tb1->page_next[n1]; | |
787 | } | |
788 | } | |
789 | ||
790 | static inline void tb_jmp_remove(TranslationBlock *tb, int n) | |
791 | { | |
792 | TranslationBlock *tb1, **ptb; | |
793 | unsigned int n1; | |
794 | ||
795 | ptb = &tb->jmp_next[n]; | |
796 | tb1 = *ptb; | |
797 | if (tb1) { | |
798 | /* find tb(n) in circular list */ | |
799 | for (;;) { | |
800 | tb1 = *ptb; | |
801 | n1 = (uintptr_t)tb1 & 3; | |
802 | tb1 = (TranslationBlock *)((uintptr_t)tb1 & ~3); | |
803 | if (n1 == n && tb1 == tb) { | |
804 | break; | |
805 | } | |
806 | if (n1 == 2) { | |
807 | ptb = &tb1->jmp_first; | |
808 | } else { | |
809 | ptb = &tb1->jmp_next[n1]; | |
810 | } | |
811 | } | |
812 | /* now we can suppress tb(n) from the list */ | |
813 | *ptb = tb->jmp_next[n]; | |
814 | ||
815 | tb->jmp_next[n] = NULL; | |
816 | } | |
817 | } | |
818 | ||
819 | /* reset the jump entry 'n' of a TB so that it is not chained to | |
820 | another TB */ | |
821 | static inline void tb_reset_jump(TranslationBlock *tb, int n) | |
822 | { | |
823 | tb_set_jmp_target(tb, n, (uintptr_t)(tb->tc_ptr + tb->tb_next_offset[n])); | |
824 | } | |
825 | ||
0c884d16 | 826 | /* invalidate one TB */ |
5b6dd868 BS |
827 | void tb_phys_invalidate(TranslationBlock *tb, tb_page_addr_t page_addr) |
828 | { | |
829 | CPUArchState *env; | |
830 | PageDesc *p; | |
831 | unsigned int h, n1; | |
832 | tb_page_addr_t phys_pc; | |
833 | TranslationBlock *tb1, *tb2; | |
834 | ||
835 | /* remove the TB from the hash list */ | |
836 | phys_pc = tb->page_addr[0] + (tb->pc & ~TARGET_PAGE_MASK); | |
837 | h = tb_phys_hash_func(phys_pc); | |
0c884d16 | 838 | tb_hash_remove(&tb_phys_hash[h], tb); |
5b6dd868 BS |
839 | |
840 | /* remove the TB from the page list */ | |
841 | if (tb->page_addr[0] != page_addr) { | |
842 | p = page_find(tb->page_addr[0] >> TARGET_PAGE_BITS); | |
843 | tb_page_remove(&p->first_tb, tb); | |
844 | invalidate_page_bitmap(p); | |
845 | } | |
846 | if (tb->page_addr[1] != -1 && tb->page_addr[1] != page_addr) { | |
847 | p = page_find(tb->page_addr[1] >> TARGET_PAGE_BITS); | |
848 | tb_page_remove(&p->first_tb, tb); | |
849 | invalidate_page_bitmap(p); | |
850 | } | |
851 | ||
852 | tb_invalidated_flag = 1; | |
853 | ||
854 | /* remove the TB from the hash list */ | |
855 | h = tb_jmp_cache_hash_func(tb->pc); | |
856 | for (env = first_cpu; env != NULL; env = env->next_cpu) { | |
857 | if (env->tb_jmp_cache[h] == tb) { | |
858 | env->tb_jmp_cache[h] = NULL; | |
859 | } | |
860 | } | |
861 | ||
862 | /* suppress this TB from the two jump lists */ | |
863 | tb_jmp_remove(tb, 0); | |
864 | tb_jmp_remove(tb, 1); | |
865 | ||
866 | /* suppress any remaining jumps to this TB */ | |
867 | tb1 = tb->jmp_first; | |
868 | for (;;) { | |
869 | n1 = (uintptr_t)tb1 & 3; | |
870 | if (n1 == 2) { | |
871 | break; | |
872 | } | |
873 | tb1 = (TranslationBlock *)((uintptr_t)tb1 & ~3); | |
874 | tb2 = tb1->jmp_next[n1]; | |
875 | tb_reset_jump(tb1, n1); | |
876 | tb1->jmp_next[n1] = NULL; | |
877 | tb1 = tb2; | |
878 | } | |
879 | tb->jmp_first = (TranslationBlock *)((uintptr_t)tb | 2); /* fail safe */ | |
880 | ||
881 | tb_phys_invalidate_count++; | |
882 | } | |
883 | ||
884 | static inline void set_bits(uint8_t *tab, int start, int len) | |
885 | { | |
886 | int end, mask, end1; | |
887 | ||
888 | end = start + len; | |
889 | tab += start >> 3; | |
890 | mask = 0xff << (start & 7); | |
891 | if ((start & ~7) == (end & ~7)) { | |
892 | if (start < end) { | |
893 | mask &= ~(0xff << (end & 7)); | |
894 | *tab |= mask; | |
895 | } | |
896 | } else { | |
897 | *tab++ |= mask; | |
898 | start = (start + 8) & ~7; | |
899 | end1 = end & ~7; | |
900 | while (start < end1) { | |
901 | *tab++ = 0xff; | |
902 | start += 8; | |
903 | } | |
904 | if (start < end) { | |
905 | mask = ~(0xff << (end & 7)); | |
906 | *tab |= mask; | |
907 | } | |
908 | } | |
909 | } | |
910 | ||
911 | static void build_page_bitmap(PageDesc *p) | |
912 | { | |
913 | int n, tb_start, tb_end; | |
914 | TranslationBlock *tb; | |
915 | ||
916 | p->code_bitmap = g_malloc0(TARGET_PAGE_SIZE / 8); | |
917 | ||
918 | tb = p->first_tb; | |
919 | while (tb != NULL) { | |
920 | n = (uintptr_t)tb & 3; | |
921 | tb = (TranslationBlock *)((uintptr_t)tb & ~3); | |
922 | /* NOTE: this is subtle as a TB may span two physical pages */ | |
923 | if (n == 0) { | |
924 | /* NOTE: tb_end may be after the end of the page, but | |
925 | it is not a problem */ | |
926 | tb_start = tb->pc & ~TARGET_PAGE_MASK; | |
927 | tb_end = tb_start + tb->size; | |
928 | if (tb_end > TARGET_PAGE_SIZE) { | |
929 | tb_end = TARGET_PAGE_SIZE; | |
930 | } | |
931 | } else { | |
932 | tb_start = 0; | |
933 | tb_end = ((tb->pc + tb->size) & ~TARGET_PAGE_MASK); | |
934 | } | |
935 | set_bits(p->code_bitmap, tb_start, tb_end - tb_start); | |
936 | tb = tb->page_next[n]; | |
937 | } | |
938 | } | |
939 | ||
940 | TranslationBlock *tb_gen_code(CPUArchState *env, | |
941 | target_ulong pc, target_ulong cs_base, | |
942 | int flags, int cflags) | |
943 | { | |
944 | TranslationBlock *tb; | |
945 | uint8_t *tc_ptr; | |
946 | tb_page_addr_t phys_pc, phys_page2; | |
947 | target_ulong virt_page2; | |
948 | int code_gen_size; | |
949 | ||
950 | phys_pc = get_page_addr_code(env, pc); | |
951 | tb = tb_alloc(pc); | |
952 | if (!tb) { | |
953 | /* flush must be done */ | |
954 | tb_flush(env); | |
955 | /* cannot fail at this point */ | |
956 | tb = tb_alloc(pc); | |
957 | /* Don't forget to invalidate previous TB info. */ | |
958 | tb_invalidated_flag = 1; | |
959 | } | |
0b0d3320 | 960 | tc_ptr = tcg_ctx.code_gen_ptr; |
5b6dd868 BS |
961 | tb->tc_ptr = tc_ptr; |
962 | tb->cs_base = cs_base; | |
963 | tb->flags = flags; | |
964 | tb->cflags = cflags; | |
965 | cpu_gen_code(env, tb, &code_gen_size); | |
0b0d3320 EV |
966 | tcg_ctx.code_gen_ptr = (void *)(((uintptr_t)tcg_ctx.code_gen_ptr + |
967 | code_gen_size + CODE_GEN_ALIGN - 1) & ~(CODE_GEN_ALIGN - 1)); | |
5b6dd868 BS |
968 | |
969 | /* check next page if needed */ | |
970 | virt_page2 = (pc + tb->size - 1) & TARGET_PAGE_MASK; | |
971 | phys_page2 = -1; | |
972 | if ((pc & TARGET_PAGE_MASK) != virt_page2) { | |
973 | phys_page2 = get_page_addr_code(env, virt_page2); | |
974 | } | |
975 | tb_link_page(tb, phys_pc, phys_page2); | |
976 | return tb; | |
977 | } | |
978 | ||
979 | /* | |
980 | * Invalidate all TBs which intersect with the target physical address range | |
981 | * [start;end[. NOTE: start and end may refer to *different* physical pages. | |
982 | * 'is_cpu_write_access' should be true if called from a real cpu write | |
983 | * access: the virtual CPU will exit the current TB if code is modified inside | |
984 | * this TB. | |
985 | */ | |
986 | void tb_invalidate_phys_range(tb_page_addr_t start, tb_page_addr_t end, | |
987 | int is_cpu_write_access) | |
988 | { | |
989 | while (start < end) { | |
990 | tb_invalidate_phys_page_range(start, end, is_cpu_write_access); | |
991 | start &= TARGET_PAGE_MASK; | |
992 | start += TARGET_PAGE_SIZE; | |
993 | } | |
994 | } | |
995 | ||
996 | /* | |
997 | * Invalidate all TBs which intersect with the target physical address range | |
998 | * [start;end[. NOTE: start and end must refer to the *same* physical page. | |
999 | * 'is_cpu_write_access' should be true if called from a real cpu write | |
1000 | * access: the virtual CPU will exit the current TB if code is modified inside | |
1001 | * this TB. | |
1002 | */ | |
1003 | void tb_invalidate_phys_page_range(tb_page_addr_t start, tb_page_addr_t end, | |
1004 | int is_cpu_write_access) | |
1005 | { | |
1006 | TranslationBlock *tb, *tb_next, *saved_tb; | |
1007 | CPUArchState *env = cpu_single_env; | |
1008 | tb_page_addr_t tb_start, tb_end; | |
1009 | PageDesc *p; | |
1010 | int n; | |
1011 | #ifdef TARGET_HAS_PRECISE_SMC | |
1012 | int current_tb_not_found = is_cpu_write_access; | |
1013 | TranslationBlock *current_tb = NULL; | |
1014 | int current_tb_modified = 0; | |
1015 | target_ulong current_pc = 0; | |
1016 | target_ulong current_cs_base = 0; | |
1017 | int current_flags = 0; | |
1018 | #endif /* TARGET_HAS_PRECISE_SMC */ | |
1019 | ||
1020 | p = page_find(start >> TARGET_PAGE_BITS); | |
1021 | if (!p) { | |
1022 | return; | |
1023 | } | |
1024 | if (!p->code_bitmap && | |
1025 | ++p->code_write_count >= SMC_BITMAP_USE_THRESHOLD && | |
1026 | is_cpu_write_access) { | |
1027 | /* build code bitmap */ | |
1028 | build_page_bitmap(p); | |
1029 | } | |
1030 | ||
1031 | /* we remove all the TBs in the range [start, end[ */ | |
1032 | /* XXX: see if in some cases it could be faster to invalidate all | |
1033 | the code */ | |
1034 | tb = p->first_tb; | |
1035 | while (tb != NULL) { | |
1036 | n = (uintptr_t)tb & 3; | |
1037 | tb = (TranslationBlock *)((uintptr_t)tb & ~3); | |
1038 | tb_next = tb->page_next[n]; | |
1039 | /* NOTE: this is subtle as a TB may span two physical pages */ | |
1040 | if (n == 0) { | |
1041 | /* NOTE: tb_end may be after the end of the page, but | |
1042 | it is not a problem */ | |
1043 | tb_start = tb->page_addr[0] + (tb->pc & ~TARGET_PAGE_MASK); | |
1044 | tb_end = tb_start + tb->size; | |
1045 | } else { | |
1046 | tb_start = tb->page_addr[1]; | |
1047 | tb_end = tb_start + ((tb->pc + tb->size) & ~TARGET_PAGE_MASK); | |
1048 | } | |
1049 | if (!(tb_end <= start || tb_start >= end)) { | |
1050 | #ifdef TARGET_HAS_PRECISE_SMC | |
1051 | if (current_tb_not_found) { | |
1052 | current_tb_not_found = 0; | |
1053 | current_tb = NULL; | |
1054 | if (env->mem_io_pc) { | |
1055 | /* now we have a real cpu fault */ | |
1056 | current_tb = tb_find_pc(env->mem_io_pc); | |
1057 | } | |
1058 | } | |
1059 | if (current_tb == tb && | |
1060 | (current_tb->cflags & CF_COUNT_MASK) != 1) { | |
1061 | /* If we are modifying the current TB, we must stop | |
1062 | its execution. We could be more precise by checking | |
1063 | that the modification is after the current PC, but it | |
1064 | would require a specialized function to partially | |
1065 | restore the CPU state */ | |
1066 | ||
1067 | current_tb_modified = 1; | |
a8a826a3 | 1068 | cpu_restore_state_from_tb(current_tb, env, env->mem_io_pc); |
5b6dd868 BS |
1069 | cpu_get_tb_cpu_state(env, ¤t_pc, ¤t_cs_base, |
1070 | ¤t_flags); | |
1071 | } | |
1072 | #endif /* TARGET_HAS_PRECISE_SMC */ | |
1073 | /* we need to do that to handle the case where a signal | |
1074 | occurs while doing tb_phys_invalidate() */ | |
1075 | saved_tb = NULL; | |
1076 | if (env) { | |
1077 | saved_tb = env->current_tb; | |
1078 | env->current_tb = NULL; | |
1079 | } | |
1080 | tb_phys_invalidate(tb, -1); | |
1081 | if (env) { | |
1082 | env->current_tb = saved_tb; | |
1083 | if (env->interrupt_request && env->current_tb) { | |
1084 | cpu_interrupt(env, env->interrupt_request); | |
1085 | } | |
1086 | } | |
1087 | } | |
1088 | tb = tb_next; | |
1089 | } | |
1090 | #if !defined(CONFIG_USER_ONLY) | |
1091 | /* if no code remaining, no need to continue to use slow writes */ | |
1092 | if (!p->first_tb) { | |
1093 | invalidate_page_bitmap(p); | |
1094 | if (is_cpu_write_access) { | |
1095 | tlb_unprotect_code_phys(env, start, env->mem_io_vaddr); | |
1096 | } | |
1097 | } | |
1098 | #endif | |
1099 | #ifdef TARGET_HAS_PRECISE_SMC | |
1100 | if (current_tb_modified) { | |
1101 | /* we generate a block containing just the instruction | |
1102 | modifying the memory. It will ensure that it cannot modify | |
1103 | itself */ | |
1104 | env->current_tb = NULL; | |
1105 | tb_gen_code(env, current_pc, current_cs_base, current_flags, 1); | |
1106 | cpu_resume_from_signal(env, NULL); | |
1107 | } | |
1108 | #endif | |
1109 | } | |
1110 | ||
1111 | /* len must be <= 8 and start must be a multiple of len */ | |
1112 | void tb_invalidate_phys_page_fast(tb_page_addr_t start, int len) | |
1113 | { | |
1114 | PageDesc *p; | |
1115 | int offset, b; | |
1116 | ||
1117 | #if 0 | |
1118 | if (1) { | |
1119 | qemu_log("modifying code at 0x%x size=%d EIP=%x PC=%08x\n", | |
1120 | cpu_single_env->mem_io_vaddr, len, | |
1121 | cpu_single_env->eip, | |
1122 | cpu_single_env->eip + | |
1123 | (intptr_t)cpu_single_env->segs[R_CS].base); | |
1124 | } | |
1125 | #endif | |
1126 | p = page_find(start >> TARGET_PAGE_BITS); | |
1127 | if (!p) { | |
1128 | return; | |
1129 | } | |
1130 | if (p->code_bitmap) { | |
1131 | offset = start & ~TARGET_PAGE_MASK; | |
1132 | b = p->code_bitmap[offset >> 3] >> (offset & 7); | |
1133 | if (b & ((1 << len) - 1)) { | |
1134 | goto do_invalidate; | |
1135 | } | |
1136 | } else { | |
1137 | do_invalidate: | |
1138 | tb_invalidate_phys_page_range(start, start + len, 1); | |
1139 | } | |
1140 | } | |
1141 | ||
1142 | #if !defined(CONFIG_SOFTMMU) | |
1143 | static void tb_invalidate_phys_page(tb_page_addr_t addr, | |
1144 | uintptr_t pc, void *puc) | |
1145 | { | |
1146 | TranslationBlock *tb; | |
1147 | PageDesc *p; | |
1148 | int n; | |
1149 | #ifdef TARGET_HAS_PRECISE_SMC | |
1150 | TranslationBlock *current_tb = NULL; | |
1151 | CPUArchState *env = cpu_single_env; | |
1152 | int current_tb_modified = 0; | |
1153 | target_ulong current_pc = 0; | |
1154 | target_ulong current_cs_base = 0; | |
1155 | int current_flags = 0; | |
1156 | #endif | |
1157 | ||
1158 | addr &= TARGET_PAGE_MASK; | |
1159 | p = page_find(addr >> TARGET_PAGE_BITS); | |
1160 | if (!p) { | |
1161 | return; | |
1162 | } | |
1163 | tb = p->first_tb; | |
1164 | #ifdef TARGET_HAS_PRECISE_SMC | |
1165 | if (tb && pc != 0) { | |
1166 | current_tb = tb_find_pc(pc); | |
1167 | } | |
1168 | #endif | |
1169 | while (tb != NULL) { | |
1170 | n = (uintptr_t)tb & 3; | |
1171 | tb = (TranslationBlock *)((uintptr_t)tb & ~3); | |
1172 | #ifdef TARGET_HAS_PRECISE_SMC | |
1173 | if (current_tb == tb && | |
1174 | (current_tb->cflags & CF_COUNT_MASK) != 1) { | |
1175 | /* If we are modifying the current TB, we must stop | |
1176 | its execution. We could be more precise by checking | |
1177 | that the modification is after the current PC, but it | |
1178 | would require a specialized function to partially | |
1179 | restore the CPU state */ | |
1180 | ||
1181 | current_tb_modified = 1; | |
a8a826a3 | 1182 | cpu_restore_state_from_tb(current_tb, env, pc); |
5b6dd868 BS |
1183 | cpu_get_tb_cpu_state(env, ¤t_pc, ¤t_cs_base, |
1184 | ¤t_flags); | |
1185 | } | |
1186 | #endif /* TARGET_HAS_PRECISE_SMC */ | |
1187 | tb_phys_invalidate(tb, addr); | |
1188 | tb = tb->page_next[n]; | |
1189 | } | |
1190 | p->first_tb = NULL; | |
1191 | #ifdef TARGET_HAS_PRECISE_SMC | |
1192 | if (current_tb_modified) { | |
1193 | /* we generate a block containing just the instruction | |
1194 | modifying the memory. It will ensure that it cannot modify | |
1195 | itself */ | |
1196 | env->current_tb = NULL; | |
1197 | tb_gen_code(env, current_pc, current_cs_base, current_flags, 1); | |
1198 | cpu_resume_from_signal(env, puc); | |
1199 | } | |
1200 | #endif | |
1201 | } | |
1202 | #endif | |
1203 | ||
1204 | /* add the tb in the target page and protect it if necessary */ | |
1205 | static inline void tb_alloc_page(TranslationBlock *tb, | |
1206 | unsigned int n, tb_page_addr_t page_addr) | |
1207 | { | |
1208 | PageDesc *p; | |
1209 | #ifndef CONFIG_USER_ONLY | |
1210 | bool page_already_protected; | |
1211 | #endif | |
1212 | ||
1213 | tb->page_addr[n] = page_addr; | |
1214 | p = page_find_alloc(page_addr >> TARGET_PAGE_BITS, 1); | |
1215 | tb->page_next[n] = p->first_tb; | |
1216 | #ifndef CONFIG_USER_ONLY | |
1217 | page_already_protected = p->first_tb != NULL; | |
1218 | #endif | |
1219 | p->first_tb = (TranslationBlock *)((uintptr_t)tb | n); | |
1220 | invalidate_page_bitmap(p); | |
1221 | ||
1222 | #if defined(TARGET_HAS_SMC) || 1 | |
1223 | ||
1224 | #if defined(CONFIG_USER_ONLY) | |
1225 | if (p->flags & PAGE_WRITE) { | |
1226 | target_ulong addr; | |
1227 | PageDesc *p2; | |
1228 | int prot; | |
1229 | ||
1230 | /* force the host page as non writable (writes will have a | |
1231 | page fault + mprotect overhead) */ | |
1232 | page_addr &= qemu_host_page_mask; | |
1233 | prot = 0; | |
1234 | for (addr = page_addr; addr < page_addr + qemu_host_page_size; | |
1235 | addr += TARGET_PAGE_SIZE) { | |
1236 | ||
1237 | p2 = page_find(addr >> TARGET_PAGE_BITS); | |
1238 | if (!p2) { | |
1239 | continue; | |
1240 | } | |
1241 | prot |= p2->flags; | |
1242 | p2->flags &= ~PAGE_WRITE; | |
1243 | } | |
1244 | mprotect(g2h(page_addr), qemu_host_page_size, | |
1245 | (prot & PAGE_BITS) & ~PAGE_WRITE); | |
1246 | #ifdef DEBUG_TB_INVALIDATE | |
1247 | printf("protecting code page: 0x" TARGET_FMT_lx "\n", | |
1248 | page_addr); | |
1249 | #endif | |
1250 | } | |
1251 | #else | |
1252 | /* if some code is already present, then the pages are already | |
1253 | protected. So we handle the case where only the first TB is | |
1254 | allocated in a physical page */ | |
1255 | if (!page_already_protected) { | |
1256 | tlb_protect_code(page_addr); | |
1257 | } | |
1258 | #endif | |
1259 | ||
1260 | #endif /* TARGET_HAS_SMC */ | |
1261 | } | |
1262 | ||
1263 | /* add a new TB and link it to the physical page tables. phys_page2 is | |
1264 | (-1) to indicate that only one page contains the TB. */ | |
1265 | static void tb_link_page(TranslationBlock *tb, tb_page_addr_t phys_pc, | |
1266 | tb_page_addr_t phys_page2) | |
1267 | { | |
1268 | unsigned int h; | |
1269 | TranslationBlock **ptb; | |
1270 | ||
1271 | /* Grab the mmap lock to stop another thread invalidating this TB | |
1272 | before we are done. */ | |
1273 | mmap_lock(); | |
1274 | /* add in the physical hash table */ | |
1275 | h = tb_phys_hash_func(phys_pc); | |
1276 | ptb = &tb_phys_hash[h]; | |
1277 | tb->phys_hash_next = *ptb; | |
1278 | *ptb = tb; | |
1279 | ||
1280 | /* add in the page list */ | |
1281 | tb_alloc_page(tb, 0, phys_pc & TARGET_PAGE_MASK); | |
1282 | if (phys_page2 != -1) { | |
1283 | tb_alloc_page(tb, 1, phys_page2); | |
1284 | } else { | |
1285 | tb->page_addr[1] = -1; | |
1286 | } | |
1287 | ||
1288 | tb->jmp_first = (TranslationBlock *)((uintptr_t)tb | 2); | |
1289 | tb->jmp_next[0] = NULL; | |
1290 | tb->jmp_next[1] = NULL; | |
1291 | ||
1292 | /* init original jump addresses */ | |
1293 | if (tb->tb_next_offset[0] != 0xffff) { | |
1294 | tb_reset_jump(tb, 0); | |
1295 | } | |
1296 | if (tb->tb_next_offset[1] != 0xffff) { | |
1297 | tb_reset_jump(tb, 1); | |
1298 | } | |
1299 | ||
1300 | #ifdef DEBUG_TB_CHECK | |
1301 | tb_page_check(); | |
1302 | #endif | |
1303 | mmap_unlock(); | |
1304 | } | |
1305 | ||
1306 | #if defined(CONFIG_QEMU_LDST_OPTIMIZATION) && defined(CONFIG_SOFTMMU) | |
1307 | /* check whether the given addr is in TCG generated code buffer or not */ | |
1308 | bool is_tcg_gen_code(uintptr_t tc_ptr) | |
1309 | { | |
1310 | /* This can be called during code generation, code_gen_buffer_max_size | |
1311 | is used instead of code_gen_ptr for upper boundary checking */ | |
0b0d3320 EV |
1312 | return (tc_ptr >= (uintptr_t)tcg_ctx.code_gen_buffer && |
1313 | tc_ptr < (uintptr_t)(tcg_ctx.code_gen_buffer + | |
1314 | tcg_ctx.code_gen_buffer_max_size)); | |
5b6dd868 BS |
1315 | } |
1316 | #endif | |
1317 | ||
1318 | /* find the TB 'tb' such that tb[0].tc_ptr <= tc_ptr < | |
1319 | tb[1].tc_ptr. Return NULL if not found */ | |
a8a826a3 | 1320 | static TranslationBlock *tb_find_pc(uintptr_t tc_ptr) |
5b6dd868 BS |
1321 | { |
1322 | int m_min, m_max, m; | |
1323 | uintptr_t v; | |
1324 | TranslationBlock *tb; | |
1325 | ||
1326 | if (nb_tbs <= 0) { | |
1327 | return NULL; | |
1328 | } | |
0b0d3320 EV |
1329 | if (tc_ptr < (uintptr_t)tcg_ctx.code_gen_buffer || |
1330 | tc_ptr >= (uintptr_t)tcg_ctx.code_gen_ptr) { | |
5b6dd868 BS |
1331 | return NULL; |
1332 | } | |
1333 | /* binary search (cf Knuth) */ | |
1334 | m_min = 0; | |
1335 | m_max = nb_tbs - 1; | |
1336 | while (m_min <= m_max) { | |
1337 | m = (m_min + m_max) >> 1; | |
1338 | tb = &tbs[m]; | |
1339 | v = (uintptr_t)tb->tc_ptr; | |
1340 | if (v == tc_ptr) { | |
1341 | return tb; | |
1342 | } else if (tc_ptr < v) { | |
1343 | m_max = m - 1; | |
1344 | } else { | |
1345 | m_min = m + 1; | |
1346 | } | |
1347 | } | |
1348 | return &tbs[m_max]; | |
1349 | } | |
1350 | ||
1351 | static void tb_reset_jump_recursive(TranslationBlock *tb); | |
1352 | ||
1353 | static inline void tb_reset_jump_recursive2(TranslationBlock *tb, int n) | |
1354 | { | |
1355 | TranslationBlock *tb1, *tb_next, **ptb; | |
1356 | unsigned int n1; | |
1357 | ||
1358 | tb1 = tb->jmp_next[n]; | |
1359 | if (tb1 != NULL) { | |
1360 | /* find head of list */ | |
1361 | for (;;) { | |
1362 | n1 = (uintptr_t)tb1 & 3; | |
1363 | tb1 = (TranslationBlock *)((uintptr_t)tb1 & ~3); | |
1364 | if (n1 == 2) { | |
1365 | break; | |
1366 | } | |
1367 | tb1 = tb1->jmp_next[n1]; | |
1368 | } | |
1369 | /* we are now sure now that tb jumps to tb1 */ | |
1370 | tb_next = tb1; | |
1371 | ||
1372 | /* remove tb from the jmp_first list */ | |
1373 | ptb = &tb_next->jmp_first; | |
1374 | for (;;) { | |
1375 | tb1 = *ptb; | |
1376 | n1 = (uintptr_t)tb1 & 3; | |
1377 | tb1 = (TranslationBlock *)((uintptr_t)tb1 & ~3); | |
1378 | if (n1 == n && tb1 == tb) { | |
1379 | break; | |
1380 | } | |
1381 | ptb = &tb1->jmp_next[n1]; | |
1382 | } | |
1383 | *ptb = tb->jmp_next[n]; | |
1384 | tb->jmp_next[n] = NULL; | |
1385 | ||
1386 | /* suppress the jump to next tb in generated code */ | |
1387 | tb_reset_jump(tb, n); | |
1388 | ||
1389 | /* suppress jumps in the tb on which we could have jumped */ | |
1390 | tb_reset_jump_recursive(tb_next); | |
1391 | } | |
1392 | } | |
1393 | ||
1394 | static void tb_reset_jump_recursive(TranslationBlock *tb) | |
1395 | { | |
1396 | tb_reset_jump_recursive2(tb, 0); | |
1397 | tb_reset_jump_recursive2(tb, 1); | |
1398 | } | |
1399 | ||
1400 | #if defined(TARGET_HAS_ICE) && !defined(CONFIG_USER_ONLY) | |
1401 | void tb_invalidate_phys_addr(hwaddr addr) | |
1402 | { | |
1403 | ram_addr_t ram_addr; | |
1404 | MemoryRegionSection *section; | |
1405 | ||
1406 | section = phys_page_find(address_space_memory.dispatch, | |
1407 | addr >> TARGET_PAGE_BITS); | |
1408 | if (!(memory_region_is_ram(section->mr) | |
1409 | || (section->mr->rom_device && section->mr->readable))) { | |
1410 | return; | |
1411 | } | |
1412 | ram_addr = (memory_region_get_ram_addr(section->mr) & TARGET_PAGE_MASK) | |
1413 | + memory_region_section_addr(section, addr); | |
1414 | tb_invalidate_phys_page_range(ram_addr, ram_addr + 1, 0); | |
1415 | } | |
1416 | #endif /* TARGET_HAS_ICE && !defined(CONFIG_USER_ONLY) */ | |
1417 | ||
1418 | void cpu_unlink_tb(CPUArchState *env) | |
1419 | { | |
1420 | /* FIXME: TB unchaining isn't SMP safe. For now just ignore the | |
1421 | problem and hope the cpu will stop of its own accord. For userspace | |
1422 | emulation this often isn't actually as bad as it sounds. Often | |
1423 | signals are used primarily to interrupt blocking syscalls. */ | |
1424 | TranslationBlock *tb; | |
1425 | static spinlock_t interrupt_lock = SPIN_LOCK_UNLOCKED; | |
1426 | ||
1427 | spin_lock(&interrupt_lock); | |
1428 | tb = env->current_tb; | |
1429 | /* if the cpu is currently executing code, we must unlink it and | |
1430 | all the potentially executing TB */ | |
1431 | if (tb) { | |
1432 | env->current_tb = NULL; | |
1433 | tb_reset_jump_recursive(tb); | |
1434 | } | |
1435 | spin_unlock(&interrupt_lock); | |
1436 | } | |
1437 | ||
1438 | void tb_check_watchpoint(CPUArchState *env) | |
1439 | { | |
1440 | TranslationBlock *tb; | |
1441 | ||
1442 | tb = tb_find_pc(env->mem_io_pc); | |
1443 | if (!tb) { | |
1444 | cpu_abort(env, "check_watchpoint: could not find TB for pc=%p", | |
1445 | (void *)env->mem_io_pc); | |
1446 | } | |
a8a826a3 | 1447 | cpu_restore_state_from_tb(tb, env, env->mem_io_pc); |
5b6dd868 BS |
1448 | tb_phys_invalidate(tb, -1); |
1449 | } | |
1450 | ||
1451 | #ifndef CONFIG_USER_ONLY | |
1452 | /* mask must never be zero, except for A20 change call */ | |
1453 | static void tcg_handle_interrupt(CPUArchState *env, int mask) | |
1454 | { | |
1455 | CPUState *cpu = ENV_GET_CPU(env); | |
1456 | int old_mask; | |
1457 | ||
1458 | old_mask = env->interrupt_request; | |
1459 | env->interrupt_request |= mask; | |
1460 | ||
1461 | /* | |
1462 | * If called from iothread context, wake the target cpu in | |
1463 | * case its halted. | |
1464 | */ | |
1465 | if (!qemu_cpu_is_self(cpu)) { | |
1466 | qemu_cpu_kick(cpu); | |
1467 | return; | |
1468 | } | |
1469 | ||
1470 | if (use_icount) { | |
1471 | env->icount_decr.u16.high = 0xffff; | |
1472 | if (!can_do_io(env) | |
1473 | && (mask & ~old_mask) != 0) { | |
1474 | cpu_abort(env, "Raised interrupt while not in I/O function"); | |
1475 | } | |
1476 | } else { | |
1477 | cpu_unlink_tb(env); | |
1478 | } | |
1479 | } | |
1480 | ||
1481 | CPUInterruptHandler cpu_interrupt_handler = tcg_handle_interrupt; | |
1482 | ||
1483 | /* in deterministic execution mode, instructions doing device I/Os | |
1484 | must be at the end of the TB */ | |
1485 | void cpu_io_recompile(CPUArchState *env, uintptr_t retaddr) | |
1486 | { | |
1487 | TranslationBlock *tb; | |
1488 | uint32_t n, cflags; | |
1489 | target_ulong pc, cs_base; | |
1490 | uint64_t flags; | |
1491 | ||
1492 | tb = tb_find_pc(retaddr); | |
1493 | if (!tb) { | |
1494 | cpu_abort(env, "cpu_io_recompile: could not find TB for pc=%p", | |
1495 | (void *)retaddr); | |
1496 | } | |
1497 | n = env->icount_decr.u16.low + tb->icount; | |
a8a826a3 | 1498 | cpu_restore_state_from_tb(tb, env, retaddr); |
5b6dd868 BS |
1499 | /* Calculate how many instructions had been executed before the fault |
1500 | occurred. */ | |
1501 | n = n - env->icount_decr.u16.low; | |
1502 | /* Generate a new TB ending on the I/O insn. */ | |
1503 | n++; | |
1504 | /* On MIPS and SH, delay slot instructions can only be restarted if | |
1505 | they were already the first instruction in the TB. If this is not | |
1506 | the first instruction in a TB then re-execute the preceding | |
1507 | branch. */ | |
1508 | #if defined(TARGET_MIPS) | |
1509 | if ((env->hflags & MIPS_HFLAG_BMASK) != 0 && n > 1) { | |
1510 | env->active_tc.PC -= 4; | |
1511 | env->icount_decr.u16.low++; | |
1512 | env->hflags &= ~MIPS_HFLAG_BMASK; | |
1513 | } | |
1514 | #elif defined(TARGET_SH4) | |
1515 | if ((env->flags & ((DELAY_SLOT | DELAY_SLOT_CONDITIONAL))) != 0 | |
1516 | && n > 1) { | |
1517 | env->pc -= 2; | |
1518 | env->icount_decr.u16.low++; | |
1519 | env->flags &= ~(DELAY_SLOT | DELAY_SLOT_CONDITIONAL); | |
1520 | } | |
1521 | #endif | |
1522 | /* This should never happen. */ | |
1523 | if (n > CF_COUNT_MASK) { | |
1524 | cpu_abort(env, "TB too big during recompile"); | |
1525 | } | |
1526 | ||
1527 | cflags = n | CF_LAST_IO; | |
1528 | pc = tb->pc; | |
1529 | cs_base = tb->cs_base; | |
1530 | flags = tb->flags; | |
1531 | tb_phys_invalidate(tb, -1); | |
1532 | /* FIXME: In theory this could raise an exception. In practice | |
1533 | we have already translated the block once so it's probably ok. */ | |
1534 | tb_gen_code(env, pc, cs_base, flags, cflags); | |
1535 | /* TODO: If env->pc != tb->pc (i.e. the faulting instruction was not | |
1536 | the first in the TB) then we end up generating a whole new TB and | |
1537 | repeating the fault, which is horribly inefficient. | |
1538 | Better would be to execute just this insn uncached, or generate a | |
1539 | second new TB. */ | |
1540 | cpu_resume_from_signal(env, NULL); | |
1541 | } | |
1542 | ||
1543 | void tb_flush_jmp_cache(CPUArchState *env, target_ulong addr) | |
1544 | { | |
1545 | unsigned int i; | |
1546 | ||
1547 | /* Discard jump cache entries for any tb which might potentially | |
1548 | overlap the flushed page. */ | |
1549 | i = tb_jmp_cache_hash_page(addr - TARGET_PAGE_SIZE); | |
1550 | memset(&env->tb_jmp_cache[i], 0, | |
1551 | TB_JMP_PAGE_SIZE * sizeof(TranslationBlock *)); | |
1552 | ||
1553 | i = tb_jmp_cache_hash_page(addr); | |
1554 | memset(&env->tb_jmp_cache[i], 0, | |
1555 | TB_JMP_PAGE_SIZE * sizeof(TranslationBlock *)); | |
1556 | } | |
1557 | ||
1558 | void dump_exec_info(FILE *f, fprintf_function cpu_fprintf) | |
1559 | { | |
1560 | int i, target_code_size, max_target_code_size; | |
1561 | int direct_jmp_count, direct_jmp2_count, cross_page; | |
1562 | TranslationBlock *tb; | |
1563 | ||
1564 | target_code_size = 0; | |
1565 | max_target_code_size = 0; | |
1566 | cross_page = 0; | |
1567 | direct_jmp_count = 0; | |
1568 | direct_jmp2_count = 0; | |
1569 | for (i = 0; i < nb_tbs; i++) { | |
1570 | tb = &tbs[i]; | |
1571 | target_code_size += tb->size; | |
1572 | if (tb->size > max_target_code_size) { | |
1573 | max_target_code_size = tb->size; | |
1574 | } | |
1575 | if (tb->page_addr[1] != -1) { | |
1576 | cross_page++; | |
1577 | } | |
1578 | if (tb->tb_next_offset[0] != 0xffff) { | |
1579 | direct_jmp_count++; | |
1580 | if (tb->tb_next_offset[1] != 0xffff) { | |
1581 | direct_jmp2_count++; | |
1582 | } | |
1583 | } | |
1584 | } | |
1585 | /* XXX: avoid using doubles ? */ | |
1586 | cpu_fprintf(f, "Translation buffer state:\n"); | |
1587 | cpu_fprintf(f, "gen code size %td/%zd\n", | |
0b0d3320 EV |
1588 | tcg_ctx.code_gen_ptr - tcg_ctx.code_gen_buffer, |
1589 | tcg_ctx.code_gen_buffer_max_size); | |
5b6dd868 | 1590 | cpu_fprintf(f, "TB count %d/%d\n", |
0b0d3320 | 1591 | nb_tbs, tcg_ctx.code_gen_max_blocks); |
5b6dd868 BS |
1592 | cpu_fprintf(f, "TB avg target size %d max=%d bytes\n", |
1593 | nb_tbs ? target_code_size / nb_tbs : 0, | |
1594 | max_target_code_size); | |
1595 | cpu_fprintf(f, "TB avg host size %td bytes (expansion ratio: %0.1f)\n", | |
0b0d3320 EV |
1596 | nb_tbs ? (tcg_ctx.code_gen_ptr - tcg_ctx.code_gen_buffer) / |
1597 | nb_tbs : 0, | |
1598 | target_code_size ? | |
1599 | (double) (tcg_ctx.code_gen_ptr - tcg_ctx.code_gen_buffer) / | |
1600 | target_code_size : 0); | |
5b6dd868 BS |
1601 | cpu_fprintf(f, "cross page TB count %d (%d%%)\n", |
1602 | cross_page, | |
1603 | nb_tbs ? (cross_page * 100) / nb_tbs : 0); | |
1604 | cpu_fprintf(f, "direct jump count %d (%d%%) (2 jumps=%d %d%%)\n", | |
1605 | direct_jmp_count, | |
1606 | nb_tbs ? (direct_jmp_count * 100) / nb_tbs : 0, | |
1607 | direct_jmp2_count, | |
1608 | nb_tbs ? (direct_jmp2_count * 100) / nb_tbs : 0); | |
1609 | cpu_fprintf(f, "\nStatistics:\n"); | |
1610 | cpu_fprintf(f, "TB flush count %d\n", tb_flush_count); | |
1611 | cpu_fprintf(f, "TB invalidate count %d\n", tb_phys_invalidate_count); | |
1612 | cpu_fprintf(f, "TLB flush count %d\n", tlb_flush_count); | |
1613 | tcg_dump_info(f, cpu_fprintf); | |
1614 | } | |
1615 | ||
1616 | #else /* CONFIG_USER_ONLY */ | |
1617 | ||
1618 | void cpu_interrupt(CPUArchState *env, int mask) | |
1619 | { | |
1620 | env->interrupt_request |= mask; | |
1621 | cpu_unlink_tb(env); | |
1622 | } | |
1623 | ||
1624 | /* | |
1625 | * Walks guest process memory "regions" one by one | |
1626 | * and calls callback function 'fn' for each region. | |
1627 | */ | |
1628 | struct walk_memory_regions_data { | |
1629 | walk_memory_regions_fn fn; | |
1630 | void *priv; | |
1631 | uintptr_t start; | |
1632 | int prot; | |
1633 | }; | |
1634 | ||
1635 | static int walk_memory_regions_end(struct walk_memory_regions_data *data, | |
1636 | abi_ulong end, int new_prot) | |
1637 | { | |
1638 | if (data->start != -1ul) { | |
1639 | int rc = data->fn(data->priv, data->start, end, data->prot); | |
1640 | if (rc != 0) { | |
1641 | return rc; | |
1642 | } | |
1643 | } | |
1644 | ||
1645 | data->start = (new_prot ? end : -1ul); | |
1646 | data->prot = new_prot; | |
1647 | ||
1648 | return 0; | |
1649 | } | |
1650 | ||
1651 | static int walk_memory_regions_1(struct walk_memory_regions_data *data, | |
1652 | abi_ulong base, int level, void **lp) | |
1653 | { | |
1654 | abi_ulong pa; | |
1655 | int i, rc; | |
1656 | ||
1657 | if (*lp == NULL) { | |
1658 | return walk_memory_regions_end(data, base, 0); | |
1659 | } | |
1660 | ||
1661 | if (level == 0) { | |
1662 | PageDesc *pd = *lp; | |
1663 | ||
1664 | for (i = 0; i < L2_SIZE; ++i) { | |
1665 | int prot = pd[i].flags; | |
1666 | ||
1667 | pa = base | (i << TARGET_PAGE_BITS); | |
1668 | if (prot != data->prot) { | |
1669 | rc = walk_memory_regions_end(data, pa, prot); | |
1670 | if (rc != 0) { | |
1671 | return rc; | |
1672 | } | |
1673 | } | |
1674 | } | |
1675 | } else { | |
1676 | void **pp = *lp; | |
1677 | ||
1678 | for (i = 0; i < L2_SIZE; ++i) { | |
1679 | pa = base | ((abi_ulong)i << | |
1680 | (TARGET_PAGE_BITS + L2_BITS * level)); | |
1681 | rc = walk_memory_regions_1(data, pa, level - 1, pp + i); | |
1682 | if (rc != 0) { | |
1683 | return rc; | |
1684 | } | |
1685 | } | |
1686 | } | |
1687 | ||
1688 | return 0; | |
1689 | } | |
1690 | ||
1691 | int walk_memory_regions(void *priv, walk_memory_regions_fn fn) | |
1692 | { | |
1693 | struct walk_memory_regions_data data; | |
1694 | uintptr_t i; | |
1695 | ||
1696 | data.fn = fn; | |
1697 | data.priv = priv; | |
1698 | data.start = -1ul; | |
1699 | data.prot = 0; | |
1700 | ||
1701 | for (i = 0; i < V_L1_SIZE; i++) { | |
1702 | int rc = walk_memory_regions_1(&data, (abi_ulong)i << V_L1_SHIFT, | |
1703 | V_L1_SHIFT / L2_BITS - 1, l1_map + i); | |
1704 | ||
1705 | if (rc != 0) { | |
1706 | return rc; | |
1707 | } | |
1708 | } | |
1709 | ||
1710 | return walk_memory_regions_end(&data, 0, 0); | |
1711 | } | |
1712 | ||
1713 | static int dump_region(void *priv, abi_ulong start, | |
1714 | abi_ulong end, unsigned long prot) | |
1715 | { | |
1716 | FILE *f = (FILE *)priv; | |
1717 | ||
1718 | (void) fprintf(f, TARGET_ABI_FMT_lx"-"TARGET_ABI_FMT_lx | |
1719 | " "TARGET_ABI_FMT_lx" %c%c%c\n", | |
1720 | start, end, end - start, | |
1721 | ((prot & PAGE_READ) ? 'r' : '-'), | |
1722 | ((prot & PAGE_WRITE) ? 'w' : '-'), | |
1723 | ((prot & PAGE_EXEC) ? 'x' : '-')); | |
1724 | ||
1725 | return 0; | |
1726 | } | |
1727 | ||
1728 | /* dump memory mappings */ | |
1729 | void page_dump(FILE *f) | |
1730 | { | |
1731 | (void) fprintf(f, "%-8s %-8s %-8s %s\n", | |
1732 | "start", "end", "size", "prot"); | |
1733 | walk_memory_regions(f, dump_region); | |
1734 | } | |
1735 | ||
1736 | int page_get_flags(target_ulong address) | |
1737 | { | |
1738 | PageDesc *p; | |
1739 | ||
1740 | p = page_find(address >> TARGET_PAGE_BITS); | |
1741 | if (!p) { | |
1742 | return 0; | |
1743 | } | |
1744 | return p->flags; | |
1745 | } | |
1746 | ||
1747 | /* Modify the flags of a page and invalidate the code if necessary. | |
1748 | The flag PAGE_WRITE_ORG is positioned automatically depending | |
1749 | on PAGE_WRITE. The mmap_lock should already be held. */ | |
1750 | void page_set_flags(target_ulong start, target_ulong end, int flags) | |
1751 | { | |
1752 | target_ulong addr, len; | |
1753 | ||
1754 | /* This function should never be called with addresses outside the | |
1755 | guest address space. If this assert fires, it probably indicates | |
1756 | a missing call to h2g_valid. */ | |
1757 | #if TARGET_ABI_BITS > L1_MAP_ADDR_SPACE_BITS | |
1758 | assert(end < ((abi_ulong)1 << L1_MAP_ADDR_SPACE_BITS)); | |
1759 | #endif | |
1760 | assert(start < end); | |
1761 | ||
1762 | start = start & TARGET_PAGE_MASK; | |
1763 | end = TARGET_PAGE_ALIGN(end); | |
1764 | ||
1765 | if (flags & PAGE_WRITE) { | |
1766 | flags |= PAGE_WRITE_ORG; | |
1767 | } | |
1768 | ||
1769 | for (addr = start, len = end - start; | |
1770 | len != 0; | |
1771 | len -= TARGET_PAGE_SIZE, addr += TARGET_PAGE_SIZE) { | |
1772 | PageDesc *p = page_find_alloc(addr >> TARGET_PAGE_BITS, 1); | |
1773 | ||
1774 | /* If the write protection bit is set, then we invalidate | |
1775 | the code inside. */ | |
1776 | if (!(p->flags & PAGE_WRITE) && | |
1777 | (flags & PAGE_WRITE) && | |
1778 | p->first_tb) { | |
1779 | tb_invalidate_phys_page(addr, 0, NULL); | |
1780 | } | |
1781 | p->flags = flags; | |
1782 | } | |
1783 | } | |
1784 | ||
1785 | int page_check_range(target_ulong start, target_ulong len, int flags) | |
1786 | { | |
1787 | PageDesc *p; | |
1788 | target_ulong end; | |
1789 | target_ulong addr; | |
1790 | ||
1791 | /* This function should never be called with addresses outside the | |
1792 | guest address space. If this assert fires, it probably indicates | |
1793 | a missing call to h2g_valid. */ | |
1794 | #if TARGET_ABI_BITS > L1_MAP_ADDR_SPACE_BITS | |
1795 | assert(start < ((abi_ulong)1 << L1_MAP_ADDR_SPACE_BITS)); | |
1796 | #endif | |
1797 | ||
1798 | if (len == 0) { | |
1799 | return 0; | |
1800 | } | |
1801 | if (start + len - 1 < start) { | |
1802 | /* We've wrapped around. */ | |
1803 | return -1; | |
1804 | } | |
1805 | ||
1806 | /* must do before we loose bits in the next step */ | |
1807 | end = TARGET_PAGE_ALIGN(start + len); | |
1808 | start = start & TARGET_PAGE_MASK; | |
1809 | ||
1810 | for (addr = start, len = end - start; | |
1811 | len != 0; | |
1812 | len -= TARGET_PAGE_SIZE, addr += TARGET_PAGE_SIZE) { | |
1813 | p = page_find(addr >> TARGET_PAGE_BITS); | |
1814 | if (!p) { | |
1815 | return -1; | |
1816 | } | |
1817 | if (!(p->flags & PAGE_VALID)) { | |
1818 | return -1; | |
1819 | } | |
1820 | ||
1821 | if ((flags & PAGE_READ) && !(p->flags & PAGE_READ)) { | |
1822 | return -1; | |
1823 | } | |
1824 | if (flags & PAGE_WRITE) { | |
1825 | if (!(p->flags & PAGE_WRITE_ORG)) { | |
1826 | return -1; | |
1827 | } | |
1828 | /* unprotect the page if it was put read-only because it | |
1829 | contains translated code */ | |
1830 | if (!(p->flags & PAGE_WRITE)) { | |
1831 | if (!page_unprotect(addr, 0, NULL)) { | |
1832 | return -1; | |
1833 | } | |
1834 | } | |
1835 | return 0; | |
1836 | } | |
1837 | } | |
1838 | return 0; | |
1839 | } | |
1840 | ||
1841 | /* called from signal handler: invalidate the code and unprotect the | |
1842 | page. Return TRUE if the fault was successfully handled. */ | |
1843 | int page_unprotect(target_ulong address, uintptr_t pc, void *puc) | |
1844 | { | |
1845 | unsigned int prot; | |
1846 | PageDesc *p; | |
1847 | target_ulong host_start, host_end, addr; | |
1848 | ||
1849 | /* Technically this isn't safe inside a signal handler. However we | |
1850 | know this only ever happens in a synchronous SEGV handler, so in | |
1851 | practice it seems to be ok. */ | |
1852 | mmap_lock(); | |
1853 | ||
1854 | p = page_find(address >> TARGET_PAGE_BITS); | |
1855 | if (!p) { | |
1856 | mmap_unlock(); | |
1857 | return 0; | |
1858 | } | |
1859 | ||
1860 | /* if the page was really writable, then we change its | |
1861 | protection back to writable */ | |
1862 | if ((p->flags & PAGE_WRITE_ORG) && !(p->flags & PAGE_WRITE)) { | |
1863 | host_start = address & qemu_host_page_mask; | |
1864 | host_end = host_start + qemu_host_page_size; | |
1865 | ||
1866 | prot = 0; | |
1867 | for (addr = host_start ; addr < host_end ; addr += TARGET_PAGE_SIZE) { | |
1868 | p = page_find(addr >> TARGET_PAGE_BITS); | |
1869 | p->flags |= PAGE_WRITE; | |
1870 | prot |= p->flags; | |
1871 | ||
1872 | /* and since the content will be modified, we must invalidate | |
1873 | the corresponding translated code. */ | |
1874 | tb_invalidate_phys_page(addr, pc, puc); | |
1875 | #ifdef DEBUG_TB_CHECK | |
1876 | tb_invalidate_check(addr); | |
1877 | #endif | |
1878 | } | |
1879 | mprotect((void *)g2h(host_start), qemu_host_page_size, | |
1880 | prot & PAGE_BITS); | |
1881 | ||
1882 | mmap_unlock(); | |
1883 | return 1; | |
1884 | } | |
1885 | mmap_unlock(); | |
1886 | return 0; | |
1887 | } | |
1888 | #endif /* CONFIG_USER_ONLY */ |