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[qemu.git] / translate-i386.c
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7d13299d
FB		 1/*
2 * i386 translation
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
3ef693a0
FB		 6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
7d13299d 10 *
3ef693a0
FB		 11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
7d13299d 15 *
3ef693a0
FB		 16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
7d13299d 19 */
367e86e8
FB		 20#include <stdarg.h>
21#include <stdlib.h>
22#include <stdio.h>
23#include <string.h>
24#include <inttypes.h>
9de5e440 25#include <signal.h>
367e86e8 26#include <assert.h>
717fc2ad 27#include <sys/mman.h>
367e86e8 28
586314f2 29#include "cpu-i386.h"
d4e8164f 30#include "exec.h"
d19893da 31#include "disas.h"
586314f2 32
04369ff2 33/* XXX: move that elsewhere */
dc99065b
FB		 34static uint16_t *gen_opc_ptr;
35static uint32_t *gen_opparam_ptr;
0ecfa993 36
9c605cb1
FB		 37#define PREFIX_REPZ 0x01
38#define PREFIX_REPNZ 0x02
39#define PREFIX_LOCK 0x04
40#define PREFIX_DATA 0x08
41#define PREFIX_ADR 0x10
367e86e8
FB		 42
43typedef struct DisasContext {
44 /* current insn context */
9c605cb1 45 int override; /* -1 if no override */
367e86e8
FB		 46 int prefix;
47 int aflag, dflag;
dab2ed99 48 uint8_t *pc; /* pc = eip + cs_base */
6dbad63e
FB		 49 int is_jmp; /* 1 = means jump (stop translation), 2 means CPU
50 static state change (stop translation) */
51 /* current block context */
dab2ed99 52 uint8_t *cs_base; /* base of CS segment */
8f186479 53 int pe; /* protected mode */
6dbad63e 54 int code32; /* 32 bit code segment */
dab2ed99 55 int ss32; /* 32 bit stack segment */
6dbad63e
FB		 56 int cc_op; /* current CC operation */
57 int addseg; /* non zero if either DS/ES/SS have a non zero base */
58 int f_st; /* currently unused */
9c605cb1 59 int vm86; /* vm86 mode */
982b4315
FB		 60 int cpl;
61 int iopl;
c50c0c3f 62 int tf; /* TF cpu flag */
dbc5594c 63 int jmp_opt; /* use direct block chaining for direct jumps */
4021dab0 64 int mem_index; /* select memory access functions */
d19893da 65 struct TranslationBlock *tb;
717fc2ad 66 int popl_esp_hack; /* for correct popl with esp base handling */
367e86e8
FB		 67} DisasContext;
68
dbc5594c
FB		 69static void gen_eob(DisasContext *s);
70static void gen_jmp(DisasContext *s, unsigned int eip);
71
367e86e8
FB		 72/* i386 arith/logic operations */
73enum {
74 OP_ADDL,
75 OP_ORL,
76 OP_ADCL,
77 OP_SBBL,
78 OP_ANDL,
79 OP_SUBL,
80 OP_XORL,
81 OP_CMPL,
82};
83
84/* i386 shift ops */
85enum {
86 OP_ROL,
87 OP_ROR,
88 OP_RCL,
89 OP_RCR,
90 OP_SHL,
91 OP_SHR,
92 OP_SHL1, /* undocumented */
93 OP_SAR = 7,
94};
95
dc99065b 96enum {
5a91de8c 97#define DEF(s, n, copy_size) INDEX_op_ ## s,
dc99065b
FB		 98#include "opc-i386.h"
99#undef DEF
100 NB_OPS,
101};
102
d19893da 103#include "gen-op-i386.h"
367e86e8
FB		 104
105/* operand size */
106enum {
107 OT_BYTE = 0,
108 OT_WORD,
109 OT_LONG,
110 OT_QUAD,
111};
112
113enum {
114 /* I386 int registers */
115 OR_EAX, /* MUST be even numbered */
116 OR_ECX,
117 OR_EDX,
118 OR_EBX,
119 OR_ESP,
120 OR_EBP,
121 OR_ESI,
122 OR_EDI,
367e86e8
FB		 123 OR_TMP0, /* temporary operand register */
124 OR_TMP1,
125 OR_A0, /* temporary register used when doing address evaluation */
367e86e8 126 OR_ZERO, /* fixed zero register */
367e86e8
FB		 127 NB_OREGS,
128};
129
367e86e8
FB		 130typedef void (GenOpFunc)(void);
131typedef void (GenOpFunc1)(long);
132typedef void (GenOpFunc2)(long, long);
d4e8164f 133typedef void (GenOpFunc3)(long, long, long);
367e86e8
FB		 134
135static GenOpFunc *gen_op_mov_reg_T0[3][8] = {
136 [OT_BYTE] = {
137 gen_op_movb_EAX_T0,
138 gen_op_movb_ECX_T0,
139 gen_op_movb_EDX_T0,
140 gen_op_movb_EBX_T0,
141 gen_op_movh_EAX_T0,
142 gen_op_movh_ECX_T0,
143 gen_op_movh_EDX_T0,
144 gen_op_movh_EBX_T0,
145 },
146 [OT_WORD] = {
147 gen_op_movw_EAX_T0,
148 gen_op_movw_ECX_T0,
149 gen_op_movw_EDX_T0,
150 gen_op_movw_EBX_T0,
151 gen_op_movw_ESP_T0,
152 gen_op_movw_EBP_T0,
153 gen_op_movw_ESI_T0,
154 gen_op_movw_EDI_T0,
155 },
156 [OT_LONG] = {
157 gen_op_movl_EAX_T0,
158 gen_op_movl_ECX_T0,
159 gen_op_movl_EDX_T0,
160 gen_op_movl_EBX_T0,
161 gen_op_movl_ESP_T0,
162 gen_op_movl_EBP_T0,
163 gen_op_movl_ESI_T0,
164 gen_op_movl_EDI_T0,
165 },
166};
167
168static GenOpFunc *gen_op_mov_reg_T1[3][8] = {
169 [OT_BYTE] = {
170 gen_op_movb_EAX_T1,
171 gen_op_movb_ECX_T1,
172 gen_op_movb_EDX_T1,
173 gen_op_movb_EBX_T1,
174 gen_op_movh_EAX_T1,
175 gen_op_movh_ECX_T1,
176 gen_op_movh_EDX_T1,
177 gen_op_movh_EBX_T1,
178 },
179 [OT_WORD] = {
180 gen_op_movw_EAX_T1,
181 gen_op_movw_ECX_T1,
182 gen_op_movw_EDX_T1,
183 gen_op_movw_EBX_T1,
184 gen_op_movw_ESP_T1,
185 gen_op_movw_EBP_T1,
186 gen_op_movw_ESI_T1,
187 gen_op_movw_EDI_T1,
188 },
189 [OT_LONG] = {
190 gen_op_movl_EAX_T1,
191 gen_op_movl_ECX_T1,
192 gen_op_movl_EDX_T1,
193 gen_op_movl_EBX_T1,
194 gen_op_movl_ESP_T1,
195 gen_op_movl_EBP_T1,
196 gen_op_movl_ESI_T1,
197 gen_op_movl_EDI_T1,
198 },
199};
200
201static GenOpFunc *gen_op_mov_reg_A0[2][8] = {
202 [0] = {
203 gen_op_movw_EAX_A0,
204 gen_op_movw_ECX_A0,
205 gen_op_movw_EDX_A0,
206 gen_op_movw_EBX_A0,
207 gen_op_movw_ESP_A0,
208 gen_op_movw_EBP_A0,
209 gen_op_movw_ESI_A0,
210 gen_op_movw_EDI_A0,
211 },
212 [1] = {
213 gen_op_movl_EAX_A0,
214 gen_op_movl_ECX_A0,
215 gen_op_movl_EDX_A0,
216 gen_op_movl_EBX_A0,
217 gen_op_movl_ESP_A0,
218 gen_op_movl_EBP_A0,
219 gen_op_movl_ESI_A0,
220 gen_op_movl_EDI_A0,
221 },
222};
223
224static GenOpFunc *gen_op_mov_TN_reg[3][2][8] =
225{
226 [OT_BYTE] = {
227 {
228 gen_op_movl_T0_EAX,
229 gen_op_movl_T0_ECX,
230 gen_op_movl_T0_EDX,
231 gen_op_movl_T0_EBX,
232 gen_op_movh_T0_EAX,
233 gen_op_movh_T0_ECX,
234 gen_op_movh_T0_EDX,
235 gen_op_movh_T0_EBX,
236 },
237 {
238 gen_op_movl_T1_EAX,
239 gen_op_movl_T1_ECX,
240 gen_op_movl_T1_EDX,
241 gen_op_movl_T1_EBX,
242 gen_op_movh_T1_EAX,
243 gen_op_movh_T1_ECX,
244 gen_op_movh_T1_EDX,
245 gen_op_movh_T1_EBX,
246 },
247 },
248 [OT_WORD] = {
249 {
250 gen_op_movl_T0_EAX,
251 gen_op_movl_T0_ECX,
252 gen_op_movl_T0_EDX,
253 gen_op_movl_T0_EBX,
254 gen_op_movl_T0_ESP,
255 gen_op_movl_T0_EBP,
256 gen_op_movl_T0_ESI,
257 gen_op_movl_T0_EDI,
258 },
259 {
260 gen_op_movl_T1_EAX,
261 gen_op_movl_T1_ECX,
262 gen_op_movl_T1_EDX,
263 gen_op_movl_T1_EBX,
264 gen_op_movl_T1_ESP,
265 gen_op_movl_T1_EBP,
266 gen_op_movl_T1_ESI,
267 gen_op_movl_T1_EDI,
268 },
269 },
270 [OT_LONG] = {
271 {
272 gen_op_movl_T0_EAX,
273 gen_op_movl_T0_ECX,
274 gen_op_movl_T0_EDX,
275 gen_op_movl_T0_EBX,
276 gen_op_movl_T0_ESP,
277 gen_op_movl_T0_EBP,
278 gen_op_movl_T0_ESI,
279 gen_op_movl_T0_EDI,
280 },
281 {
282 gen_op_movl_T1_EAX,
283 gen_op_movl_T1_ECX,
284 gen_op_movl_T1_EDX,
285 gen_op_movl_T1_EBX,
286 gen_op_movl_T1_ESP,
287 gen_op_movl_T1_EBP,
288 gen_op_movl_T1_ESI,
289 gen_op_movl_T1_EDI,
290 },
291 },
292};
293
294static GenOpFunc *gen_op_movl_A0_reg[8] = {
295 gen_op_movl_A0_EAX,
296 gen_op_movl_A0_ECX,
297 gen_op_movl_A0_EDX,
298 gen_op_movl_A0_EBX,
299 gen_op_movl_A0_ESP,
300 gen_op_movl_A0_EBP,
301 gen_op_movl_A0_ESI,
302 gen_op_movl_A0_EDI,
303};
304
305static GenOpFunc *gen_op_addl_A0_reg_sN[4][8] = {
306 [0] = {
307 gen_op_addl_A0_EAX,
308 gen_op_addl_A0_ECX,
309 gen_op_addl_A0_EDX,
310 gen_op_addl_A0_EBX,
311 gen_op_addl_A0_ESP,
312 gen_op_addl_A0_EBP,
313 gen_op_addl_A0_ESI,
314 gen_op_addl_A0_EDI,
315 },
316 [1] = {
317 gen_op_addl_A0_EAX_s1,
318 gen_op_addl_A0_ECX_s1,
319 gen_op_addl_A0_EDX_s1,
320 gen_op_addl_A0_EBX_s1,
321 gen_op_addl_A0_ESP_s1,
322 gen_op_addl_A0_EBP_s1,
323 gen_op_addl_A0_ESI_s1,
324 gen_op_addl_A0_EDI_s1,
325 },
326 [2] = {
327 gen_op_addl_A0_EAX_s2,
328 gen_op_addl_A0_ECX_s2,
329 gen_op_addl_A0_EDX_s2,
330 gen_op_addl_A0_EBX_s2,
331 gen_op_addl_A0_ESP_s2,
332 gen_op_addl_A0_EBP_s2,
333 gen_op_addl_A0_ESI_s2,
334 gen_op_addl_A0_EDI_s2,
335 },
336 [3] = {
337 gen_op_addl_A0_EAX_s3,
338 gen_op_addl_A0_ECX_s3,
339 gen_op_addl_A0_EDX_s3,
340 gen_op_addl_A0_EBX_s3,
341 gen_op_addl_A0_ESP_s3,
342 gen_op_addl_A0_EBP_s3,
343 gen_op_addl_A0_ESI_s3,
344 gen_op_addl_A0_EDI_s3,
345 },
346};
347
5dd9488c
FB		 348static GenOpFunc *gen_op_cmov_reg_T1_T0[2][8] = {
349 [0] = {
350 gen_op_cmovw_EAX_T1_T0,
351 gen_op_cmovw_ECX_T1_T0,
352 gen_op_cmovw_EDX_T1_T0,
353 gen_op_cmovw_EBX_T1_T0,
354 gen_op_cmovw_ESP_T1_T0,
355 gen_op_cmovw_EBP_T1_T0,
356 gen_op_cmovw_ESI_T1_T0,
357 gen_op_cmovw_EDI_T1_T0,
358 },
359 [1] = {
360 gen_op_cmovl_EAX_T1_T0,
361 gen_op_cmovl_ECX_T1_T0,
362 gen_op_cmovl_EDX_T1_T0,
363 gen_op_cmovl_EBX_T1_T0,
364 gen_op_cmovl_ESP_T1_T0,
365 gen_op_cmovl_EBP_T1_T0,
366 gen_op_cmovl_ESI_T1_T0,
367 gen_op_cmovl_EDI_T1_T0,
368 },
369};
370
367e86e8 371static GenOpFunc *gen_op_arith_T0_T1_cc[8] = {
4b74fe1f 372 NULL,
5797fa5d
FB		 373 gen_op_orl_T0_T1,
374 NULL,
375 NULL,
376 gen_op_andl_T0_T1,
377 NULL,
378 gen_op_xorl_T0_T1,
4b74fe1f 379 NULL,
367e86e8
FB		 380};
381
4b74fe1f
FB		 382static GenOpFunc *gen_op_arithc_T0_T1_cc[3][2] = {
383 [OT_BYTE] = {
384 gen_op_adcb_T0_T1_cc,
385 gen_op_sbbb_T0_T1_cc,
386 },
387 [OT_WORD] = {
388 gen_op_adcw_T0_T1_cc,
389 gen_op_sbbw_T0_T1_cc,
390 },
391 [OT_LONG] = {
392 gen_op_adcl_T0_T1_cc,
393 gen_op_sbbl_T0_T1_cc,
394 },
395};
396
e477b8b8
FB		 397static GenOpFunc *gen_op_arithc_mem_T0_T1_cc[3][2] = {
398 [OT_BYTE] = {
399 gen_op_adcb_mem_T0_T1_cc,
400 gen_op_sbbb_mem_T0_T1_cc,
401 },
402 [OT_WORD] = {
403 gen_op_adcw_mem_T0_T1_cc,
404 gen_op_sbbw_mem_T0_T1_cc,
405 },
406 [OT_LONG] = {
407 gen_op_adcl_mem_T0_T1_cc,
408 gen_op_sbbl_mem_T0_T1_cc,
409 },
410};
411
367e86e8
FB		 412static const int cc_op_arithb[8] = {
413 CC_OP_ADDB,
414 CC_OP_LOGICB,
415 CC_OP_ADDB,
416 CC_OP_SUBB,
417 CC_OP_LOGICB,
418 CC_OP_SUBB,
419 CC_OP_LOGICB,
420 CC_OP_SUBB,
421};
422
1a9353d2
FB		 423static GenOpFunc *gen_op_cmpxchg_T0_T1_EAX_cc[3] = {
424 gen_op_cmpxchgb_T0_T1_EAX_cc,
425 gen_op_cmpxchgw_T0_T1_EAX_cc,
426 gen_op_cmpxchgl_T0_T1_EAX_cc,
427};
428
e477b8b8
FB		 429static GenOpFunc *gen_op_cmpxchg_mem_T0_T1_EAX_cc[3] = {
430 gen_op_cmpxchgb_mem_T0_T1_EAX_cc,
431 gen_op_cmpxchgw_mem_T0_T1_EAX_cc,
432 gen_op_cmpxchgl_mem_T0_T1_EAX_cc,
433};
434
367e86e8
FB		 435static GenOpFunc *gen_op_shift_T0_T1_cc[3][8] = {
436 [OT_BYTE] = {
437 gen_op_rolb_T0_T1_cc,
438 gen_op_rorb_T0_T1_cc,
439 gen_op_rclb_T0_T1_cc,
440 gen_op_rcrb_T0_T1_cc,
441 gen_op_shlb_T0_T1_cc,
442 gen_op_shrb_T0_T1_cc,
443 gen_op_shlb_T0_T1_cc,
444 gen_op_sarb_T0_T1_cc,
445 },
446 [OT_WORD] = {
447 gen_op_rolw_T0_T1_cc,
448 gen_op_rorw_T0_T1_cc,
449 gen_op_rclw_T0_T1_cc,
450 gen_op_rcrw_T0_T1_cc,
451 gen_op_shlw_T0_T1_cc,
452 gen_op_shrw_T0_T1_cc,
453 gen_op_shlw_T0_T1_cc,
454 gen_op_sarw_T0_T1_cc,
455 },
456 [OT_LONG] = {
457 gen_op_roll_T0_T1_cc,
458 gen_op_rorl_T0_T1_cc,
459 gen_op_rcll_T0_T1_cc,
460 gen_op_rcrl_T0_T1_cc,
461 gen_op_shll_T0_T1_cc,
462 gen_op_shrl_T0_T1_cc,
463 gen_op_shll_T0_T1_cc,
464 gen_op_sarl_T0_T1_cc,
465 },
466};
467
e477b8b8
FB		 468static GenOpFunc *gen_op_shift_mem_T0_T1_cc[3][8] = {
469 [OT_BYTE] = {
470 gen_op_rolb_mem_T0_T1_cc,
471 gen_op_rorb_mem_T0_T1_cc,
472 gen_op_rclb_mem_T0_T1_cc,
473 gen_op_rcrb_mem_T0_T1_cc,
474 gen_op_shlb_mem_T0_T1_cc,
475 gen_op_shrb_mem_T0_T1_cc,
476 gen_op_shlb_mem_T0_T1_cc,
477 gen_op_sarb_mem_T0_T1_cc,
478 },
479 [OT_WORD] = {
480 gen_op_rolw_mem_T0_T1_cc,
481 gen_op_rorw_mem_T0_T1_cc,
482 gen_op_rclw_mem_T0_T1_cc,
483 gen_op_rcrw_mem_T0_T1_cc,
484 gen_op_shlw_mem_T0_T1_cc,
485 gen_op_shrw_mem_T0_T1_cc,
486 gen_op_shlw_mem_T0_T1_cc,
487 gen_op_sarw_mem_T0_T1_cc,
488 },
489 [OT_LONG] = {
490 gen_op_roll_mem_T0_T1_cc,
491 gen_op_rorl_mem_T0_T1_cc,
492 gen_op_rcll_mem_T0_T1_cc,
493 gen_op_rcrl_mem_T0_T1_cc,
494 gen_op_shll_mem_T0_T1_cc,
495 gen_op_shrl_mem_T0_T1_cc,
496 gen_op_shll_mem_T0_T1_cc,
497 gen_op_sarl_mem_T0_T1_cc,
498 },
499};
500
d57c4e01
FB		 501static GenOpFunc1 *gen_op_shiftd_T0_T1_im_cc[2][2] = {
502 [0] = {
503 gen_op_shldw_T0_T1_im_cc,
504 gen_op_shrdw_T0_T1_im_cc,
505 },
506 [1] = {
507 gen_op_shldl_T0_T1_im_cc,
508 gen_op_shrdl_T0_T1_im_cc,
509 },
510};
511
512static GenOpFunc *gen_op_shiftd_T0_T1_ECX_cc[2][2] = {
513 [0] = {
514 gen_op_shldw_T0_T1_ECX_cc,
515 gen_op_shrdw_T0_T1_ECX_cc,
516 },
517 [1] = {
518 gen_op_shldl_T0_T1_ECX_cc,
519 gen_op_shrdl_T0_T1_ECX_cc,
520 },
521};
522
e477b8b8
FB		 523static GenOpFunc1 *gen_op_shiftd_mem_T0_T1_im_cc[2][2] = {
524 [0] = {
525 gen_op_shldw_mem_T0_T1_im_cc,
526 gen_op_shrdw_mem_T0_T1_im_cc,
527 },
528 [1] = {
529 gen_op_shldl_mem_T0_T1_im_cc,
530 gen_op_shrdl_mem_T0_T1_im_cc,
531 },
532};
533
534static GenOpFunc *gen_op_shiftd_mem_T0_T1_ECX_cc[2][2] = {
535 [0] = {
536 gen_op_shldw_mem_T0_T1_ECX_cc,
537 gen_op_shrdw_mem_T0_T1_ECX_cc,
538 },
539 [1] = {
540 gen_op_shldl_mem_T0_T1_ECX_cc,
541 gen_op_shrdl_mem_T0_T1_ECX_cc,
542 },
543};
544
4b74fe1f
FB		 545static GenOpFunc *gen_op_btx_T0_T1_cc[2][4] = {
546 [0] = {
547 gen_op_btw_T0_T1_cc,
548 gen_op_btsw_T0_T1_cc,
549 gen_op_btrw_T0_T1_cc,
550 gen_op_btcw_T0_T1_cc,
551 },
552 [1] = {
553 gen_op_btl_T0_T1_cc,
554 gen_op_btsl_T0_T1_cc,
555 gen_op_btrl_T0_T1_cc,
556 gen_op_btcl_T0_T1_cc,
557 },
558};
559
77f8dd5a
FB		 560static GenOpFunc *gen_op_bsx_T0_cc[2][2] = {
561 [0] = {
562 gen_op_bsfw_T0_cc,
563 gen_op_bsrw_T0_cc,
564 },
565 [1] = {
566 gen_op_bsfl_T0_cc,
567 gen_op_bsrl_T0_cc,
568 },
569};
570
4021dab0 571static GenOpFunc *gen_op_lds_T0_A0[3 * 3] = {
367e86e8
FB		 572 gen_op_ldsb_T0_A0,
573 gen_op_ldsw_T0_A0,
4021dab0
FB		 574 NULL,
575
576 gen_op_ldsb_kernel_T0_A0,
577 gen_op_ldsw_kernel_T0_A0,
578 NULL,
579
580 gen_op_ldsb_user_T0_A0,
581 gen_op_ldsw_user_T0_A0,
582 NULL,
367e86e8
FB		 583};
584
4021dab0 585static GenOpFunc *gen_op_ldu_T0_A0[3 * 3] = {
367e86e8
FB		 586 gen_op_ldub_T0_A0,
587 gen_op_lduw_T0_A0,
4021dab0
FB		 588 NULL,
589
590 gen_op_ldub_kernel_T0_A0,
591 gen_op_lduw_kernel_T0_A0,
592 NULL,
593
594 gen_op_ldub_user_T0_A0,
595 gen_op_lduw_user_T0_A0,
596 NULL,
367e86e8
FB		 597};
598
4021dab0
FB		 599/* sign does not matter, except for lidt/lgdt call (TODO: fix it) */
600static GenOpFunc *gen_op_ld_T0_A0[3 * 3] = {
367e86e8
FB		 601 gen_op_ldub_T0_A0,
602 gen_op_lduw_T0_A0,
603 gen_op_ldl_T0_A0,
4021dab0
FB		 604
605 gen_op_ldub_kernel_T0_A0,
606 gen_op_lduw_kernel_T0_A0,
607 gen_op_ldl_kernel_T0_A0,
608
609 gen_op_ldub_user_T0_A0,
610 gen_op_lduw_user_T0_A0,
611 gen_op_ldl_user_T0_A0,
367e86e8
FB		 612};
613
4021dab0 614static GenOpFunc *gen_op_ld_T1_A0[3 * 3] = {
367e86e8
FB		 615 gen_op_ldub_T1_A0,
616 gen_op_lduw_T1_A0,
617 gen_op_ldl_T1_A0,
4021dab0
FB		 618
619 gen_op_ldub_kernel_T1_A0,
620 gen_op_lduw_kernel_T1_A0,
621 gen_op_ldl_kernel_T1_A0,
622
623 gen_op_ldub_user_T1_A0,
624 gen_op_lduw_user_T1_A0,
625 gen_op_ldl_user_T1_A0,
367e86e8
FB		 626};
627
4021dab0 628static GenOpFunc *gen_op_st_T0_A0[3 * 3] = {
367e86e8
FB		 629 gen_op_stb_T0_A0,
630 gen_op_stw_T0_A0,
631 gen_op_stl_T0_A0,
4021dab0
FB		 632
633 gen_op_stb_kernel_T0_A0,
634 gen_op_stw_kernel_T0_A0,
635 gen_op_stl_kernel_T0_A0,
636
637 gen_op_stb_user_T0_A0,
638 gen_op_stw_user_T0_A0,
639 gen_op_stl_user_T0_A0,
367e86e8
FB		 640};
641
4021dab0
FB		 642static inline void gen_string_movl_A0_ESI(DisasContext *s)
643{
644 int override;
367e86e8 645
4021dab0
FB		 646 override = s->override;
647 if (s->aflag) {
648 /* 32 bit address */
649 if (s->addseg && override < 0)
650 override = R_DS;
651 if (override >= 0) {
652 gen_op_movl_A0_seg(offsetof(CPUX86State,segs[override].base));
653 gen_op_addl_A0_reg_sN[0][R_ESI]();
654 } else {
655 gen_op_movl_A0_reg[R_ESI]();
656 }
657 } else {
658 /* 16 address, always override */
659 if (override < 0)
660 override = R_DS;
661 gen_op_movl_A0_reg[R_ESI]();
662 gen_op_andl_A0_ffff();
663 gen_op_addl_A0_seg(offsetof(CPUX86State,segs[override].base));
664 }
665}
666
667static inline void gen_string_movl_A0_EDI(DisasContext *s)
668{
669 if (s->aflag) {
670 if (s->addseg) {
671 gen_op_movl_A0_seg(offsetof(CPUX86State,segs[R_ES].base));
672 gen_op_addl_A0_reg_sN[0][R_EDI]();
673 } else {
674 gen_op_movl_A0_reg[R_EDI]();
675 }
676 } else {
677 gen_op_movl_A0_reg[R_EDI]();
678 gen_op_andl_A0_ffff();
679 gen_op_addl_A0_seg(offsetof(CPUX86State,segs[R_ES].base));
680 }
681}
682
683static GenOpFunc *gen_op_movl_T0_Dshift[3] = {
684 gen_op_movl_T0_Dshiftb,
685 gen_op_movl_T0_Dshiftw,
686 gen_op_movl_T0_Dshiftl,
367e86e8
FB		 687};
688
4021dab0
FB		 689static GenOpFunc2 *gen_op_jz_ecx[2] = {
690 gen_op_jz_ecxw,
691 gen_op_jz_ecxl,
692};
693
dbc5594c
FB		 694static GenOpFunc1 *gen_op_jz_ecx_im[2] = {
695 gen_op_jz_ecxw_im,
696 gen_op_jz_ecxl_im,
697};
698
4021dab0
FB		 699static GenOpFunc *gen_op_dec_ECX[2] = {
700 gen_op_decw_ECX,
701 gen_op_decl_ECX,
367e86e8
FB		 702};
703
dbc5594c 704static GenOpFunc1 *gen_op_string_jnz_sub[2][3] = {
4021dab0
FB		 705 {
706 gen_op_string_jnz_subb,
707 gen_op_string_jnz_subw,
708 gen_op_string_jnz_subl,
709 },
710 {
711 gen_op_string_jz_subb,
712 gen_op_string_jz_subw,
713 gen_op_string_jz_subl,
714 },
367e86e8
FB		 715};
716
dbc5594c
FB		 717static GenOpFunc1 *gen_op_string_jnz_sub_im[2][3] = {
718 {
719 gen_op_string_jnz_subb_im,
720 gen_op_string_jnz_subw_im,
721 gen_op_string_jnz_subl_im,
722 },
723 {
724 gen_op_string_jz_subb_im,
725 gen_op_string_jz_subw_im,
726 gen_op_string_jz_subl_im,
727 },
728};
729
4021dab0
FB		 730static GenOpFunc *gen_op_in_DX_T0[3] = {
731 gen_op_inb_DX_T0,
732 gen_op_inw_DX_T0,
733 gen_op_inl_DX_T0,
734};
367e86e8 735
4021dab0
FB		 736static GenOpFunc *gen_op_out_DX_T0[3] = {
737 gen_op_outb_DX_T0,
738 gen_op_outw_DX_T0,
739 gen_op_outl_DX_T0,
367e86e8
FB		 740};
741
4021dab0
FB		 742static inline void gen_movs(DisasContext *s, int ot)
743{
744 gen_string_movl_A0_ESI(s);
745 gen_op_ld_T0_A0[ot + s->mem_index]();
746 gen_string_movl_A0_EDI(s);
747 gen_op_st_T0_A0[ot + s->mem_index]();
748 gen_op_movl_T0_Dshift[ot]();
749 if (s->aflag) {
750 gen_op_addl_ESI_T0();
751 gen_op_addl_EDI_T0();
752 } else {
753 gen_op_addw_ESI_T0();
754 gen_op_addw_EDI_T0();
755 }
756}
757
dbc5594c 758static inline void gen_update_cc_op(DisasContext *s)
4021dab0 759{
dbc5594c 760 if (s->cc_op != CC_OP_DYNAMIC) {
4021dab0 761 gen_op_set_cc_op(s->cc_op);
dbc5594c
FB		 762 s->cc_op = CC_OP_DYNAMIC;
763 }
764}
765
766static inline void gen_jz_ecx_string(DisasContext *s, unsigned int next_eip)
767{
768 if (s->jmp_opt) {
769 gen_op_jz_ecx[s->aflag]((long)s->tb, next_eip);
770 } else {
771 /* XXX: does not work with gdbstub "ice" single step - not a
772 serious problem */
773 gen_op_jz_ecx_im[s->aflag](next_eip);
774 }
4021dab0
FB		 775}
776
777static inline void gen_stos(DisasContext *s, int ot)
778{
779 gen_op_mov_TN_reg[OT_LONG][0][R_EAX]();
780 gen_string_movl_A0_EDI(s);
781 gen_op_st_T0_A0[ot + s->mem_index]();
782 gen_op_movl_T0_Dshift[ot]();
783 if (s->aflag) {
784 gen_op_addl_EDI_T0();
785 } else {
786 gen_op_addw_EDI_T0();
787 }
788}
789
4021dab0
FB		 790static inline void gen_lods(DisasContext *s, int ot)
791{
792 gen_string_movl_A0_ESI(s);
793 gen_op_ld_T0_A0[ot + s->mem_index]();
794 gen_op_mov_reg_T0[ot][R_EAX]();
795 gen_op_movl_T0_Dshift[ot]();
796 if (s->aflag) {
797 gen_op_addl_ESI_T0();
798 } else {
799 gen_op_addw_ESI_T0();
800 }
801}
802
4021dab0
FB		 803static inline void gen_scas(DisasContext *s, int ot)
804{
805 gen_op_mov_TN_reg[OT_LONG][0][R_EAX]();
806 gen_string_movl_A0_EDI(s);
807 gen_op_ld_T1_A0[ot + s->mem_index]();
808 gen_op_cmpl_T0_T1_cc();
809 gen_op_movl_T0_Dshift[ot]();
810 if (s->aflag) {
811 gen_op_addl_EDI_T0();
812 } else {
813 gen_op_addw_EDI_T0();
814 }
815}
816
4021dab0
FB		 817static inline void gen_cmps(DisasContext *s, int ot)
818{
819 gen_string_movl_A0_ESI(s);
820 gen_op_ld_T0_A0[ot + s->mem_index]();
821 gen_string_movl_A0_EDI(s);
822 gen_op_ld_T1_A0[ot + s->mem_index]();
823 gen_op_cmpl_T0_T1_cc();
824 gen_op_movl_T0_Dshift[ot]();
825 if (s->aflag) {
826 gen_op_addl_ESI_T0();
827 gen_op_addl_EDI_T0();
828 } else {
829 gen_op_addw_ESI_T0();
830 gen_op_addw_EDI_T0();
831 }
832}
833
834static inline void gen_ins(DisasContext *s, int ot)
835{
836 gen_op_in_DX_T0[ot]();
837 gen_string_movl_A0_EDI(s);
838 gen_op_st_T0_A0[ot + s->mem_index]();
839 gen_op_movl_T0_Dshift[ot]();
840 if (s->aflag) {
841 gen_op_addl_EDI_T0();
842 } else {
843 gen_op_addw_EDI_T0();
844 }
845}
846
4021dab0
FB		 847static inline void gen_outs(DisasContext *s, int ot)
848{
849 gen_string_movl_A0_ESI(s);
850 gen_op_ld_T0_A0[ot + s->mem_index]();
851 gen_op_out_DX_T0[ot]();
852 gen_op_movl_T0_Dshift[ot]();
853 if (s->aflag) {
854 gen_op_addl_ESI_T0();
855 } else {
856 gen_op_addw_ESI_T0();
857 }
858}
859
dbc5594c
FB		 860/* same method as Valgrind : we generate jumps to current or next
861 instruction */
862#define GEN_REPZ(op) \
863static inline void gen_repz_ ## op(DisasContext *s, int ot, \
864 unsigned int cur_eip, unsigned int next_eip) \
865{ \
866 gen_update_cc_op(s); \
867 gen_jz_ecx_string(s, next_eip); \
868 gen_ ## op(s, ot); \
869 gen_op_dec_ECX[s->aflag](); \
870 /* a loop would cause two single step exceptions if ECX = 1 \
871 before rep string_insn */ \
872 if (!s->jmp_opt) \
873 gen_op_jz_ecx_im[s->aflag](next_eip); \
874 gen_jmp(s, cur_eip); \
4021dab0 875}
9c605cb1 876
dbc5594c
FB		 877#define GEN_REPZ2(op) \
878static inline void gen_repz_ ## op(DisasContext *s, int ot, \
879 unsigned int cur_eip, \
880 unsigned int next_eip, \
881 int nz) \
882{ \
883 gen_update_cc_op(s); \
884 gen_jz_ecx_string(s, next_eip); \
885 gen_ ## op(s, ot); \
886 gen_op_dec_ECX[s->aflag](); \
887 gen_op_set_cc_op(CC_OP_SUBB + ot); \
888 if (!s->jmp_opt) \
889 gen_op_string_jnz_sub_im[nz][ot](next_eip); \
890 else \
891 gen_op_string_jnz_sub[nz][ot]((long)s->tb); \
892 if (!s->jmp_opt) \
893 gen_op_jz_ecx_im[s->aflag](next_eip); \
894 gen_jmp(s, cur_eip); \
9c605cb1
FB		 895}
896
dbc5594c
FB		 897GEN_REPZ(movs)
898GEN_REPZ(stos)
899GEN_REPZ(lods)
900GEN_REPZ(ins)
901GEN_REPZ(outs)
902GEN_REPZ2(scas)
903GEN_REPZ2(cmps)
9c605cb1 904
ba1c6e37
FB		 905static GenOpFunc *gen_op_in[3] = {
906 gen_op_inb_T0_T1,
907 gen_op_inw_T0_T1,
908 gen_op_inl_T0_T1,
909};
910
911static GenOpFunc *gen_op_out[3] = {
912 gen_op_outb_T0_T1,
913 gen_op_outw_T0_T1,
914 gen_op_outl_T0_T1,
915};
916
367e86e8
FB		 917enum {
918 JCC_O,
919 JCC_B,
920 JCC_Z,
921 JCC_BE,
922 JCC_S,
923 JCC_P,
924 JCC_L,
925 JCC_LE,
926};
927
d4e8164f 928static GenOpFunc3 *gen_jcc_sub[3][8] = {
367e86e8
FB		 929 [OT_BYTE] = {
930 NULL,
931 gen_op_jb_subb,
932 gen_op_jz_subb,
933 gen_op_jbe_subb,
934 gen_op_js_subb,
935 NULL,
936 gen_op_jl_subb,
937 gen_op_jle_subb,
938 },
939 [OT_WORD] = {
940 NULL,
941 gen_op_jb_subw,
942 gen_op_jz_subw,
943 gen_op_jbe_subw,
944 gen_op_js_subw,
945 NULL,
946 gen_op_jl_subw,
947 gen_op_jle_subw,
948 },
949 [OT_LONG] = {
950 NULL,
951 gen_op_jb_subl,
952 gen_op_jz_subl,
953 gen_op_jbe_subl,
954 gen_op_js_subl,
955 NULL,
956 gen_op_jl_subl,
957 gen_op_jle_subl,
958 },
959};
1a9353d2
FB		 960static GenOpFunc2 *gen_op_loop[2][4] = {
961 [0] = {
962 gen_op_loopnzw,
963 gen_op_loopzw,
964 gen_op_loopw,
965 gen_op_jecxzw,
966 },
967 [1] = {
968 gen_op_loopnzl,
969 gen_op_loopzl,
970 gen_op_loopl,
971 gen_op_jecxzl,
972 },
973};
367e86e8
FB		 974
975static GenOpFunc *gen_setcc_slow[8] = {
976 gen_op_seto_T0_cc,
977 gen_op_setb_T0_cc,
978 gen_op_setz_T0_cc,
979 gen_op_setbe_T0_cc,
980 gen_op_sets_T0_cc,
981 gen_op_setp_T0_cc,
982 gen_op_setl_T0_cc,
983 gen_op_setle_T0_cc,
984};
985
986static GenOpFunc *gen_setcc_sub[3][8] = {
987 [OT_BYTE] = {
988 NULL,
989 gen_op_setb_T0_subb,
990 gen_op_setz_T0_subb,
991 gen_op_setbe_T0_subb,
992 gen_op_sets_T0_subb,
993 NULL,
994 gen_op_setl_T0_subb,
995 gen_op_setle_T0_subb,
996 },
997 [OT_WORD] = {
998 NULL,
999 gen_op_setb_T0_subw,
1000 gen_op_setz_T0_subw,
1001 gen_op_setbe_T0_subw,
1002 gen_op_sets_T0_subw,
1003 NULL,
1004 gen_op_setl_T0_subw,
1005 gen_op_setle_T0_subw,
1006 },
1007 [OT_LONG] = {
1008 NULL,
1009 gen_op_setb_T0_subl,
1010 gen_op_setz_T0_subl,
1011 gen_op_setbe_T0_subl,
1012 gen_op_sets_T0_subl,
1013 NULL,
1014 gen_op_setl_T0_subl,
1015 gen_op_setle_T0_subl,
1016 },
1017};
1018
927f621e
FB		 1019static GenOpFunc *gen_op_fp_arith_ST0_FT0[8] = {
1020 gen_op_fadd_ST0_FT0,
1021 gen_op_fmul_ST0_FT0,
1022 gen_op_fcom_ST0_FT0,
1023 gen_op_fcom_ST0_FT0,
1024 gen_op_fsub_ST0_FT0,
1025 gen_op_fsubr_ST0_FT0,
1026 gen_op_fdiv_ST0_FT0,
1027 gen_op_fdivr_ST0_FT0,
1028};
1029
77f8dd5a 1030/* NOTE the exception in "r" op ordering */
927f621e
FB		 1031static GenOpFunc1 *gen_op_fp_arith_STN_ST0[8] = {
1032 gen_op_fadd_STN_ST0,
1033 gen_op_fmul_STN_ST0,
1034 NULL,
1035 NULL,
927f621e 1036 gen_op_fsubr_STN_ST0,
77f8dd5a 1037 gen_op_fsub_STN_ST0,
927f621e 1038 gen_op_fdivr_STN_ST0,
77f8dd5a 1039 gen_op_fdiv_STN_ST0,
927f621e
FB		 1040};
1041
5797fa5d
FB		 1042/* if d == OR_TMP0, it means memory operand (address in A0) */
1043static void gen_op(DisasContext *s1, int op, int ot, int d)
367e86e8 1044{
5797fa5d
FB		 1045 GenOpFunc *gen_update_cc;
1046
1047 if (d != OR_TMP0) {
367e86e8 1048 gen_op_mov_TN_reg[ot][0][d]();
5797fa5d 1049 } else {
4021dab0 1050 gen_op_ld_T0_A0[ot + s1->mem_index]();
5797fa5d
FB		 1051 }
1052 switch(op) {
1053 case OP_ADCL:
1054 case OP_SBBL:
4b74fe1f
FB		 1055 if (s1->cc_op != CC_OP_DYNAMIC)
1056 gen_op_set_cc_op(s1->cc_op);
e477b8b8
FB		 1057 if (d != OR_TMP0) {
1058 gen_op_arithc_T0_T1_cc[ot][op - OP_ADCL]();
1059 gen_op_mov_reg_T0[ot][d]();
1060 } else {
1061 gen_op_arithc_mem_T0_T1_cc[ot][op - OP_ADCL]();
1062 }
4b74fe1f 1063 s1->cc_op = CC_OP_DYNAMIC;
e477b8b8 1064 goto the_end;
5797fa5d
FB		 1065 case OP_ADDL:
1066 gen_op_addl_T0_T1();
1067 s1->cc_op = CC_OP_ADDB + ot;
1068 gen_update_cc = gen_op_update2_cc;
1069 break;
1070 case OP_SUBL:
1071 gen_op_subl_T0_T1();
1072 s1->cc_op = CC_OP_SUBB + ot;
1073 gen_update_cc = gen_op_update2_cc;
1074 break;
1075 default:
1076 case OP_ANDL:
1077 case OP_ORL:
1078 case OP_XORL:
4b74fe1f 1079 gen_op_arith_T0_T1_cc[op]();
5797fa5d
FB		 1080 s1->cc_op = CC_OP_LOGICB + ot;
1081 gen_update_cc = gen_op_update1_cc;
1082 break;
1083 case OP_CMPL:
1084 gen_op_cmpl_T0_T1_cc();
1085 s1->cc_op = CC_OP_SUBB + ot;
1086 gen_update_cc = NULL;
1087 break;
4b74fe1f 1088 }
5797fa5d
FB		 1089 if (op != OP_CMPL) {
1090 if (d != OR_TMP0)
1091 gen_op_mov_reg_T0[ot][d]();
1092 else
4021dab0 1093 gen_op_st_T0_A0[ot + s1->mem_index]();
5797fa5d
FB		 1094 }
1095 /* the flags update must happen after the memory write (precise
1096 exception support) */
1097 if (gen_update_cc)
1098 gen_update_cc();
e477b8b8 1099 the_end: ;
367e86e8
FB		 1100}
1101
5797fa5d 1102/* if d == OR_TMP0, it means memory operand (address in A0) */
367e86e8
FB		 1103static void gen_inc(DisasContext *s1, int ot, int d, int c)
1104{
1105 if (d != OR_TMP0)
1106 gen_op_mov_TN_reg[ot][0][d]();
5797fa5d 1107 else
4021dab0 1108 gen_op_ld_T0_A0[ot + s1->mem_index]();
367e86e8
FB		 1109 if (s1->cc_op != CC_OP_DYNAMIC)
1110 gen_op_set_cc_op(s1->cc_op);
4b74fe1f 1111 if (c > 0) {
5797fa5d 1112 gen_op_incl_T0();
4b74fe1f
FB		 1113 s1->cc_op = CC_OP_INCB + ot;
1114 } else {
5797fa5d 1115 gen_op_decl_T0();
4b74fe1f
FB		 1116 s1->cc_op = CC_OP_DECB + ot;
1117 }
367e86e8
FB		 1118 if (d != OR_TMP0)
1119 gen_op_mov_reg_T0[ot][d]();
5797fa5d 1120 else
4021dab0 1121 gen_op_st_T0_A0[ot + s1->mem_index]();
5797fa5d 1122 gen_op_update_inc_cc();
367e86e8
FB		 1123}
1124
1125static void gen_shift(DisasContext *s1, int op, int ot, int d, int s)
1126{
1127 if (d != OR_TMP0)
1128 gen_op_mov_TN_reg[ot][0][d]();
e477b8b8 1129 else
4021dab0 1130 gen_op_ld_T0_A0[ot + s1->mem_index]();
367e86e8
FB		 1131 if (s != OR_TMP1)
1132 gen_op_mov_TN_reg[ot][1][s]();
4b74fe1f
FB		 1133 /* for zero counts, flags are not updated, so must do it dynamically */
1134 if (s1->cc_op != CC_OP_DYNAMIC)
1135 gen_op_set_cc_op(s1->cc_op);
e477b8b8
FB		 1136
1137 if (d != OR_TMP0)
1138 gen_op_shift_T0_T1_cc[ot][op]();
1139 else
1140 gen_op_shift_mem_T0_T1_cc[ot][op]();
367e86e8
FB		 1141 if (d != OR_TMP0)
1142 gen_op_mov_reg_T0[ot][d]();
1143 s1->cc_op = CC_OP_DYNAMIC; /* cannot predict flags after */
1144}
1145
1146static void gen_shifti(DisasContext *s1, int op, int ot, int d, int c)
1147{
1148 /* currently not optimized */
ba1c6e37 1149 gen_op_movl_T1_im(c);
367e86e8
FB		 1150 gen_shift(s1, op, ot, d, OR_TMP1);
1151}
1152
1153static void gen_lea_modrm(DisasContext *s, int modrm, int *reg_ptr, int *offset_ptr)
1154{
1155 int havesib;
367e86e8 1156 int base, disp;
6dbad63e
FB		 1157 int index;
1158 int scale;
1159 int opreg;
1160 int mod, rm, code, override, must_add_seg;
1161
9c605cb1 1162 override = s->override;
6dbad63e 1163 must_add_seg = s->addseg;
9c605cb1 1164 if (override >= 0)
6dbad63e 1165 must_add_seg = 1;
367e86e8
FB		 1166 mod = (modrm >> 6) & 3;
1167 rm = modrm & 7;
1168
1169 if (s->aflag) {
1170
1171 havesib = 0;
367e86e8 1172 base = rm;
6dbad63e
FB		 1173 index = 0;
1174 scale = 0;
367e86e8
FB		 1175
1176 if (base == 4) {
1177 havesib = 1;
1178 code = ldub(s->pc++);
1179 scale = (code >> 6) & 3;
1180 index = (code >> 3) & 7;
1181 base = code & 7;
1182 }
1183
1184 switch (mod) {
1185 case 0:
1186 if (base == 5) {
6dbad63e 1187 base = -1;
367e86e8
FB		 1188 disp = ldl(s->pc);
1189 s->pc += 4;
1190 } else {
1191 disp = 0;
1192 }
1193 break;
1194 case 1:
1195 disp = (int8_t)ldub(s->pc++);
1196 break;
1197 default:
1198 case 2:
1199 disp = ldl(s->pc);
1200 s->pc += 4;
1201 break;
1202 }
6dbad63e
FB		 1203
1204 if (base >= 0) {
717fc2ad
FB		 1205 /* for correct popl handling with esp */
1206 if (base == 4 && s->popl_esp_hack)
8f186479 1207 disp += s->popl_esp_hack;
6dbad63e
FB		 1208 gen_op_movl_A0_reg[base]();
1209 if (disp != 0)
1210 gen_op_addl_A0_im(disp);
367e86e8 1211 } else {
6dbad63e
FB		 1212 gen_op_movl_A0_im(disp);
1213 }
717fc2ad 1214 /* XXX: index == 4 is always invalid */
6dbad63e
FB		 1215 if (havesib && (index != 4 || scale != 0)) {
1216 gen_op_addl_A0_reg_sN[scale][index]();
1217 }
1218 if (must_add_seg) {
1219 if (override < 0) {
1220 if (base == R_EBP || base == R_ESP)
1221 override = R_SS;
1222 else
1223 override = R_DS;
367e86e8 1224 }
d8bc1fd0 1225 gen_op_addl_A0_seg(offsetof(CPUX86State,segs[override].base));
367e86e8 1226 }
367e86e8 1227 } else {
4b74fe1f
FB		 1228 switch (mod) {
1229 case 0:
1230 if (rm == 6) {
1231 disp = lduw(s->pc);
1232 s->pc += 2;
1233 gen_op_movl_A0_im(disp);
6dbad63e 1234 rm = 0; /* avoid SS override */
4b74fe1f
FB		 1235 goto no_rm;
1236 } else {
1237 disp = 0;
1238 }
1239 break;
1240 case 1:
1241 disp = (int8_t)ldub(s->pc++);
1242 break;
1243 default:
1244 case 2:
1245 disp = lduw(s->pc);
1246 s->pc += 2;
1247 break;
1248 }
1249 switch(rm) {
1250 case 0:
1251 gen_op_movl_A0_reg[R_EBX]();
1252 gen_op_addl_A0_reg_sN[0][R_ESI]();
1253 break;
1254 case 1:
1255 gen_op_movl_A0_reg[R_EBX]();
1256 gen_op_addl_A0_reg_sN[0][R_EDI]();
1257 break;
1258 case 2:
1259 gen_op_movl_A0_reg[R_EBP]();
1260 gen_op_addl_A0_reg_sN[0][R_ESI]();
1261 break;
1262 case 3:
1263 gen_op_movl_A0_reg[R_EBP]();
1264 gen_op_addl_A0_reg_sN[0][R_EDI]();
1265 break;
1266 case 4:
1267 gen_op_movl_A0_reg[R_ESI]();
1268 break;
1269 case 5:
1270 gen_op_movl_A0_reg[R_EDI]();
1271 break;
1272 case 6:
1273 gen_op_movl_A0_reg[R_EBP]();
1274 break;
1275 default:
1276 case 7:
1277 gen_op_movl_A0_reg[R_EBX]();
1278 break;
1279 }
1280 if (disp != 0)
1281 gen_op_addl_A0_im(disp);
1282 gen_op_andl_A0_ffff();
6dbad63e
FB		 1283 no_rm:
1284 if (must_add_seg) {
1285 if (override < 0) {
1286 if (rm == 2 || rm == 3 || rm == 6)
1287 override = R_SS;
1288 else
1289 override = R_DS;
1290 }
d8bc1fd0 1291 gen_op_addl_A0_seg(offsetof(CPUX86State,segs[override].base));
6dbad63e 1292 }
367e86e8 1293 }
6dbad63e 1294
4b74fe1f
FB		 1295 opreg = OR_A0;
1296 disp = 0;
367e86e8
FB		 1297 *reg_ptr = opreg;
1298 *offset_ptr = disp;
1299}
1300
1301/* generate modrm memory load or store of 'reg'. TMP0 is used if reg !=
1302 OR_TMP0 */
1303static void gen_ldst_modrm(DisasContext *s, int modrm, int ot, int reg, int is_store)
1304{
1305 int mod, rm, opreg, disp;
1306
1307 mod = (modrm >> 6) & 3;
1308 rm = modrm & 7;
1309 if (mod == 3) {
1310 if (is_store) {
1311 if (reg != OR_TMP0)
1312 gen_op_mov_TN_reg[ot][0][reg]();
1313 gen_op_mov_reg_T0[ot][rm]();
1314 } else {
1315 gen_op_mov_TN_reg[ot][0][rm]();
1316 if (reg != OR_TMP0)
1317 gen_op_mov_reg_T0[ot][reg]();
1318 }
1319 } else {
1320 gen_lea_modrm(s, modrm, &opreg, &disp);
1321 if (is_store) {
1322 if (reg != OR_TMP0)
1323 gen_op_mov_TN_reg[ot][0][reg]();
4021dab0 1324 gen_op_st_T0_A0[ot + s->mem_index]();
367e86e8 1325 } else {
4021dab0 1326 gen_op_ld_T0_A0[ot + s->mem_index]();
367e86e8
FB		 1327 if (reg != OR_TMP0)
1328 gen_op_mov_reg_T0[ot][reg]();
1329 }
1330 }
1331}
1332
1333static inline uint32_t insn_get(DisasContext *s, int ot)
1334{
1335 uint32_t ret;
1336
1337 switch(ot) {
1338 case OT_BYTE:
1339 ret = ldub(s->pc);
1340 s->pc++;
1341 break;
1342 case OT_WORD:
1343 ret = lduw(s->pc);
1344 s->pc += 2;
1345 break;
1346 default:
1347 case OT_LONG:
1348 ret = ldl(s->pc);
1349 s->pc += 4;
1350 break;
1351 }
1352 return ret;
1353}
1354
dab2ed99 1355static inline void gen_jcc(DisasContext *s, int b, int val, int next_eip)
367e86e8 1356{
d4e8164f 1357 TranslationBlock *tb;
367e86e8 1358 int inv, jcc_op;
d4e8164f 1359 GenOpFunc3 *func;
367e86e8
FB		 1360
1361 inv = b & 1;
1362 jcc_op = (b >> 1) & 7;
dbc5594c
FB		 1363
1364 if (s->jmp_opt) {
1365 switch(s->cc_op) {
1366 /* we optimize the cmp/jcc case */
1367 case CC_OP_SUBB:
1368 case CC_OP_SUBW:
1369 case CC_OP_SUBL:
1370 func = gen_jcc_sub[s->cc_op - CC_OP_SUBB][jcc_op];
367e86e8 1371 break;
dbc5594c
FB		 1372
1373 /* some jumps are easy to compute */
1374 case CC_OP_ADDB:
1375 case CC_OP_ADDW:
1376 case CC_OP_ADDL:
1377 case CC_OP_ADCB:
1378 case CC_OP_ADCW:
1379 case CC_OP_ADCL:
1380 case CC_OP_SBBB:
1381 case CC_OP_SBBW:
1382 case CC_OP_SBBL:
1383 case CC_OP_LOGICB:
1384 case CC_OP_LOGICW:
1385 case CC_OP_LOGICL:
1386 case CC_OP_INCB:
1387 case CC_OP_INCW:
1388 case CC_OP_INCL:
1389 case CC_OP_DECB:
1390 case CC_OP_DECW:
1391 case CC_OP_DECL:
1392 case CC_OP_SHLB:
1393 case CC_OP_SHLW:
1394 case CC_OP_SHLL:
1395 case CC_OP_SARB:
1396 case CC_OP_SARW:
1397 case CC_OP_SARL:
1398 switch(jcc_op) {
1399 case JCC_Z:
1400 func = gen_jcc_sub[(s->cc_op - CC_OP_ADDB) % 3][jcc_op];
1401 break;
1402 case JCC_S:
1403 func = gen_jcc_sub[(s->cc_op - CC_OP_ADDB) % 3][jcc_op];
1404 break;
1405 default:
1406 func = NULL;
1407 break;
1408 }
367e86e8
FB		 1409 break;
1410 default:
d4e8164f
FB		 1411 func = NULL;
1412 break;
367e86e8 1413 }
d4e8164f 1414
dbc5594c
FB		 1415 if (s->cc_op != CC_OP_DYNAMIC)
1416 gen_op_set_cc_op(s->cc_op);
d4e8164f 1417
dbc5594c
FB		 1418 if (!func) {
1419 gen_setcc_slow[jcc_op]();
1420 func = gen_op_jcc;
1421 }
d4e8164f 1422
dbc5594c
FB		 1423 tb = s->tb;
1424 if (!inv) {
1425 func((long)tb, val, next_eip);
1426 } else {
1427 func((long)tb, next_eip, val);
1428 }
1429 s->is_jmp = 3;
367e86e8 1430 } else {
dbc5594c
FB		 1431 if (s->cc_op != CC_OP_DYNAMIC) {
1432 gen_op_set_cc_op(s->cc_op);
1433 s->cc_op = CC_OP_DYNAMIC;
1434 }
1435 gen_setcc_slow[jcc_op]();
1436 if (!inv) {
1437 gen_op_jcc_im(val, next_eip);
1438 } else {
1439 gen_op_jcc_im(next_eip, val);
1440 }
1441 gen_eob(s);
367e86e8
FB		 1442 }
1443}
1444
1445static void gen_setcc(DisasContext *s, int b)
1446{
1447 int inv, jcc_op;
1448 GenOpFunc *func;
1449
1450 inv = b & 1;
1451 jcc_op = (b >> 1) & 7;
1452 switch(s->cc_op) {
1453 /* we optimize the cmp/jcc case */
1454 case CC_OP_SUBB:
1455 case CC_OP_SUBW:
1456 case CC_OP_SUBL:
1457 func = gen_setcc_sub[s->cc_op - CC_OP_SUBB][jcc_op];
1458 if (!func)
1459 goto slow_jcc;
1460 break;
1461
1462 /* some jumps are easy to compute */
1463 case CC_OP_ADDB:
1464 case CC_OP_ADDW:
1465 case CC_OP_ADDL:
1466 case CC_OP_LOGICB:
1467 case CC_OP_LOGICW:
1468 case CC_OP_LOGICL:
1469 case CC_OP_INCB:
1470 case CC_OP_INCW:
1471 case CC_OP_INCL:
1472 case CC_OP_DECB:
1473 case CC_OP_DECW:
1474 case CC_OP_DECL:
1475 case CC_OP_SHLB:
1476 case CC_OP_SHLW:
1477 case CC_OP_SHLL:
1478 switch(jcc_op) {
1479 case JCC_Z:
1017ebe9 1480 func = gen_setcc_sub[(s->cc_op - CC_OP_ADDB) % 3][jcc_op];
367e86e8
FB		 1481 break;
1482 case JCC_S:
1017ebe9 1483 func = gen_setcc_sub[(s->cc_op - CC_OP_ADDB) % 3][jcc_op];
367e86e8
FB		 1484 break;
1485 default:
1486 goto slow_jcc;
1487 }
1488 break;
1489 default:
1490 slow_jcc:
1491 if (s->cc_op != CC_OP_DYNAMIC)
1017ebe9 1492 gen_op_set_cc_op(s->cc_op);
367e86e8
FB		 1493 func = gen_setcc_slow[jcc_op];
1494 break;
1495 }
1496 func();
1497 if (inv) {
1498 gen_op_xor_T0_1();
1499 }
1500}
1501
2e255c6b
FB		 1502/* move T0 to seg_reg and compute if the CPU state may change. Never
1503 call this function with seg_reg == R_CS */
5a91de8c 1504static void gen_movl_seg_T0(DisasContext *s, int seg_reg, unsigned int cur_eip)
6dbad63e 1505{
8f186479 1506 if (s->pe && !s->vm86)
5a91de8c
FB		 1507 gen_op_movl_seg_T0(seg_reg, cur_eip);
1508 else
d8bc1fd0 1509 gen_op_movl_seg_T0_vm(offsetof(CPUX86State,segs[seg_reg]));
8a4c1cc4 1510 /* abort translation because the register may have a non zero base
3f337316
FB		 1511 or because ss32 may change. For R_SS, translation must always
1512 stop as a special handling must be done to disable hardware
1513 interrupts for the next instruction */
8a4c1cc4 1514 if (seg_reg == R_SS || (!s->addseg && seg_reg < R_FS))
dbc5594c 1515 s->is_jmp = 3;
6dbad63e
FB		 1516}
1517
dab2ed99
FB		 1518/* generate a push. It depends on ss32, addseg and dflag */
1519static void gen_push_T0(DisasContext *s)
1520{
1521 if (s->ss32) {
1522 if (!s->addseg) {
1523 if (s->dflag)
1524 gen_op_pushl_T0();
1525 else
1526 gen_op_pushw_T0();
1527 } else {
1528 if (s->dflag)
1529 gen_op_pushl_ss32_T0();
1530 else
1531 gen_op_pushw_ss32_T0();
1532 }
1533 } else {
1534 if (s->dflag)
1535 gen_op_pushl_ss16_T0();
1536 else
1537 gen_op_pushw_ss16_T0();
1538 }
1539}
1540
1541/* two step pop is necessary for precise exceptions */
1542static void gen_pop_T0(DisasContext *s)
1543{
1544 if (s->ss32) {
1545 if (!s->addseg) {
1546 if (s->dflag)
1547 gen_op_popl_T0();
1548 else
1549 gen_op_popw_T0();
1550 } else {
1551 if (s->dflag)
1552 gen_op_popl_ss32_T0();
1553 else
1554 gen_op_popw_ss32_T0();
1555 }
1556 } else {
1557 if (s->dflag)
1558 gen_op_popl_ss16_T0();
1559 else
1560 gen_op_popw_ss16_T0();
1561 }
1562}
1563
d0a1ffc9 1564static inline void gen_stack_update(DisasContext *s, int addend)
dab2ed99
FB		 1565{
1566 if (s->ss32) {
d0a1ffc9 1567 if (addend == 2)
dab2ed99 1568 gen_op_addl_ESP_2();
d0a1ffc9
FB		 1569 else if (addend == 4)
1570 gen_op_addl_ESP_4();
1571 else
1572 gen_op_addl_ESP_im(addend);
dab2ed99 1573 } else {
d0a1ffc9
FB		 1574 if (addend == 2)
1575 gen_op_addw_ESP_2();
1576 else if (addend == 4)
dab2ed99
FB		 1577 gen_op_addw_ESP_4();
1578 else
d0a1ffc9 1579 gen_op_addw_ESP_im(addend);
dab2ed99
FB		 1580 }
1581}
1582
d0a1ffc9
FB		 1583static void gen_pop_update(DisasContext *s)
1584{
1585 gen_stack_update(s, 2 << s->dflag);
1586}
1587
1588static void gen_stack_A0(DisasContext *s)
1589{
1590 gen_op_movl_A0_ESP();
1591 if (!s->ss32)
1592 gen_op_andl_A0_ffff();
1593 gen_op_movl_T1_A0();
1594 if (s->addseg)
d8bc1fd0 1595 gen_op_addl_A0_seg(offsetof(CPUX86State,segs[R_SS].base));
d0a1ffc9
FB		 1596}
1597
dab2ed99
FB		 1598/* NOTE: wrap around in 16 bit not fully handled */
1599static void gen_pusha(DisasContext *s)
1600{
1601 int i;
1602 gen_op_movl_A0_ESP();
1603 gen_op_addl_A0_im(-16 << s->dflag);
1604 if (!s->ss32)
1605 gen_op_andl_A0_ffff();
1606 gen_op_movl_T1_A0();
1607 if (s->addseg)
d8bc1fd0 1608 gen_op_addl_A0_seg(offsetof(CPUX86State,segs[R_SS].base));
dab2ed99
FB		 1609 for(i = 0;i < 8; i++) {
1610 gen_op_mov_TN_reg[OT_LONG][0][7 - i]();
4021dab0 1611 gen_op_st_T0_A0[OT_WORD + s->dflag + s->mem_index]();
dab2ed99
FB		 1612 gen_op_addl_A0_im(2 << s->dflag);
1613 }
1614 gen_op_mov_reg_T1[OT_WORD + s->dflag][R_ESP]();
1615}
1616
1617/* NOTE: wrap around in 16 bit not fully handled */
1618static void gen_popa(DisasContext *s)
1619{
1620 int i;
1621 gen_op_movl_A0_ESP();
1622 if (!s->ss32)
1623 gen_op_andl_A0_ffff();
1624 gen_op_movl_T1_A0();
1625 gen_op_addl_T1_im(16 << s->dflag);
1626 if (s->addseg)
d8bc1fd0 1627 gen_op_addl_A0_seg(offsetof(CPUX86State,segs[R_SS].base));
dab2ed99
FB		 1628 for(i = 0;i < 8; i++) {
1629 /* ESP is not reloaded */
1630 if (i != 3) {
4021dab0 1631 gen_op_ld_T0_A0[OT_WORD + s->dflag + s->mem_index]();
dab2ed99
FB		 1632 gen_op_mov_reg_T0[OT_WORD + s->dflag][7 - i]();
1633 }
1634 gen_op_addl_A0_im(2 << s->dflag);
1635 }
1636 gen_op_mov_reg_T1[OT_WORD + s->dflag][R_ESP]();
1637}
1638
1639/* NOTE: wrap around in 16 bit not fully handled */
1640/* XXX: check this */
1641static void gen_enter(DisasContext *s, int esp_addend, int level)
1642{
1643 int ot, level1, addend, opsize;
1644
1645 ot = s->dflag + OT_WORD;
1646 level &= 0x1f;
1647 level1 = level;
1648 opsize = 2 << s->dflag;
1649
1650 gen_op_movl_A0_ESP();
1651 gen_op_addl_A0_im(-opsize);
1652 if (!s->ss32)
1653 gen_op_andl_A0_ffff();
1654 gen_op_movl_T1_A0();
1655 if (s->addseg)
d8bc1fd0 1656 gen_op_addl_A0_seg(offsetof(CPUX86State,segs[R_SS].base));
dab2ed99
FB		 1657 /* push bp */
1658 gen_op_mov_TN_reg[OT_LONG][0][R_EBP]();
4021dab0 1659 gen_op_st_T0_A0[ot + s->mem_index]();
dab2ed99
FB		 1660 if (level) {
1661 while (level--) {
1662 gen_op_addl_A0_im(-opsize);
1663 gen_op_addl_T0_im(-opsize);
4021dab0 1664 gen_op_st_T0_A0[ot + s->mem_index]();
dab2ed99
FB		 1665 }
1666 gen_op_addl_A0_im(-opsize);
1667 /* XXX: add st_T1_A0 ? */
1668 gen_op_movl_T0_T1();
4021dab0 1669 gen_op_st_T0_A0[ot + s->mem_index]();
dab2ed99
FB		 1670 }
1671 gen_op_mov_reg_T1[ot][R_EBP]();
1672 addend = -esp_addend;
1673 if (level1)
1674 addend -= opsize * (level1 + 1);
1675 gen_op_addl_T1_im(addend);
1676 gen_op_mov_reg_T1[ot][R_ESP]();
1677}
1678
c50c0c3f
FB		 1679static void gen_exception(DisasContext *s, int trapno, unsigned int cur_eip)
1680{
1681 if (s->cc_op != CC_OP_DYNAMIC)
1682 gen_op_set_cc_op(s->cc_op);
1683 gen_op_jmp_im(cur_eip);
1684 gen_op_raise_exception(trapno);
dbc5594c 1685 s->is_jmp = 3;
c50c0c3f
FB		 1686}
1687
5a91de8c
FB		 1688/* an interrupt is different from an exception because of the
1689 priviledge checks */
1690static void gen_interrupt(DisasContext *s, int intno,
1691 unsigned int cur_eip, unsigned int next_eip)
1692{
1693 if (s->cc_op != CC_OP_DYNAMIC)
1694 gen_op_set_cc_op(s->cc_op);
1695 gen_op_jmp_im(cur_eip);
1696 gen_op_raise_interrupt(intno, next_eip);
dbc5594c 1697 s->is_jmp = 3;
5a91de8c
FB		 1698}
1699
4c3a88a2
FB		 1700static void gen_debug(DisasContext *s, unsigned int cur_eip)
1701{
1702 if (s->cc_op != CC_OP_DYNAMIC)
1703 gen_op_set_cc_op(s->cc_op);
1704 gen_op_jmp_im(cur_eip);
1705 gen_op_debug();
dbc5594c
FB		 1706 s->is_jmp = 3;
1707}
1708
1709/* generate a generic end of block. Trace exception is also generated
1710 if needed */
1711static void gen_eob(DisasContext *s)
1712{
1713 if (s->cc_op != CC_OP_DYNAMIC)
1714 gen_op_set_cc_op(s->cc_op);
1715 if (s->tf) {
1716 gen_op_raise_exception(EXCP01_SSTP);
1717 } else {
1718 gen_op_movl_T0_0();
1719 gen_op_exit_tb();
1720 }
1721 s->is_jmp = 3;
4c3a88a2
FB		 1722}
1723
d4e8164f
FB		 1724/* generate a jump to eip. No segment change must happen before as a
1725 direct call to the next block may occur */
1726static void gen_jmp(DisasContext *s, unsigned int eip)
1727{
1728 TranslationBlock *tb = s->tb;
1729
dbc5594c
FB		 1730 if (s->jmp_opt) {
1731 if (s->cc_op != CC_OP_DYNAMIC)
1732 gen_op_set_cc_op(s->cc_op);
1733 gen_op_jmp((long)tb, eip);
1734 s->is_jmp = 3;
1735 } else {
1736 gen_op_jmp_im(eip);
1737 gen_eob(s);
1738 }
d4e8164f
FB		 1739}
1740
dbc5594c
FB		 1741/* convert one instruction. s->is_jmp is set if the translation must
1742 be stopped. Return the next pc value */
1743static uint8_t *disas_insn(DisasContext *s, uint8_t *pc_start)
367e86e8
FB		 1744{
1745 int b, prefixes, aflag, dflag;
1746 int shift, ot;
1747 int modrm, reg, rm, mod, reg_addr, op, opreg, offset_addr, val;
dab2ed99 1748 unsigned int next_eip;
367e86e8
FB		 1749
1750 s->pc = pc_start;
1751 prefixes = 0;
6dbad63e
FB		 1752 aflag = s->code32;
1753 dflag = s->code32;
9c605cb1 1754 s->override = -1;
367e86e8
FB		 1755 next_byte:
1756 b = ldub(s->pc);
367e86e8
FB		 1757 s->pc++;
1758 /* check prefixes */
1759 switch (b) {
1760 case 0xf3:
1761 prefixes |= PREFIX_REPZ;
1762 goto next_byte;
1763 case 0xf2:
1764 prefixes |= PREFIX_REPNZ;
1765 goto next_byte;
1766 case 0xf0:
1767 prefixes |= PREFIX_LOCK;
1768 goto next_byte;
1769 case 0x2e:
9c605cb1 1770 s->override = R_CS;
367e86e8
FB		 1771 goto next_byte;
1772 case 0x36:
9c605cb1 1773 s->override = R_SS;
367e86e8
FB		 1774 goto next_byte;
1775 case 0x3e:
9c605cb1 1776 s->override = R_DS;
367e86e8
FB		 1777 goto next_byte;
1778 case 0x26:
9c605cb1 1779 s->override = R_ES;
367e86e8
FB		 1780 goto next_byte;
1781 case 0x64:
9c605cb1 1782 s->override = R_FS;
367e86e8
FB		 1783 goto next_byte;
1784 case 0x65:
9c605cb1 1785 s->override = R_GS;
367e86e8
FB		 1786 goto next_byte;
1787 case 0x66:
1788 prefixes |= PREFIX_DATA;
1789 goto next_byte;
1790 case 0x67:
1791 prefixes |= PREFIX_ADR;
1792 goto next_byte;
367e86e8
FB		 1793 }
1794
1795 if (prefixes & PREFIX_DATA)
1796 dflag ^= 1;
1797 if (prefixes & PREFIX_ADR)
1798 aflag ^= 1;
1799
1800 s->prefix = prefixes;
1801 s->aflag = aflag;
1802 s->dflag = dflag;
1803
1b6b029e
FB		 1804 /* lock generation */
1805 if (prefixes & PREFIX_LOCK)
1806 gen_op_lock();
1807
367e86e8
FB		 1808 /* now check op code */
1809 reswitch:
1810 switch(b) {
1811 case 0x0f:
1812 /**************************/
1813 /* extended op code */
1814 b = ldub(s->pc++) | 0x100;
1815 goto reswitch;
1816
1817 /**************************/
1818 /* arith & logic */
1819 case 0x00 ... 0x05:
1820 case 0x08 ... 0x0d:
1821 case 0x10 ... 0x15:
1822 case 0x18 ... 0x1d:
1823 case 0x20 ... 0x25:
1824 case 0x28 ... 0x2d:
1825 case 0x30 ... 0x35:
1826 case 0x38 ... 0x3d:
1827 {
1828 int op, f, val;
1829 op = (b >> 3) & 7;
1830 f = (b >> 1) & 3;
1831
1832 if ((b & 1) == 0)
1833 ot = OT_BYTE;
1834 else
1835 ot = dflag ? OT_LONG : OT_WORD;
1836
1837 switch(f) {
1838 case 0: /* OP Ev, Gv */
1839 modrm = ldub(s->pc++);
3c1cf9fa 1840 reg = ((modrm >> 3) & 7);
367e86e8
FB		 1841 mod = (modrm >> 6) & 3;
1842 rm = modrm & 7;
1843 if (mod != 3) {
1844 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
367e86e8 1845 opreg = OR_TMP0;
3c1cf9fa
FB		 1846 } else if (op == OP_XORL && rm == reg) {
1847 xor_zero:
1848 /* xor reg, reg optimisation */
1849 gen_op_movl_T0_0();
1850 s->cc_op = CC_OP_LOGICB + ot;
1851 gen_op_mov_reg_T0[ot][reg]();
1852 gen_op_update1_cc();
1853 break;
367e86e8 1854 } else {
3c1cf9fa 1855 opreg = rm;
367e86e8 1856 }
5797fa5d
FB		 1857 gen_op_mov_TN_reg[ot][1][reg]();
1858 gen_op(s, op, ot, opreg);
367e86e8
FB		 1859 break;
1860 case 1: /* OP Gv, Ev */
1861 modrm = ldub(s->pc++);
1862 mod = (modrm >> 6) & 3;
3c1cf9fa 1863 reg = ((modrm >> 3) & 7);
367e86e8
FB		 1864 rm = modrm & 7;
1865 if (mod != 3) {
1866 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
4021dab0 1867 gen_op_ld_T1_A0[ot + s->mem_index]();
3c1cf9fa
FB		 1868 } else if (op == OP_XORL && rm == reg) {
1869 goto xor_zero;
367e86e8 1870 } else {
5797fa5d 1871 gen_op_mov_TN_reg[ot][1][rm]();
367e86e8 1872 }
5797fa5d 1873 gen_op(s, op, ot, reg);
367e86e8
FB		 1874 break;
1875 case 2: /* OP A, Iv */
1876 val = insn_get(s, ot);
5797fa5d
FB		 1877 gen_op_movl_T1_im(val);
1878 gen_op(s, op, ot, OR_EAX);
367e86e8
FB		 1879 break;
1880 }
1881 }
1882 break;
1883
1884 case 0x80: /* GRP1 */
1885 case 0x81:
1886 case 0x83:
1887 {
1888 int val;
1889
1890 if ((b & 1) == 0)
1891 ot = OT_BYTE;
1892 else
1893 ot = dflag ? OT_LONG : OT_WORD;
1894
1895 modrm = ldub(s->pc++);
1896 mod = (modrm >> 6) & 3;
1897 rm = modrm & 7;
1898 op = (modrm >> 3) & 7;
1899
1900 if (mod != 3) {
1901 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
367e86e8
FB		 1902 opreg = OR_TMP0;
1903 } else {
1904 opreg = rm + OR_EAX;
1905 }
1906
1907 switch(b) {
1908 default:
1909 case 0x80:
1910 case 0x81:
1911 val = insn_get(s, ot);
1912 break;
1913 case 0x83:
1914 val = (int8_t)insn_get(s, OT_BYTE);
1915 break;
1916 }
5797fa5d
FB		 1917 gen_op_movl_T1_im(val);
1918 gen_op(s, op, ot, opreg);
367e86e8
FB		 1919 }
1920 break;
1921
1922 /**************************/
1923 /* inc, dec, and other misc arith */
1924 case 0x40 ... 0x47: /* inc Gv */
1925 ot = dflag ? OT_LONG : OT_WORD;
1926 gen_inc(s, ot, OR_EAX + (b & 7), 1);
1927 break;
1928 case 0x48 ... 0x4f: /* dec Gv */
1929 ot = dflag ? OT_LONG : OT_WORD;
1930 gen_inc(s, ot, OR_EAX + (b & 7), -1);
1931 break;
1932 case 0xf6: /* GRP3 */
1933 case 0xf7:
1934 if ((b & 1) == 0)
1935 ot = OT_BYTE;
1936 else
1937 ot = dflag ? OT_LONG : OT_WORD;
1938
1939 modrm = ldub(s->pc++);
1940 mod = (modrm >> 6) & 3;
1941 rm = modrm & 7;
1942 op = (modrm >> 3) & 7;
1943 if (mod != 3) {
1944 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
4021dab0 1945 gen_op_ld_T0_A0[ot + s->mem_index]();
367e86e8
FB		 1946 } else {
1947 gen_op_mov_TN_reg[ot][0][rm]();
1948 }
1949
1950 switch(op) {
1951 case 0: /* test */
1952 val = insn_get(s, ot);
ba1c6e37 1953 gen_op_movl_T1_im(val);
367e86e8
FB		 1954 gen_op_testl_T0_T1_cc();
1955 s->cc_op = CC_OP_LOGICB + ot;
1956 break;
1957 case 2: /* not */
1958 gen_op_notl_T0();
1959 if (mod != 3) {
4021dab0 1960 gen_op_st_T0_A0[ot + s->mem_index]();
367e86e8
FB		 1961 } else {
1962 gen_op_mov_reg_T0[ot][rm]();
1963 }
1964 break;
1965 case 3: /* neg */
5797fa5d 1966 gen_op_negl_T0();
367e86e8 1967 if (mod != 3) {
4021dab0 1968 gen_op_st_T0_A0[ot + s->mem_index]();
367e86e8
FB		 1969 } else {
1970 gen_op_mov_reg_T0[ot][rm]();
1971 }
5797fa5d 1972 gen_op_update_neg_cc();
367e86e8
FB		 1973 s->cc_op = CC_OP_SUBB + ot;
1974 break;
1975 case 4: /* mul */
1976 switch(ot) {
1977 case OT_BYTE:
1978 gen_op_mulb_AL_T0();
1979 break;
1980 case OT_WORD:
1981 gen_op_mulw_AX_T0();
1982 break;
1983 default:
1984 case OT_LONG:
1985 gen_op_mull_EAX_T0();
1986 break;
1987 }
0ecfa993 1988 s->cc_op = CC_OP_MUL;
367e86e8
FB		 1989 break;
1990 case 5: /* imul */
1991 switch(ot) {
1992 case OT_BYTE:
1993 gen_op_imulb_AL_T0();
1994 break;
1995 case OT_WORD:
1996 gen_op_imulw_AX_T0();
1997 break;
1998 default:
1999 case OT_LONG:
2000 gen_op_imull_EAX_T0();
2001 break;
2002 }
0ecfa993 2003 s->cc_op = CC_OP_MUL;
367e86e8
FB		 2004 break;
2005 case 6: /* div */
2006 switch(ot) {
2007 case OT_BYTE:
5a91de8c 2008 gen_op_divb_AL_T0(pc_start - s->cs_base);
367e86e8
FB		 2009 break;
2010 case OT_WORD:
5a91de8c 2011 gen_op_divw_AX_T0(pc_start - s->cs_base);
367e86e8
FB		 2012 break;
2013 default:
2014 case OT_LONG:
5a91de8c 2015 gen_op_divl_EAX_T0(pc_start - s->cs_base);
367e86e8
FB		 2016 break;
2017 }
2018 break;
2019 case 7: /* idiv */
2020 switch(ot) {
2021 case OT_BYTE:
5a91de8c 2022 gen_op_idivb_AL_T0(pc_start - s->cs_base);
367e86e8
FB		 2023 break;
2024 case OT_WORD:
5a91de8c 2025 gen_op_idivw_AX_T0(pc_start - s->cs_base);
367e86e8
FB		 2026 break;
2027 default:
2028 case OT_LONG:
5a91de8c 2029 gen_op_idivl_EAX_T0(pc_start - s->cs_base);
367e86e8
FB		 2030 break;
2031 }
2032 break;
2033 default:
1a9353d2 2034 goto illegal_op;
367e86e8
FB		 2035 }
2036 break;
2037
2038 case 0xfe: /* GRP4 */
2039 case 0xff: /* GRP5 */
2040 if ((b & 1) == 0)
2041 ot = OT_BYTE;
2042 else
2043 ot = dflag ? OT_LONG : OT_WORD;
2044
2045 modrm = ldub(s->pc++);
2046 mod = (modrm >> 6) & 3;
2047 rm = modrm & 7;
2048 op = (modrm >> 3) & 7;
2049 if (op >= 2 && b == 0xfe) {
1a9353d2 2050 goto illegal_op;
367e86e8
FB		 2051 }
2052 if (mod != 3) {
2053 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
5797fa5d 2054 if (op >= 2 && op != 3 && op != 5)
4021dab0 2055 gen_op_ld_T0_A0[ot + s->mem_index]();
367e86e8
FB		 2056 } else {
2057 gen_op_mov_TN_reg[ot][0][rm]();
2058 }
2059
2060 switch(op) {
2061 case 0: /* inc Ev */
367e86e8 2062 if (mod != 3)
5797fa5d 2063 opreg = OR_TMP0;
4b74fe1f 2064 else
5797fa5d
FB		 2065 opreg = rm;
2066 gen_inc(s, ot, opreg, 1);
367e86e8
FB		 2067 break;
2068 case 1: /* dec Ev */
367e86e8 2069 if (mod != 3)
5797fa5d 2070 opreg = OR_TMP0;
4b74fe1f 2071 else
5797fa5d
FB		 2072 opreg = rm;
2073 gen_inc(s, ot, opreg, -1);
367e86e8
FB		 2074 break;
2075 case 2: /* call Ev */
dab2ed99
FB		 2076 /* XXX: optimize if memory (no and is necessary) */
2077 if (s->dflag == 0)
2078 gen_op_andl_T0_ffff();
2079 gen_op_jmp_T0();
2080 next_eip = s->pc - s->cs_base;
2081 gen_op_movl_T0_im(next_eip);
2082 gen_push_T0(s);
dbc5594c 2083 gen_eob(s);
dab2ed99 2084 break;
dbc5594c 2085 case 3: /*< lcall Ev */
4021dab0 2086 gen_op_ld_T1_A0[ot + s->mem_index]();
dab2ed99 2087 gen_op_addl_A0_im(1 << (ot - OT_WORD + 1));
4021dab0 2088 gen_op_ld_T0_A0[OT_WORD + s->mem_index]();
2c1794c4
FB		 2089 do_lcall:
2090 if (s->pe && !s->vm86) {
2091 if (s->cc_op != CC_OP_DYNAMIC)
2092 gen_op_set_cc_op(s->cc_op);
2093 gen_op_jmp_im(pc_start - s->cs_base);
2094 gen_op_lcall_protected_T0_T1(dflag, s->pc - s->cs_base);
2095 } else {
2096 gen_op_lcall_real_T0_T1(dflag, s->pc - s->cs_base);
2097 }
dbc5594c 2098 gen_eob(s);
367e86e8
FB		 2099 break;
2100 case 4: /* jmp Ev */
dab2ed99
FB		 2101 if (s->dflag == 0)
2102 gen_op_andl_T0_ffff();
2103 gen_op_jmp_T0();
dbc5594c 2104 gen_eob(s);
dab2ed99
FB		 2105 break;
2106 case 5: /* ljmp Ev */
4021dab0 2107 gen_op_ld_T1_A0[ot + s->mem_index]();
dab2ed99
FB		 2108 gen_op_addl_A0_im(1 << (ot - OT_WORD + 1));
2109 gen_op_lduw_T0_A0();
2c1794c4 2110 do_ljmp:
8f186479 2111 if (s->pe && !s->vm86) {
2c1794c4
FB		 2112 if (s->cc_op != CC_OP_DYNAMIC)
2113 gen_op_set_cc_op(s->cc_op);
d8bc1fd0 2114 gen_op_jmp_im(pc_start - s->cs_base);
2c1794c4 2115 gen_op_ljmp_protected_T0_T1();
d8bc1fd0
FB		 2116 } else {
2117 gen_op_movl_seg_T0_vm(offsetof(CPUX86State,segs[R_CS]));
2118 gen_op_movl_T0_T1();
2119 gen_op_jmp_T0();
2120 }
dbc5594c 2121 gen_eob(s);
367e86e8
FB		 2122 break;
2123 case 6: /* push Ev */
dab2ed99 2124 gen_push_T0(s);
367e86e8
FB		 2125 break;
2126 default:
1a9353d2 2127 goto illegal_op;
367e86e8
FB		 2128 }
2129 break;
2130
2131 case 0x84: /* test Ev, Gv */
2132 case 0x85:
2133 if ((b & 1) == 0)
2134 ot = OT_BYTE;
2135 else
2136 ot = dflag ? OT_LONG : OT_WORD;
2137
2138 modrm = ldub(s->pc++);
2139 mod = (modrm >> 6) & 3;
2140 rm = modrm & 7;
2141 reg = (modrm >> 3) & 7;
2142
2143 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
2144 gen_op_mov_TN_reg[ot][1][reg + OR_EAX]();
2145 gen_op_testl_T0_T1_cc();
2146 s->cc_op = CC_OP_LOGICB + ot;
2147 break;
2148
2149 case 0xa8: /* test eAX, Iv */
2150 case 0xa9:
2151 if ((b & 1) == 0)
2152 ot = OT_BYTE;
2153 else
2154 ot = dflag ? OT_LONG : OT_WORD;
2155 val = insn_get(s, ot);
2156
2157 gen_op_mov_TN_reg[ot][0][OR_EAX]();
ba1c6e37 2158 gen_op_movl_T1_im(val);
367e86e8
FB		 2159 gen_op_testl_T0_T1_cc();
2160 s->cc_op = CC_OP_LOGICB + ot;
2161 break;
2162
2163 case 0x98: /* CWDE/CBW */
2164 if (dflag)
2165 gen_op_movswl_EAX_AX();
2166 else
2167 gen_op_movsbw_AX_AL();
2168 break;
2169 case 0x99: /* CDQ/CWD */
2170 if (dflag)
2171 gen_op_movslq_EDX_EAX();
2172 else
2173 gen_op_movswl_DX_AX();
2174 break;
2175 case 0x1af: /* imul Gv, Ev */
2176 case 0x69: /* imul Gv, Ev, I */
2177 case 0x6b:
2178 ot = dflag ? OT_LONG : OT_WORD;
2179 modrm = ldub(s->pc++);
2180 reg = ((modrm >> 3) & 7) + OR_EAX;
367e86e8
FB		 2181 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
2182 if (b == 0x69) {
2183 val = insn_get(s, ot);
ba1c6e37 2184 gen_op_movl_T1_im(val);
367e86e8
FB		 2185 } else if (b == 0x6b) {
2186 val = insn_get(s, OT_BYTE);
ba1c6e37 2187 gen_op_movl_T1_im(val);
367e86e8
FB		 2188 } else {
2189 gen_op_mov_TN_reg[ot][1][reg]();
2190 }
2191
2192 if (ot == OT_LONG) {
4b74fe1f 2193 gen_op_imull_T0_T1();
367e86e8 2194 } else {
4b74fe1f 2195 gen_op_imulw_T0_T1();
367e86e8
FB		 2196 }
2197 gen_op_mov_reg_T0[ot][reg]();
0ecfa993 2198 s->cc_op = CC_OP_MUL;
367e86e8 2199 break;
1a9353d2
FB		 2200 case 0x1c0:
2201 case 0x1c1: /* xadd Ev, Gv */
2202 if ((b & 1) == 0)
2203 ot = OT_BYTE;
2204 else
2205 ot = dflag ? OT_LONG : OT_WORD;
2206 modrm = ldub(s->pc++);
2207 reg = (modrm >> 3) & 7;
2208 mod = (modrm >> 6) & 3;
2209 if (mod == 3) {
2210 rm = modrm & 7;
2211 gen_op_mov_TN_reg[ot][0][reg]();
2212 gen_op_mov_TN_reg[ot][1][rm]();
5797fa5d 2213 gen_op_addl_T0_T1();
1a9353d2
FB		 2214 gen_op_mov_reg_T0[ot][rm]();
2215 gen_op_mov_reg_T1[ot][reg]();
2216 } else {
2217 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
2218 gen_op_mov_TN_reg[ot][0][reg]();
4021dab0 2219 gen_op_ld_T1_A0[ot + s->mem_index]();
5797fa5d 2220 gen_op_addl_T0_T1();
4021dab0 2221 gen_op_st_T0_A0[ot + s->mem_index]();
1a9353d2
FB		 2222 gen_op_mov_reg_T1[ot][reg]();
2223 }
5797fa5d 2224 gen_op_update2_cc();
1a9353d2
FB		 2225 s->cc_op = CC_OP_ADDB + ot;
2226 break;
2227 case 0x1b0:
2228 case 0x1b1: /* cmpxchg Ev, Gv */
2229 if ((b & 1) == 0)
2230 ot = OT_BYTE;
2231 else
2232 ot = dflag ? OT_LONG : OT_WORD;
2233 modrm = ldub(s->pc++);
2234 reg = (modrm >> 3) & 7;
2235 mod = (modrm >> 6) & 3;
2236 gen_op_mov_TN_reg[ot][1][reg]();
2237 if (mod == 3) {
2238 rm = modrm & 7;
2239 gen_op_mov_TN_reg[ot][0][rm]();
2240 gen_op_cmpxchg_T0_T1_EAX_cc[ot]();
2241 gen_op_mov_reg_T0[ot][rm]();
2242 } else {
2243 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
4021dab0 2244 gen_op_ld_T0_A0[ot + s->mem_index]();
e477b8b8 2245 gen_op_cmpxchg_mem_T0_T1_EAX_cc[ot]();
1a9353d2
FB		 2246 }
2247 s->cc_op = CC_OP_SUBB + ot;
2248 break;
9c605cb1
FB		 2249 case 0x1c7: /* cmpxchg8b */
2250 modrm = ldub(s->pc++);
2251 mod = (modrm >> 6) & 3;
2252 if (mod == 3)
2253 goto illegal_op;
2254 if (s->cc_op != CC_OP_DYNAMIC)
2255 gen_op_set_cc_op(s->cc_op);
2256 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
2257 gen_op_cmpxchg8b();
2258 s->cc_op = CC_OP_EFLAGS;
2259 break;
367e86e8
FB		 2260
2261 /**************************/
2262 /* push/pop */
2263 case 0x50 ... 0x57: /* push */
927f621e 2264 gen_op_mov_TN_reg[OT_LONG][0][b & 7]();
dab2ed99 2265 gen_push_T0(s);
367e86e8
FB		 2266 break;
2267 case 0x58 ... 0x5f: /* pop */
dab2ed99
FB		 2268 ot = dflag ? OT_LONG : OT_WORD;
2269 gen_pop_T0(s);
2270 gen_op_mov_reg_T0[ot][b & 7]();
2271 gen_pop_update(s);
367e86e8 2272 break;
27362c82 2273 case 0x60: /* pusha */
dab2ed99 2274 gen_pusha(s);
27362c82
FB		 2275 break;
2276 case 0x61: /* popa */
dab2ed99 2277 gen_popa(s);
27362c82 2278 break;
367e86e8
FB		 2279 case 0x68: /* push Iv */
2280 case 0x6a:
2281 ot = dflag ? OT_LONG : OT_WORD;
2282 if (b == 0x68)
2283 val = insn_get(s, ot);
2284 else
2285 val = (int8_t)insn_get(s, OT_BYTE);
ba1c6e37 2286 gen_op_movl_T0_im(val);
dab2ed99 2287 gen_push_T0(s);
367e86e8
FB		 2288 break;
2289 case 0x8f: /* pop Ev */
2290 ot = dflag ? OT_LONG : OT_WORD;
2291 modrm = ldub(s->pc++);
dab2ed99 2292 gen_pop_T0(s);
8f186479 2293 s->popl_esp_hack = 2 << dflag;
367e86e8 2294 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 1);
717fc2ad 2295 s->popl_esp_hack = 0;
dab2ed99 2296 gen_pop_update(s);
367e86e8 2297 break;
27362c82
FB		 2298 case 0xc8: /* enter */
2299 {
2300 int level;
2301 val = lduw(s->pc);
2302 s->pc += 2;
2303 level = ldub(s->pc++);
dab2ed99 2304 gen_enter(s, val, level);
27362c82
FB		 2305 }
2306 break;
367e86e8 2307 case 0xc9: /* leave */
d0a1ffc9 2308 /* XXX: exception not precise (ESP is updated before potential exception) */
dab2ed99
FB		 2309 if (s->ss32) {
2310 gen_op_mov_TN_reg[OT_LONG][0][R_EBP]();
2311 gen_op_mov_reg_T0[OT_LONG][R_ESP]();
2312 } else {
2313 gen_op_mov_TN_reg[OT_WORD][0][R_EBP]();
2314 gen_op_mov_reg_T0[OT_WORD][R_ESP]();
2315 }
2316 gen_pop_T0(s);
2317 ot = dflag ? OT_LONG : OT_WORD;
2318 gen_op_mov_reg_T0[ot][R_EBP]();
2319 gen_pop_update(s);
367e86e8 2320 break;
6dbad63e
FB		 2321 case 0x06: /* push es */
2322 case 0x0e: /* push cs */
2323 case 0x16: /* push ss */
2324 case 0x1e: /* push ds */
2325 gen_op_movl_T0_seg(b >> 3);
dab2ed99 2326 gen_push_T0(s);
6dbad63e
FB		 2327 break;
2328 case 0x1a0: /* push fs */
2329 case 0x1a8: /* push gs */
f631ef9b 2330 gen_op_movl_T0_seg((b >> 3) & 7);
dab2ed99 2331 gen_push_T0(s);
6dbad63e
FB		 2332 break;
2333 case 0x07: /* pop es */
2334 case 0x17: /* pop ss */
2335 case 0x1f: /* pop ds */
3f337316 2336 reg = b >> 3;
dab2ed99 2337 gen_pop_T0(s);
3f337316 2338 gen_movl_seg_T0(s, reg, pc_start - s->cs_base);
dab2ed99 2339 gen_pop_update(s);
3f337316
FB		 2340 if (reg == R_SS) {
2341 /* if reg == SS, inhibit interrupts/trace */
2342 gen_op_set_inhibit_irq();
dbc5594c
FB		 2343 s->tf = 0;
2344 }
2345 if (s->is_jmp) {
2346 gen_op_jmp_im(s->pc - s->cs_base);
2347 gen_eob(s);
3f337316 2348 }
6dbad63e
FB		 2349 break;
2350 case 0x1a1: /* pop fs */
2351 case 0x1a9: /* pop gs */
dab2ed99 2352 gen_pop_T0(s);
5a91de8c 2353 gen_movl_seg_T0(s, (b >> 3) & 7, pc_start - s->cs_base);
dab2ed99 2354 gen_pop_update(s);
dbc5594c
FB		 2355 if (s->is_jmp) {
2356 gen_op_jmp_im(s->pc - s->cs_base);
2357 gen_eob(s);
2358 }
6dbad63e
FB		 2359 break;
2360
367e86e8
FB		 2361 /**************************/
2362 /* mov */
2363 case 0x88:
2364 case 0x89: /* mov Gv, Ev */
2365 if ((b & 1) == 0)
2366 ot = OT_BYTE;
2367 else
2368 ot = dflag ? OT_LONG : OT_WORD;
2369 modrm = ldub(s->pc++);
2370 reg = (modrm >> 3) & 7;
2371
2372 /* generate a generic store */
2373 gen_ldst_modrm(s, modrm, ot, OR_EAX + reg, 1);
2374 break;
2375 case 0xc6:
2376 case 0xc7: /* mov Ev, Iv */
2377 if ((b & 1) == 0)
2378 ot = OT_BYTE;
2379 else
2380 ot = dflag ? OT_LONG : OT_WORD;
2381 modrm = ldub(s->pc++);
2382 mod = (modrm >> 6) & 3;
0ecfa993
FB		 2383 if (mod != 3)
2384 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
367e86e8 2385 val = insn_get(s, ot);
ba1c6e37 2386 gen_op_movl_T0_im(val);
0ecfa993 2387 if (mod != 3)
4021dab0 2388 gen_op_st_T0_A0[ot + s->mem_index]();
0ecfa993
FB		 2389 else
2390 gen_op_mov_reg_T0[ot][modrm & 7]();
367e86e8
FB		 2391 break;
2392 case 0x8a:
2393 case 0x8b: /* mov Ev, Gv */
2394 if ((b & 1) == 0)
2395 ot = OT_BYTE;
2396 else
2397 ot = dflag ? OT_LONG : OT_WORD;
2398 modrm = ldub(s->pc++);
2399 reg = (modrm >> 3) & 7;
2400
2401 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
2402 gen_op_mov_reg_T0[ot][reg]();
2403 break;
6dbad63e 2404 case 0x8e: /* mov seg, Gv */
6dbad63e
FB		 2405 modrm = ldub(s->pc++);
2406 reg = (modrm >> 3) & 7;
dab2ed99 2407 if (reg >= 6 || reg == R_CS)
6dbad63e 2408 goto illegal_op;
8f186479 2409 gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
5a91de8c 2410 gen_movl_seg_T0(s, reg, pc_start - s->cs_base);
3f337316
FB		 2411 if (reg == R_SS) {
2412 /* if reg == SS, inhibit interrupts/trace */
2413 gen_op_set_inhibit_irq();
dbc5594c
FB		 2414 s->tf = 0;
2415 }
2416 if (s->is_jmp) {
2417 gen_op_jmp_im(s->pc - s->cs_base);
2418 gen_eob(s);
3f337316 2419 }
6dbad63e
FB		 2420 break;
2421 case 0x8c: /* mov Gv, seg */
6dbad63e
FB		 2422 modrm = ldub(s->pc++);
2423 reg = (modrm >> 3) & 7;
8f186479 2424 mod = (modrm >> 6) & 3;
6dbad63e
FB		 2425 if (reg >= 6)
2426 goto illegal_op;
2427 gen_op_movl_T0_seg(reg);
8f186479
FB		 2428 ot = OT_WORD;
2429 if (mod == 3 && dflag)
2430 ot = OT_LONG;
6dbad63e
FB		 2431 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 1);
2432 break;
367e86e8
FB		 2433
2434 case 0x1b6: /* movzbS Gv, Eb */
2435 case 0x1b7: /* movzwS Gv, Eb */
2436 case 0x1be: /* movsbS Gv, Eb */
2437 case 0x1bf: /* movswS Gv, Eb */
2438 {
2439 int d_ot;
2440 /* d_ot is the size of destination */
2441 d_ot = dflag + OT_WORD;
2442 /* ot is the size of source */
2443 ot = (b & 1) + OT_BYTE;
2444 modrm = ldub(s->pc++);
2445 reg = ((modrm >> 3) & 7) + OR_EAX;
2446 mod = (modrm >> 6) & 3;
2447 rm = modrm & 7;
2448
2449 if (mod == 3) {
2450 gen_op_mov_TN_reg[ot][0][rm]();
2451 switch(ot | (b & 8)) {
2452 case OT_BYTE:
2453 gen_op_movzbl_T0_T0();
2454 break;
2455 case OT_BYTE | 8:
2456 gen_op_movsbl_T0_T0();
2457 break;
2458 case OT_WORD:
2459 gen_op_movzwl_T0_T0();
2460 break;
2461 default:
2462 case OT_WORD | 8:
2463 gen_op_movswl_T0_T0();
2464 break;
2465 }
2466 gen_op_mov_reg_T0[d_ot][reg]();
2467 } else {
2468 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
2469 if (b & 8) {
4021dab0 2470 gen_op_lds_T0_A0[ot + s->mem_index]();
367e86e8 2471 } else {
4021dab0 2472 gen_op_ldu_T0_A0[ot + s->mem_index]();
367e86e8
FB		 2473 }
2474 gen_op_mov_reg_T0[d_ot][reg]();
2475 }
2476 }
2477 break;
2478
2479 case 0x8d: /* lea */
2480 ot = dflag ? OT_LONG : OT_WORD;
2481 modrm = ldub(s->pc++);
2482 reg = (modrm >> 3) & 7;
6dbad63e 2483 /* we must ensure that no segment is added */
9c605cb1 2484 s->override = -1;
6dbad63e
FB		 2485 val = s->addseg;
2486 s->addseg = 0;
367e86e8 2487 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
6dbad63e 2488 s->addseg = val;
367e86e8
FB		 2489 gen_op_mov_reg_A0[ot - OT_WORD][reg]();
2490 break;
2491
2492 case 0xa0: /* mov EAX, Ov */
2493 case 0xa1:
2494 case 0xa2: /* mov Ov, EAX */
2495 case 0xa3:
2496 if ((b & 1) == 0)
2497 ot = OT_BYTE;
2498 else
2499 ot = dflag ? OT_LONG : OT_WORD;
2500 if (s->aflag)
2501 offset_addr = insn_get(s, OT_LONG);
2502 else
2503 offset_addr = insn_get(s, OT_WORD);
4b74fe1f 2504 gen_op_movl_A0_im(offset_addr);
1a9353d2 2505 /* handle override */
1a9353d2
FB		 2506 {
2507 int override, must_add_seg;
1a9353d2 2508 must_add_seg = s->addseg;
9c605cb1
FB		 2509 if (s->override >= 0) {
2510 override = s->override;
1a9353d2 2511 must_add_seg = 1;
9c605cb1
FB		 2512 } else {
2513 override = R_DS;
1a9353d2
FB		 2514 }
2515 if (must_add_seg) {
d8bc1fd0 2516 gen_op_addl_A0_seg(offsetof(CPUX86State,segs[override].base));
1a9353d2
FB		 2517 }
2518 }
367e86e8 2519 if ((b & 2) == 0) {
4021dab0 2520 gen_op_ld_T0_A0[ot + s->mem_index]();
367e86e8
FB		 2521 gen_op_mov_reg_T0[ot][R_EAX]();
2522 } else {
2523 gen_op_mov_TN_reg[ot][0][R_EAX]();
4021dab0 2524 gen_op_st_T0_A0[ot + s->mem_index]();
367e86e8
FB		 2525 }
2526 break;
31bb950b 2527 case 0xd7: /* xlat */
31bb950b
FB		 2528 gen_op_movl_A0_reg[R_EBX]();
2529 gen_op_addl_A0_AL();
2530 if (s->aflag == 0)
2531 gen_op_andl_A0_ffff();
9c605cb1 2532 /* handle override */
31bb950b
FB		 2533 {
2534 int override, must_add_seg;
31bb950b 2535 must_add_seg = s->addseg;
9c605cb1
FB		 2536 override = R_DS;
2537 if (s->override >= 0) {
2538 override = s->override;
31bb950b 2539 must_add_seg = 1;
9c605cb1
FB		 2540 } else {
2541 override = R_DS;
31bb950b
FB		 2542 }
2543 if (must_add_seg) {
d8bc1fd0 2544 gen_op_addl_A0_seg(offsetof(CPUX86State,segs[override].base));
31bb950b
FB		 2545 }
2546 }
4021dab0 2547 gen_op_ldu_T0_A0[OT_BYTE + s->mem_index]();
31bb950b
FB		 2548 gen_op_mov_reg_T0[OT_BYTE][R_EAX]();
2549 break;
367e86e8
FB		 2550 case 0xb0 ... 0xb7: /* mov R, Ib */
2551 val = insn_get(s, OT_BYTE);
ba1c6e37 2552 gen_op_movl_T0_im(val);
367e86e8
FB		 2553 gen_op_mov_reg_T0[OT_BYTE][b & 7]();
2554 break;
2555 case 0xb8 ... 0xbf: /* mov R, Iv */
2556 ot = dflag ? OT_LONG : OT_WORD;
2557 val = insn_get(s, ot);
2558 reg = OR_EAX + (b & 7);
ba1c6e37 2559 gen_op_movl_T0_im(val);
367e86e8
FB		 2560 gen_op_mov_reg_T0[ot][reg]();
2561 break;
2562
2563 case 0x91 ... 0x97: /* xchg R, EAX */
2564 ot = dflag ? OT_LONG : OT_WORD;
2565 reg = b & 7;
1a9353d2
FB		 2566 rm = R_EAX;
2567 goto do_xchg_reg;
367e86e8
FB		 2568 case 0x86:
2569 case 0x87: /* xchg Ev, Gv */
2570 if ((b & 1) == 0)
2571 ot = OT_BYTE;
2572 else
2573 ot = dflag ? OT_LONG : OT_WORD;
2574 modrm = ldub(s->pc++);
2575 reg = (modrm >> 3) & 7;
1a9353d2
FB		 2576 mod = (modrm >> 6) & 3;
2577 if (mod == 3) {
2578 rm = modrm & 7;
2579 do_xchg_reg:
2580 gen_op_mov_TN_reg[ot][0][reg]();
2581 gen_op_mov_TN_reg[ot][1][rm]();
2582 gen_op_mov_reg_T0[ot][rm]();
2583 gen_op_mov_reg_T1[ot][reg]();
2584 } else {
2585 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
2586 gen_op_mov_TN_reg[ot][0][reg]();
31bb950b
FB		 2587 /* for xchg, lock is implicit */
2588 if (!(prefixes & PREFIX_LOCK))
2589 gen_op_lock();
4021dab0
FB		 2590 gen_op_ld_T1_A0[ot + s->mem_index]();
2591 gen_op_st_T0_A0[ot + s->mem_index]();
31bb950b
FB		 2592 if (!(prefixes & PREFIX_LOCK))
2593 gen_op_unlock();
1a9353d2
FB		 2594 gen_op_mov_reg_T1[ot][reg]();
2595 }
367e86e8 2596 break;
6dbad63e
FB		 2597 case 0xc4: /* les Gv */
2598 op = R_ES;
2599 goto do_lxx;
2600 case 0xc5: /* lds Gv */
2601 op = R_DS;
2602 goto do_lxx;
2603 case 0x1b2: /* lss Gv */
2604 op = R_SS;
2605 goto do_lxx;
2606 case 0x1b4: /* lfs Gv */
2607 op = R_FS;
2608 goto do_lxx;
2609 case 0x1b5: /* lgs Gv */
2610 op = R_GS;
2611 do_lxx:
2612 ot = dflag ? OT_LONG : OT_WORD;
2613 modrm = ldub(s->pc++);
2614 reg = (modrm >> 3) & 7;
2615 mod = (modrm >> 6) & 3;
2616 if (mod == 3)
2617 goto illegal_op;
9c605cb1 2618 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
4021dab0 2619 gen_op_ld_T1_A0[ot + s->mem_index]();
dc99065b 2620 gen_op_addl_A0_im(1 << (ot - OT_WORD + 1));
6dbad63e
FB		 2621 /* load the segment first to handle exceptions properly */
2622 gen_op_lduw_T0_A0();
5a91de8c 2623 gen_movl_seg_T0(s, op, pc_start - s->cs_base);
6dbad63e
FB		 2624 /* then put the data */
2625 gen_op_mov_reg_T1[ot][reg]();
dbc5594c
FB		 2626 if (s->is_jmp) {
2627 gen_op_jmp_im(s->pc - s->cs_base);
2628 gen_eob(s);
2629 }
6dbad63e 2630 break;
367e86e8
FB		 2631
2632 /************************/
2633 /* shifts */
2634 case 0xc0:
2635 case 0xc1:
2636 /* shift Ev,Ib */
2637 shift = 2;
2638 grp2:
2639 {
2640 if ((b & 1) == 0)
2641 ot = OT_BYTE;
2642 else
2643 ot = dflag ? OT_LONG : OT_WORD;
2644
2645 modrm = ldub(s->pc++);
2646 mod = (modrm >> 6) & 3;
2647 rm = modrm & 7;
2648 op = (modrm >> 3) & 7;
2649
2650 if (mod != 3) {
2651 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
367e86e8
FB		 2652 opreg = OR_TMP0;
2653 } else {
2654 opreg = rm + OR_EAX;
2655 }
2656
2657 /* simpler op */
2658 if (shift == 0) {
2659 gen_shift(s, op, ot, opreg, OR_ECX);
2660 } else {
2661 if (shift == 2) {
2662 shift = ldub(s->pc++);
2663 }
2664 gen_shifti(s, op, ot, opreg, shift);
2665 }
367e86e8
FB		 2666 }
2667 break;
2668 case 0xd0:
2669 case 0xd1:
2670 /* shift Ev,1 */
2671 shift = 1;
2672 goto grp2;
2673 case 0xd2:
2674 case 0xd3:
2675 /* shift Ev,cl */
2676 shift = 0;
2677 goto grp2;
2678
d57c4e01
FB		 2679 case 0x1a4: /* shld imm */
2680 op = 0;
2681 shift = 1;
2682 goto do_shiftd;
2683 case 0x1a5: /* shld cl */
2684 op = 0;
2685 shift = 0;
2686 goto do_shiftd;
2687 case 0x1ac: /* shrd imm */
2688 op = 1;
2689 shift = 1;
2690 goto do_shiftd;
2691 case 0x1ad: /* shrd cl */
2692 op = 1;
2693 shift = 0;
2694 do_shiftd:
2695 ot = dflag ? OT_LONG : OT_WORD;
2696 modrm = ldub(s->pc++);
2697 mod = (modrm >> 6) & 3;
2698 rm = modrm & 7;
2699 reg = (modrm >> 3) & 7;
2700
2701 if (mod != 3) {
2702 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
4021dab0 2703 gen_op_ld_T0_A0[ot + s->mem_index]();
d57c4e01
FB		 2704 } else {
2705 gen_op_mov_TN_reg[ot][0][rm]();
2706 }
2707 gen_op_mov_TN_reg[ot][1][reg]();
2708
2709 if (shift) {
2710 val = ldub(s->pc++);
2711 val &= 0x1f;
2712 if (val) {
e477b8b8
FB		 2713 if (mod == 3)
2714 gen_op_shiftd_T0_T1_im_cc[ot - OT_WORD][op](val);
2715 else
2716 gen_op_shiftd_mem_T0_T1_im_cc[ot - OT_WORD][op](val);
d57c4e01
FB		 2717 if (op == 0 && ot != OT_WORD)
2718 s->cc_op = CC_OP_SHLB + ot;
2719 else
2720 s->cc_op = CC_OP_SARB + ot;
2721 }
2722 } else {
2723 if (s->cc_op != CC_OP_DYNAMIC)
2724 gen_op_set_cc_op(s->cc_op);
e477b8b8
FB		 2725 if (mod == 3)
2726 gen_op_shiftd_T0_T1_ECX_cc[ot - OT_WORD][op]();
2727 else
2728 gen_op_shiftd_mem_T0_T1_ECX_cc[ot - OT_WORD][op]();
d57c4e01
FB		 2729 s->cc_op = CC_OP_DYNAMIC; /* cannot predict flags after */
2730 }
e477b8b8 2731 if (mod == 3) {
d57c4e01
FB		 2732 gen_op_mov_reg_T0[ot][rm]();
2733 }
2734 break;
2735
367e86e8
FB		 2736 /************************/
2737 /* floats */
367e86e8
FB		 2738 case 0xd8 ... 0xdf:
2739 modrm = ldub(s->pc++);
2740 mod = (modrm >> 6) & 3;
2741 rm = modrm & 7;
2742 op = ((b & 7) << 3) | ((modrm >> 3) & 7);
2743
2744 if (mod != 3) {
2745 /* memory op */
2746 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
2747 switch(op) {
2748 case 0x00 ... 0x07: /* fxxxs */
2749 case 0x10 ... 0x17: /* fixxxl */
2750 case 0x20 ... 0x27: /* fxxxl */
2751 case 0x30 ... 0x37: /* fixxx */
2752 {
927f621e
FB		 2753 int op1;
2754 op1 = op & 7;
367e86e8
FB		 2755
2756 switch(op >> 4) {
2757 case 0:
927f621e 2758 gen_op_flds_FT0_A0();
367e86e8
FB		 2759 break;
2760 case 1:
927f621e 2761 gen_op_fildl_FT0_A0();
367e86e8
FB		 2762 break;
2763 case 2:
927f621e 2764 gen_op_fldl_FT0_A0();
367e86e8
FB		 2765 break;
2766 case 3:
2767 default:
927f621e 2768 gen_op_fild_FT0_A0();
367e86e8
FB		 2769 break;
2770 }
2771
927f621e
FB		 2772 gen_op_fp_arith_ST0_FT0[op1]();
2773 if (op1 == 3) {
367e86e8 2774 /* fcomp needs pop */
927f621e 2775 gen_op_fpop();
367e86e8
FB		 2776 }
2777 }
2778 break;
2779 case 0x08: /* flds */
2780 case 0x0a: /* fsts */
2781 case 0x0b: /* fstps */
2782 case 0x18: /* fildl */
2783 case 0x1a: /* fistl */
2784 case 0x1b: /* fistpl */
2785 case 0x28: /* fldl */
2786 case 0x2a: /* fstl */
2787 case 0x2b: /* fstpl */
2788 case 0x38: /* filds */
2789 case 0x3a: /* fists */
2790 case 0x3b: /* fistps */
2791
367e86e8
FB		 2792 switch(op & 7) {
2793 case 0:
927f621e
FB		 2794 switch(op >> 4) {
2795 case 0:
2796 gen_op_flds_ST0_A0();
2797 break;
2798 case 1:
2799 gen_op_fildl_ST0_A0();
2800 break;
2801 case 2:
2802 gen_op_fldl_ST0_A0();
2803 break;
2804 case 3:
2805 default:
2806 gen_op_fild_ST0_A0();
2807 break;
367e86e8
FB		 2808 }
2809 break;
2810 default:
927f621e
FB		 2811 switch(op >> 4) {
2812 case 0:
2813 gen_op_fsts_ST0_A0();
2814 break;
2815 case 1:
2816 gen_op_fistl_ST0_A0();
2817 break;
2818 case 2:
2819 gen_op_fstl_ST0_A0();
2820 break;
2821 case 3:
2822 default:
2823 gen_op_fist_ST0_A0();
2824 break;
367e86e8
FB		 2825 }
2826 if ((op & 7) == 3)
927f621e 2827 gen_op_fpop();
367e86e8
FB		 2828 break;
2829 }
2830 break;
d0a1ffc9
FB		 2831 case 0x0c: /* fldenv mem */
2832 gen_op_fldenv_A0(s->dflag);
2833 break;
4b74fe1f
FB		 2834 case 0x0d: /* fldcw mem */
2835 gen_op_fldcw_A0();
2836 break;
d0a1ffc9
FB		 2837 case 0x0e: /* fnstenv mem */
2838 gen_op_fnstenv_A0(s->dflag);
2839 break;
4b74fe1f
FB		 2840 case 0x0f: /* fnstcw mem */
2841 gen_op_fnstcw_A0();
2842 break;
77f8dd5a 2843 case 0x1d: /* fldt mem */
77f8dd5a
FB		 2844 gen_op_fldt_ST0_A0();
2845 break;
2846 case 0x1f: /* fstpt mem */
2847 gen_op_fstt_ST0_A0();
2848 gen_op_fpop();
2849 break;
d0a1ffc9
FB		 2850 case 0x2c: /* frstor mem */
2851 gen_op_frstor_A0(s->dflag);
2852 break;
2853 case 0x2e: /* fnsave mem */
2854 gen_op_fnsave_A0(s->dflag);
2855 break;
367e86e8 2856 case 0x2f: /* fnstsw mem */
4b74fe1f 2857 gen_op_fnstsw_A0();
367e86e8 2858 break;
367e86e8 2859 case 0x3c: /* fbld */
1017ebe9 2860 gen_op_fbld_ST0_A0();
77f8dd5a 2861 break;
367e86e8 2862 case 0x3e: /* fbstp */
77f8dd5a
FB		 2863 gen_op_fbst_ST0_A0();
2864 gen_op_fpop();
2865 break;
367e86e8 2866 case 0x3d: /* fildll */
927f621e 2867 gen_op_fildll_ST0_A0();
367e86e8
FB		 2868 break;
2869 case 0x3f: /* fistpll */
927f621e
FB		 2870 gen_op_fistll_ST0_A0();
2871 gen_op_fpop();
367e86e8
FB		 2872 break;
2873 default:
1a9353d2 2874 goto illegal_op;
367e86e8
FB		 2875 }
2876 } else {
2877 /* register float ops */
927f621e 2878 opreg = rm;
367e86e8
FB		 2879
2880 switch(op) {
2881 case 0x08: /* fld sti */
927f621e
FB		 2882 gen_op_fpush();
2883 gen_op_fmov_ST0_STN((opreg + 1) & 7);
367e86e8
FB		 2884 break;
2885 case 0x09: /* fxchg sti */
77f8dd5a 2886 gen_op_fxchg_ST0_STN(opreg);
367e86e8
FB		 2887 break;
2888 case 0x0a: /* grp d9/2 */
2889 switch(rm) {
2890 case 0: /* fnop */
367e86e8
FB		 2891 break;
2892 default:
1a9353d2 2893 goto illegal_op;
367e86e8
FB		 2894 }
2895 break;
2896 case 0x0c: /* grp d9/4 */
2897 switch(rm) {
2898 case 0: /* fchs */
927f621e 2899 gen_op_fchs_ST0();
367e86e8
FB		 2900 break;
2901 case 1: /* fabs */
927f621e 2902 gen_op_fabs_ST0();
367e86e8
FB		 2903 break;
2904 case 4: /* ftst */
927f621e
FB		 2905 gen_op_fldz_FT0();
2906 gen_op_fcom_ST0_FT0();
367e86e8
FB		 2907 break;
2908 case 5: /* fxam */
927f621e 2909 gen_op_fxam_ST0();
367e86e8
FB		 2910 break;
2911 default:
1a9353d2 2912 goto illegal_op;
367e86e8
FB		 2913 }
2914 break;
2915 case 0x0d: /* grp d9/5 */
2916 {
927f621e
FB		 2917 switch(rm) {
2918 case 0:
77f8dd5a 2919 gen_op_fpush();
927f621e
FB		 2920 gen_op_fld1_ST0();
2921 break;
2922 case 1:
77f8dd5a
FB		 2923 gen_op_fpush();
2924 gen_op_fldl2t_ST0();
927f621e
FB		 2925 break;
2926 case 2:
77f8dd5a
FB		 2927 gen_op_fpush();
2928 gen_op_fldl2e_ST0();
927f621e
FB		 2929 break;
2930 case 3:
77f8dd5a 2931 gen_op_fpush();
927f621e
FB		 2932 gen_op_fldpi_ST0();
2933 break;
2934 case 4:
77f8dd5a 2935 gen_op_fpush();
927f621e
FB		 2936 gen_op_fldlg2_ST0();
2937 break;
2938 case 5:
77f8dd5a 2939 gen_op_fpush();
927f621e
FB		 2940 gen_op_fldln2_ST0();
2941 break;
2942 case 6:
77f8dd5a 2943 gen_op_fpush();
927f621e
FB		 2944 gen_op_fldz_ST0();
2945 break;
2946 default:
1a9353d2 2947 goto illegal_op;
367e86e8 2948 }
367e86e8
FB		 2949 }
2950 break;
2951 case 0x0e: /* grp d9/6 */
2952 switch(rm) {
2953 case 0: /* f2xm1 */
927f621e 2954 gen_op_f2xm1();
367e86e8
FB		 2955 break;
2956 case 1: /* fyl2x */
927f621e 2957 gen_op_fyl2x();
367e86e8
FB		 2958 break;
2959 case 2: /* fptan */
927f621e 2960 gen_op_fptan();
367e86e8
FB		 2961 break;
2962 case 3: /* fpatan */
927f621e 2963 gen_op_fpatan();
367e86e8
FB		 2964 break;
2965 case 4: /* fxtract */
927f621e 2966 gen_op_fxtract();
367e86e8
FB		 2967 break;
2968 case 5: /* fprem1 */
927f621e 2969 gen_op_fprem1();
367e86e8
FB		 2970 break;
2971 case 6: /* fdecstp */
927f621e 2972 gen_op_fdecstp();
367e86e8
FB		 2973 break;
2974 default:
927f621e
FB		 2975 case 7: /* fincstp */
2976 gen_op_fincstp();
367e86e8
FB		 2977 break;
2978 }
2979 break;
2980 case 0x0f: /* grp d9/7 */
2981 switch(rm) {
2982 case 0: /* fprem */
927f621e 2983 gen_op_fprem();
367e86e8
FB		 2984 break;
2985 case 1: /* fyl2xp1 */
927f621e
FB		 2986 gen_op_fyl2xp1();
2987 break;
2988 case 2: /* fsqrt */
2989 gen_op_fsqrt();
367e86e8
FB		 2990 break;
2991 case 3: /* fsincos */
927f621e 2992 gen_op_fsincos();
367e86e8
FB		 2993 break;
2994 case 5: /* fscale */
927f621e 2995 gen_op_fscale();
367e86e8 2996 break;
367e86e8 2997 case 4: /* frndint */
927f621e
FB		 2998 gen_op_frndint();
2999 break;
367e86e8 3000 case 6: /* fsin */
927f621e
FB		 3001 gen_op_fsin();
3002 break;
367e86e8
FB		 3003 default:
3004 case 7: /* fcos */
927f621e 3005 gen_op_fcos();
367e86e8
FB		 3006 break;
3007 }
3008 break;
3009 case 0x00: case 0x01: case 0x04 ... 0x07: /* fxxx st, sti */
3010 case 0x20: case 0x21: case 0x24 ... 0x27: /* fxxx sti, st */
3011 case 0x30: case 0x31: case 0x34 ... 0x37: /* fxxxp sti, st */
3012 {
927f621e 3013 int op1;
367e86e8 3014
927f621e 3015 op1 = op & 7;
367e86e8 3016 if (op >= 0x20) {
927f621e 3017 gen_op_fp_arith_STN_ST0[op1](opreg);
77f8dd5a
FB		 3018 if (op >= 0x30)
3019 gen_op_fpop();
367e86e8 3020 } else {
927f621e
FB		 3021 gen_op_fmov_FT0_STN(opreg);
3022 gen_op_fp_arith_ST0_FT0[op1]();
367e86e8 3023 }
367e86e8
FB		 3024 }
3025 break;
3026 case 0x02: /* fcom */
927f621e
FB		 3027 gen_op_fmov_FT0_STN(opreg);
3028 gen_op_fcom_ST0_FT0();
367e86e8
FB		 3029 break;
3030 case 0x03: /* fcomp */
927f621e
FB		 3031 gen_op_fmov_FT0_STN(opreg);
3032 gen_op_fcom_ST0_FT0();
3033 gen_op_fpop();
367e86e8
FB		 3034 break;
3035 case 0x15: /* da/5 */
3036 switch(rm) {
3037 case 1: /* fucompp */
927f621e 3038 gen_op_fmov_FT0_STN(1);
77f8dd5a 3039 gen_op_fucom_ST0_FT0();
927f621e
FB		 3040 gen_op_fpop();
3041 gen_op_fpop();
367e86e8
FB		 3042 break;
3043 default:
1a9353d2
FB		 3044 goto illegal_op;
3045 }
3046 break;
3047 case 0x1c:
3048 switch(rm) {
d8bc1fd0
FB		 3049 case 0: /* feni (287 only, just do nop here) */
3050 break;
3051 case 1: /* fdisi (287 only, just do nop here) */
3052 break;
1a9353d2
FB		 3053 case 2: /* fclex */
3054 gen_op_fclex();
3055 break;
3056 case 3: /* fninit */
3057 gen_op_fninit();
3058 break;
d8bc1fd0
FB		 3059 case 4: /* fsetpm (287 only, just do nop here) */
3060 break;
1a9353d2
FB		 3061 default:
3062 goto illegal_op;
367e86e8
FB		 3063 }
3064 break;
d0a1ffc9
FB		 3065 case 0x1d: /* fucomi */
3066 if (s->cc_op != CC_OP_DYNAMIC)
3067 gen_op_set_cc_op(s->cc_op);
3068 gen_op_fmov_FT0_STN(opreg);
3069 gen_op_fucomi_ST0_FT0();
3070 s->cc_op = CC_OP_EFLAGS;
3071 break;
3072 case 0x1e: /* fcomi */
3073 if (s->cc_op != CC_OP_DYNAMIC)
3074 gen_op_set_cc_op(s->cc_op);
3075 gen_op_fmov_FT0_STN(opreg);
3076 gen_op_fcomi_ST0_FT0();
3077 s->cc_op = CC_OP_EFLAGS;
3078 break;
367e86e8 3079 case 0x2a: /* fst sti */
927f621e 3080 gen_op_fmov_STN_ST0(opreg);
367e86e8
FB		 3081 break;
3082 case 0x2b: /* fstp sti */
927f621e
FB		 3083 gen_op_fmov_STN_ST0(opreg);
3084 gen_op_fpop();
367e86e8 3085 break;
77f8dd5a
FB		 3086 case 0x2c: /* fucom st(i) */
3087 gen_op_fmov_FT0_STN(opreg);
3088 gen_op_fucom_ST0_FT0();
3089 break;
3090 case 0x2d: /* fucomp st(i) */
3091 gen_op_fmov_FT0_STN(opreg);
3092 gen_op_fucom_ST0_FT0();
3093 gen_op_fpop();
3094 break;
367e86e8
FB		 3095 case 0x33: /* de/3 */
3096 switch(rm) {
3097 case 1: /* fcompp */
927f621e
FB		 3098 gen_op_fmov_FT0_STN(1);
3099 gen_op_fcom_ST0_FT0();
3100 gen_op_fpop();
3101 gen_op_fpop();
367e86e8
FB		 3102 break;
3103 default:
1a9353d2 3104 goto illegal_op;
367e86e8
FB		 3105 }
3106 break;
3107 case 0x3c: /* df/4 */
3108 switch(rm) {
3109 case 0:
77f8dd5a 3110 gen_op_fnstsw_EAX();
367e86e8
FB		 3111 break;
3112 default:
1a9353d2 3113 goto illegal_op;
367e86e8
FB		 3114 }
3115 break;
d0a1ffc9
FB		 3116 case 0x3d: /* fucomip */
3117 if (s->cc_op != CC_OP_DYNAMIC)
3118 gen_op_set_cc_op(s->cc_op);
3119 gen_op_fmov_FT0_STN(opreg);
3120 gen_op_fucomi_ST0_FT0();
3121 gen_op_fpop();
3122 s->cc_op = CC_OP_EFLAGS;
3123 break;
3124 case 0x3e: /* fcomip */
3125 if (s->cc_op != CC_OP_DYNAMIC)
3126 gen_op_set_cc_op(s->cc_op);
3127 gen_op_fmov_FT0_STN(opreg);
3128 gen_op_fcomi_ST0_FT0();
3129 gen_op_fpop();
3130 s->cc_op = CC_OP_EFLAGS;
3131 break;
367e86e8 3132 default:
1a9353d2 3133 goto illegal_op;
367e86e8
FB		 3134 }
3135 }
3136 break;
367e86e8
FB		 3137 /************************/
3138 /* string ops */
9c605cb1 3139
367e86e8
FB		 3140 case 0xa4: /* movsS */
3141 case 0xa5:
3142 if ((b & 1) == 0)
3143 ot = OT_BYTE;
3144 else
3145 ot = dflag ? OT_LONG : OT_WORD;
9c605cb1 3146
2c1794c4 3147 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) {
4021dab0 3148 gen_repz_movs(s, ot, pc_start - s->cs_base, s->pc - s->cs_base);
367e86e8 3149 } else {
4021dab0 3150 gen_movs(s, ot);
367e86e8
FB		 3151 }
3152 break;
3153
3154 case 0xaa: /* stosS */
3155 case 0xab:
3156 if ((b & 1) == 0)
3157 ot = OT_BYTE;
3158 else
3159 ot = dflag ? OT_LONG : OT_WORD;
9c605cb1 3160
2c1794c4 3161 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) {
4021dab0 3162 gen_repz_stos(s, ot, pc_start - s->cs_base, s->pc - s->cs_base);
367e86e8 3163 } else {
4021dab0 3164 gen_stos(s, ot);
367e86e8
FB		 3165 }
3166 break;
3167 case 0xac: /* lodsS */
3168 case 0xad:
3169 if ((b & 1) == 0)
3170 ot = OT_BYTE;
3171 else
3172 ot = dflag ? OT_LONG : OT_WORD;
2c1794c4 3173 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) {
4021dab0 3174 gen_repz_lods(s, ot, pc_start - s->cs_base, s->pc - s->cs_base);
367e86e8 3175 } else {
4021dab0 3176 gen_lods(s, ot);
367e86e8
FB		 3177 }
3178 break;
3179 case 0xae: /* scasS */
3180 case 0xaf:
3181 if ((b & 1) == 0)
3182 ot = OT_BYTE;
3183 else
9c605cb1 3184 ot = dflag ? OT_LONG : OT_WORD;
367e86e8 3185 if (prefixes & PREFIX_REPNZ) {
dbc5594c 3186 gen_repz_scas(s, ot, pc_start - s->cs_base, s->pc - s->cs_base, 1);
367e86e8 3187 } else if (prefixes & PREFIX_REPZ) {
dbc5594c 3188 gen_repz_scas(s, ot, pc_start - s->cs_base, s->pc - s->cs_base, 0);
367e86e8 3189 } else {
4021dab0 3190 gen_scas(s, ot);
4b74fe1f 3191 s->cc_op = CC_OP_SUBB + ot;
367e86e8
FB		 3192 }
3193 break;
3194
3195 case 0xa6: /* cmpsS */
3196 case 0xa7:
3197 if ((b & 1) == 0)
3198 ot = OT_BYTE;
3199 else
3200 ot = dflag ? OT_LONG : OT_WORD;
3201 if (prefixes & PREFIX_REPNZ) {
dbc5594c 3202 gen_repz_cmps(s, ot, pc_start - s->cs_base, s->pc - s->cs_base, 1);
367e86e8 3203 } else if (prefixes & PREFIX_REPZ) {
dbc5594c 3204 gen_repz_cmps(s, ot, pc_start - s->cs_base, s->pc - s->cs_base, 0);
367e86e8 3205 } else {
4021dab0 3206 gen_cmps(s, ot);
4b74fe1f 3207 s->cc_op = CC_OP_SUBB + ot;
367e86e8
FB		 3208 }
3209 break;
367e86e8
FB		 3210 case 0x6c: /* insS */
3211 case 0x6d:
8f186479 3212 if (s->pe && (s->cpl > s->iopl || s->vm86)) {
982b4315 3213 /* NOTE: even for (E)CX = 0 the exception is raised */
c50c0c3f 3214 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
367e86e8 3215 } else {
982b4315
FB		 3216 if ((b & 1) == 0)
3217 ot = OT_BYTE;
3218 else
3219 ot = dflag ? OT_LONG : OT_WORD;
2c1794c4 3220 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) {
4021dab0 3221 gen_repz_ins(s, ot, pc_start - s->cs_base, s->pc - s->cs_base);
982b4315 3222 } else {
4021dab0 3223 gen_ins(s, ot);
982b4315 3224 }
367e86e8
FB		 3225 }
3226 break;
3227 case 0x6e: /* outsS */
3228 case 0x6f:
8f186479 3229 if (s->pe && (s->cpl > s->iopl || s->vm86)) {
982b4315 3230 /* NOTE: even for (E)CX = 0 the exception is raised */
c50c0c3f 3231 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
367e86e8 3232 } else {
982b4315
FB		 3233 if ((b & 1) == 0)
3234 ot = OT_BYTE;
3235 else
3236 ot = dflag ? OT_LONG : OT_WORD;
2c1794c4 3237 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) {
4021dab0 3238 gen_repz_outs(s, ot, pc_start - s->cs_base, s->pc - s->cs_base);
982b4315 3239 } else {
4021dab0 3240 gen_outs(s, ot);
982b4315 3241 }
367e86e8
FB		 3242 }
3243 break;
9c605cb1
FB		 3244
3245 /************************/
3246 /* port I/O */
ba1c6e37
FB		 3247 case 0xe4:
3248 case 0xe5:
8f186479 3249 if (s->pe && (s->cpl > s->iopl || s->vm86)) {
c50c0c3f 3250 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
982b4315
FB		 3251 } else {
3252 if ((b & 1) == 0)
3253 ot = OT_BYTE;
3254 else
3255 ot = dflag ? OT_LONG : OT_WORD;
3256 val = ldub(s->pc++);
3257 gen_op_movl_T0_im(val);
3258 gen_op_in[ot]();
3259 gen_op_mov_reg_T1[ot][R_EAX]();
3260 }
ba1c6e37
FB		 3261 break;
3262 case 0xe6:
3263 case 0xe7:
8f186479 3264 if (s->pe && (s->cpl > s->iopl || s->vm86)) {
c50c0c3f 3265 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
982b4315
FB		 3266 } else {
3267 if ((b & 1) == 0)
3268 ot = OT_BYTE;
3269 else
3270 ot = dflag ? OT_LONG : OT_WORD;
3271 val = ldub(s->pc++);
3272 gen_op_movl_T0_im(val);
3273 gen_op_mov_TN_reg[ot][1][R_EAX]();
3274 gen_op_out[ot]();
3275 }
ba1c6e37
FB		 3276 break;
3277 case 0xec:
3278 case 0xed:
8f186479 3279 if (s->pe && (s->cpl > s->iopl || s->vm86)) {
c50c0c3f 3280 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
982b4315
FB		 3281 } else {
3282 if ((b & 1) == 0)
3283 ot = OT_BYTE;
3284 else
3285 ot = dflag ? OT_LONG : OT_WORD;
3286 gen_op_mov_TN_reg[OT_WORD][0][R_EDX]();
3287 gen_op_in[ot]();
3288 gen_op_mov_reg_T1[ot][R_EAX]();
3289 }
ba1c6e37
FB		 3290 break;
3291 case 0xee:
3292 case 0xef:
8f186479 3293 if (s->pe && (s->cpl > s->iopl || s->vm86)) {
c50c0c3f 3294 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
982b4315
FB		 3295 } else {
3296 if ((b & 1) == 0)
3297 ot = OT_BYTE;
3298 else
3299 ot = dflag ? OT_LONG : OT_WORD;
3300 gen_op_mov_TN_reg[OT_WORD][0][R_EDX]();
3301 gen_op_mov_TN_reg[ot][1][R_EAX]();
3302 gen_op_out[ot]();
3303 }
ba1c6e37 3304 break;
367e86e8
FB		 3305
3306 /************************/
3307 /* control */
3308 case 0xc2: /* ret im */
367e86e8
FB		 3309 val = ldsw(s->pc);
3310 s->pc += 2;
dab2ed99 3311 gen_pop_T0(s);
d0a1ffc9 3312 gen_stack_update(s, val + (2 << s->dflag));
dab2ed99
FB		 3313 if (s->dflag == 0)
3314 gen_op_andl_T0_ffff();
367e86e8 3315 gen_op_jmp_T0();
dbc5594c 3316 gen_eob(s);
367e86e8
FB		 3317 break;
3318 case 0xc3: /* ret */
dab2ed99
FB		 3319 gen_pop_T0(s);
3320 gen_pop_update(s);
3321 if (s->dflag == 0)
3322 gen_op_andl_T0_ffff();
367e86e8 3323 gen_op_jmp_T0();
dbc5594c 3324 gen_eob(s);
367e86e8 3325 break;
dab2ed99
FB		 3326 case 0xca: /* lret im */
3327 val = ldsw(s->pc);
3328 s->pc += 2;
d0a1ffc9 3329 do_lret:
2c1794c4
FB		 3330 if (s->pe && !s->vm86) {
3331 if (s->cc_op != CC_OP_DYNAMIC)
3332 gen_op_set_cc_op(s->cc_op);
3333 gen_op_jmp_im(pc_start - s->cs_base);
3334 gen_op_lret_protected(s->dflag, val);
3335 } else {
3336 gen_stack_A0(s);
3337 /* pop offset */
4021dab0 3338 gen_op_ld_T0_A0[1 + s->dflag + s->mem_index]();
2c1794c4
FB		 3339 if (s->dflag == 0)
3340 gen_op_andl_T0_ffff();
3341 /* NOTE: keeping EIP updated is not a problem in case of
3342 exception */
3343 gen_op_jmp_T0();
3344 /* pop selector */
3345 gen_op_addl_A0_im(2 << s->dflag);
4021dab0 3346 gen_op_ld_T0_A0[1 + s->dflag + s->mem_index]();
2c1794c4
FB		 3347 gen_op_movl_seg_T0_vm(offsetof(CPUX86State,segs[R_CS]));
3348 /* add stack offset */
3349 gen_stack_update(s, val + (4 << s->dflag));
3350 }
dbc5594c 3351 gen_eob(s);
dab2ed99
FB		 3352 break;
3353 case 0xcb: /* lret */
d0a1ffc9
FB		 3354 val = 0;
3355 goto do_lret;
f631ef9b 3356 case 0xcf: /* iret */
8f186479
FB		 3357 if (!s->pe) {
3358 /* real mode */
3359 gen_op_iret_real(s->dflag);
3360 s->cc_op = CC_OP_EFLAGS;
3361 } else if (s->vm86 && s->iopl != 3) {
c50c0c3f 3362 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
f631ef9b 3363 } else {
717fc2ad
FB		 3364 if (s->cc_op != CC_OP_DYNAMIC)
3365 gen_op_set_cc_op(s->cc_op);
3366 gen_op_jmp_im(pc_start - s->cs_base);
3367 gen_op_iret_protected(s->dflag);
148dfc2a 3368 s->cc_op = CC_OP_EFLAGS;
f631ef9b 3369 }
dbc5594c 3370 gen_eob(s);
f631ef9b 3371 break;
dab2ed99
FB		 3372 case 0xe8: /* call im */
3373 {
3374 unsigned int next_eip;
3375 ot = dflag ? OT_LONG : OT_WORD;
3376 val = insn_get(s, ot);
3377 next_eip = s->pc - s->cs_base;
3378 val += next_eip;
3379 if (s->dflag == 0)
3380 val &= 0xffff;
3381 gen_op_movl_T0_im(next_eip);
3382 gen_push_T0(s);
d4e8164f 3383 gen_jmp(s, val);
dab2ed99
FB		 3384 }
3385 break;
3386 case 0x9a: /* lcall im */
3387 {
3388 unsigned int selector, offset;
3389
3390 ot = dflag ? OT_LONG : OT_WORD;
3391 offset = insn_get(s, ot);
3392 selector = insn_get(s, OT_WORD);
3393
dab2ed99 3394 gen_op_movl_T0_im(selector);
2c1794c4 3395 gen_op_movl_T1_im(offset);
dab2ed99 3396 }
2c1794c4 3397 goto do_lcall;
367e86e8 3398 case 0xe9: /* jmp */
dab2ed99
FB		 3399 ot = dflag ? OT_LONG : OT_WORD;
3400 val = insn_get(s, ot);
3401 val += s->pc - s->cs_base;
3402 if (s->dflag == 0)
3403 val = val & 0xffff;
d4e8164f 3404 gen_jmp(s, val);
367e86e8 3405 break;
dab2ed99
FB		 3406 case 0xea: /* ljmp im */
3407 {
3408 unsigned int selector, offset;
3409
3410 ot = dflag ? OT_LONG : OT_WORD;
3411 offset = insn_get(s, ot);
3412 selector = insn_get(s, OT_WORD);
3413
dab2ed99 3414 gen_op_movl_T0_im(selector);
2c1794c4 3415 gen_op_movl_T1_im(offset);
dab2ed99 3416 }
2c1794c4 3417 goto do_ljmp;
367e86e8
FB		 3418 case 0xeb: /* jmp Jb */
3419 val = (int8_t)insn_get(s, OT_BYTE);
dab2ed99
FB		 3420 val += s->pc - s->cs_base;
3421 if (s->dflag == 0)
3422 val = val & 0xffff;
d4e8164f 3423 gen_jmp(s, val);
367e86e8
FB		 3424 break;
3425 case 0x70 ... 0x7f: /* jcc Jb */
3426 val = (int8_t)insn_get(s, OT_BYTE);
367e86e8
FB		 3427 goto do_jcc;
3428 case 0x180 ... 0x18f: /* jcc Jv */
3429 if (dflag) {
3430 val = insn_get(s, OT_LONG);
3431 } else {
3432 val = (int16_t)insn_get(s, OT_WORD);
3433 }
367e86e8 3434 do_jcc:
dab2ed99
FB		 3435 next_eip = s->pc - s->cs_base;
3436 val += next_eip;
3437 if (s->dflag == 0)
3438 val &= 0xffff;
3439 gen_jcc(s, b, val, next_eip);
367e86e8
FB		 3440 break;
3441
5dd9488c 3442 case 0x190 ... 0x19f: /* setcc Gv */
367e86e8
FB		 3443 modrm = ldub(s->pc++);
3444 gen_setcc(s, b);
3445 gen_ldst_modrm(s, modrm, OT_BYTE, OR_TMP0, 1);
3446 break;
5dd9488c
FB		 3447 case 0x140 ... 0x14f: /* cmov Gv, Ev */
3448 ot = dflag ? OT_LONG : OT_WORD;
3449 modrm = ldub(s->pc++);
3450 reg = (modrm >> 3) & 7;
3451 mod = (modrm >> 6) & 3;
3452 gen_setcc(s, b);
3453 if (mod != 3) {
3454 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
4021dab0 3455 gen_op_ld_T1_A0[ot + s->mem_index]();
5dd9488c
FB		 3456 } else {
3457 rm = modrm & 7;
3458 gen_op_mov_TN_reg[ot][1][rm]();
3459 }
3460 gen_op_cmov_reg_T1_T0[ot - OT_WORD][reg]();
3461 break;
3462
367e86e8
FB		 3463 /************************/
3464 /* flags */
3465 case 0x9c: /* pushf */
148dfc2a 3466 if (s->vm86 && s->iopl != 3) {
c50c0c3f 3467 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
148dfc2a
FB		 3468 } else {
3469 if (s->cc_op != CC_OP_DYNAMIC)
3470 gen_op_set_cc_op(s->cc_op);
f631ef9b 3471 gen_op_movl_T0_eflags();
148dfc2a
FB		 3472 gen_push_T0(s);
3473 }
367e86e8
FB		 3474 break;
3475 case 0x9d: /* popf */
148dfc2a 3476 if (s->vm86 && s->iopl != 3) {
c50c0c3f 3477 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
f631ef9b 3478 } else {
148dfc2a 3479 gen_pop_T0(s);
717fc2ad
FB		 3480 if (s->cpl == 0) {
3481 if (s->dflag) {
3482 gen_op_movl_eflags_T0_cpl0();
3483 } else {
3484 gen_op_movw_eflags_T0_cpl0();
3485 }
148dfc2a 3486 } else {
717fc2ad
FB		 3487 if (s->dflag) {
3488 gen_op_movl_eflags_T0();
3489 } else {
3490 gen_op_movw_eflags_T0();
3491 }
148dfc2a
FB		 3492 }
3493 gen_pop_update(s);
3494 s->cc_op = CC_OP_EFLAGS;
dbc5594c
FB		 3495 /* abort translation because TF flag may change */
3496 gen_op_jmp_im(s->pc - s->cs_base);
3497 gen_eob(s);
f631ef9b 3498 }
367e86e8
FB		 3499 break;
3500 case 0x9e: /* sahf */
3501 gen_op_mov_TN_reg[OT_BYTE][0][R_AH]();
3502 if (s->cc_op != CC_OP_DYNAMIC)
1017ebe9 3503 gen_op_set_cc_op(s->cc_op);
367e86e8
FB		 3504 gen_op_movb_eflags_T0();
3505 s->cc_op = CC_OP_EFLAGS;
3506 break;
3507 case 0x9f: /* lahf */
3508 if (s->cc_op != CC_OP_DYNAMIC)
1017ebe9 3509 gen_op_set_cc_op(s->cc_op);
367e86e8
FB		 3510 gen_op_movl_T0_eflags();
3511 gen_op_mov_reg_T0[OT_BYTE][R_AH]();
3512 break;
3513 case 0xf5: /* cmc */
3514 if (s->cc_op != CC_OP_DYNAMIC)
1017ebe9 3515 gen_op_set_cc_op(s->cc_op);
367e86e8
FB		 3516 gen_op_cmc();
3517 s->cc_op = CC_OP_EFLAGS;
3518 break;
3519 case 0xf8: /* clc */
3520 if (s->cc_op != CC_OP_DYNAMIC)
1017ebe9 3521 gen_op_set_cc_op(s->cc_op);
367e86e8
FB		 3522 gen_op_clc();
3523 s->cc_op = CC_OP_EFLAGS;
3524 break;
3525 case 0xf9: /* stc */
3526 if (s->cc_op != CC_OP_DYNAMIC)
1017ebe9 3527 gen_op_set_cc_op(s->cc_op);
367e86e8
FB		 3528 gen_op_stc();
3529 s->cc_op = CC_OP_EFLAGS;
3530 break;
3531 case 0xfc: /* cld */
3532 gen_op_cld();
3533 break;
3534 case 0xfd: /* std */
3535 gen_op_std();
3536 break;
3537
4b74fe1f
FB		 3538 /************************/
3539 /* bit operations */
3540 case 0x1ba: /* bt/bts/btr/btc Gv, im */
3541 ot = dflag ? OT_LONG : OT_WORD;
3542 modrm = ldub(s->pc++);
3543 op = (modrm >> 3) & 7;
3544 mod = (modrm >> 6) & 3;
3545 rm = modrm & 7;
3546 if (mod != 3) {
3547 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
4021dab0 3548 gen_op_ld_T0_A0[ot + s->mem_index]();
4b74fe1f
FB		 3549 } else {
3550 gen_op_mov_TN_reg[ot][0][rm]();
3551 }
3552 /* load shift */
3553 val = ldub(s->pc++);
3554 gen_op_movl_T1_im(val);
3555 if (op < 4)
1a9353d2 3556 goto illegal_op;
4b74fe1f
FB		 3557 op -= 4;
3558 gen_op_btx_T0_T1_cc[ot - OT_WORD][op]();
d57c4e01 3559 s->cc_op = CC_OP_SARB + ot;
4b74fe1f
FB		 3560 if (op != 0) {
3561 if (mod != 3)
4021dab0 3562 gen_op_st_T0_A0[ot + s->mem_index]();
4b74fe1f
FB		 3563 else
3564 gen_op_mov_reg_T0[ot][rm]();
e477b8b8 3565 gen_op_update_bt_cc();
4b74fe1f
FB		 3566 }
3567 break;
3568 case 0x1a3: /* bt Gv, Ev */
3569 op = 0;
3570 goto do_btx;
3571 case 0x1ab: /* bts */
3572 op = 1;
3573 goto do_btx;
3574 case 0x1b3: /* btr */
3575 op = 2;
3576 goto do_btx;
3577 case 0x1bb: /* btc */
3578 op = 3;
3579 do_btx:
3580 ot = dflag ? OT_LONG : OT_WORD;
3581 modrm = ldub(s->pc++);
3582 reg = (modrm >> 3) & 7;
3583 mod = (modrm >> 6) & 3;
3584 rm = modrm & 7;
3585 gen_op_mov_TN_reg[OT_LONG][1][reg]();
3586 if (mod != 3) {
3587 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3588 /* specific case: we need to add a displacement */
3589 if (ot == OT_WORD)
3590 gen_op_add_bitw_A0_T1();
3591 else
3592 gen_op_add_bitl_A0_T1();
4021dab0 3593 gen_op_ld_T0_A0[ot + s->mem_index]();
4b74fe1f
FB		 3594 } else {
3595 gen_op_mov_TN_reg[ot][0][rm]();
3596 }
3597 gen_op_btx_T0_T1_cc[ot - OT_WORD][op]();
d57c4e01 3598 s->cc_op = CC_OP_SARB + ot;
4b74fe1f
FB		 3599 if (op != 0) {
3600 if (mod != 3)
4021dab0 3601 gen_op_st_T0_A0[ot + s->mem_index]();
4b74fe1f
FB		 3602 else
3603 gen_op_mov_reg_T0[ot][rm]();
e477b8b8 3604 gen_op_update_bt_cc();
4b74fe1f
FB		 3605 }
3606 break;
77f8dd5a
FB		 3607 case 0x1bc: /* bsf */
3608 case 0x1bd: /* bsr */
3609 ot = dflag ? OT_LONG : OT_WORD;
3610 modrm = ldub(s->pc++);
3611 reg = (modrm >> 3) & 7;
3612 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
3613 gen_op_bsx_T0_cc[ot - OT_WORD][b & 1]();
3614 /* NOTE: we always write back the result. Intel doc says it is
3615 undefined if T0 == 0 */
3616 gen_op_mov_reg_T0[ot][reg]();
3617 s->cc_op = CC_OP_LOGICB + ot;
3618 break;
367e86e8 3619 /************************/
27362c82
FB		 3620 /* bcd */
3621 case 0x27: /* daa */
3622 if (s->cc_op != CC_OP_DYNAMIC)
3623 gen_op_set_cc_op(s->cc_op);
3624 gen_op_daa();
3625 s->cc_op = CC_OP_EFLAGS;
3626 break;
3627 case 0x2f: /* das */
3628 if (s->cc_op != CC_OP_DYNAMIC)
3629 gen_op_set_cc_op(s->cc_op);
3630 gen_op_das();
3631 s->cc_op = CC_OP_EFLAGS;
3632 break;
3633 case 0x37: /* aaa */
3634 if (s->cc_op != CC_OP_DYNAMIC)
3635 gen_op_set_cc_op(s->cc_op);
3636 gen_op_aaa();
3637 s->cc_op = CC_OP_EFLAGS;
3638 break;
3639 case 0x3f: /* aas */
3640 if (s->cc_op != CC_OP_DYNAMIC)
3641 gen_op_set_cc_op(s->cc_op);
3642 gen_op_aas();
3643 s->cc_op = CC_OP_EFLAGS;
3644 break;
3645 case 0xd4: /* aam */
3646 val = ldub(s->pc++);
3647 gen_op_aam(val);
3648 s->cc_op = CC_OP_LOGICB;
3649 break;
3650 case 0xd5: /* aad */
3651 val = ldub(s->pc++);
3652 gen_op_aad(val);
3653 s->cc_op = CC_OP_LOGICB;
3654 break;
3655 /************************/
367e86e8
FB		 3656 /* misc */
3657 case 0x90: /* nop */
3658 break;
a37904dd
FB		 3659 case 0x9b: /* fwait */
3660 break;
0ecfa993 3661 case 0xcc: /* int3 */
5a91de8c 3662 gen_interrupt(s, EXCP03_INT3, pc_start - s->cs_base, s->pc - s->cs_base);
0ecfa993
FB		 3663 break;
3664 case 0xcd: /* int N */
3665 val = ldub(s->pc++);
5a91de8c
FB		 3666 /* XXX: add error code for vm86 GPF */
3667 if (!s->vm86)
3668 gen_interrupt(s, val, pc_start - s->cs_base, s->pc - s->cs_base);
3669 else
3670 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
0ecfa993
FB		 3671 break;
3672 case 0xce: /* into */
3673 if (s->cc_op != CC_OP_DYNAMIC)
3674 gen_op_set_cc_op(s->cc_op);
78c34e98 3675 gen_op_into(s->pc - s->cs_base);
9c605cb1 3676 break;
8a4c1cc4
FB		 3677 case 0xf1: /* icebp (undocumented, exits to external debugger) */
3678 gen_debug(s, pc_start - s->cs_base);
3679 break;
f631ef9b 3680 case 0xfa: /* cli */
982b4315 3681 if (!s->vm86) {
148dfc2a 3682 if (s->cpl <= s->iopl) {
982b4315 3683 gen_op_cli();
148dfc2a 3684 } else {
c50c0c3f 3685 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
148dfc2a 3686 }
982b4315 3687 } else {
148dfc2a 3688 if (s->iopl == 3) {
982b4315 3689 gen_op_cli();
148dfc2a 3690 } else {
c50c0c3f 3691 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
148dfc2a 3692 }
982b4315 3693 }
f631ef9b
FB		 3694 break;
3695 case 0xfb: /* sti */
982b4315 3696 if (!s->vm86) {
148dfc2a 3697 if (s->cpl <= s->iopl) {
dbc5594c 3698 gen_sti:
982b4315 3699 gen_op_sti();
3f337316
FB		 3700 /* interruptions are enabled only the first insn after sti */
3701 gen_op_set_inhibit_irq();
dbc5594c
FB		 3702 /* give a chance to handle pending irqs */
3703 gen_op_jmp_im(s->pc - s->cs_base);
3704 gen_eob(s);
148dfc2a 3705 } else {
c50c0c3f 3706 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
148dfc2a 3707 }
982b4315 3708 } else {
148dfc2a 3709 if (s->iopl == 3) {
dbc5594c 3710 goto gen_sti;
148dfc2a 3711 } else {
c50c0c3f 3712 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
148dfc2a 3713 }
982b4315 3714 }
f631ef9b 3715 break;
9c605cb1
FB		 3716 case 0x62: /* bound */
3717 ot = dflag ? OT_LONG : OT_WORD;
3718 modrm = ldub(s->pc++);
3719 reg = (modrm >> 3) & 7;
3720 mod = (modrm >> 6) & 3;
3721 if (mod == 3)
3722 goto illegal_op;
3723 gen_op_mov_reg_T0[ot][reg]();
3724 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3725 if (ot == OT_WORD)
5a91de8c 3726 gen_op_boundw(pc_start - s->cs_base);
9c605cb1 3727 else
5a91de8c 3728 gen_op_boundl(pc_start - s->cs_base);
0ecfa993 3729 break;
4b74fe1f 3730 case 0x1c8 ... 0x1cf: /* bswap reg */
27362c82
FB		 3731 reg = b & 7;
3732 gen_op_mov_TN_reg[OT_LONG][0][reg]();
3733 gen_op_bswapl_T0();
3734 gen_op_mov_reg_T0[OT_LONG][reg]();
3735 break;
3736 case 0xd6: /* salc */
3737 if (s->cc_op != CC_OP_DYNAMIC)
3738 gen_op_set_cc_op(s->cc_op);
3739 gen_op_salc();
3740 break;
1a9353d2
FB		 3741 case 0xe0: /* loopnz */
3742 case 0xe1: /* loopz */
3743 if (s->cc_op != CC_OP_DYNAMIC)
3744 gen_op_set_cc_op(s->cc_op);
3745 /* FALL THRU */
3746 case 0xe2: /* loop */
3747 case 0xe3: /* jecxz */
3748 val = (int8_t)insn_get(s, OT_BYTE);
dab2ed99
FB		 3749 next_eip = s->pc - s->cs_base;
3750 val += next_eip;
3751 if (s->dflag == 0)
3752 val &= 0xffff;
3753 gen_op_loop[s->aflag][b & 3](val, next_eip);
dbc5594c 3754 gen_eob(s);
1a9353d2 3755 break;
3c1cf9fa
FB		 3756 case 0x130: /* wrmsr */
3757 case 0x132: /* rdmsr */
3758 if (s->cpl != 0) {
3759 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
3760 } else {
3761 if (b & 2)
3762 gen_op_rdmsr();
3763 else
3764 gen_op_wrmsr();
3765 }
3766 break;
5dd9488c 3767 case 0x131: /* rdtsc */
27362c82
FB		 3768 gen_op_rdtsc();
3769 break;
367e86e8 3770 case 0x1a2: /* cpuid */
9c605cb1 3771 gen_op_cpuid();
367e86e8 3772 break;
982b4315 3773 case 0xf4: /* hlt */
717fc2ad
FB		 3774 if (s->cpl != 0) {
3775 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
3776 } else {
3777 if (s->cc_op != CC_OP_DYNAMIC)
3778 gen_op_set_cc_op(s->cc_op);
3779 gen_op_jmp_im(s->pc - s->cs_base);
3780 gen_op_hlt();
dbc5594c 3781 s->is_jmp = 3;
717fc2ad 3782 }
982b4315 3783 break;
d8bc1fd0
FB		 3784 case 0x100:
3785 modrm = ldub(s->pc++);
3786 mod = (modrm >> 6) & 3;
3787 op = (modrm >> 3) & 7;
3788 switch(op) {
3789 case 0: /* sldt */
3790 gen_op_movl_T0_env(offsetof(CPUX86State,ldt.selector));
3791 ot = OT_WORD;
3792 if (mod == 3)
3793 ot += s->dflag;
3794 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 1);
3795 break;
3796 case 2: /* lldt */
3797 if (s->cpl != 0) {
3798 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
3799 } else {
3800 gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
3801 gen_op_jmp_im(pc_start - s->cs_base);
3802 gen_op_lldt_T0();
3803 }
3804 break;
3805 case 1: /* str */
3806 gen_op_movl_T0_env(offsetof(CPUX86State,tr.selector));
3807 ot = OT_WORD;
3808 if (mod == 3)
3809 ot += s->dflag;
3810 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 1);
3811 break;
3812 case 3: /* ltr */
3813 if (s->cpl != 0) {
3814 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
3815 } else {
3816 gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
3817 gen_op_jmp_im(pc_start - s->cs_base);
3818 gen_op_ltr_T0();
3819 }
3820 break;
3821 case 4: /* verr */
3822 case 5: /* verw */
3823 default:
3824 goto illegal_op;
3825 }
3826 break;
3827 case 0x101:
3828 modrm = ldub(s->pc++);
3829 mod = (modrm >> 6) & 3;
3830 op = (modrm >> 3) & 7;
3831 switch(op) {
3832 case 0: /* sgdt */
3833 case 1: /* sidt */
3834 if (mod == 3)
3835 goto illegal_op;
3836 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3837 if (op == 0)
3838 gen_op_movl_T0_env(offsetof(CPUX86State,gdt.limit));
3839 else
3840 gen_op_movl_T0_env(offsetof(CPUX86State,idt.limit));
4021dab0 3841 gen_op_st_T0_A0[OT_WORD + s->mem_index]();
d8bc1fd0
FB		 3842 gen_op_addl_A0_im(2);
3843 if (op == 0)
3844 gen_op_movl_T0_env(offsetof(CPUX86State,gdt.base));
3845 else
3846 gen_op_movl_T0_env(offsetof(CPUX86State,idt.base));
3847 if (!s->dflag)
3848 gen_op_andl_T0_im(0xffffff);
4021dab0 3849 gen_op_st_T0_A0[OT_LONG + s->mem_index]();
d8bc1fd0
FB		 3850 break;
3851 case 2: /* lgdt */
3852 case 3: /* lidt */
3853 if (mod == 3)
3854 goto illegal_op;
3855 if (s->cpl != 0) {
3856 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
3857 } else {
3858 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
4021dab0 3859 gen_op_ld_T1_A0[OT_WORD + s->mem_index]();
d8bc1fd0 3860 gen_op_addl_A0_im(2);
4021dab0 3861 gen_op_ld_T0_A0[OT_LONG + s->mem_index]();
d8bc1fd0
FB		 3862 if (!s->dflag)
3863 gen_op_andl_T0_im(0xffffff);
3864 if (op == 2) {
3865 gen_op_movl_env_T0(offsetof(CPUX86State,gdt.base));
3866 gen_op_movl_env_T1(offsetof(CPUX86State,gdt.limit));
3867 } else {
3868 gen_op_movl_env_T0(offsetof(CPUX86State,idt.base));
3869 gen_op_movl_env_T1(offsetof(CPUX86State,idt.limit));
3870 }
3871 }
3872 break;
3873 case 4: /* smsw */
3874 gen_op_movl_T0_env(offsetof(CPUX86State,cr[0]));
3875 gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 1);
3876 break;
3877 case 6: /* lmsw */
3878 if (s->cpl != 0) {
3879 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
3880 } else {
3881 gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
3882 gen_op_lmsw_T0();
3883 }
3884 break;
717fc2ad
FB		 3885 case 7: /* invlpg */
3886 if (s->cpl != 0) {
3887 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
3888 } else {
3889 if (mod == 3)
3890 goto illegal_op;
3891 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3892 gen_op_invlpg_A0();
3893 }
3894 break;
d8bc1fd0
FB		 3895 default:
3896 goto illegal_op;
3897 }
3898 break;
78c34e98
FB		 3899 case 0x102: /* lar */
3900 case 0x103: /* lsl */
8f186479 3901 if (!s->pe || s->vm86)
78c34e98
FB		 3902 goto illegal_op;
3903 ot = dflag ? OT_LONG : OT_WORD;
3904 modrm = ldub(s->pc++);
3905 reg = (modrm >> 3) & 7;
3906 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
3907 gen_op_mov_TN_reg[ot][1][reg]();
3908 if (s->cc_op != CC_OP_DYNAMIC)
3909 gen_op_set_cc_op(s->cc_op);
3910 if (b == 0x102)
3911 gen_op_lar();
3912 else
3913 gen_op_lsl();
3914 s->cc_op = CC_OP_EFLAGS;
3915 gen_op_mov_reg_T1[ot][reg]();
3916 break;
d8bc1fd0
FB		 3917 case 0x118:
3918 modrm = ldub(s->pc++);
3919 mod = (modrm >> 6) & 3;
3920 op = (modrm >> 3) & 7;
3921 switch(op) {
3922 case 0: /* prefetchnta */
3923 case 1: /* prefetchnt0 */
3924 case 2: /* prefetchnt0 */
3925 case 3: /* prefetchnt0 */
3926 if (mod == 3)
3927 goto illegal_op;
3928 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3929 /* nothing more to do */
3930 break;
3931 default:
3932 goto illegal_op;
3933 }
3934 break;
3935 case 0x120: /* mov reg, crN */
3936 case 0x122: /* mov crN, reg */
3937 if (s->cpl != 0) {
3938 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
3939 } else {
3940 modrm = ldub(s->pc++);
3941 if ((modrm & 0xc0) != 0xc0)
3942 goto illegal_op;
3943 rm = modrm & 7;
3944 reg = (modrm >> 3) & 7;
3945 switch(reg) {
3946 case 0:
3947 case 2:
3948 case 3:
3949 case 4:
3950 if (b & 2) {
3951 gen_op_mov_TN_reg[OT_LONG][0][rm]();
3952 gen_op_movl_crN_T0(reg);
dbc5594c
FB		 3953 gen_op_jmp_im(s->pc - s->cs_base);
3954 gen_eob(s);
d8bc1fd0
FB		 3955 } else {
3956 gen_op_movl_T0_env(offsetof(CPUX86State,cr[reg]));
3957 gen_op_mov_reg_T0[OT_LONG][rm]();
3958 }
3959 break;
3960 default:
3961 goto illegal_op;
3962 }
3963 }
3964 break;
3965 case 0x121: /* mov reg, drN */
3966 case 0x123: /* mov drN, reg */
3967 if (s->cpl != 0) {
3968 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
3969 } else {
3970 modrm = ldub(s->pc++);
3971 if ((modrm & 0xc0) != 0xc0)
3972 goto illegal_op;
3973 rm = modrm & 7;
3974 reg = (modrm >> 3) & 7;
3975 /* XXX: do it dynamically with CR4.DE bit */
3976 if (reg == 4 || reg == 5)
3977 goto illegal_op;
3978 if (b & 2) {
3979 gen_op_mov_TN_reg[OT_LONG][0][rm]();
3980 gen_op_movl_drN_T0(reg);
dbc5594c
FB		 3981 gen_op_jmp_im(s->pc - s->cs_base);
3982 gen_eob(s);
d8bc1fd0
FB		 3983 } else {
3984 gen_op_movl_T0_env(offsetof(CPUX86State,dr[reg]));
3985 gen_op_mov_reg_T0[OT_LONG][rm]();
3986 }
3987 }
3988 break;
3989 case 0x106: /* clts */
3990 if (s->cpl != 0) {
3991 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
3992 } else {
3993 gen_op_clts();
3994 }
3995 break;
367e86e8 3996 default:
1a9353d2 3997 goto illegal_op;
367e86e8 3998 }
1b6b029e
FB		 3999 /* lock generation */
4000 if (s->prefix & PREFIX_LOCK)
4001 gen_op_unlock();
dbc5594c 4002 return s->pc;
6dbad63e 4003 illegal_op:
1b6b029e 4004 /* XXX: ensure that no lock was generated */
dbc5594c
FB		 4005 gen_exception(s, EXCP06_ILLOP, pc_start - s->cs_base);
4006 return s->pc;
367e86e8
FB		 4007}
4008
dc99065b
FB		 4009#define CC_OSZAPC (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C)
4010#define CC_OSZAP (CC_O | CC_S | CC_Z | CC_A | CC_P)
4011
4012/* flags read by an operation */
4013static uint16_t opc_read_flags[NB_OPS] = {
4014 [INDEX_op_aas] = CC_A,
4015 [INDEX_op_aaa] = CC_A,
4016 [INDEX_op_das] = CC_A | CC_C,
4017 [INDEX_op_daa] = CC_A | CC_C,
4018
4019 [INDEX_op_adcb_T0_T1_cc] = CC_C,
4020 [INDEX_op_adcw_T0_T1_cc] = CC_C,
4021 [INDEX_op_adcl_T0_T1_cc] = CC_C,
4022 [INDEX_op_sbbb_T0_T1_cc] = CC_C,
4023 [INDEX_op_sbbw_T0_T1_cc] = CC_C,
4024 [INDEX_op_sbbl_T0_T1_cc] = CC_C,
4025
e477b8b8
FB		 4026 [INDEX_op_adcb_mem_T0_T1_cc] = CC_C,
4027 [INDEX_op_adcw_mem_T0_T1_cc] = CC_C,
4028 [INDEX_op_adcl_mem_T0_T1_cc] = CC_C,
4029 [INDEX_op_sbbb_mem_T0_T1_cc] = CC_C,
4030 [INDEX_op_sbbw_mem_T0_T1_cc] = CC_C,
4031 [INDEX_op_sbbl_mem_T0_T1_cc] = CC_C,
4032
982b4315 4033 /* subtle: due to the incl/decl implementation, C is used */
5797fa5d 4034 [INDEX_op_update_inc_cc] = CC_C,
982b4315 4035
dc99065b
FB		 4036 [INDEX_op_into] = CC_O,
4037
dc99065b
FB		 4038 [INDEX_op_jb_subb] = CC_C,
4039 [INDEX_op_jb_subw] = CC_C,
4040 [INDEX_op_jb_subl] = CC_C,
4041
4042 [INDEX_op_jz_subb] = CC_Z,
4043 [INDEX_op_jz_subw] = CC_Z,
4044 [INDEX_op_jz_subl] = CC_Z,
4045
4046 [INDEX_op_jbe_subb] = CC_Z | CC_C,
4047 [INDEX_op_jbe_subw] = CC_Z | CC_C,
4048 [INDEX_op_jbe_subl] = CC_Z | CC_C,
4049
4050 [INDEX_op_js_subb] = CC_S,
4051 [INDEX_op_js_subw] = CC_S,
4052 [INDEX_op_js_subl] = CC_S,
4053
4054 [INDEX_op_jl_subb] = CC_O | CC_S,
4055 [INDEX_op_jl_subw] = CC_O | CC_S,
4056 [INDEX_op_jl_subl] = CC_O | CC_S,
4057
4058 [INDEX_op_jle_subb] = CC_O | CC_S | CC_Z,
4059 [INDEX_op_jle_subw] = CC_O | CC_S | CC_Z,
4060 [INDEX_op_jle_subl] = CC_O | CC_S | CC_Z,
4061
4062 [INDEX_op_loopnzw] = CC_Z,
4063 [INDEX_op_loopnzl] = CC_Z,
4064 [INDEX_op_loopzw] = CC_Z,
4065 [INDEX_op_loopzl] = CC_Z,
4066
4067 [INDEX_op_seto_T0_cc] = CC_O,
4068 [INDEX_op_setb_T0_cc] = CC_C,
4069 [INDEX_op_setz_T0_cc] = CC_Z,
4070 [INDEX_op_setbe_T0_cc] = CC_Z | CC_C,
4071 [INDEX_op_sets_T0_cc] = CC_S,
4072 [INDEX_op_setp_T0_cc] = CC_P,
4073 [INDEX_op_setl_T0_cc] = CC_O | CC_S,
4074 [INDEX_op_setle_T0_cc] = CC_O | CC_S | CC_Z,
4075
4076 [INDEX_op_setb_T0_subb] = CC_C,
4077 [INDEX_op_setb_T0_subw] = CC_C,
4078 [INDEX_op_setb_T0_subl] = CC_C,
4079
4080 [INDEX_op_setz_T0_subb] = CC_Z,
4081 [INDEX_op_setz_T0_subw] = CC_Z,
4082 [INDEX_op_setz_T0_subl] = CC_Z,
4083
4084 [INDEX_op_setbe_T0_subb] = CC_Z | CC_C,
4085 [INDEX_op_setbe_T0_subw] = CC_Z | CC_C,
4086 [INDEX_op_setbe_T0_subl] = CC_Z | CC_C,
4087
4088 [INDEX_op_sets_T0_subb] = CC_S,
4089 [INDEX_op_sets_T0_subw] = CC_S,
4090 [INDEX_op_sets_T0_subl] = CC_S,
4091
4092 [INDEX_op_setl_T0_subb] = CC_O | CC_S,
4093 [INDEX_op_setl_T0_subw] = CC_O | CC_S,
4094 [INDEX_op_setl_T0_subl] = CC_O | CC_S,
4095
4096 [INDEX_op_setle_T0_subb] = CC_O | CC_S | CC_Z,
4097 [INDEX_op_setle_T0_subw] = CC_O | CC_S | CC_Z,
4098 [INDEX_op_setle_T0_subl] = CC_O | CC_S | CC_Z,
4099
4100 [INDEX_op_movl_T0_eflags] = CC_OSZAPC,
4101 [INDEX_op_cmc] = CC_C,
4102 [INDEX_op_salc] = CC_C,
4103
4104 [INDEX_op_rclb_T0_T1_cc] = CC_C,
4105 [INDEX_op_rclw_T0_T1_cc] = CC_C,
4106 [INDEX_op_rcll_T0_T1_cc] = CC_C,
4107 [INDEX_op_rcrb_T0_T1_cc] = CC_C,
4108 [INDEX_op_rcrw_T0_T1_cc] = CC_C,
4109 [INDEX_op_rcrl_T0_T1_cc] = CC_C,
e477b8b8
FB		 4110
4111 [INDEX_op_rclb_mem_T0_T1_cc] = CC_C,
4112 [INDEX_op_rclw_mem_T0_T1_cc] = CC_C,
4113 [INDEX_op_rcll_mem_T0_T1_cc] = CC_C,
4114 [INDEX_op_rcrb_mem_T0_T1_cc] = CC_C,
4115 [INDEX_op_rcrw_mem_T0_T1_cc] = CC_C,
4116 [INDEX_op_rcrl_mem_T0_T1_cc] = CC_C,
dc99065b
FB		 4117};
4118
4119/* flags written by an operation */
4120static uint16_t opc_write_flags[NB_OPS] = {
5797fa5d
FB		 4121 [INDEX_op_update2_cc] = CC_OSZAPC,
4122 [INDEX_op_update1_cc] = CC_OSZAPC,
e477b8b8
FB		 4123 [INDEX_op_cmpl_T0_T1_cc] = CC_OSZAPC,
4124 [INDEX_op_update_neg_cc] = CC_OSZAPC,
4125 /* subtle: due to the incl/decl implementation, C is used */
4126 [INDEX_op_update_inc_cc] = CC_OSZAPC,
4127 [INDEX_op_testl_T0_T1_cc] = CC_OSZAPC,
4128
dc99065b
FB		 4129 [INDEX_op_adcb_T0_T1_cc] = CC_OSZAPC,
4130 [INDEX_op_adcw_T0_T1_cc] = CC_OSZAPC,
4131 [INDEX_op_adcl_T0_T1_cc] = CC_OSZAPC,
4132 [INDEX_op_sbbb_T0_T1_cc] = CC_OSZAPC,
4133 [INDEX_op_sbbw_T0_T1_cc] = CC_OSZAPC,
4134 [INDEX_op_sbbl_T0_T1_cc] = CC_OSZAPC,
e477b8b8
FB		 4135
4136 [INDEX_op_adcb_mem_T0_T1_cc] = CC_OSZAPC,
4137 [INDEX_op_adcw_mem_T0_T1_cc] = CC_OSZAPC,
4138 [INDEX_op_adcl_mem_T0_T1_cc] = CC_OSZAPC,
4139 [INDEX_op_sbbb_mem_T0_T1_cc] = CC_OSZAPC,
4140 [INDEX_op_sbbw_mem_T0_T1_cc] = CC_OSZAPC,
4141 [INDEX_op_sbbl_mem_T0_T1_cc] = CC_OSZAPC,
dc99065b
FB		 4142
4143 [INDEX_op_mulb_AL_T0] = CC_OSZAPC,
4144 [INDEX_op_imulb_AL_T0] = CC_OSZAPC,
4145 [INDEX_op_mulw_AX_T0] = CC_OSZAPC,
4146 [INDEX_op_imulw_AX_T0] = CC_OSZAPC,
4147 [INDEX_op_mull_EAX_T0] = CC_OSZAPC,
4148 [INDEX_op_imull_EAX_T0] = CC_OSZAPC,
4149 [INDEX_op_imulw_T0_T1] = CC_OSZAPC,
4150 [INDEX_op_imull_T0_T1] = CC_OSZAPC,
4151
4152 /* bcd */
4153 [INDEX_op_aam] = CC_OSZAPC,
4154 [INDEX_op_aad] = CC_OSZAPC,
4155 [INDEX_op_aas] = CC_OSZAPC,
4156 [INDEX_op_aaa] = CC_OSZAPC,
4157 [INDEX_op_das] = CC_OSZAPC,
4158 [INDEX_op_daa] = CC_OSZAPC,
4159
4160 [INDEX_op_movb_eflags_T0] = CC_S | CC_Z | CC_A | CC_P | CC_C,
f631ef9b 4161 [INDEX_op_movw_eflags_T0] = CC_OSZAPC,
dc99065b
FB		 4162 [INDEX_op_movl_eflags_T0] = CC_OSZAPC,
4163 [INDEX_op_clc] = CC_C,
4164 [INDEX_op_stc] = CC_C,
4165 [INDEX_op_cmc] = CC_C,
4166
4167 [INDEX_op_rolb_T0_T1_cc] = CC_O | CC_C,
4168 [INDEX_op_rolw_T0_T1_cc] = CC_O | CC_C,
4169 [INDEX_op_roll_T0_T1_cc] = CC_O | CC_C,
4170 [INDEX_op_rorb_T0_T1_cc] = CC_O | CC_C,
4171 [INDEX_op_rorw_T0_T1_cc] = CC_O | CC_C,
4172 [INDEX_op_rorl_T0_T1_cc] = CC_O | CC_C,
4173
4174 [INDEX_op_rclb_T0_T1_cc] = CC_O | CC_C,
4175 [INDEX_op_rclw_T0_T1_cc] = CC_O | CC_C,
4176 [INDEX_op_rcll_T0_T1_cc] = CC_O | CC_C,
4177 [INDEX_op_rcrb_T0_T1_cc] = CC_O | CC_C,
4178 [INDEX_op_rcrw_T0_T1_cc] = CC_O | CC_C,
4179 [INDEX_op_rcrl_T0_T1_cc] = CC_O | CC_C,
4180
4181 [INDEX_op_shlb_T0_T1_cc] = CC_OSZAPC,
4182 [INDEX_op_shlw_T0_T1_cc] = CC_OSZAPC,
4183 [INDEX_op_shll_T0_T1_cc] = CC_OSZAPC,
4184
4185 [INDEX_op_shrb_T0_T1_cc] = CC_OSZAPC,
4186 [INDEX_op_shrw_T0_T1_cc] = CC_OSZAPC,
4187 [INDEX_op_shrl_T0_T1_cc] = CC_OSZAPC,
4188
4189 [INDEX_op_sarb_T0_T1_cc] = CC_OSZAPC,
4190 [INDEX_op_sarw_T0_T1_cc] = CC_OSZAPC,
4191 [INDEX_op_sarl_T0_T1_cc] = CC_OSZAPC,
4192
4193 [INDEX_op_shldw_T0_T1_ECX_cc] = CC_OSZAPC,
4194 [INDEX_op_shldl_T0_T1_ECX_cc] = CC_OSZAPC,
4195 [INDEX_op_shldw_T0_T1_im_cc] = CC_OSZAPC,
4196 [INDEX_op_shldl_T0_T1_im_cc] = CC_OSZAPC,
4197
4198 [INDEX_op_shrdw_T0_T1_ECX_cc] = CC_OSZAPC,
4199 [INDEX_op_shrdl_T0_T1_ECX_cc] = CC_OSZAPC,
4200 [INDEX_op_shrdw_T0_T1_im_cc] = CC_OSZAPC,
4201 [INDEX_op_shrdl_T0_T1_im_cc] = CC_OSZAPC,
4202
e477b8b8
FB		 4203 [INDEX_op_rolb_mem_T0_T1_cc] = CC_O | CC_C,
4204 [INDEX_op_rolw_mem_T0_T1_cc] = CC_O | CC_C,
4205 [INDEX_op_roll_mem_T0_T1_cc] = CC_O | CC_C,
4206 [INDEX_op_rorb_mem_T0_T1_cc] = CC_O | CC_C,
4207 [INDEX_op_rorw_mem_T0_T1_cc] = CC_O | CC_C,
4208 [INDEX_op_rorl_mem_T0_T1_cc] = CC_O | CC_C,
4209
4210 [INDEX_op_rclb_mem_T0_T1_cc] = CC_O | CC_C,
4211 [INDEX_op_rclw_mem_T0_T1_cc] = CC_O | CC_C,
4212 [INDEX_op_rcll_mem_T0_T1_cc] = CC_O | CC_C,
4213 [INDEX_op_rcrb_mem_T0_T1_cc] = CC_O | CC_C,
4214 [INDEX_op_rcrw_mem_T0_T1_cc] = CC_O | CC_C,
4215 [INDEX_op_rcrl_mem_T0_T1_cc] = CC_O | CC_C,
4216
4217 [INDEX_op_shlb_mem_T0_T1_cc] = CC_OSZAPC,
4218 [INDEX_op_shlw_mem_T0_T1_cc] = CC_OSZAPC,
4219 [INDEX_op_shll_mem_T0_T1_cc] = CC_OSZAPC,
4220
4221 [INDEX_op_shrb_mem_T0_T1_cc] = CC_OSZAPC,
4222 [INDEX_op_shrw_mem_T0_T1_cc] = CC_OSZAPC,
4223 [INDEX_op_shrl_mem_T0_T1_cc] = CC_OSZAPC,
4224
4225 [INDEX_op_sarb_mem_T0_T1_cc] = CC_OSZAPC,
4226 [INDEX_op_sarw_mem_T0_T1_cc] = CC_OSZAPC,
4227 [INDEX_op_sarl_mem_T0_T1_cc] = CC_OSZAPC,
4228
4229 [INDEX_op_shldw_mem_T0_T1_ECX_cc] = CC_OSZAPC,
4230 [INDEX_op_shldl_mem_T0_T1_ECX_cc] = CC_OSZAPC,
4231 [INDEX_op_shldw_mem_T0_T1_im_cc] = CC_OSZAPC,
4232 [INDEX_op_shldl_mem_T0_T1_im_cc] = CC_OSZAPC,
4233
4234 [INDEX_op_shrdw_mem_T0_T1_ECX_cc] = CC_OSZAPC,
4235 [INDEX_op_shrdl_mem_T0_T1_ECX_cc] = CC_OSZAPC,
4236 [INDEX_op_shrdw_mem_T0_T1_im_cc] = CC_OSZAPC,
4237 [INDEX_op_shrdl_mem_T0_T1_im_cc] = CC_OSZAPC,
4238
dc99065b
FB		 4239 [INDEX_op_btw_T0_T1_cc] = CC_OSZAPC,
4240 [INDEX_op_btl_T0_T1_cc] = CC_OSZAPC,
4241 [INDEX_op_btsw_T0_T1_cc] = CC_OSZAPC,
4242 [INDEX_op_btsl_T0_T1_cc] = CC_OSZAPC,
4243 [INDEX_op_btrw_T0_T1_cc] = CC_OSZAPC,
4244 [INDEX_op_btrl_T0_T1_cc] = CC_OSZAPC,
4245 [INDEX_op_btcw_T0_T1_cc] = CC_OSZAPC,
4246 [INDEX_op_btcl_T0_T1_cc] = CC_OSZAPC,
4247
4248 [INDEX_op_bsfw_T0_cc] = CC_OSZAPC,
4249 [INDEX_op_bsfl_T0_cc] = CC_OSZAPC,
4250 [INDEX_op_bsrw_T0_cc] = CC_OSZAPC,
4251 [INDEX_op_bsrl_T0_cc] = CC_OSZAPC,
4252
9c605cb1 4253 [INDEX_op_cmpxchgb_T0_T1_EAX_cc] = CC_OSZAPC,
dc99065b
FB		 4254 [INDEX_op_cmpxchgw_T0_T1_EAX_cc] = CC_OSZAPC,
4255 [INDEX_op_cmpxchgl_T0_T1_EAX_cc] = CC_OSZAPC,
9c605cb1 4256
e477b8b8
FB		 4257 [INDEX_op_cmpxchgb_mem_T0_T1_EAX_cc] = CC_OSZAPC,
4258 [INDEX_op_cmpxchgw_mem_T0_T1_EAX_cc] = CC_OSZAPC,
4259 [INDEX_op_cmpxchgl_mem_T0_T1_EAX_cc] = CC_OSZAPC,
4260
9c605cb1 4261 [INDEX_op_cmpxchg8b] = CC_Z,
78c34e98
FB		 4262 [INDEX_op_lar] = CC_Z,
4263 [INDEX_op_lsl] = CC_Z,
d0a1ffc9
FB		 4264 [INDEX_op_fcomi_ST0_FT0] = CC_Z | CC_P | CC_C,
4265 [INDEX_op_fucomi_ST0_FT0] = CC_Z | CC_P | CC_C,
dc99065b
FB		 4266};
4267
4268/* simpler form of an operation if no flags need to be generated */
4269static uint16_t opc_simpler[NB_OPS] = {
5797fa5d
FB		 4270 [INDEX_op_update2_cc] = INDEX_op_nop,
4271 [INDEX_op_update1_cc] = INDEX_op_nop,
4272 [INDEX_op_update_neg_cc] = INDEX_op_nop,
e477b8b8
FB		 4273#if 0
4274 /* broken: CC_OP logic must be rewritten */
5797fa5d 4275 [INDEX_op_update_inc_cc] = INDEX_op_nop,
e477b8b8 4276#endif
dc99065b
FB		 4277 [INDEX_op_rolb_T0_T1_cc] = INDEX_op_rolb_T0_T1,
4278 [INDEX_op_rolw_T0_T1_cc] = INDEX_op_rolw_T0_T1,
4279 [INDEX_op_roll_T0_T1_cc] = INDEX_op_roll_T0_T1,
4280
4281 [INDEX_op_rorb_T0_T1_cc] = INDEX_op_rorb_T0_T1,
4282 [INDEX_op_rorw_T0_T1_cc] = INDEX_op_rorw_T0_T1,
4283 [INDEX_op_rorl_T0_T1_cc] = INDEX_op_rorl_T0_T1,
4284
e477b8b8
FB		 4285 [INDEX_op_rolb_mem_T0_T1_cc] = INDEX_op_rolb_mem_T0_T1,
4286 [INDEX_op_rolw_mem_T0_T1_cc] = INDEX_op_rolw_mem_T0_T1,
4287 [INDEX_op_roll_mem_T0_T1_cc] = INDEX_op_roll_mem_T0_T1,
4288
4289 [INDEX_op_rorb_mem_T0_T1_cc] = INDEX_op_rorb_mem_T0_T1,
4290 [INDEX_op_rorw_mem_T0_T1_cc] = INDEX_op_rorw_mem_T0_T1,
4291 [INDEX_op_rorl_mem_T0_T1_cc] = INDEX_op_rorl_mem_T0_T1,
4292
dc99065b
FB		 4293 [INDEX_op_shlb_T0_T1_cc] = INDEX_op_shlb_T0_T1,
4294 [INDEX_op_shlw_T0_T1_cc] = INDEX_op_shlw_T0_T1,
4295 [INDEX_op_shll_T0_T1_cc] = INDEX_op_shll_T0_T1,
4296
4297 [INDEX_op_shrb_T0_T1_cc] = INDEX_op_shrb_T0_T1,
4298 [INDEX_op_shrw_T0_T1_cc] = INDEX_op_shrw_T0_T1,
4299 [INDEX_op_shrl_T0_T1_cc] = INDEX_op_shrl_T0_T1,
4300
4301 [INDEX_op_sarb_T0_T1_cc] = INDEX_op_sarb_T0_T1,
4302 [INDEX_op_sarw_T0_T1_cc] = INDEX_op_sarw_T0_T1,
4303 [INDEX_op_sarl_T0_T1_cc] = INDEX_op_sarl_T0_T1,
4304};
4305
4021dab0 4306void optimize_flags_init(void)
dc99065b
FB		 4307{
4308 int i;
4309 /* put default values in arrays */
4310 for(i = 0; i < NB_OPS; i++) {
4311 if (opc_simpler[i] == 0)
4312 opc_simpler[i] = i;
4313 }
4314}
4315
4316/* CPU flags computation optimization: we move backward thru the
4317 generated code to see which flags are needed. The operation is
4318 modified if suitable */
4319static void optimize_flags(uint16_t *opc_buf, int opc_buf_len)
4320{
4321 uint16_t *opc_ptr;
4322 int live_flags, write_flags, op;
4323
4324 opc_ptr = opc_buf + opc_buf_len;
4325 /* live_flags contains the flags needed by the next instructions
4326 in the code. At the end of the bloc, we consider that all the
4327 flags are live. */
4328 live_flags = CC_OSZAPC;
4329 while (opc_ptr > opc_buf) {
4330 op = *--opc_ptr;
4331 /* if none of the flags written by the instruction is used,
4332 then we can try to find a simpler instruction */
4333 write_flags = opc_write_flags[op];
4334 if ((live_flags & write_flags) == 0) {
4335 *opc_ptr = opc_simpler[op];
4336 }
4337 /* compute the live flags before the instruction */
4338 live_flags &= ~write_flags;
4339 live_flags |= opc_read_flags[op];
4340 }
4341}
4342
5a91de8c
FB		 4343/* generate intermediate code in gen_opc_buf and gen_opparam_buf for
4344 basic block 'tb'. If search_pc is TRUE, also generate PC
4345 information for each intermediate instruction. */
4c3a88a2
FB		 4346static inline int gen_intermediate_code_internal(CPUState *env,
4347 TranslationBlock *tb,
4348 int search_pc)
ba1c6e37
FB		 4349{
4350 DisasContext dc1, *dc = &dc1;
dc99065b
FB		 4351 uint8_t *pc_ptr;
4352 uint16_t *gen_opc_end;
5a91de8c 4353 int flags, j, lj;
5a91de8c
FB		 4354 uint8_t *pc_start;
4355 uint8_t *cs_base;
dc99065b
FB		 4356
4357 /* generate intermediate code */
5a91de8c
FB		 4358 pc_start = (uint8_t *)tb->pc;
4359 cs_base = (uint8_t *)tb->cs_base;
4360 flags = tb->flags;
4361
8f186479 4362 dc->pe = env->cr[0] & CR0_PE_MASK;
3f337316
FB		 4363 dc->code32 = (flags >> HF_CS32_SHIFT) & 1;
4364 dc->ss32 = (flags >> HF_SS32_SHIFT) & 1;
4365 dc->addseg = (flags >> HF_ADDSEG_SHIFT) & 1;
4366 dc->f_st = 0;
4367 dc->vm86 = (flags >> VM_SHIFT) & 1;
4368 dc->cpl = (flags >> HF_CPL_SHIFT) & 3;
4369 dc->iopl = (flags >> IOPL_SHIFT) & 3;
4370 dc->tf = (flags >> TF_SHIFT) & 1;
ba1c6e37 4371 dc->cc_op = CC_OP_DYNAMIC;
dab2ed99 4372 dc->cs_base = cs_base;
d4e8164f 4373 dc->tb = tb;
717fc2ad 4374 dc->popl_esp_hack = 0;
4021dab0
FB		 4375 /* select memory access functions */
4376 dc->mem_index = 0;
3f337316 4377 if (flags & HF_SOFTMMU_MASK) {
4021dab0
FB		 4378 if (dc->cpl == 3)
4379 dc->mem_index = 6;
4380 else
4381 dc->mem_index = 3;
4382 }
dbc5594c
FB		 4383 dc->jmp_opt = !(dc->tf || env->singlestep_enabled
4384#ifndef CONFIG_SOFT_MMU
4385 || (flags & HF_SOFTMMU_MASK)
4386#endif
4387 );
dc99065b
FB		 4388 gen_opc_ptr = gen_opc_buf;
4389 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
4390 gen_opparam_ptr = gen_opparam_buf;
0ecfa993 4391
d19893da 4392 dc->is_jmp = DISAS_NEXT;
1017ebe9 4393 pc_ptr = pc_start;
5a91de8c 4394 lj = -1;
3f337316
FB		 4395
4396 /* if irq were inhibited for the next instruction, we can disable
4397 them here as it is simpler (otherwise jumps would have to
4398 handled as special case) */
4399 if (flags & HF_INHIBIT_IRQ_MASK) {
4400 gen_op_reset_inhibit_irq();
4401 }
dbc5594c 4402 for(;;) {
4c3a88a2
FB		 4403 if (env->nb_breakpoints > 0) {
4404 for(j = 0; j < env->nb_breakpoints; j++) {
4405 if (env->breakpoints[j] == (unsigned long)pc_ptr) {
4406 gen_debug(dc, pc_ptr - dc->cs_base);
dbc5594c 4407 break;
4c3a88a2
FB		 4408 }
4409 }
4410 }
5a91de8c
FB		 4411 if (search_pc) {
4412 j = gen_opc_ptr - gen_opc_buf;
4413 if (lj < j) {
4414 lj++;
4415 while (lj < j)
4416 gen_opc_instr_start[lj++] = 0;
5a91de8c 4417 }
7739f36e
FB		 4418 gen_opc_pc[lj] = (uint32_t)pc_ptr;
4419 gen_opc_cc_op[lj] = dc->cc_op;
4420 gen_opc_instr_start[lj] = 1;
5a91de8c 4421 }
dbc5594c
FB		 4422 pc_ptr = disas_insn(dc, pc_ptr);
4423 /* stop translation if indicated */
4424 if (dc->is_jmp)
4425 break;
c50c0c3f
FB		 4426 /* if single step mode, we generate only one instruction and
4427 generate an exception */
dbc5594c
FB		 4428 if (dc->tf) {
4429 gen_op_jmp_im(pc_ptr - dc->cs_base);
4430 gen_eob(dc);
4431 break;
4432 }
4433 /* if too long translation, stop generation too */
4434 if (gen_opc_ptr >= gen_opc_end ||
4435 (pc_ptr - pc_start) >= (TARGET_PAGE_SIZE - 32)) {
4436 gen_op_jmp_im(pc_ptr - dc->cs_base);
4437 gen_eob(dc);
c50c0c3f 4438 break;
d4e8164f 4439 }
d4e8164f 4440 }
dc99065b 4441 *gen_opc_ptr = INDEX_op_end;
e477b8b8
FB		 4442 /* we don't forget to fill the last values */
4443 if (search_pc) {
4444 j = gen_opc_ptr - gen_opc_buf;
4445 lj++;
4446 while (lj <= j)
4447 gen_opc_instr_start[lj++] = 0;
4448 }
4449
0ecfa993 4450#ifdef DEBUG_DISAS
586314f2 4451 if (loglevel) {
dc99065b 4452 fprintf(logfile, "----------------\n");
b9adb4a6 4453 fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
d19893da 4454 disas(logfile, pc_start, pc_ptr - pc_start, 0, !dc->code32);
1017ebe9 4455 fprintf(logfile, "\n");
982b4315 4456
dc99065b 4457 fprintf(logfile, "OP:\n");
9c605cb1 4458 dump_ops(gen_opc_buf, gen_opparam_buf);
dc99065b
FB		 4459 fprintf(logfile, "\n");
4460 }
4461#endif
4462
4463 /* optimize flag computations */
4464 optimize_flags(gen_opc_buf, gen_opc_ptr - gen_opc_buf);
4465
4466#ifdef DEBUG_DISAS
4467 if (loglevel) {
4468 fprintf(logfile, "AFTER FLAGS OPT:\n");
9c605cb1 4469 dump_ops(gen_opc_buf, gen_opparam_buf);
dc99065b
FB		 4470 fprintf(logfile, "\n");
4471 }
4472#endif
5a91de8c
FB		 4473 if (!search_pc)
4474 tb->size = pc_ptr - pc_start;
4475 return 0;
4476}
4477
4c3a88a2 4478int gen_intermediate_code(CPUState *env, TranslationBlock *tb)
717fc2ad 4479{
4c3a88a2 4480 return gen_intermediate_code_internal(env, tb, 0);
717fc2ad
FB		 4481}
4482
4c3a88a2 4483int gen_intermediate_code_pc(CPUState *env, TranslationBlock *tb)
717fc2ad 4484{
4c3a88a2 4485 return gen_intermediate_code_internal(env, tb, 1);
717fc2ad
FB		 4486}
4487
Qemu copy for testing