]> git.proxmox.com Git - qemu.git/blame - translate.c
convert signal numbers
[qemu.git] / translate.c
CommitLineData
d19893da
FB
1/*
2 * Host code generation
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20#include <stdarg.h>
21#include <stdlib.h>
22#include <stdio.h>
23#include <string.h>
24#include <inttypes.h>
25
26#include "config.h"
2054396a 27
d19893da 28#define IN_OP_I386
2054396a
FB
29#if defined(TARGET_I386)
30#include "cpu-i386.h"
31#define OPC_CPU_H "opc-i386.h"
32#elif defined(TARGET_ARM)
33#include "cpu-arm.h"
34#define OPC_CPU_H "opc-arm.h"
35#else
36#error unsupported target CPU
37#endif
38
d19893da
FB
39#include "exec.h"
40#include "disas.h"
41
42enum {
43#define DEF(s, n, copy_size) INDEX_op_ ## s,
2054396a 44#include OPC_CPU_H
d19893da
FB
45#undef DEF
46 NB_OPS,
47};
48
49#include "dyngen.h"
2054396a
FB
50#if defined(TARGET_I386)
51#include "op-i386.h"
52#elif defined(TARGET_ARM)
53#include "op-arm.h"
54#else
55#error unsupported target CPU
56#endif
d19893da
FB
57
58uint16_t gen_opc_buf[OPC_BUF_SIZE];
59uint32_t gen_opparam_buf[OPPARAM_BUF_SIZE];
60uint32_t gen_opc_pc[OPC_BUF_SIZE];
61uint8_t gen_opc_instr_start[OPC_BUF_SIZE];
f76af4b3
FB
62#if defined(TARGET_I386)
63uint8_t gen_opc_cc_op[OPC_BUF_SIZE];
64#endif
d19893da
FB
65
66#ifdef DEBUG_DISAS
67static const char *op_str[] = {
68#define DEF(s, n, copy_size) #s,
2054396a 69#include OPC_CPU_H
d19893da
FB
70#undef DEF
71};
72
73static uint8_t op_nb_args[] = {
74#define DEF(s, n, copy_size) n,
2054396a 75#include OPC_CPU_H
d19893da
FB
76#undef DEF
77};
78
79void dump_ops(const uint16_t *opc_buf, const uint32_t *opparam_buf)
80{
81 const uint16_t *opc_ptr;
82 const uint32_t *opparam_ptr;
83 int c, n, i;
84
85 opc_ptr = opc_buf;
86 opparam_ptr = opparam_buf;
87 for(;;) {
88 c = *opc_ptr++;
89 n = op_nb_args[c];
90 fprintf(logfile, "0x%04x: %s",
91 (int)(opc_ptr - opc_buf - 1), op_str[c]);
92 for(i = 0; i < n; i++) {
93 fprintf(logfile, " 0x%x", opparam_ptr[i]);
94 }
95 fprintf(logfile, "\n");
96 if (c == INDEX_op_end)
97 break;
98 opparam_ptr += n;
99 }
100}
101
102#endif
103
104/* return non zero if the very first instruction is invalid so that
105 the virtual CPU can trigger an exception.
106
107 '*gen_code_size_ptr' contains the size of the generated code (host
108 code).
109*/
110int cpu_gen_code(TranslationBlock *tb,
111 int max_code_size, int *gen_code_size_ptr)
112{
113 uint8_t *gen_code_buf;
114 int gen_code_size;
115
f76af4b3 116 if (gen_intermediate_code(tb) < 0)
d19893da
FB
117 return -1;
118
119 /* generate machine code */
120 tb->tb_next_offset[0] = 0xffff;
121 tb->tb_next_offset[1] = 0xffff;
122 gen_code_buf = tb->tc_ptr;
123 gen_code_size = dyngen_code(gen_code_buf, tb->tb_next_offset,
124#ifdef USE_DIRECT_JUMP
125 tb->tb_jmp_offset,
126#else
127 NULL,
128#endif
129 gen_opc_buf, gen_opparam_buf);
130 *gen_code_size_ptr = gen_code_size;
131#ifdef DEBUG_DISAS
132 if (loglevel) {
133 fprintf(logfile, "OUT: [size=%d]\n", *gen_code_size_ptr);
134 disas(logfile, gen_code_buf, *gen_code_size_ptr, 1, 0);
135 fprintf(logfile, "\n");
136 fflush(logfile);
137 }
138#endif
139 return 0;
140}
141
142static const unsigned short opc_copy_size[] = {
143#define DEF(s, n, copy_size) copy_size,
2054396a 144#include OPC_CPU_H
d19893da
FB
145#undef DEF
146};
147
f76af4b3 148/* The cpu state corresponding to 'searched_pc' is restored.
d19893da 149 */
f76af4b3
FB
150int cpu_restore_state(TranslationBlock *tb,
151 CPUState *env, unsigned long searched_pc)
d19893da
FB
152{
153 int j, c;
154 unsigned long tc_ptr;
155 uint16_t *opc_ptr;
156
f76af4b3 157 if (gen_intermediate_code_pc(tb) < 0)
d19893da
FB
158 return -1;
159
160 /* find opc index corresponding to search_pc */
161 tc_ptr = (unsigned long)tb->tc_ptr;
162 if (searched_pc < tc_ptr)
163 return -1;
164 j = 0;
165 opc_ptr = gen_opc_buf;
166 for(;;) {
167 c = *opc_ptr;
168 if (c == INDEX_op_end)
169 return -1;
170 tc_ptr += opc_copy_size[c];
171 if (searched_pc < tc_ptr)
172 break;
173 opc_ptr++;
174 }
175 j = opc_ptr - gen_opc_buf;
176 /* now find start of instruction before */
177 while (gen_opc_instr_start[j] == 0)
178 j--;
f76af4b3
FB
179#if defined(TARGET_I386)
180 {
181 int cc_op;
3c1cf9fa
FB
182#ifdef DEBUG_DISAS
183 if (loglevel) {
184 int i;
185 for(i=0;i<=j; i++) {
186 if (gen_opc_instr_start[i]) {
187 fprintf(logfile, "0x%04x: 0x%08x", i, gen_opc_pc[i]);
188 }
189 }
190 fprintf(logfile, "j=0x%x eip=0x%lx cs_base=%lx\n",
191 j, gen_opc_pc[j] - tb->cs_base, tb->cs_base);
192 }
193#endif
f76af4b3
FB
194 env->eip = gen_opc_pc[j] - tb->cs_base;
195 cc_op = gen_opc_cc_op[j];
196 if (cc_op != CC_OP_DYNAMIC)
197 env->cc_op = cc_op;
198 }
199#elif defined(TARGET_ARM)
200 env->regs[15] = gen_opc_pc[j];
201#endif
d19893da
FB
202 return 0;
203}
204
205