[qemu.git] / user-exec.c

/*
 *  User emulator execution
 *
 *  Copyright (c) 2003-2005 Fabrice Bellard
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
 */
#include "config.h"
#include "cpu.h"
#include "disas/disas.h"
#include "tcg.h"

#undef EAX
#undef ECX
#undef EDX
#undef EBX
#undef ESP
#undef EBP
#undef ESI
#undef EDI
#undef EIP
#include <signal.h>
#ifdef __linux__
#include <sys/ucontext.h>
#endif

//#define DEBUG_SIGNAL

static void exception_action(CPUArchState *env1)
{
#if defined(TARGET_I386)
    raise_exception_err(env1, env1->exception_index, env1->error_code);
#else
    cpu_loop_exit(env1);
#endif
}

/* exit the current TB from a signal handler. The host registers are
   restored in a state compatible with the CPU emulator
 */
void cpu_resume_from_signal(CPUArchState *env1, void *puc)
{
#ifdef __linux__
    struct ucontext *uc = puc;
#elif defined(__OpenBSD__)
    struct sigcontext *uc = puc;
#endif

    if (puc) {
        /* XXX: use siglongjmp ? */
#ifdef __linux__
#ifdef __ia64
        sigprocmask(SIG_SETMASK, (sigset_t *)&uc->uc_sigmask, NULL);
#else
        sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL);
#endif
#elif defined(__OpenBSD__)
        sigprocmask(SIG_SETMASK, &uc->sc_mask, NULL);
#endif
    }
    env1->exception_index = -1;
    siglongjmp(env1->jmp_env, 1);
}

/* 'pc' is the host PC at which the exception was raised. 'address' is
   the effective address of the memory exception. 'is_write' is 1 if a
   write caused the exception and otherwise 0'. 'old_set' is the
   signal set which should be restored */
static inline int handle_cpu_signal(uintptr_t pc, unsigned long address,
                                    int is_write, sigset_t *old_set,
                                    void *puc)
{
    CPUArchState *env;
    int ret;

#if defined(DEBUG_SIGNAL)
    qemu_printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
                pc, address, is_write, *(unsigned long *)old_set);
#endif
    /* XXX: locking issue */
    if (is_write && h2g_valid(address)
        && page_unprotect(h2g(address), pc, puc)) {
        return 1;
    }

    env = current_cpu->env_ptr;
    /* see if it is an MMU fault */
    ret = cpu_handle_mmu_fault(env, address, is_write, MMU_USER_IDX);
    if (ret < 0) {
        return 0; /* not an MMU fault */
    }
    if (ret == 0) {
        return 1; /* the MMU fault was handled without causing real CPU fault */
    }
    /* now we have a real cpu fault */
    cpu_restore_state(env, pc);

    /* we restore the process signal mask as the sigreturn should
       do it (XXX: use sigsetjmp) */
    sigprocmask(SIG_SETMASK, old_set, NULL);
    exception_action(env);

    /* never comes here */
    return 1;
}

#if defined(__i386__)

#if defined(__APPLE__)
#include <sys/ucontext.h>

#define EIP_sig(context)  (*((unsigned long *)&(context)->uc_mcontext->ss.eip))
#define TRAP_sig(context)    ((context)->uc_mcontext->es.trapno)
#define ERROR_sig(context)   ((context)->uc_mcontext->es.err)
#define MASK_sig(context)    ((context)->uc_sigmask)
#elif defined(__NetBSD__)
#include <ucontext.h>

#define EIP_sig(context)     ((context)->uc_mcontext.__gregs[_REG_EIP])
#define TRAP_sig(context)    ((context)->uc_mcontext.__gregs[_REG_TRAPNO])
#define ERROR_sig(context)   ((context)->uc_mcontext.__gregs[_REG_ERR])
#define MASK_sig(context)    ((context)->uc_sigmask)
#elif defined(__FreeBSD__) || defined(__DragonFly__)
#include <ucontext.h>

#define EIP_sig(context)  (*((unsigned long *)&(context)->uc_mcontext.mc_eip))
#define TRAP_sig(context)    ((context)->uc_mcontext.mc_trapno)
#define ERROR_sig(context)   ((context)->uc_mcontext.mc_err)
#define MASK_sig(context)    ((context)->uc_sigmask)
#elif defined(__OpenBSD__)
#define EIP_sig(context)     ((context)->sc_eip)
#define TRAP_sig(context)    ((context)->sc_trapno)
#define ERROR_sig(context)   ((context)->sc_err)
#define MASK_sig(context)    ((context)->sc_mask)
#else
#define EIP_sig(context)     ((context)->uc_mcontext.gregs[REG_EIP])
#define TRAP_sig(context)    ((context)->uc_mcontext.gregs[REG_TRAPNO])
#define ERROR_sig(context)   ((context)->uc_mcontext.gregs[REG_ERR])
#define MASK_sig(context)    ((context)->uc_sigmask)
#endif

int cpu_signal_handler(int host_signum, void *pinfo,
                       void *puc)
{
    siginfo_t *info = pinfo;
#if defined(__NetBSD__) || defined(__FreeBSD__) || defined(__DragonFly__)
    ucontext_t *uc = puc;
#elif defined(__OpenBSD__)
    struct sigcontext *uc = puc;
#else
    struct ucontext *uc = puc;
#endif
    unsigned long pc;
    int trapno;

#ifndef REG_EIP
/* for glibc 2.1 */
#define REG_EIP    EIP
#define REG_ERR    ERR
#define REG_TRAPNO TRAPNO
#endif
    pc = EIP_sig(uc);
    trapno = TRAP_sig(uc);
    return handle_cpu_signal(pc, (unsigned long)info->si_addr,
                             trapno == 0xe ?
                             (ERROR_sig(uc) >> 1) & 1 : 0,
                             &MASK_sig(uc), puc);
}

#elif defined(__x86_64__)

#ifdef __NetBSD__
#define PC_sig(context)       _UC_MACHINE_PC(context)
#define TRAP_sig(context)     ((context)->uc_mcontext.__gregs[_REG_TRAPNO])
#define ERROR_sig(context)    ((context)->uc_mcontext.__gregs[_REG_ERR])
#define MASK_sig(context)     ((context)->uc_sigmask)
#elif defined(__OpenBSD__)
#define PC_sig(context)       ((context)->sc_rip)
#define TRAP_sig(context)     ((context)->sc_trapno)
#define ERROR_sig(context)    ((context)->sc_err)
#define MASK_sig(context)     ((context)->sc_mask)
#elif defined(__FreeBSD__) || defined(__DragonFly__)
#include <ucontext.h>

#define PC_sig(context)  (*((unsigned long *)&(context)->uc_mcontext.mc_rip))
#define TRAP_sig(context)     ((context)->uc_mcontext.mc_trapno)
#define ERROR_sig(context)    ((context)->uc_mcontext.mc_err)
#define MASK_sig(context)     ((context)->uc_sigmask)
#else
#define PC_sig(context)       ((context)->uc_mcontext.gregs[REG_RIP])
#define TRAP_sig(context)     ((context)->uc_mcontext.gregs[REG_TRAPNO])
#define ERROR_sig(context)    ((context)->uc_mcontext.gregs[REG_ERR])
#define MASK_sig(context)     ((context)->uc_sigmask)
#endif

int cpu_signal_handler(int host_signum, void *pinfo,
                       void *puc)
{
    siginfo_t *info = pinfo;
    unsigned long pc;
#if defined(__NetBSD__) || defined(__FreeBSD__) || defined(__DragonFly__)
    ucontext_t *uc = puc;
#elif defined(__OpenBSD__)
    struct sigcontext *uc = puc;
#else
    struct ucontext *uc = puc;
#endif

    pc = PC_sig(uc);
    return handle_cpu_signal(pc, (unsigned long)info->si_addr,
                             TRAP_sig(uc) == 0xe ?
                             (ERROR_sig(uc) >> 1) & 1 : 0,
                             &MASK_sig(uc), puc);
}

#elif defined(_ARCH_PPC)

/***********************************************************************
 * signal context platform-specific definitions
 * From Wine
 */
#ifdef linux
/* All Registers access - only for local access */
#define REG_sig(reg_name, context)              \
    ((context)->uc_mcontext.regs->reg_name)
/* Gpr Registers access  */
#define GPR_sig(reg_num, context)              REG_sig(gpr[reg_num], context)
/* Program counter */
#define IAR_sig(context)                       REG_sig(nip, context)
/* Machine State Register (Supervisor) */
#define MSR_sig(context)                       REG_sig(msr, context)
/* Count register */
#define CTR_sig(context)                       REG_sig(ctr, context)
/* User's integer exception register */
#define XER_sig(context)                       REG_sig(xer, context)
/* Link register */
#define LR_sig(context)                        REG_sig(link, context)
/* Condition register */
#define CR_sig(context)                        REG_sig(ccr, context)

/* Float Registers access  */
#define FLOAT_sig(reg_num, context)                                     \
    (((double *)((char *)((context)->uc_mcontext.regs + 48 * 4)))[reg_num])
#define FPSCR_sig(context) \
    (*(int *)((char *)((context)->uc_mcontext.regs + (48 + 32 * 2) * 4)))
/* Exception Registers access */
#define DAR_sig(context)                       REG_sig(dar, context)
#define DSISR_sig(context)                     REG_sig(dsisr, context)
#define TRAP_sig(context)                      REG_sig(trap, context)
#endif /* linux */

#if defined(__FreeBSD__) || defined(__FreeBSD_kernel__)
#include <ucontext.h>
#define IAR_sig(context)               ((context)->uc_mcontext.mc_srr0)
#define MSR_sig(context)               ((context)->uc_mcontext.mc_srr1)
#define CTR_sig(context)               ((context)->uc_mcontext.mc_ctr)
#define XER_sig(context)               ((context)->uc_mcontext.mc_xer)
#define LR_sig(context)                ((context)->uc_mcontext.mc_lr)
#define CR_sig(context)                ((context)->uc_mcontext.mc_cr)
/* Exception Registers access */
#define DAR_sig(context)               ((context)->uc_mcontext.mc_dar)
#define DSISR_sig(context)             ((context)->uc_mcontext.mc_dsisr)
#define TRAP_sig(context)              ((context)->uc_mcontext.mc_exc)
#endif /* __FreeBSD__|| __FreeBSD_kernel__ */

#ifdef __APPLE__
#include <sys/ucontext.h>
typedef struct ucontext SIGCONTEXT;
/* All Registers access - only for local access */
#define REG_sig(reg_name, context)              \
    ((context)->uc_mcontext->ss.reg_name)
#define FLOATREG_sig(reg_name, context)         \
    ((context)->uc_mcontext->fs.reg_name)
#define EXCEPREG_sig(reg_name, context)         \
    ((context)->uc_mcontext->es.reg_name)
#define VECREG_sig(reg_name, context)           \
    ((context)->uc_mcontext->vs.reg_name)
/* Gpr Registers access */
#define GPR_sig(reg_num, context)              REG_sig(r##reg_num, context)
/* Program counter */
#define IAR_sig(context)                       REG_sig(srr0, context)
/* Machine State Register (Supervisor) */
#define MSR_sig(context)                       REG_sig(srr1, context)
#define CTR_sig(context)                       REG_sig(ctr, context)
/* Link register */
#define XER_sig(context)                       REG_sig(xer, context)
/* User's integer exception register */
#define LR_sig(context)                        REG_sig(lr, context)
/* Condition register */
#define CR_sig(context)                        REG_sig(cr, context)
/* Float Registers access */
#define FLOAT_sig(reg_num, context)             \
    FLOATREG_sig(fpregs[reg_num], context)
#define FPSCR_sig(context)                      \
    ((double)FLOATREG_sig(fpscr, context))
/* Exception Registers access */
/* Fault registers for coredump */
#define DAR_sig(context)                       EXCEPREG_sig(dar, context)
#define DSISR_sig(context)                     EXCEPREG_sig(dsisr, context)
/* number of powerpc exception taken */
#define TRAP_sig(context)                      EXCEPREG_sig(exception, context)
#endif /* __APPLE__ */

int cpu_signal_handler(int host_signum, void *pinfo,
                       void *puc)
{
    siginfo_t *info = pinfo;
#if defined(__FreeBSD__) || defined(__FreeBSD_kernel__)
    ucontext_t *uc = puc;
#else
    struct ucontext *uc = puc;
#endif
    unsigned long pc;
    int is_write;

    pc = IAR_sig(uc);
    is_write = 0;
#if 0
    /* ppc 4xx case */
    if (DSISR_sig(uc) & 0x00800000) {
        is_write = 1;
    }
#else
    if (TRAP_sig(uc) != 0x400 && (DSISR_sig(uc) & 0x02000000)) {
        is_write = 1;
    }
#endif
    return handle_cpu_signal(pc, (unsigned long)info->si_addr,
                             is_write, &uc->uc_sigmask, puc);
}

#elif defined(__alpha__)

int cpu_signal_handler(int host_signum, void *pinfo,
                           void *puc)
{
    siginfo_t *info = pinfo;
    struct ucontext *uc = puc;
    uint32_t *pc = uc->uc_mcontext.sc_pc;
    uint32_t insn = *pc;
    int is_write = 0;

    /* XXX: need kernel patch to get write flag faster */
    switch (insn >> 26) {
    case 0x0d: /* stw */
    case 0x0e: /* stb */
    case 0x0f: /* stq_u */
    case 0x24: /* stf */
    case 0x25: /* stg */
    case 0x26: /* sts */
    case 0x27: /* stt */
    case 0x2c: /* stl */
    case 0x2d: /* stq */
    case 0x2e: /* stl_c */
    case 0x2f: /* stq_c */
        is_write = 1;
    }

    return handle_cpu_signal(pc, (unsigned long)info->si_addr,
                             is_write, &uc->uc_sigmask, puc);
}
#elif defined(__sparc__)

int cpu_signal_handler(int host_signum, void *pinfo,
                       void *puc)
{
    siginfo_t *info = pinfo;
    int is_write;
    uint32_t insn;
#if !defined(__arch64__) || defined(CONFIG_SOLARIS)
    uint32_t *regs = (uint32_t *)(info + 1);
    void *sigmask = (regs + 20);
    /* XXX: is there a standard glibc define ? */
    unsigned long pc = regs[1];
#else
#ifdef __linux__
    struct sigcontext *sc = puc;
    unsigned long pc = sc->sigc_regs.tpc;
    void *sigmask = (void *)sc->sigc_mask;
#elif defined(__OpenBSD__)
    struct sigcontext *uc = puc;
    unsigned long pc = uc->sc_pc;
    void *sigmask = (void *)(long)uc->sc_mask;
#endif
#endif

    /* XXX: need kernel patch to get write flag faster */
    is_write = 0;
    insn = *(uint32_t *)pc;
    if ((insn >> 30) == 3) {
        switch ((insn >> 19) & 0x3f) {
        case 0x05: /* stb */
        case 0x15: /* stba */
        case 0x06: /* sth */
        case 0x16: /* stha */
        case 0x04: /* st */
        case 0x14: /* sta */
        case 0x07: /* std */
        case 0x17: /* stda */
        case 0x0e: /* stx */
        case 0x1e: /* stxa */
        case 0x24: /* stf */
        case 0x34: /* stfa */
        case 0x27: /* stdf */
        case 0x37: /* stdfa */
        case 0x26: /* stqf */
        case 0x36: /* stqfa */
        case 0x25: /* stfsr */
        case 0x3c: /* casa */
        case 0x3e: /* casxa */
            is_write = 1;
            break;
        }
    }
    return handle_cpu_signal(pc, (unsigned long)info->si_addr,
                             is_write, sigmask, NULL);
}

#elif defined(__arm__)

int cpu_signal_handler(int host_signum, void *pinfo,
                       void *puc)
{
    siginfo_t *info = pinfo;
    struct ucontext *uc = puc;
    unsigned long pc;
    int is_write;

#if defined(__GLIBC__) && (__GLIBC__ < 2 || (__GLIBC__ == 2 && __GLIBC_MINOR__ <= 3))
    pc = uc->uc_mcontext.gregs[R15];
#else
    pc = uc->uc_mcontext.arm_pc;
#endif
    /* XXX: compute is_write */
    is_write = 0;
    return handle_cpu_signal(pc, (unsigned long)info->si_addr,
                             is_write,
                             &uc->uc_sigmask, puc);
}

#elif defined(__aarch64__)

int cpu_signal_handler(int host_signum, void *pinfo,
                       void *puc)
{
    siginfo_t *info = pinfo;
    struct ucontext *uc = puc;
    uint64_t pc;
    int is_write = 0; /* XXX how to determine? */

    pc = uc->uc_mcontext.pc;
    return handle_cpu_signal(pc, (uint64_t)info->si_addr,
                             is_write, &uc->uc_sigmask, puc);
}

#elif defined(__mc68000)

int cpu_signal_handler(int host_signum, void *pinfo,
                       void *puc)
{
    siginfo_t *info = pinfo;
    struct ucontext *uc = puc;
    unsigned long pc;
    int is_write;

    pc = uc->uc_mcontext.gregs[16];
    /* XXX: compute is_write */
    is_write = 0;
    return handle_cpu_signal(pc, (unsigned long)info->si_addr,
                             is_write,
                             &uc->uc_sigmask, puc);
}

#elif defined(__ia64)

#ifndef __ISR_VALID
  /* This ought to be in <bits/siginfo.h>... */
# define __ISR_VALID    1
#endif

int cpu_signal_handler(int host_signum, void *pinfo, void *puc)
{
    siginfo_t *info = pinfo;
    struct ucontext *uc = puc;
    unsigned long ip;
    int is_write = 0;

    ip = uc->uc_mcontext.sc_ip;
    switch (host_signum) {
    case SIGILL:
    case SIGFPE:
    case SIGSEGV:
    case SIGBUS:
    case SIGTRAP:
        if (info->si_code && (info->si_segvflags & __ISR_VALID)) {
            /* ISR.W (write-access) is bit 33:  */
            is_write = (info->si_isr >> 33) & 1;
        }
        break;

    default:
        break;
    }
    return handle_cpu_signal(ip, (unsigned long)info->si_addr,
                             is_write,
                             (sigset_t *)&uc->uc_sigmask, puc);
}

#elif defined(__s390__)

int cpu_signal_handler(int host_signum, void *pinfo,
                       void *puc)
{
    siginfo_t *info = pinfo;
    struct ucontext *uc = puc;
    unsigned long pc;
    uint16_t *pinsn;
    int is_write = 0;

    pc = uc->uc_mcontext.psw.addr;

    /* ??? On linux, the non-rt signal handler has 4 (!) arguments instead
       of the normal 2 arguments.  The 3rd argument contains the "int_code"
       from the hardware which does in fact contain the is_write value.
       The rt signal handler, as far as I can tell, does not give this value
       at all.  Not that we could get to it from here even if it were.  */
    /* ??? This is not even close to complete, since it ignores all
       of the read-modify-write instructions.  */
    pinsn = (uint16_t *)pc;
    switch (pinsn[0] >> 8) {
    case 0x50: /* ST */
    case 0x42: /* STC */
    case 0x40: /* STH */
        is_write = 1;
        break;
    case 0xc4: /* RIL format insns */
        switch (pinsn[0] & 0xf) {
        case 0xf: /* STRL */
        case 0xb: /* STGRL */
        case 0x7: /* STHRL */
            is_write = 1;
        }
        break;
    case 0xe3: /* RXY format insns */
        switch (pinsn[2] & 0xff) {
        case 0x50: /* STY */
        case 0x24: /* STG */
        case 0x72: /* STCY */
        case 0x70: /* STHY */
        case 0x8e: /* STPQ */
        case 0x3f: /* STRVH */
        case 0x3e: /* STRV */
        case 0x2f: /* STRVG */
            is_write = 1;
        }
        break;
    }
    return handle_cpu_signal(pc, (unsigned long)info->si_addr,
                             is_write, &uc->uc_sigmask, puc);
}

#elif defined(__mips__)

int cpu_signal_handler(int host_signum, void *pinfo,
                       void *puc)
{
    siginfo_t *info = pinfo;
    struct ucontext *uc = puc;
    greg_t pc = uc->uc_mcontext.pc;
    int is_write;

    /* XXX: compute is_write */
    is_write = 0;
    return handle_cpu_signal(pc, (unsigned long)info->si_addr,
                             is_write, &uc->uc_sigmask, puc);
}

#elif defined(__hppa__)

int cpu_signal_handler(int host_signum, void *pinfo,
                       void *puc)
{
    siginfo_t *info = pinfo;
    struct ucontext *uc = puc;
    unsigned long pc = uc->uc_mcontext.sc_iaoq[0];
    uint32_t insn = *(uint32_t *)pc;
    int is_write = 0;

    /* XXX: need kernel patch to get write flag faster.  */
    switch (insn >> 26) {
    case 0x1a: /* STW */
    case 0x19: /* STH */
    case 0x18: /* STB */
    case 0x1b: /* STWM */
        is_write = 1;
        break;

    case 0x09: /* CSTWX, FSTWX, FSTWS */
    case 0x0b: /* CSTDX, FSTDX, FSTDS */
        /* Distinguish from coprocessor load ... */
        is_write = (insn >> 9) & 1;
        break;

    case 0x03:
        switch ((insn >> 6) & 15) {
        case 0xa: /* STWS */
        case 0x9: /* STHS */
        case 0x8: /* STBS */
        case 0xe: /* STWAS */
        case 0xc: /* STBYS */
            is_write = 1;
        }
        break;
    }

    return handle_cpu_signal(pc, (unsigned long)info->si_addr,
                             is_write, &uc->uc_sigmask, puc);
}

#else

#error host CPU specific signal handler needed

#endif
Commit	Line	Data
42a623c7 BS	1	/*
	2	* User emulator execution
	3	*
	4	* Copyright (c) 2003-2005 Fabrice Bellard
	5	*
	6	* This library is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU Lesser General Public
	8	* License as published by the Free Software Foundation; either
	9	* version 2 of the License, or (at your option) any later version.
	10	*
	11	* This library is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	14	* Lesser General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU Lesser General Public
	17	* License along with this library; if not, see <http://www.gnu.org/licenses/>.
	18	*/
	19	#include "config.h"
3e457172	20	#include "cpu.h"
76cad711	21	#include "disas/disas.h"
42a623c7 BS	22	#include "tcg.h"
	23
	24	#undef EAX
	25	#undef ECX
	26	#undef EDX
	27	#undef EBX
	28	#undef ESP
	29	#undef EBP
	30	#undef ESI
	31	#undef EDI
	32	#undef EIP
	33	#include <signal.h>
	34	#ifdef __linux__
	35	#include <sys/ucontext.h>
	36	#endif
	37
	38	//#define DEBUG_SIGNAL
	39
9349b4f9	40	static void exception_action(CPUArchState *env1)
1162c041	41	{
42a623c7	42	#if defined(TARGET_I386)
77b2bc2c	43	raise_exception_err(env1, env1->exception_index, env1->error_code);
42a623c7	44	#else
1162c041	45	cpu_loop_exit(env1);
42a623c7	46	#endif
1162c041	47	}
42a623c7 BS	48
	49	/* exit the current TB from a signal handler. The host registers are
	50	restored in a state compatible with the CPU emulator
	51	*/
9349b4f9	52	void cpu_resume_from_signal(CPUArchState env1, void puc)
42a623c7 BS	53	{
	54	#ifdef __linux__
	55	struct ucontext *uc = puc;
	56	#elif defined(__OpenBSD__)
	57	struct sigcontext *uc = puc;
	58	#endif
	59
42a623c7 BS	60	if (puc) {
	61	/* XXX: use siglongjmp ? */
	62	#ifdef __linux__
	63	#ifdef __ia64
	64	sigprocmask(SIG_SETMASK, (sigset_t *)&uc->uc_sigmask, NULL);
	65	#else
	66	sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL);
	67	#endif
	68	#elif defined(__OpenBSD__)
	69	sigprocmask(SIG_SETMASK, &uc->sc_mask, NULL);
	70	#endif
	71	}
1846ec2c	72	env1->exception_index = -1;
6ab7e546	73	siglongjmp(env1->jmp_env, 1);
42a623c7 BS	74	}
	75
	76	/* 'pc' is the host PC at which the exception was raised. 'address' is
	77	the effective address of the memory exception. 'is_write' is 1 if a
	78	write caused the exception and otherwise 0'. 'old_set' is the
	79	signal set which should be restored */
20503968	80	static inline int handle_cpu_signal(uintptr_t pc, unsigned long address,
42a623c7 BS	81	int is_write, sigset_t *old_set,
	82	void *puc)
	83	{
4917cf44	84	CPUArchState *env;
42a623c7 BS	85	int ret;
42a623c7 BS	86
42a623c7 BS	87	#if defined(DEBUG_SIGNAL)
	88	qemu_printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
	89	pc, address, is_write, (unsigned long )old_set);
	90	#endif
	91	/* XXX: locking issue */
c5954819 PM	92	if (is_write && h2g_valid(address)
c5954819 PM	93	&& page_unprotect(h2g(address), pc, puc)) {
42a623c7 BS	94	return 1;
	95	}
	96
4917cf44	97	env = current_cpu->env_ptr;
42a623c7	98	/* see if it is an MMU fault */
4917cf44	99	ret = cpu_handle_mmu_fault(env, address, is_write, MMU_USER_IDX);
42a623c7 BS	100	if (ret < 0) {
	101	return 0; /* not an MMU fault */
	102	}
	103	if (ret == 0) {
	104	return 1; /* the MMU fault was handled without causing real CPU fault */
	105	}
	106	/* now we have a real cpu fault */
4917cf44	107	cpu_restore_state(env, pc);
42a623c7 BS	108
	109	/* we restore the process signal mask as the sigreturn should
	110	do it (XXX: use sigsetjmp) */
	111	sigprocmask(SIG_SETMASK, old_set, NULL);
4917cf44	112	exception_action(env);
42a623c7 BS	113
	114	/* never comes here */
	115	return 1;
	116	}
	117
	118	#if defined(__i386__)
	119
	120	#if defined(__APPLE__)
	121	#include <sys/ucontext.h>
	122
	123	#define EIP_sig(context) (((unsigned long )&(context)->uc_mcontext->ss.eip))
	124	#define TRAP_sig(context) ((context)->uc_mcontext->es.trapno)
	125	#define ERROR_sig(context) ((context)->uc_mcontext->es.err)
	126	#define MASK_sig(context) ((context)->uc_sigmask)
	127	#elif defined(__NetBSD__)
	128	#include <ucontext.h>
	129
	130	#define EIP_sig(context) ((context)->uc_mcontext.__gregs[_REG_EIP])
	131	#define TRAP_sig(context) ((context)->uc_mcontext.__gregs[_REG_TRAPNO])
	132	#define ERROR_sig(context) ((context)->uc_mcontext.__gregs[_REG_ERR])
	133	#define MASK_sig(context) ((context)->uc_sigmask)
	134	#elif defined(__FreeBSD__) \|\| defined(__DragonFly__)
	135	#include <ucontext.h>
	136
	137	#define EIP_sig(context) (((unsigned long )&(context)->uc_mcontext.mc_eip))
	138	#define TRAP_sig(context) ((context)->uc_mcontext.mc_trapno)
	139	#define ERROR_sig(context) ((context)->uc_mcontext.mc_err)
	140	#define MASK_sig(context) ((context)->uc_sigmask)
	141	#elif defined(__OpenBSD__)
	142	#define EIP_sig(context) ((context)->sc_eip)
	143	#define TRAP_sig(context) ((context)->sc_trapno)
	144	#define ERROR_sig(context) ((context)->sc_err)
	145	#define MASK_sig(context) ((context)->sc_mask)
	146	#else
	147	#define EIP_sig(context) ((context)->uc_mcontext.gregs[REG_EIP])
	148	#define TRAP_sig(context) ((context)->uc_mcontext.gregs[REG_TRAPNO])
	149	#define ERROR_sig(context) ((context)->uc_mcontext.gregs[REG_ERR])
	150	#define MASK_sig(context) ((context)->uc_sigmask)
	151	#endif
	152
	153	int cpu_signal_handler(int host_signum, void *pinfo,
	154	void *puc)
	155	{
	156	siginfo_t *info = pinfo;
	157	#if defined(__NetBSD__) \|\| defined(__FreeBSD__) \|\| defined(__DragonFly__)
	158	ucontext_t *uc = puc;
	159	#elif defined(__OpenBSD__)
	160	struct sigcontext *uc = puc;
	161	#else
	162	struct ucontext *uc = puc;
	163	#endif
	164	unsigned long pc;
	165	int trapno;
	166
	167	#ifndef REG_EIP
	168	/* for glibc 2.1 */
	169	#define REG_EIP EIP
	170	#define REG_ERR ERR
	171	#define REG_TRAPNO TRAPNO
	172	#endif
	173	pc = EIP_sig(uc);
	174	trapno = TRAP_sig(uc);
	175	return handle_cpu_signal(pc, (unsigned long)info->si_addr,
	176	trapno == 0xe ?
177	(ERROR_sig(uc) >> 1) & 1 : 0,
178	&MASK_sig(uc), puc);
179	}
180
181	#elif defined(__x86_64__)
182
183	#ifdef __NetBSD__
184	#define PC_sig(context) _UC_MACHINE_PC(context)
185	#define TRAP_sig(context) ((context)->uc_mcontext.__gregs[_REG_TRAPNO])
186	#define ERROR_sig(context) ((context)->uc_mcontext.__gregs[_REG_ERR])
187	#define MASK_sig(context) ((context)->uc_sigmask)
188	#elif defined(__OpenBSD__)
189	#define PC_sig(context) ((context)->sc_rip)
190	#define TRAP_sig(context) ((context)->sc_trapno)
191	#define ERROR_sig(context) ((context)->sc_err)
192	#define MASK_sig(context) ((context)->sc_mask)
193	#elif defined(__FreeBSD__) \|\| defined(__DragonFly__)
194	#include <ucontext.h>
195
196	#define PC_sig(context) (((unsigned long )&(context)->uc_mcontext.mc_rip))
197	#define TRAP_sig(context) ((context)->uc_mcontext.mc_trapno)
198	#define ERROR_sig(context) ((context)->uc_mcontext.mc_err)
199	#define MASK_sig(context) ((context)->uc_sigmask)
200	#else
201	#define PC_sig(context) ((context)->uc_mcontext.gregs[REG_RIP])
202	#define TRAP_sig(context) ((context)->uc_mcontext.gregs[REG_TRAPNO])
203	#define ERROR_sig(context) ((context)->uc_mcontext.gregs[REG_ERR])
204	#define MASK_sig(context) ((context)->uc_sigmask)
205	#endif
206
207	int cpu_signal_handler(int host_signum, void *pinfo,
208	void *puc)
209	{
210	siginfo_t *info = pinfo;
211	unsigned long pc;
212	#if defined(__NetBSD__) \|\| defined(__FreeBSD__) \|\| defined(__DragonFly__)
213	ucontext_t *uc = puc;
214	#elif defined(__OpenBSD__)
215	struct sigcontext *uc = puc;
216	#else
217	struct ucontext *uc = puc;
218	#endif
219
220	pc = PC_sig(uc);
221	return handle_cpu_signal(pc, (unsigned long)info->si_addr,
222	TRAP_sig(uc) == 0xe ?
223	(ERROR_sig(uc) >> 1) & 1 : 0,
224	&MASK_sig(uc), puc);
225	}
226
227	#elif defined(_ARCH_PPC)
228
229	/***********************************************************************
230	* signal context platform-specific definitions
231	* From Wine
232	*/
233	#ifdef linux
234	/* All Registers access - only for local access */
235	#define REG_sig(reg_name, context) \
236	((context)->uc_mcontext.regs->reg_name)
237	/* Gpr Registers access */
238	#define GPR_sig(reg_num, context) REG_sig(gpr[reg_num], context)
239	/* Program counter */
240	#define IAR_sig(context) REG_sig(nip, context)
241	/* Machine State Register (Supervisor) */
242	#define MSR_sig(context) REG_sig(msr, context)
243	/* Count register */
244	#define CTR_sig(context) REG_sig(ctr, context)
245	/* User's integer exception register */
246	#define XER_sig(context) REG_sig(xer, context)
247	/* Link register */
248	#define LR_sig(context) REG_sig(link, context)
249	/* Condition register */
250	#define CR_sig(context) REG_sig(ccr, context)
251
252	/* Float Registers access */
253	#define FLOAT_sig(reg_num, context) \
254	(((double )((char )((context)->uc_mcontext.regs + 48 * 4)))[reg_num])
255	#define FPSCR_sig(context) \
256	((int )((char )((context)->uc_mcontext.regs + (48 + 32 2) * 4)))
257	/* Exception Registers access */
258	#define DAR_sig(context) REG_sig(dar, context)
259	#define DSISR_sig(context) REG_sig(dsisr, context)
260	#define TRAP_sig(context) REG_sig(trap, context)
261	#endif /* linux */
262
263	#if defined(__FreeBSD__) \|\| defined(__FreeBSD_kernel__)
264	#include <ucontext.h>
265	#define IAR_sig(context) ((context)->uc_mcontext.mc_srr0)
266	#define MSR_sig(context) ((context)->uc_mcontext.mc_srr1)
267	#define CTR_sig(context) ((context)->uc_mcontext.mc_ctr)
268	#define XER_sig(context) ((context)->uc_mcontext.mc_xer)
269	#define LR_sig(context) ((context)->uc_mcontext.mc_lr)
270	#define CR_sig(context) ((context)->uc_mcontext.mc_cr)
271	/* Exception Registers access */
272	#define DAR_sig(context) ((context)->uc_mcontext.mc_dar)
273	#define DSISR_sig(context) ((context)->uc_mcontext.mc_dsisr)
274	#define TRAP_sig(context) ((context)->uc_mcontext.mc_exc)
275	#endif /* __FreeBSD__\|\| __FreeBSD_kernel__ */
276
277	#ifdef __APPLE__
278	#include <sys/ucontext.h>
279	typedef struct ucontext SIGCONTEXT;
280	/* All Registers access - only for local access */
281	#define REG_sig(reg_name, context) \
282	((context)->uc_mcontext->ss.reg_name)
283	#define FLOATREG_sig(reg_name, context) \
284	((context)->uc_mcontext->fs.reg_name)
285	#define EXCEPREG_sig(reg_name, context) \
286	((context)->uc_mcontext->es.reg_name)
287	#define VECREG_sig(reg_name, context) \
288	((context)->uc_mcontext->vs.reg_name)
289	/* Gpr Registers access */
290	#define GPR_sig(reg_num, context) REG_sig(r##reg_num, context)
291	/* Program counter */
292	#define IAR_sig(context) REG_sig(srr0, context)
293	/* Machine State Register (Supervisor) */
294	#define MSR_sig(context) REG_sig(srr1, context)
295	#define CTR_sig(context) REG_sig(ctr, context)
296	/* Link register */
297	#define XER_sig(context) REG_sig(xer, context)
298	/* User's integer exception register */
299	#define LR_sig(context) REG_sig(lr, context)
300	/* Condition register */
301	#define CR_sig(context) REG_sig(cr, context)
302	/* Float Registers access */
303	#define FLOAT_sig(reg_num, context) \
304	FLOATREG_sig(fpregs[reg_num], context)
305	#define FPSCR_sig(context) \
306	((double)FLOATREG_sig(fpscr, context))
307	/* Exception Registers access */
308	/* Fault registers for coredump */
309	#define DAR_sig(context) EXCEPREG_sig(dar, context)
310	#define DSISR_sig(context) EXCEPREG_sig(dsisr, context)
311	/* number of powerpc exception taken */
312	#define TRAP_sig(context) EXCEPREG_sig(exception, context)
313	#endif /* __APPLE__ */
314
315	int cpu_signal_handler(int host_signum, void *pinfo,
316	void *puc)
317	{
318	siginfo_t *info = pinfo;
319	#if defined(__FreeBSD__) \|\| defined(__FreeBSD_kernel__)
320	ucontext_t *uc = puc;
321	#else
322	struct ucontext *uc = puc;
323	#endif
324	unsigned long pc;
325	int is_write;
326
327	pc = IAR_sig(uc);
328	is_write = 0;
329	#if 0
330	/* ppc 4xx case */
331	if (DSISR_sig(uc) & 0x00800000) {
332	is_write = 1;
333	}
334	#else
335	if (TRAP_sig(uc) != 0x400 && (DSISR_sig(uc) & 0x02000000)) {
336	is_write = 1;
337	}
338	#endif
339	return handle_cpu_signal(pc, (unsigned long)info->si_addr,
340	is_write, &uc->uc_sigmask, puc);
341	}
342
343	#elif defined(__alpha__)
344
345	int cpu_signal_handler(int host_signum, void *pinfo,
346	void *puc)
347	{
348	siginfo_t *info = pinfo;
349	struct ucontext *uc = puc;
350	uint32_t *pc = uc->uc_mcontext.sc_pc;
351	uint32_t insn = *pc;
352	int is_write = 0;
353
354	/* XXX: need kernel patch to get write flag faster */
355	switch (insn >> 26) {
356	case 0x0d: /* stw */
357	case 0x0e: /* stb */
358	case 0x0f: /* stq_u */
359	case 0x24: /* stf */
360	case 0x25: /* stg */
361	case 0x26: /* sts */
362	case 0x27: /* stt */
363	case 0x2c: /* stl */
364	case 0x2d: /* stq */
365	case 0x2e: /* stl_c */
366	case 0x2f: /* stq_c */
367	is_write = 1;
368	}
369
370	return handle_cpu_signal(pc, (unsigned long)info->si_addr,
371	is_write, &uc->uc_sigmask, puc);
372	}
373	#elif defined(__sparc__)
374
375	int cpu_signal_handler(int host_signum, void *pinfo,
376	void *puc)
377	{
378	siginfo_t *info = pinfo;
379	int is_write;
380	uint32_t insn;
381	#if !defined(__arch64__) \|\| defined(CONFIG_SOLARIS)
382	uint32_t regs = (uint32_t )(info + 1);
383	void *sigmask = (regs + 20);
384	/* XXX: is there a standard glibc define ? */
385	unsigned long pc = regs[1];
386	#else
387	#ifdef __linux__
388	struct sigcontext *sc = puc;
389	unsigned long pc = sc->sigc_regs.tpc;
390	void sigmask = (void )sc->sigc_mask;
391	#elif defined(__OpenBSD__)
392	struct sigcontext *uc = puc;
393	unsigned long pc = uc->sc_pc;
394	void sigmask = (void )(long)uc->sc_mask;
395	#endif
396	#endif
397
398	/* XXX: need kernel patch to get write flag faster */
399	is_write = 0;
400	insn = (uint32_t )pc;
401	if ((insn >> 30) == 3) {
402	switch ((insn >> 19) & 0x3f) {
403	case 0x05: /* stb */
404	case 0x15: /* stba */
405	case 0x06: /* sth */
406	case 0x16: /* stha */
407	case 0x04: /* st */
408	case 0x14: /* sta */
409	case 0x07: /* std */
410	case 0x17: /* stda */
411	case 0x0e: /* stx */
412	case 0x1e: /* stxa */
413	case 0x24: /* stf */
414	case 0x34: /* stfa */
415	case 0x27: /* stdf */
416	case 0x37: /* stdfa */
417	case 0x26: /* stqf */
418	case 0x36: /* stqfa */
419	case 0x25: /* stfsr */
420	case 0x3c: /* casa */
421	case 0x3e: /* casxa */
422	is_write = 1;
423	break;
424	}
425	}
426	return handle_cpu_signal(pc, (unsigned long)info->si_addr,
427	is_write, sigmask, NULL);
428	}
429
430	#elif defined(__arm__)
431
432	int cpu_signal_handler(int host_signum, void *pinfo,
433	void *puc)
434	{
435	siginfo_t *info = pinfo;
436	struct ucontext *uc = puc;
437	unsigned long pc;
438	int is_write;
439
e12cdb1b	440	#if defined(__GLIBC__) && (__GLIBC__ < 2 \|\| (__GLIBC__ == 2 && __GLIBC_MINOR__ <= 3))
42a623c7 BS	441	pc = uc->uc_mcontext.gregs[R15];
	442	#else
	443	pc = uc->uc_mcontext.arm_pc;
	444	#endif
	445	/* XXX: compute is_write */
	446	is_write = 0;
	447	return handle_cpu_signal(pc, (unsigned long)info->si_addr,
	448	is_write,
	449	&uc->uc_sigmask, puc);
	450	}
	451
f129061c CF	452	#elif defined(__aarch64__)
	453
	454	int cpu_signal_handler(int host_signum, void *pinfo,
	455	void *puc)
	456	{
	457	siginfo_t *info = pinfo;
	458	struct ucontext *uc = puc;
	459	uint64_t pc;
	460	int is_write = 0; /* XXX how to determine? */
	461
	462	pc = uc->uc_mcontext.pc;
	463	return handle_cpu_signal(pc, (uint64_t)info->si_addr,
	464	is_write, &uc->uc_sigmask, puc);
	465	}
	466
42a623c7 BS	467	#elif defined(__mc68000)
	468
	469	int cpu_signal_handler(int host_signum, void *pinfo,
	470	void *puc)
	471	{
	472	siginfo_t *info = pinfo;
	473	struct ucontext *uc = puc;
	474	unsigned long pc;
	475	int is_write;
	476
	477	pc = uc->uc_mcontext.gregs[16];
	478	/* XXX: compute is_write */
	479	is_write = 0;
	480	return handle_cpu_signal(pc, (unsigned long)info->si_addr,
	481	is_write,
	482	&uc->uc_sigmask, puc);
	483	}
	484
	485	#elif defined(__ia64)
	486
	487	#ifndef __ISR_VALID
	488	/* This ought to be in <bits/siginfo.h>... */
	489	# define __ISR_VALID 1
	490	#endif
	491
	492	int cpu_signal_handler(int host_signum, void pinfo, void puc)
	493	{
	494	siginfo_t *info = pinfo;
	495	struct ucontext *uc = puc;
	496	unsigned long ip;
	497	int is_write = 0;
	498
	499	ip = uc->uc_mcontext.sc_ip;
	500	switch (host_signum) {
	501	case SIGILL:
	502	case SIGFPE:
	503	case SIGSEGV:
	504	case SIGBUS:
	505	case SIGTRAP:
	506	if (info->si_code && (info->si_segvflags & __ISR_VALID)) {
	507	/* ISR.W (write-access) is bit 33: */
	508	is_write = (info->si_isr >> 33) & 1;
	509	}
	510	break;
	511
	512	default:
	513	break;
	514	}
	515	return handle_cpu_signal(ip, (unsigned long)info->si_addr,
	516	is_write,
	517	(sigset_t *)&uc->uc_sigmask, puc);
	518	}
	519
	520	#elif defined(__s390__)
	521
	522	int cpu_signal_handler(int host_signum, void *pinfo,
	523	void *puc)
	524	{
	525	siginfo_t *info = pinfo;
	526	struct ucontext *uc = puc;
	527	unsigned long pc;
	528	uint16_t *pinsn;
	529	int is_write = 0;
	530
531	pc = uc->uc_mcontext.psw.addr;
532
533	/* ??? On linux, the non-rt signal handler has 4 (!) arguments instead
534	of the normal 2 arguments. The 3rd argument contains the "int_code"
535	from the hardware which does in fact contain the is_write value.
536	The rt signal handler, as far as I can tell, does not give this value
537	at all. Not that we could get to it from here even if it were. */
538	/* ??? This is not even close to complete, since it ignores all
539	of the read-modify-write instructions. */
540	pinsn = (uint16_t *)pc;
541	switch (pinsn[0] >> 8) {
542	case 0x50: /* ST */
543	case 0x42: /* STC */
544	case 0x40: /* STH */
545	is_write = 1;
546	break;
547	case 0xc4: /* RIL format insns */
548	switch (pinsn[0] & 0xf) {
549	case 0xf: /* STRL */
550	case 0xb: /* STGRL */
551	case 0x7: /* STHRL */
552	is_write = 1;
553	}
554	break;
555	case 0xe3: /* RXY format insns */
556	switch (pinsn[2] & 0xff) {
557	case 0x50: /* STY */
558	case 0x24: /* STG */
559	case 0x72: /* STCY */
560	case 0x70: /* STHY */
561	case 0x8e: /* STPQ */
562	case 0x3f: /* STRVH */
563	case 0x3e: /* STRV */
564	case 0x2f: /* STRVG */
565	is_write = 1;
566	}
567	break;
568	}
569	return handle_cpu_signal(pc, (unsigned long)info->si_addr,
570	is_write, &uc->uc_sigmask, puc);
571	}
572
573	#elif defined(__mips__)
574
575	int cpu_signal_handler(int host_signum, void *pinfo,
576	void *puc)
577	{
578	siginfo_t *info = pinfo;
579	struct ucontext *uc = puc;
580	greg_t pc = uc->uc_mcontext.pc;
581	int is_write;
582
583	/* XXX: compute is_write */
584	is_write = 0;
585	return handle_cpu_signal(pc, (unsigned long)info->si_addr,
586	is_write, &uc->uc_sigmask, puc);
587	}
588
589	#elif defined(__hppa__)
590
591	int cpu_signal_handler(int host_signum, void *pinfo,
592	void *puc)
593	{
02d2bd5d	594	siginfo_t *info = pinfo;
42a623c7 BS	595	struct ucontext *uc = puc;
	596	unsigned long pc = uc->uc_mcontext.sc_iaoq[0];
	597	uint32_t insn = (uint32_t )pc;
	598	int is_write = 0;
	599
	600	/* XXX: need kernel patch to get write flag faster. */
	601	switch (insn >> 26) {
	602	case 0x1a: /* STW */
	603	case 0x19: /* STH */
	604	case 0x18: /* STB */
	605	case 0x1b: /* STWM */
	606	is_write = 1;
	607	break;
	608
	609	case 0x09: /* CSTWX, FSTWX, FSTWS */
	610	case 0x0b: /* CSTDX, FSTDX, FSTDS */
	611	/* Distinguish from coprocessor load ... */
	612	is_write = (insn >> 9) & 1;
	613	break;
	614
	615	case 0x03:
	616	switch ((insn >> 6) & 15) {
	617	case 0xa: /* STWS */
	618	case 0x9: /* STHS */
	619	case 0x8: /* STBS */
	620	case 0xe: /* STWAS */
	621	case 0xc: /* STBYS */
	622	is_write = 1;
	623	}
	624	break;
	625	}
	626
	627	return handle_cpu_signal(pc, (unsigned long)info->si_addr,
	628	is_write, &uc->uc_sigmask, puc);
	629	}
	630
	631	#else
	632
	633	#error host CPU specific signal handler needed
	634
	635	#endif