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Commit | Line | Data |
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0824d6fc | 1 | /* |
1df912cf | 2 | * QEMU PC System Emulator |
0824d6fc | 3 | * |
1df912cf | 4 | * Copyright (c) 2003 Fabrice Bellard |
0824d6fc | 5 | * |
1df912cf FB |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
0824d6fc FB |
23 | */ |
24 | #include <stdlib.h> | |
25 | #include <stdio.h> | |
1df912cf | 26 | #include <stdarg.h> |
0824d6fc | 27 | #include <string.h> |
c45886db | 28 | #include <ctype.h> |
0824d6fc FB |
29 | #include <getopt.h> |
30 | #include <inttypes.h> | |
31 | #include <unistd.h> | |
32 | #include <sys/mman.h> | |
33 | #include <fcntl.h> | |
34 | #include <signal.h> | |
35 | #include <time.h> | |
36 | #include <sys/time.h> | |
37 | #include <malloc.h> | |
38 | #include <termios.h> | |
39 | #include <sys/poll.h> | |
40 | #include <errno.h> | |
f1510b2c FB |
41 | #include <sys/wait.h> |
42 | ||
43 | #include <sys/ioctl.h> | |
44 | #include <sys/socket.h> | |
45 | #include <linux/if.h> | |
46 | #include <linux/if_tun.h> | |
0824d6fc | 47 | |
0824d6fc | 48 | #include "disas.h" |
fc01f7e7 FB |
49 | #include "thunk.h" |
50 | ||
51 | #include "vl.h" | |
0824d6fc | 52 | |
5a67135a | 53 | #define DEFAULT_NETWORK_SCRIPT "/etc/qemu-ifup" |
330d0414 FB |
54 | #define BIOS_FILENAME "bios.bin" |
55 | #define VGABIOS_FILENAME "vgabios.bin" | |
a735aa31 | 56 | #define LINUX_BOOT_FILENAME "linux_boot.bin" |
f1510b2c | 57 | |
0824d6fc | 58 | //#define DEBUG_UNUSED_IOPORT |
330d0414 | 59 | |
c9159e53 | 60 | //#define DEBUG_IRQ_LATENCY |
0824d6fc | 61 | |
330d0414 FB |
62 | /* output Bochs bios info messages */ |
63 | //#define DEBUG_BIOS | |
64 | ||
7dea1da4 FB |
65 | //#define DEBUG_CMOS |
66 | ||
330d0414 FB |
67 | /* debug PIC */ |
68 | //#define DEBUG_PIC | |
69 | ||
70 | /* debug NE2000 card */ | |
71 | //#define DEBUG_NE2000 | |
72 | ||
73 | /* debug PC keyboard */ | |
74 | //#define DEBUG_KBD | |
75 | ||
313aa567 FB |
76 | /* debug PC keyboard : only mouse */ |
77 | //#define DEBUG_MOUSE | |
78 | ||
7dea1da4 FB |
79 | //#define DEBUG_SERIAL |
80 | ||
bb551faa | 81 | #if !defined(CONFIG_SOFTMMU) |
7916e224 | 82 | #define PHYS_RAM_MAX_SIZE (256 * 1024 * 1024) |
bb551faa FB |
83 | #else |
84 | #define PHYS_RAM_MAX_SIZE (2047 * 1024 * 1024) | |
85 | #endif | |
7916e224 | 86 | |
c45886db | 87 | #if defined (TARGET_I386) |
0824d6fc | 88 | #define KERNEL_LOAD_ADDR 0x00100000 |
c45886db FB |
89 | #elif defined (TARGET_PPC) |
90 | //#define USE_OPEN_FIRMWARE | |
3f5dcc34 | 91 | #if !defined (USE_OPEN_FIRMWARE) |
c45886db FB |
92 | #define KERNEL_LOAD_ADDR 0x01000000 |
93 | #define KERNEL_STACK_ADDR 0x01200000 | |
94 | #else | |
95 | #define KERNEL_LOAD_ADDR 0x00000000 | |
96 | #define KERNEL_STACK_ADDR 0x00400000 | |
97 | #endif | |
98 | #endif | |
77fef8c1 FB |
99 | #define INITRD_LOAD_ADDR 0x00400000 |
100 | #define KERNEL_PARAMS_ADDR 0x00090000 | |
101 | #define KERNEL_CMDLINE_ADDR 0x00099000 | |
0824d6fc | 102 | |
313aa567 FB |
103 | #define GUI_REFRESH_INTERVAL 30 |
104 | ||
7dea1da4 FB |
105 | /* XXX: use a two level table to limit memory usage */ |
106 | #define MAX_IOPORTS 65536 | |
0824d6fc | 107 | |
5a67135a | 108 | static const char *bios_dir = CONFIG_QEMU_SHAREDIR; |
0824d6fc | 109 | char phys_ram_file[1024]; |
c45886db FB |
110 | CPUState *global_env; |
111 | CPUState *cpu_single_env; | |
fc01f7e7 FB |
112 | IOPortReadFunc *ioport_read_table[3][MAX_IOPORTS]; |
113 | IOPortWriteFunc *ioport_write_table[3][MAX_IOPORTS]; | |
c45886db | 114 | BlockDriverState *bs_table[MAX_DISKS], *fd_table[MAX_FD]; |
313aa567 FB |
115 | int vga_ram_size; |
116 | static DisplayState display_state; | |
a20dd508 | 117 | int nographic; |
313aa567 FB |
118 | int term_inited; |
119 | int64_t ticks_per_sec; | |
36b486bb | 120 | int boot_device = 'c'; |
1ccde1cb | 121 | static int ram_size; |
0824d6fc FB |
122 | |
123 | /***********************************************************/ | |
124 | /* x86 io ports */ | |
125 | ||
c45886db | 126 | uint32_t default_ioport_readb(CPUState *env, uint32_t address) |
0824d6fc FB |
127 | { |
128 | #ifdef DEBUG_UNUSED_IOPORT | |
129 | fprintf(stderr, "inb: port=0x%04x\n", address); | |
130 | #endif | |
fc01f7e7 | 131 | return 0xff; |
0824d6fc FB |
132 | } |
133 | ||
c45886db | 134 | void default_ioport_writeb(CPUState *env, uint32_t address, uint32_t data) |
0824d6fc FB |
135 | { |
136 | #ifdef DEBUG_UNUSED_IOPORT | |
137 | fprintf(stderr, "outb: port=0x%04x data=0x%02x\n", address, data); | |
138 | #endif | |
139 | } | |
140 | ||
141 | /* default is to make two byte accesses */ | |
c45886db | 142 | uint32_t default_ioport_readw(CPUState *env, uint32_t address) |
0824d6fc FB |
143 | { |
144 | uint32_t data; | |
330d0414 FB |
145 | data = ioport_read_table[0][address & (MAX_IOPORTS - 1)](env, address); |
146 | data |= ioport_read_table[0][(address + 1) & (MAX_IOPORTS - 1)](env, address + 1) << 8; | |
0824d6fc FB |
147 | return data; |
148 | } | |
149 | ||
c45886db | 150 | void default_ioport_writew(CPUState *env, uint32_t address, uint32_t data) |
0824d6fc | 151 | { |
330d0414 FB |
152 | ioport_write_table[0][address & (MAX_IOPORTS - 1)](env, address, data & 0xff); |
153 | ioport_write_table[0][(address + 1) & (MAX_IOPORTS - 1)](env, address + 1, (data >> 8) & 0xff); | |
0824d6fc FB |
154 | } |
155 | ||
c45886db | 156 | uint32_t default_ioport_readl(CPUState *env, uint32_t address) |
0824d6fc | 157 | { |
fc01f7e7 FB |
158 | #ifdef DEBUG_UNUSED_IOPORT |
159 | fprintf(stderr, "inl: port=0x%04x\n", address); | |
160 | #endif | |
161 | return 0xffffffff; | |
0824d6fc FB |
162 | } |
163 | ||
c45886db | 164 | void default_ioport_writel(CPUState *env, uint32_t address, uint32_t data) |
0824d6fc | 165 | { |
fc01f7e7 FB |
166 | #ifdef DEBUG_UNUSED_IOPORT |
167 | fprintf(stderr, "outl: port=0x%04x data=0x%02x\n", address, data); | |
168 | #endif | |
0824d6fc FB |
169 | } |
170 | ||
fc01f7e7 | 171 | void init_ioports(void) |
0824d6fc FB |
172 | { |
173 | int i; | |
174 | ||
fc01f7e7 FB |
175 | for(i = 0; i < MAX_IOPORTS; i++) { |
176 | ioport_read_table[0][i] = default_ioport_readb; | |
177 | ioport_write_table[0][i] = default_ioport_writeb; | |
178 | ioport_read_table[1][i] = default_ioport_readw; | |
179 | ioport_write_table[1][i] = default_ioport_writew; | |
180 | ioport_read_table[2][i] = default_ioport_readl; | |
181 | ioport_write_table[2][i] = default_ioport_writel; | |
182 | } | |
0824d6fc FB |
183 | } |
184 | ||
fc01f7e7 FB |
185 | /* size is the word size in byte */ |
186 | int register_ioport_read(int start, int length, IOPortReadFunc *func, int size) | |
f1510b2c | 187 | { |
fc01f7e7 | 188 | int i, bsize; |
f1510b2c | 189 | |
fc01f7e7 FB |
190 | if (size == 1) |
191 | bsize = 0; | |
192 | else if (size == 2) | |
193 | bsize = 1; | |
194 | else if (size == 4) | |
195 | bsize = 2; | |
196 | else | |
197 | return -1; | |
198 | for(i = start; i < start + length; i += size) | |
199 | ioport_read_table[bsize][i] = func; | |
f1510b2c FB |
200 | return 0; |
201 | } | |
202 | ||
fc01f7e7 FB |
203 | /* size is the word size in byte */ |
204 | int register_ioport_write(int start, int length, IOPortWriteFunc *func, int size) | |
f1510b2c | 205 | { |
fc01f7e7 | 206 | int i, bsize; |
f1510b2c | 207 | |
fc01f7e7 FB |
208 | if (size == 1) |
209 | bsize = 0; | |
210 | else if (size == 2) | |
211 | bsize = 1; | |
212 | else if (size == 4) | |
213 | bsize = 2; | |
214 | else | |
215 | return -1; | |
216 | for(i = start; i < start + length; i += size) | |
217 | ioport_write_table[bsize][i] = func; | |
f1510b2c FB |
218 | return 0; |
219 | } | |
220 | ||
0824d6fc FB |
221 | void pstrcpy(char *buf, int buf_size, const char *str) |
222 | { | |
223 | int c; | |
224 | char *q = buf; | |
225 | ||
226 | if (buf_size <= 0) | |
227 | return; | |
228 | ||
229 | for(;;) { | |
230 | c = *str++; | |
231 | if (c == 0 || q >= buf + buf_size - 1) | |
232 | break; | |
233 | *q++ = c; | |
234 | } | |
235 | *q = '\0'; | |
236 | } | |
237 | ||
238 | /* strcat and truncate. */ | |
239 | char *pstrcat(char *buf, int buf_size, const char *s) | |
240 | { | |
241 | int len; | |
242 | len = strlen(buf); | |
243 | if (len < buf_size) | |
244 | pstrcpy(buf + len, buf_size - len, s); | |
245 | return buf; | |
246 | } | |
247 | ||
77fef8c1 FB |
248 | #if defined (TARGET_I386) |
249 | int load_kernel(const char *filename, uint8_t *addr, | |
250 | uint8_t *real_addr) | |
0824d6fc | 251 | { |
c45886db | 252 | int fd, size; |
c45886db | 253 | int setup_sects; |
0824d6fc FB |
254 | |
255 | fd = open(filename, O_RDONLY); | |
256 | if (fd < 0) | |
257 | return -1; | |
77fef8c1 FB |
258 | |
259 | /* load 16 bit code */ | |
260 | if (read(fd, real_addr, 512) != 512) | |
0824d6fc | 261 | goto fail; |
77fef8c1 | 262 | setup_sects = real_addr[0x1F1]; |
0824d6fc FB |
263 | if (!setup_sects) |
264 | setup_sects = 4; | |
77fef8c1 FB |
265 | if (read(fd, real_addr + 512, setup_sects * 512) != |
266 | setup_sects * 512) | |
267 | goto fail; | |
268 | ||
269 | /* load 32 bit code */ | |
0824d6fc FB |
270 | size = read(fd, addr, 16 * 1024 * 1024); |
271 | if (size < 0) | |
272 | goto fail; | |
273 | close(fd); | |
274 | return size; | |
275 | fail: | |
276 | close(fd); | |
277 | return -1; | |
278 | } | |
77fef8c1 | 279 | #endif |
0824d6fc FB |
280 | |
281 | /* return the size or -1 if error */ | |
282 | int load_image(const char *filename, uint8_t *addr) | |
283 | { | |
284 | int fd, size; | |
285 | fd = open(filename, O_RDONLY); | |
286 | if (fd < 0) | |
287 | return -1; | |
288 | size = lseek(fd, 0, SEEK_END); | |
289 | lseek(fd, 0, SEEK_SET); | |
290 | if (read(fd, addr, size) != size) { | |
291 | close(fd); | |
292 | return -1; | |
293 | } | |
294 | close(fd); | |
295 | return size; | |
296 | } | |
297 | ||
c45886db | 298 | void cpu_outb(CPUState *env, int addr, int val) |
0824d6fc | 299 | { |
fc01f7e7 | 300 | ioport_write_table[0][addr & (MAX_IOPORTS - 1)](env, addr, val); |
0824d6fc FB |
301 | } |
302 | ||
c45886db | 303 | void cpu_outw(CPUState *env, int addr, int val) |
0824d6fc | 304 | { |
fc01f7e7 | 305 | ioport_write_table[1][addr & (MAX_IOPORTS - 1)](env, addr, val); |
0824d6fc FB |
306 | } |
307 | ||
c45886db | 308 | void cpu_outl(CPUState *env, int addr, int val) |
0824d6fc | 309 | { |
fc01f7e7 | 310 | ioport_write_table[2][addr & (MAX_IOPORTS - 1)](env, addr, val); |
0824d6fc FB |
311 | } |
312 | ||
c45886db | 313 | int cpu_inb(CPUState *env, int addr) |
0824d6fc | 314 | { |
fc01f7e7 | 315 | return ioport_read_table[0][addr & (MAX_IOPORTS - 1)](env, addr); |
0824d6fc FB |
316 | } |
317 | ||
c45886db | 318 | int cpu_inw(CPUState *env, int addr) |
0824d6fc | 319 | { |
fc01f7e7 | 320 | return ioport_read_table[1][addr & (MAX_IOPORTS - 1)](env, addr); |
0824d6fc FB |
321 | } |
322 | ||
c45886db | 323 | int cpu_inl(CPUState *env, int addr) |
0824d6fc | 324 | { |
fc01f7e7 | 325 | return ioport_read_table[2][addr & (MAX_IOPORTS - 1)](env, addr); |
0824d6fc FB |
326 | } |
327 | ||
328 | /***********************************************************/ | |
c45886db | 329 | void ioport80_write(CPUState *env, uint32_t addr, uint32_t data) |
0824d6fc FB |
330 | { |
331 | } | |
332 | ||
333 | void hw_error(const char *fmt, ...) | |
334 | { | |
335 | va_list ap; | |
336 | ||
337 | va_start(ap, fmt); | |
338 | fprintf(stderr, "qemu: hardware error: "); | |
339 | vfprintf(stderr, fmt, ap); | |
340 | fprintf(stderr, "\n"); | |
341 | #ifdef TARGET_I386 | |
342 | cpu_x86_dump_state(global_env, stderr, X86_DUMP_FPU | X86_DUMP_CCOP); | |
c45886db FB |
343 | #else |
344 | cpu_dump_state(global_env, stderr, 0); | |
0824d6fc FB |
345 | #endif |
346 | va_end(ap); | |
347 | abort(); | |
348 | } | |
349 | ||
0824d6fc FB |
350 | /***********************************************************/ |
351 | /* cmos emulation */ | |
352 | ||
c45886db | 353 | #if defined (TARGET_I386) |
0824d6fc FB |
354 | #define RTC_SECONDS 0 |
355 | #define RTC_SECONDS_ALARM 1 | |
356 | #define RTC_MINUTES 2 | |
357 | #define RTC_MINUTES_ALARM 3 | |
358 | #define RTC_HOURS 4 | |
359 | #define RTC_HOURS_ALARM 5 | |
360 | #define RTC_ALARM_DONT_CARE 0xC0 | |
361 | ||
362 | #define RTC_DAY_OF_WEEK 6 | |
363 | #define RTC_DAY_OF_MONTH 7 | |
364 | #define RTC_MONTH 8 | |
365 | #define RTC_YEAR 9 | |
366 | ||
367 | #define RTC_REG_A 10 | |
368 | #define RTC_REG_B 11 | |
369 | #define RTC_REG_C 12 | |
370 | #define RTC_REG_D 13 | |
371 | ||
372 | /* PC cmos mappings */ | |
373 | #define REG_EQUIPMENT_BYTE 0x14 | |
dc887a4d | 374 | #define REG_IBM_CENTURY_BYTE 0x32 |
77fef8c1 | 375 | #define REG_IBM_PS2_CENTURY_BYTE 0x37 |
0824d6fc FB |
376 | |
377 | uint8_t cmos_data[128]; | |
378 | uint8_t cmos_index; | |
379 | ||
c45886db | 380 | void cmos_ioport_write(CPUState *env, uint32_t addr, uint32_t data) |
0824d6fc FB |
381 | { |
382 | if (addr == 0x70) { | |
383 | cmos_index = data & 0x7f; | |
7dea1da4 FB |
384 | } else { |
385 | #ifdef DEBUG_CMOS | |
386 | printf("cmos: write index=0x%02x val=0x%02x\n", | |
387 | cmos_index, data); | |
388 | #endif | |
389 | switch(addr) { | |
390 | case RTC_SECONDS_ALARM: | |
391 | case RTC_MINUTES_ALARM: | |
392 | case RTC_HOURS_ALARM: | |
393 | /* XXX: not supported */ | |
394 | cmos_data[cmos_index] = data; | |
395 | break; | |
396 | case RTC_SECONDS: | |
397 | case RTC_MINUTES: | |
398 | case RTC_HOURS: | |
399 | case RTC_DAY_OF_WEEK: | |
400 | case RTC_DAY_OF_MONTH: | |
401 | case RTC_MONTH: | |
402 | case RTC_YEAR: | |
403 | cmos_data[cmos_index] = data; | |
404 | break; | |
405 | case RTC_REG_A: | |
406 | case RTC_REG_B: | |
407 | cmos_data[cmos_index] = data; | |
408 | break; | |
409 | case RTC_REG_C: | |
410 | case RTC_REG_D: | |
411 | /* cannot write to them */ | |
412 | break; | |
413 | default: | |
414 | cmos_data[cmos_index] = data; | |
415 | break; | |
416 | } | |
0824d6fc FB |
417 | } |
418 | } | |
419 | ||
6e44ba7f FB |
420 | static inline int to_bcd(int a) |
421 | { | |
422 | return ((a / 10) << 4) | (a % 10); | |
423 | } | |
424 | ||
425 | static void cmos_update_time(void) | |
426 | { | |
427 | struct tm *tm; | |
428 | time_t ti; | |
429 | ||
430 | ti = time(NULL); | |
431 | tm = gmtime(&ti); | |
432 | cmos_data[RTC_SECONDS] = to_bcd(tm->tm_sec); | |
433 | cmos_data[RTC_MINUTES] = to_bcd(tm->tm_min); | |
434 | cmos_data[RTC_HOURS] = to_bcd(tm->tm_hour); | |
435 | cmos_data[RTC_DAY_OF_WEEK] = to_bcd(tm->tm_wday); | |
436 | cmos_data[RTC_DAY_OF_MONTH] = to_bcd(tm->tm_mday); | |
437 | cmos_data[RTC_MONTH] = to_bcd(tm->tm_mon + 1); | |
438 | cmos_data[RTC_YEAR] = to_bcd(tm->tm_year % 100); | |
439 | cmos_data[REG_IBM_CENTURY_BYTE] = to_bcd((tm->tm_year / 100) + 19); | |
77fef8c1 | 440 | cmos_data[REG_IBM_PS2_CENTURY_BYTE] = cmos_data[REG_IBM_CENTURY_BYTE]; |
6e44ba7f FB |
441 | } |
442 | ||
c45886db | 443 | uint32_t cmos_ioport_read(CPUState *env, uint32_t addr) |
0824d6fc FB |
444 | { |
445 | int ret; | |
446 | ||
447 | if (addr == 0x70) { | |
448 | return 0xff; | |
449 | } else { | |
7dea1da4 | 450 | switch(cmos_index) { |
6e44ba7f FB |
451 | case RTC_SECONDS: |
452 | case RTC_MINUTES: | |
453 | case RTC_HOURS: | |
454 | case RTC_DAY_OF_WEEK: | |
455 | case RTC_DAY_OF_MONTH: | |
456 | case RTC_MONTH: | |
457 | case RTC_YEAR: | |
458 | case REG_IBM_CENTURY_BYTE: | |
77fef8c1 | 459 | case REG_IBM_PS2_CENTURY_BYTE: |
6e44ba7f FB |
460 | cmos_update_time(); |
461 | ret = cmos_data[cmos_index]; | |
462 | break; | |
7dea1da4 | 463 | case RTC_REG_A: |
6e44ba7f | 464 | ret = cmos_data[cmos_index]; |
7dea1da4 FB |
465 | /* toggle update-in-progress bit for Linux (same hack as |
466 | plex86) */ | |
0824d6fc | 467 | cmos_data[RTC_REG_A] ^= 0x80; |
7dea1da4 FB |
468 | break; |
469 | case RTC_REG_C: | |
6e44ba7f | 470 | ret = cmos_data[cmos_index]; |
7dea1da4 | 471 | pic_set_irq(8, 0); |
0824d6fc | 472 | cmos_data[RTC_REG_C] = 0x00; |
7dea1da4 | 473 | break; |
6e44ba7f FB |
474 | default: |
475 | ret = cmos_data[cmos_index]; | |
476 | break; | |
7dea1da4 FB |
477 | } |
478 | #ifdef DEBUG_CMOS | |
479 | printf("cmos: read index=0x%02x val=0x%02x\n", | |
480 | cmos_index, ret); | |
481 | #endif | |
0824d6fc FB |
482 | return ret; |
483 | } | |
484 | } | |
485 | ||
0824d6fc FB |
486 | void cmos_init(void) |
487 | { | |
330d0414 | 488 | int val; |
0824d6fc | 489 | |
6e44ba7f | 490 | cmos_update_time(); |
0824d6fc FB |
491 | |
492 | cmos_data[RTC_REG_A] = 0x26; | |
493 | cmos_data[RTC_REG_B] = 0x02; | |
494 | cmos_data[RTC_REG_C] = 0x00; | |
495 | cmos_data[RTC_REG_D] = 0x80; | |
496 | ||
330d0414 FB |
497 | /* various important CMOS locations needed by PC/Bochs bios */ |
498 | ||
0824d6fc | 499 | cmos_data[REG_EQUIPMENT_BYTE] = 0x02; /* FPU is there */ |
313aa567 | 500 | cmos_data[REG_EQUIPMENT_BYTE] |= 0x04; /* PS/2 mouse installed */ |
0824d6fc | 501 | |
330d0414 | 502 | /* memory size */ |
1ccde1cb | 503 | val = (ram_size / 1024) - 1024; |
330d0414 FB |
504 | if (val > 65535) |
505 | val = 65535; | |
506 | cmos_data[0x17] = val; | |
507 | cmos_data[0x18] = val >> 8; | |
508 | cmos_data[0x30] = val; | |
509 | cmos_data[0x31] = val >> 8; | |
510 | ||
1ccde1cb | 511 | val = (ram_size / 65536) - ((16 * 1024 * 1024) / 65536); |
330d0414 FB |
512 | if (val > 65535) |
513 | val = 65535; | |
514 | cmos_data[0x34] = val; | |
515 | cmos_data[0x35] = val >> 8; | |
516 | ||
36b486bb FB |
517 | switch(boot_device) { |
518 | case 'a': | |
c45886db | 519 | case 'b': |
36b486bb FB |
520 | cmos_data[0x3d] = 0x01; /* floppy boot */ |
521 | break; | |
522 | default: | |
523 | case 'c': | |
524 | cmos_data[0x3d] = 0x02; /* hard drive boot */ | |
525 | break; | |
526 | case 'd': | |
527 | cmos_data[0x3d] = 0x03; /* CD-ROM boot */ | |
528 | break; | |
529 | } | |
530 | ||
fc01f7e7 FB |
531 | register_ioport_write(0x70, 2, cmos_ioport_write, 1); |
532 | register_ioport_read(0x70, 2, cmos_ioport_read, 1); | |
0824d6fc FB |
533 | } |
534 | ||
c45886db FB |
535 | void cmos_register_fd (uint8_t fd0, uint8_t fd1) |
536 | { | |
537 | int nb = 0; | |
538 | ||
539 | cmos_data[0x10] = 0; | |
540 | switch (fd0) { | |
541 | case 0: | |
542 | /* 1.44 Mb 3"5 drive */ | |
543 | cmos_data[0x10] |= 0x40; | |
544 | break; | |
545 | case 1: | |
546 | /* 2.88 Mb 3"5 drive */ | |
547 | cmos_data[0x10] |= 0x60; | |
548 | break; | |
549 | case 2: | |
550 | /* 1.2 Mb 5"5 drive */ | |
551 | cmos_data[0x10] |= 0x20; | |
552 | break; | |
553 | } | |
554 | switch (fd1) { | |
555 | case 0: | |
556 | /* 1.44 Mb 3"5 drive */ | |
557 | cmos_data[0x10] |= 0x04; | |
558 | break; | |
559 | case 1: | |
560 | /* 2.88 Mb 3"5 drive */ | |
561 | cmos_data[0x10] |= 0x06; | |
562 | break; | |
563 | case 2: | |
564 | /* 1.2 Mb 5"5 drive */ | |
565 | cmos_data[0x10] |= 0x02; | |
566 | break; | |
567 | } | |
568 | if (fd0 < 3) | |
569 | nb++; | |
570 | if (fd1 < 3) | |
571 | nb++; | |
572 | switch (nb) { | |
573 | case 0: | |
574 | break; | |
575 | case 1: | |
576 | cmos_data[REG_EQUIPMENT_BYTE] |= 0x01; /* 1 drive, ready for boot */ | |
577 | break; | |
578 | case 2: | |
579 | cmos_data[REG_EQUIPMENT_BYTE] |= 0x41; /* 2 drives, ready for boot */ | |
580 | break; | |
581 | } | |
582 | } | |
583 | #endif /* TARGET_I386 */ | |
584 | ||
0824d6fc FB |
585 | /***********************************************************/ |
586 | /* 8259 pic emulation */ | |
587 | ||
588 | typedef struct PicState { | |
589 | uint8_t last_irr; /* edge detection */ | |
590 | uint8_t irr; /* interrupt request register */ | |
591 | uint8_t imr; /* interrupt mask register */ | |
592 | uint8_t isr; /* interrupt service register */ | |
6e44ba7f | 593 | uint8_t priority_add; /* highest irq priority */ |
0824d6fc FB |
594 | uint8_t irq_base; |
595 | uint8_t read_reg_select; | |
c45886db | 596 | uint8_t poll; |
0824d6fc FB |
597 | uint8_t special_mask; |
598 | uint8_t init_state; | |
599 | uint8_t auto_eoi; | |
6e44ba7f FB |
600 | uint8_t rotate_on_auto_eoi; |
601 | uint8_t special_fully_nested_mode; | |
0824d6fc FB |
602 | uint8_t init4; /* true if 4 byte init */ |
603 | } PicState; | |
604 | ||
605 | /* 0 is master pic, 1 is slave pic */ | |
606 | PicState pics[2]; | |
607 | int pic_irq_requested; | |
608 | ||
609 | /* set irq level. If an edge is detected, then the IRR is set to 1 */ | |
610 | static inline void pic_set_irq1(PicState *s, int irq, int level) | |
611 | { | |
612 | int mask; | |
613 | mask = 1 << irq; | |
614 | if (level) { | |
615 | if ((s->last_irr & mask) == 0) | |
616 | s->irr |= mask; | |
617 | s->last_irr |= mask; | |
618 | } else { | |
619 | s->last_irr &= ~mask; | |
620 | } | |
621 | } | |
622 | ||
6e44ba7f FB |
623 | /* return the highest priority found in mask (highest = smallest |
624 | number). Return 8 if no irq */ | |
0824d6fc FB |
625 | static inline int get_priority(PicState *s, int mask) |
626 | { | |
627 | int priority; | |
628 | if (mask == 0) | |
6e44ba7f FB |
629 | return 8; |
630 | priority = 0; | |
0824d6fc | 631 | while ((mask & (1 << ((priority + s->priority_add) & 7))) == 0) |
6e44ba7f | 632 | priority++; |
0824d6fc FB |
633 | return priority; |
634 | } | |
635 | ||
636 | /* return the pic wanted interrupt. return -1 if none */ | |
637 | static int pic_get_irq(PicState *s) | |
638 | { | |
639 | int mask, cur_priority, priority; | |
640 | ||
641 | mask = s->irr & ~s->imr; | |
642 | priority = get_priority(s, mask); | |
6e44ba7f | 643 | if (priority == 8) |
0824d6fc | 644 | return -1; |
6e44ba7f FB |
645 | /* compute current priority. If special fully nested mode on the |
646 | master, the IRQ coming from the slave is not taken into account | |
647 | for the priority computation. */ | |
648 | mask = s->isr; | |
649 | if (s->special_fully_nested_mode && s == &pics[0]) | |
650 | mask &= ~(1 << 2); | |
651 | cur_priority = get_priority(s, mask); | |
652 | if (priority < cur_priority) { | |
0824d6fc | 653 | /* higher priority found: an irq should be generated */ |
6e44ba7f | 654 | return (priority + s->priority_add) & 7; |
0824d6fc FB |
655 | } else { |
656 | return -1; | |
657 | } | |
658 | } | |
659 | ||
c9159e53 FB |
660 | /* raise irq to CPU if necessary. must be called every time the active |
661 | irq may change */ | |
c45886db | 662 | void pic_update_irq(void) |
0824d6fc FB |
663 | { |
664 | int irq2, irq; | |
665 | ||
666 | /* first look at slave pic */ | |
667 | irq2 = pic_get_irq(&pics[1]); | |
668 | if (irq2 >= 0) { | |
669 | /* if irq request by slave pic, signal master PIC */ | |
670 | pic_set_irq1(&pics[0], 2, 1); | |
671 | pic_set_irq1(&pics[0], 2, 0); | |
672 | } | |
673 | /* look at requested irq */ | |
674 | irq = pic_get_irq(&pics[0]); | |
675 | if (irq >= 0) { | |
676 | if (irq == 2) { | |
677 | /* from slave pic */ | |
678 | pic_irq_requested = 8 + irq2; | |
679 | } else { | |
680 | /* from master pic */ | |
681 | pic_irq_requested = irq; | |
682 | } | |
6e44ba7f FB |
683 | #if defined(DEBUG_PIC) |
684 | { | |
685 | int i; | |
686 | for(i = 0; i < 2; i++) { | |
687 | printf("pic%d: imr=%x irr=%x padd=%d\n", | |
688 | i, pics[i].imr, pics[i].irr, pics[i].priority_add); | |
689 | ||
690 | } | |
691 | } | |
692 | printf("pic: cpu_interrupt req=%d\n", pic_irq_requested); | |
693 | #endif | |
c45886db | 694 | cpu_interrupt(global_env, CPU_INTERRUPT_HARD); |
0824d6fc FB |
695 | } |
696 | } | |
697 | ||
c9159e53 FB |
698 | #ifdef DEBUG_IRQ_LATENCY |
699 | int64_t irq_time[16]; | |
700 | int64_t cpu_get_ticks(void); | |
701 | #endif | |
313aa567 | 702 | #if defined(DEBUG_PIC) |
b118d61e FB |
703 | int irq_level[16]; |
704 | #endif | |
c9159e53 FB |
705 | |
706 | void pic_set_irq(int irq, int level) | |
707 | { | |
313aa567 | 708 | #if defined(DEBUG_PIC) |
b118d61e FB |
709 | if (level != irq_level[irq]) { |
710 | printf("pic_set_irq: irq=%d level=%d\n", irq, level); | |
711 | irq_level[irq] = level; | |
712 | } | |
713 | #endif | |
c9159e53 FB |
714 | #ifdef DEBUG_IRQ_LATENCY |
715 | if (level) { | |
716 | irq_time[irq] = cpu_get_ticks(); | |
717 | } | |
718 | #endif | |
719 | pic_set_irq1(&pics[irq >> 3], irq & 7, level); | |
720 | pic_update_irq(); | |
721 | } | |
722 | ||
6e44ba7f FB |
723 | /* acknowledge interrupt 'irq' */ |
724 | static inline void pic_intack(PicState *s, int irq) | |
725 | { | |
726 | if (s->auto_eoi) { | |
727 | if (s->rotate_on_auto_eoi) | |
728 | s->priority_add = (irq + 1) & 7; | |
729 | } else { | |
730 | s->isr |= (1 << irq); | |
731 | } | |
732 | s->irr &= ~(1 << irq); | |
733 | } | |
734 | ||
c45886db | 735 | int cpu_x86_get_pic_interrupt(CPUState *env) |
0824d6fc FB |
736 | { |
737 | int irq, irq2, intno; | |
738 | ||
739 | /* signal the pic that the irq was acked by the CPU */ | |
740 | irq = pic_irq_requested; | |
c9159e53 | 741 | #ifdef DEBUG_IRQ_LATENCY |
313aa567 FB |
742 | printf("IRQ%d latency=%0.3fus\n", |
743 | irq, | |
744 | (double)(cpu_get_ticks() - irq_time[irq]) * 1000000.0 / ticks_per_sec); | |
c9159e53 | 745 | #endif |
7dea1da4 | 746 | #if defined(DEBUG_PIC) |
b118d61e FB |
747 | printf("pic_interrupt: irq=%d\n", irq); |
748 | #endif | |
c9159e53 | 749 | |
0824d6fc FB |
750 | if (irq >= 8) { |
751 | irq2 = irq & 7; | |
6e44ba7f | 752 | pic_intack(&pics[1], irq2); |
0824d6fc FB |
753 | irq = 2; |
754 | intno = pics[1].irq_base + irq2; | |
755 | } else { | |
756 | intno = pics[0].irq_base + irq; | |
757 | } | |
6e44ba7f | 758 | pic_intack(&pics[0], irq); |
0824d6fc FB |
759 | return intno; |
760 | } | |
761 | ||
c45886db | 762 | void pic_ioport_write(CPUState *env, uint32_t addr, uint32_t val) |
0824d6fc FB |
763 | { |
764 | PicState *s; | |
6e44ba7f | 765 | int priority, cmd, irq; |
0824d6fc | 766 | |
b118d61e FB |
767 | #ifdef DEBUG_PIC |
768 | printf("pic_write: addr=0x%02x val=0x%02x\n", addr, val); | |
769 | #endif | |
0824d6fc FB |
770 | s = &pics[addr >> 7]; |
771 | addr &= 1; | |
772 | if (addr == 0) { | |
773 | if (val & 0x10) { | |
774 | /* init */ | |
775 | memset(s, 0, sizeof(PicState)); | |
776 | s->init_state = 1; | |
777 | s->init4 = val & 1; | |
778 | if (val & 0x02) | |
779 | hw_error("single mode not supported"); | |
780 | if (val & 0x08) | |
781 | hw_error("level sensitive irq not supported"); | |
782 | } else if (val & 0x08) { | |
6e44ba7f | 783 | if (val & 0x04) |
c45886db | 784 | s->poll = 1; |
0824d6fc FB |
785 | if (val & 0x02) |
786 | s->read_reg_select = val & 1; | |
787 | if (val & 0x40) | |
788 | s->special_mask = (val >> 5) & 1; | |
789 | } else { | |
6e44ba7f FB |
790 | cmd = val >> 5; |
791 | switch(cmd) { | |
792 | case 0: | |
793 | case 4: | |
794 | s->rotate_on_auto_eoi = cmd >> 2; | |
0824d6fc | 795 | break; |
6e44ba7f FB |
796 | case 1: /* end of interrupt */ |
797 | case 5: | |
0824d6fc | 798 | priority = get_priority(s, s->isr); |
6e44ba7f FB |
799 | if (priority != 8) { |
800 | irq = (priority + s->priority_add) & 7; | |
801 | s->isr &= ~(1 << irq); | |
802 | if (cmd == 5) | |
803 | s->priority_add = (irq + 1) & 7; | |
804 | pic_update_irq(); | |
0824d6fc | 805 | } |
0824d6fc | 806 | break; |
6e44ba7f FB |
807 | case 3: |
808 | irq = val & 7; | |
809 | s->isr &= ~(1 << irq); | |
313aa567 | 810 | pic_update_irq(); |
0824d6fc | 811 | break; |
6e44ba7f | 812 | case 6: |
0824d6fc | 813 | s->priority_add = (val + 1) & 7; |
313aa567 | 814 | pic_update_irq(); |
0824d6fc | 815 | break; |
6e44ba7f FB |
816 | case 7: |
817 | irq = val & 7; | |
818 | s->isr &= ~(1 << irq); | |
819 | s->priority_add = (irq + 1) & 7; | |
313aa567 | 820 | pic_update_irq(); |
0824d6fc | 821 | break; |
6e44ba7f FB |
822 | default: |
823 | /* no operation */ | |
824 | break; | |
0824d6fc FB |
825 | } |
826 | } | |
827 | } else { | |
828 | switch(s->init_state) { | |
829 | case 0: | |
830 | /* normal mode */ | |
831 | s->imr = val; | |
c9159e53 | 832 | pic_update_irq(); |
0824d6fc FB |
833 | break; |
834 | case 1: | |
835 | s->irq_base = val & 0xf8; | |
836 | s->init_state = 2; | |
837 | break; | |
838 | case 2: | |
839 | if (s->init4) { | |
840 | s->init_state = 3; | |
841 | } else { | |
842 | s->init_state = 0; | |
843 | } | |
844 | break; | |
845 | case 3: | |
6e44ba7f | 846 | s->special_fully_nested_mode = (val >> 4) & 1; |
0824d6fc FB |
847 | s->auto_eoi = (val >> 1) & 1; |
848 | s->init_state = 0; | |
849 | break; | |
850 | } | |
851 | } | |
852 | } | |
853 | ||
c45886db FB |
854 | static uint32_t pic_poll_read (PicState *s, uint32_t addr1) |
855 | { | |
856 | int ret; | |
857 | ||
858 | ret = pic_get_irq(s); | |
859 | if (ret >= 0) { | |
860 | if (addr1 >> 7) { | |
861 | pics[0].isr &= ~(1 << 2); | |
862 | pics[0].irr &= ~(1 << 2); | |
863 | } | |
864 | s->irr &= ~(1 << ret); | |
865 | s->isr &= ~(1 << ret); | |
866 | if (addr1 >> 7 || ret != 2) | |
867 | pic_update_irq(); | |
868 | } else { | |
869 | ret = 0x07; | |
870 | pic_update_irq(); | |
871 | } | |
872 | ||
873 | return ret; | |
874 | } | |
875 | ||
876 | uint32_t pic_ioport_read(CPUState *env, uint32_t addr1) | |
0824d6fc FB |
877 | { |
878 | PicState *s; | |
b118d61e FB |
879 | unsigned int addr; |
880 | int ret; | |
881 | ||
882 | addr = addr1; | |
0824d6fc FB |
883 | s = &pics[addr >> 7]; |
884 | addr &= 1; | |
6e44ba7f | 885 | if (s->poll) { |
c45886db FB |
886 | ret = pic_poll_read(s, addr1); |
887 | s->poll = 0; | |
888 | } else { | |
6e44ba7f FB |
889 | if (addr == 0) { |
890 | if (s->read_reg_select) | |
891 | ret = s->isr; | |
892 | else | |
893 | ret = s->irr; | |
894 | } else { | |
895 | ret = s->imr; | |
896 | } | |
c45886db | 897 | } |
b118d61e FB |
898 | #ifdef DEBUG_PIC |
899 | printf("pic_read: addr=0x%02x val=0x%02x\n", addr1, ret); | |
900 | #endif | |
901 | return ret; | |
0824d6fc FB |
902 | } |
903 | ||
c45886db FB |
904 | /* memory mapped interrupt status */ |
905 | uint32_t pic_intack_read(CPUState *env) | |
906 | { | |
907 | int ret; | |
908 | ||
909 | ret = pic_poll_read(&pics[0], 0x00); | |
910 | if (ret == 2) | |
911 | ret = pic_poll_read(&pics[1], 0x80) + 8; | |
912 | /* Prepare for ISR read */ | |
913 | pics[0].read_reg_select = 1; | |
914 | ||
915 | return ret; | |
916 | } | |
917 | ||
0824d6fc FB |
918 | void pic_init(void) |
919 | { | |
c45886db | 920 | #if defined (TARGET_I386) || defined (TARGET_PPC) |
fc01f7e7 FB |
921 | register_ioport_write(0x20, 2, pic_ioport_write, 1); |
922 | register_ioport_read(0x20, 2, pic_ioport_read, 1); | |
923 | register_ioport_write(0xa0, 2, pic_ioport_write, 1); | |
924 | register_ioport_read(0xa0, 2, pic_ioport_read, 1); | |
c45886db | 925 | #endif |
0824d6fc FB |
926 | } |
927 | ||
928 | /***********************************************************/ | |
929 | /* 8253 PIT emulation */ | |
930 | ||
931 | #define PIT_FREQ 1193182 | |
932 | ||
933 | #define RW_STATE_LSB 0 | |
934 | #define RW_STATE_MSB 1 | |
935 | #define RW_STATE_WORD0 2 | |
936 | #define RW_STATE_WORD1 3 | |
937 | #define RW_STATE_LATCHED_WORD0 4 | |
938 | #define RW_STATE_LATCHED_WORD1 5 | |
939 | ||
940 | typedef struct PITChannelState { | |
87858c89 | 941 | int count; /* can be 65536 */ |
0824d6fc FB |
942 | uint16_t latched_count; |
943 | uint8_t rw_state; | |
944 | uint8_t mode; | |
945 | uint8_t bcd; /* not supported */ | |
946 | uint8_t gate; /* timer start */ | |
947 | int64_t count_load_time; | |
87858c89 | 948 | int64_t count_last_edge_check_time; |
0824d6fc FB |
949 | } PITChannelState; |
950 | ||
951 | PITChannelState pit_channels[3]; | |
952 | int speaker_data_on; | |
61a2ad53 | 953 | int dummy_refresh_clock; |
87858c89 | 954 | int pit_min_timer_count = 0; |
0824d6fc | 955 | |
34865134 FB |
956 | |
957 | #if defined(__powerpc__) | |
958 | ||
959 | static inline uint32_t get_tbl(void) | |
0824d6fc | 960 | { |
34865134 FB |
961 | uint32_t tbl; |
962 | asm volatile("mftb %0" : "=r" (tbl)); | |
963 | return tbl; | |
0824d6fc FB |
964 | } |
965 | ||
34865134 FB |
966 | static inline uint32_t get_tbu(void) |
967 | { | |
968 | uint32_t tbl; | |
969 | asm volatile("mftbu %0" : "=r" (tbl)); | |
970 | return tbl; | |
971 | } | |
972 | ||
973 | int64_t cpu_get_real_ticks(void) | |
974 | { | |
975 | uint32_t l, h, h1; | |
976 | /* NOTE: we test if wrapping has occurred */ | |
977 | do { | |
978 | h = get_tbu(); | |
979 | l = get_tbl(); | |
980 | h1 = get_tbu(); | |
981 | } while (h != h1); | |
982 | return ((int64_t)h << 32) | l; | |
983 | } | |
984 | ||
985 | #elif defined(__i386__) | |
986 | ||
987 | int64_t cpu_get_real_ticks(void) | |
0824d6fc FB |
988 | { |
989 | int64_t val; | |
990 | asm("rdtsc" : "=A" (val)); | |
991 | return val; | |
992 | } | |
993 | ||
34865134 FB |
994 | #else |
995 | #error unsupported CPU | |
996 | #endif | |
997 | ||
998 | static int64_t cpu_ticks_offset; | |
999 | static int64_t cpu_ticks_last; | |
1000 | ||
1001 | int64_t cpu_get_ticks(void) | |
1002 | { | |
1003 | return cpu_get_real_ticks() + cpu_ticks_offset; | |
1004 | } | |
1005 | ||
1006 | /* enable cpu_get_ticks() */ | |
1007 | void cpu_enable_ticks(void) | |
1008 | { | |
1009 | cpu_ticks_offset = cpu_ticks_last - cpu_get_real_ticks(); | |
1010 | } | |
1011 | ||
1012 | /* disable cpu_get_ticks() : the clock is stopped. You must not call | |
1013 | cpu_get_ticks() after that. */ | |
1014 | void cpu_disable_ticks(void) | |
1015 | { | |
1016 | cpu_ticks_last = cpu_get_ticks(); | |
1017 | } | |
1018 | ||
1019 | int64_t get_clock(void) | |
1020 | { | |
1021 | struct timeval tv; | |
1022 | gettimeofday(&tv, NULL); | |
1023 | return tv.tv_sec * 1000000LL + tv.tv_usec; | |
1024 | } | |
1025 | ||
0824d6fc FB |
1026 | void cpu_calibrate_ticks(void) |
1027 | { | |
1028 | int64_t usec, ticks; | |
1029 | ||
1030 | usec = get_clock(); | |
1031 | ticks = cpu_get_ticks(); | |
1032 | usleep(50 * 1000); | |
1033 | usec = get_clock() - usec; | |
1034 | ticks = cpu_get_ticks() - ticks; | |
1035 | ticks_per_sec = (ticks * 1000000LL + (usec >> 1)) / usec; | |
1036 | } | |
1037 | ||
87858c89 FB |
1038 | /* compute with 96 bit intermediate result: (a*b)/c */ |
1039 | static uint64_t muldiv64(uint64_t a, uint32_t b, uint32_t c) | |
1040 | { | |
1041 | union { | |
1042 | uint64_t ll; | |
1043 | struct { | |
1044 | #ifdef WORDS_BIGENDIAN | |
1045 | uint32_t high, low; | |
1046 | #else | |
1047 | uint32_t low, high; | |
1048 | #endif | |
1049 | } l; | |
1050 | } u, res; | |
1051 | uint64_t rl, rh; | |
1052 | ||
1053 | u.ll = a; | |
1054 | rl = (uint64_t)u.l.low * (uint64_t)b; | |
1055 | rh = (uint64_t)u.l.high * (uint64_t)b; | |
1056 | rh += (rl >> 32); | |
1057 | res.l.high = rh / c; | |
1058 | res.l.low = (((rh % c) << 32) + (rl & 0xffffffff)) / c; | |
1059 | return res.ll; | |
1060 | } | |
1061 | ||
0824d6fc FB |
1062 | static int pit_get_count(PITChannelState *s) |
1063 | { | |
87858c89 | 1064 | uint64_t d; |
0824d6fc FB |
1065 | int counter; |
1066 | ||
87858c89 | 1067 | d = muldiv64(cpu_get_ticks() - s->count_load_time, PIT_FREQ, ticks_per_sec); |
0824d6fc FB |
1068 | switch(s->mode) { |
1069 | case 0: | |
1070 | case 1: | |
1071 | case 4: | |
1072 | case 5: | |
1073 | counter = (s->count - d) & 0xffff; | |
1074 | break; | |
c2655080 FB |
1075 | case 3: |
1076 | /* XXX: may be incorrect for odd counts */ | |
1077 | counter = s->count - ((2 * d) % s->count); | |
1078 | break; | |
0824d6fc FB |
1079 | default: |
1080 | counter = s->count - (d % s->count); | |
1081 | break; | |
1082 | } | |
1083 | return counter; | |
1084 | } | |
1085 | ||
1086 | /* get pit output bit */ | |
1087 | static int pit_get_out(PITChannelState *s) | |
1088 | { | |
87858c89 | 1089 | uint64_t d; |
0824d6fc FB |
1090 | int out; |
1091 | ||
87858c89 | 1092 | d = muldiv64(cpu_get_ticks() - s->count_load_time, PIT_FREQ, ticks_per_sec); |
0824d6fc FB |
1093 | switch(s->mode) { |
1094 | default: | |
1095 | case 0: | |
1096 | out = (d >= s->count); | |
1097 | break; | |
1098 | case 1: | |
1099 | out = (d < s->count); | |
1100 | break; | |
1101 | case 2: | |
1102 | if ((d % s->count) == 0 && d != 0) | |
1103 | out = 1; | |
1104 | else | |
1105 | out = 0; | |
1106 | break; | |
1107 | case 3: | |
c2655080 | 1108 | out = (d % s->count) < ((s->count + 1) >> 1); |
0824d6fc FB |
1109 | break; |
1110 | case 4: | |
1111 | case 5: | |
1112 | out = (d == s->count); | |
1113 | break; | |
1114 | } | |
1115 | return out; | |
1116 | } | |
1117 | ||
87858c89 FB |
1118 | /* get the number of 0 to 1 transitions we had since we call this |
1119 | function */ | |
1120 | /* XXX: maybe better to use ticks precision to avoid getting edges | |
1121 | twice if checks are done at very small intervals */ | |
1122 | static int pit_get_out_edges(PITChannelState *s) | |
1123 | { | |
1124 | uint64_t d1, d2; | |
1125 | int64_t ticks; | |
1126 | int ret, v; | |
1127 | ||
1128 | ticks = cpu_get_ticks(); | |
1129 | d1 = muldiv64(s->count_last_edge_check_time - s->count_load_time, | |
1130 | PIT_FREQ, ticks_per_sec); | |
1131 | d2 = muldiv64(ticks - s->count_load_time, | |
1132 | PIT_FREQ, ticks_per_sec); | |
1133 | s->count_last_edge_check_time = ticks; | |
1134 | switch(s->mode) { | |
1135 | default: | |
1136 | case 0: | |
1137 | if (d1 < s->count && d2 >= s->count) | |
1138 | ret = 1; | |
1139 | else | |
1140 | ret = 0; | |
1141 | break; | |
1142 | case 1: | |
1143 | ret = 0; | |
1144 | break; | |
1145 | case 2: | |
1146 | d1 /= s->count; | |
1147 | d2 /= s->count; | |
1148 | ret = d2 - d1; | |
1149 | break; | |
1150 | case 3: | |
c2655080 | 1151 | v = s->count - ((s->count + 1) >> 1); |
87858c89 FB |
1152 | d1 = (d1 + v) / s->count; |
1153 | d2 = (d2 + v) / s->count; | |
1154 | ret = d2 - d1; | |
1155 | break; | |
1156 | case 4: | |
1157 | case 5: | |
1158 | if (d1 < s->count && d2 >= s->count) | |
1159 | ret = 1; | |
1160 | else | |
1161 | ret = 0; | |
1162 | break; | |
1163 | } | |
1164 | return ret; | |
1165 | } | |
1166 | ||
c2655080 FB |
1167 | /* val must be 0 or 1 */ |
1168 | static inline void pit_set_gate(PITChannelState *s, int val) | |
1169 | { | |
1170 | switch(s->mode) { | |
1171 | default: | |
1172 | case 0: | |
1173 | case 4: | |
1174 | /* XXX: just disable/enable counting */ | |
1175 | break; | |
1176 | case 1: | |
1177 | case 5: | |
1178 | if (s->gate < val) { | |
1179 | /* restart counting on rising edge */ | |
1180 | s->count_load_time = cpu_get_ticks(); | |
1181 | s->count_last_edge_check_time = s->count_load_time; | |
1182 | } | |
1183 | break; | |
1184 | case 2: | |
1185 | case 3: | |
1186 | if (s->gate < val) { | |
1187 | /* restart counting on rising edge */ | |
1188 | s->count_load_time = cpu_get_ticks(); | |
1189 | s->count_last_edge_check_time = s->count_load_time; | |
1190 | } | |
1191 | /* XXX: disable/enable counting */ | |
1192 | break; | |
1193 | } | |
1194 | s->gate = val; | |
1195 | } | |
1196 | ||
87858c89 FB |
1197 | static inline void pit_load_count(PITChannelState *s, int val) |
1198 | { | |
1199 | if (val == 0) | |
1200 | val = 0x10000; | |
1201 | s->count_load_time = cpu_get_ticks(); | |
1202 | s->count_last_edge_check_time = s->count_load_time; | |
1203 | s->count = val; | |
1204 | if (s == &pit_channels[0] && val <= pit_min_timer_count) { | |
1205 | fprintf(stderr, | |
bb551faa | 1206 | "\nWARNING: qemu: on your system, accurate timer emulation is impossible if its frequency is more than %d Hz. If using a 2.6 guest Linux kernel, you must patch asm/param.h to change HZ from 1000 to 100.\n\n", |
87858c89 FB |
1207 | PIT_FREQ / pit_min_timer_count); |
1208 | } | |
1209 | } | |
1210 | ||
c45886db | 1211 | void pit_ioport_write(CPUState *env, uint32_t addr, uint32_t val) |
0824d6fc FB |
1212 | { |
1213 | int channel, access; | |
1214 | PITChannelState *s; | |
87858c89 | 1215 | |
0824d6fc FB |
1216 | addr &= 3; |
1217 | if (addr == 3) { | |
1218 | channel = val >> 6; | |
1219 | if (channel == 3) | |
1220 | return; | |
1221 | s = &pit_channels[channel]; | |
1222 | access = (val >> 4) & 3; | |
1223 | switch(access) { | |
1224 | case 0: | |
1225 | s->latched_count = pit_get_count(s); | |
1226 | s->rw_state = RW_STATE_LATCHED_WORD0; | |
1227 | break; | |
1228 | default: | |
87858c89 FB |
1229 | s->mode = (val >> 1) & 7; |
1230 | s->bcd = val & 1; | |
0824d6fc FB |
1231 | s->rw_state = access - 1 + RW_STATE_LSB; |
1232 | break; | |
1233 | } | |
0824d6fc FB |
1234 | } else { |
1235 | s = &pit_channels[addr]; | |
1236 | switch(s->rw_state) { | |
1237 | case RW_STATE_LSB: | |
87858c89 | 1238 | pit_load_count(s, val); |
0824d6fc FB |
1239 | break; |
1240 | case RW_STATE_MSB: | |
87858c89 | 1241 | pit_load_count(s, val << 8); |
0824d6fc FB |
1242 | break; |
1243 | case RW_STATE_WORD0: | |
1244 | case RW_STATE_WORD1: | |
1245 | if (s->rw_state & 1) { | |
87858c89 | 1246 | pit_load_count(s, (s->latched_count & 0xff) | (val << 8)); |
0824d6fc FB |
1247 | } else { |
1248 | s->latched_count = val; | |
1249 | } | |
1250 | s->rw_state ^= 1; | |
1251 | break; | |
1252 | } | |
1253 | } | |
1254 | } | |
1255 | ||
c45886db | 1256 | uint32_t pit_ioport_read(CPUState *env, uint32_t addr) |
0824d6fc FB |
1257 | { |
1258 | int ret, count; | |
1259 | PITChannelState *s; | |
1260 | ||
1261 | addr &= 3; | |
1262 | s = &pit_channels[addr]; | |
1263 | switch(s->rw_state) { | |
1264 | case RW_STATE_LSB: | |
1265 | case RW_STATE_MSB: | |
1266 | case RW_STATE_WORD0: | |
1267 | case RW_STATE_WORD1: | |
1268 | count = pit_get_count(s); | |
1269 | if (s->rw_state & 1) | |
1270 | ret = (count >> 8) & 0xff; | |
1271 | else | |
1272 | ret = count & 0xff; | |
1273 | if (s->rw_state & 2) | |
1274 | s->rw_state ^= 1; | |
1275 | break; | |
1276 | default: | |
1277 | case RW_STATE_LATCHED_WORD0: | |
1278 | case RW_STATE_LATCHED_WORD1: | |
1279 | if (s->rw_state & 1) | |
1280 | ret = s->latched_count >> 8; | |
1281 | else | |
1282 | ret = s->latched_count & 0xff; | |
1283 | s->rw_state ^= 1; | |
1284 | break; | |
1285 | } | |
1286 | return ret; | |
1287 | } | |
1288 | ||
c45886db FB |
1289 | #if defined (TARGET_I386) |
1290 | void speaker_ioport_write(CPUState *env, uint32_t addr, uint32_t val) | |
0824d6fc FB |
1291 | { |
1292 | speaker_data_on = (val >> 1) & 1; | |
c2655080 | 1293 | pit_set_gate(&pit_channels[2], val & 1); |
0824d6fc FB |
1294 | } |
1295 | ||
c45886db | 1296 | uint32_t speaker_ioport_read(CPUState *env, uint32_t addr) |
0824d6fc FB |
1297 | { |
1298 | int out; | |
1299 | out = pit_get_out(&pit_channels[2]); | |
61a2ad53 FB |
1300 | dummy_refresh_clock ^= 1; |
1301 | return (speaker_data_on << 1) | pit_channels[2].gate | (out << 5) | | |
1302 | (dummy_refresh_clock << 4); | |
0824d6fc | 1303 | } |
c45886db | 1304 | #endif |
0824d6fc FB |
1305 | |
1306 | void pit_init(void) | |
1307 | { | |
87858c89 FB |
1308 | PITChannelState *s; |
1309 | int i; | |
1310 | ||
1311 | cpu_calibrate_ticks(); | |
1312 | ||
1313 | for(i = 0;i < 3; i++) { | |
1314 | s = &pit_channels[i]; | |
1315 | s->mode = 3; | |
1316 | s->gate = (i != 2); | |
1317 | pit_load_count(s, 0); | |
1318 | } | |
1319 | ||
fc01f7e7 FB |
1320 | register_ioport_write(0x40, 4, pit_ioport_write, 1); |
1321 | register_ioport_read(0x40, 3, pit_ioport_read, 1); | |
0824d6fc | 1322 | |
c45886db | 1323 | #if defined (TARGET_I386) |
fc01f7e7 FB |
1324 | register_ioport_read(0x61, 1, speaker_ioport_read, 1); |
1325 | register_ioport_write(0x61, 1, speaker_ioport_write, 1); | |
c45886db | 1326 | #endif |
0824d6fc FB |
1327 | } |
1328 | ||
1329 | /***********************************************************/ | |
1330 | /* serial port emulation */ | |
1331 | ||
1332 | #define UART_IRQ 4 | |
1333 | ||
1334 | #define UART_LCR_DLAB 0x80 /* Divisor latch access bit */ | |
1335 | ||
1336 | #define UART_IER_MSI 0x08 /* Enable Modem status interrupt */ | |
1337 | #define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */ | |
1338 | #define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */ | |
1339 | #define UART_IER_RDI 0x01 /* Enable receiver data interrupt */ | |
1340 | ||
1341 | #define UART_IIR_NO_INT 0x01 /* No interrupts pending */ | |
1342 | #define UART_IIR_ID 0x06 /* Mask for the interrupt ID */ | |
1343 | ||
1344 | #define UART_IIR_MSI 0x00 /* Modem status interrupt */ | |
1345 | #define UART_IIR_THRI 0x02 /* Transmitter holding register empty */ | |
1346 | #define UART_IIR_RDI 0x04 /* Receiver data interrupt */ | |
1347 | #define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */ | |
1348 | ||
7dea1da4 FB |
1349 | /* |
1350 | * These are the definitions for the Modem Control Register | |
1351 | */ | |
1352 | #define UART_MCR_LOOP 0x10 /* Enable loopback test mode */ | |
1353 | #define UART_MCR_OUT2 0x08 /* Out2 complement */ | |
1354 | #define UART_MCR_OUT1 0x04 /* Out1 complement */ | |
1355 | #define UART_MCR_RTS 0x02 /* RTS complement */ | |
1356 | #define UART_MCR_DTR 0x01 /* DTR complement */ | |
1357 | ||
1358 | /* | |
1359 | * These are the definitions for the Modem Status Register | |
1360 | */ | |
1361 | #define UART_MSR_DCD 0x80 /* Data Carrier Detect */ | |
1362 | #define UART_MSR_RI 0x40 /* Ring Indicator */ | |
1363 | #define UART_MSR_DSR 0x20 /* Data Set Ready */ | |
1364 | #define UART_MSR_CTS 0x10 /* Clear to Send */ | |
1365 | #define UART_MSR_DDCD 0x08 /* Delta DCD */ | |
1366 | #define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */ | |
1367 | #define UART_MSR_DDSR 0x02 /* Delta DSR */ | |
1368 | #define UART_MSR_DCTS 0x01 /* Delta CTS */ | |
1369 | #define UART_MSR_ANY_DELTA 0x0F /* Any of the delta bits! */ | |
1370 | ||
0824d6fc FB |
1371 | #define UART_LSR_TEMT 0x40 /* Transmitter empty */ |
1372 | #define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */ | |
1373 | #define UART_LSR_BI 0x10 /* Break interrupt indicator */ | |
1374 | #define UART_LSR_FE 0x08 /* Frame error indicator */ | |
1375 | #define UART_LSR_PE 0x04 /* Parity error indicator */ | |
1376 | #define UART_LSR_OE 0x02 /* Overrun error indicator */ | |
1377 | #define UART_LSR_DR 0x01 /* Receiver data ready */ | |
1378 | ||
1379 | typedef struct SerialState { | |
1380 | uint8_t divider; | |
1381 | uint8_t rbr; /* receive register */ | |
1382 | uint8_t ier; | |
1383 | uint8_t iir; /* read only */ | |
1384 | uint8_t lcr; | |
1385 | uint8_t mcr; | |
1386 | uint8_t lsr; /* read only */ | |
1387 | uint8_t msr; | |
1388 | uint8_t scr; | |
7dea1da4 FB |
1389 | /* NOTE: this hidden state is necessary for tx irq generation as |
1390 | it can be reset while reading iir */ | |
1391 | int thr_ipending; | |
0824d6fc FB |
1392 | } SerialState; |
1393 | ||
1394 | SerialState serial_ports[1]; | |
1395 | ||
1396 | void serial_update_irq(void) | |
1397 | { | |
1398 | SerialState *s = &serial_ports[0]; | |
1399 | ||
1400 | if ((s->lsr & UART_LSR_DR) && (s->ier & UART_IER_RDI)) { | |
1401 | s->iir = UART_IIR_RDI; | |
7dea1da4 | 1402 | } else if (s->thr_ipending && (s->ier & UART_IER_THRI)) { |
0824d6fc FB |
1403 | s->iir = UART_IIR_THRI; |
1404 | } else { | |
1405 | s->iir = UART_IIR_NO_INT; | |
1406 | } | |
1407 | if (s->iir != UART_IIR_NO_INT) { | |
1408 | pic_set_irq(UART_IRQ, 1); | |
1409 | } else { | |
1410 | pic_set_irq(UART_IRQ, 0); | |
1411 | } | |
1412 | } | |
1413 | ||
c45886db | 1414 | void serial_ioport_write(CPUState *env, uint32_t addr, uint32_t val) |
0824d6fc FB |
1415 | { |
1416 | SerialState *s = &serial_ports[0]; | |
1417 | unsigned char ch; | |
1418 | int ret; | |
1419 | ||
1420 | addr &= 7; | |
7dea1da4 FB |
1421 | #ifdef DEBUG_SERIAL |
1422 | printf("serial: write addr=0x%02x val=0x%02x\n", addr, val); | |
1423 | #endif | |
0824d6fc FB |
1424 | switch(addr) { |
1425 | default: | |
1426 | case 0: | |
1427 | if (s->lcr & UART_LCR_DLAB) { | |
1428 | s->divider = (s->divider & 0xff00) | val; | |
1429 | } else { | |
7dea1da4 | 1430 | s->thr_ipending = 0; |
0824d6fc FB |
1431 | s->lsr &= ~UART_LSR_THRE; |
1432 | serial_update_irq(); | |
1433 | ||
1434 | ch = val; | |
1435 | do { | |
1436 | ret = write(1, &ch, 1); | |
1437 | } while (ret != 1); | |
7dea1da4 | 1438 | s->thr_ipending = 1; |
0824d6fc FB |
1439 | s->lsr |= UART_LSR_THRE; |
1440 | s->lsr |= UART_LSR_TEMT; | |
1441 | serial_update_irq(); | |
1442 | } | |
1443 | break; | |
1444 | case 1: | |
1445 | if (s->lcr & UART_LCR_DLAB) { | |
1446 | s->divider = (s->divider & 0x00ff) | (val << 8); | |
1447 | } else { | |
1448 | s->ier = val; | |
1449 | serial_update_irq(); | |
1450 | } | |
1451 | break; | |
1452 | case 2: | |
1453 | break; | |
1454 | case 3: | |
1455 | s->lcr = val; | |
1456 | break; | |
1457 | case 4: | |
1458 | s->mcr = val; | |
1459 | break; | |
1460 | case 5: | |
1461 | break; | |
1462 | case 6: | |
1463 | s->msr = val; | |
1464 | break; | |
1465 | case 7: | |
1466 | s->scr = val; | |
1467 | break; | |
1468 | } | |
1469 | } | |
1470 | ||
c45886db | 1471 | uint32_t serial_ioport_read(CPUState *env, uint32_t addr) |
0824d6fc FB |
1472 | { |
1473 | SerialState *s = &serial_ports[0]; | |
1474 | uint32_t ret; | |
1475 | ||
1476 | addr &= 7; | |
1477 | switch(addr) { | |
1478 | default: | |
1479 | case 0: | |
1480 | if (s->lcr & UART_LCR_DLAB) { | |
1481 | ret = s->divider & 0xff; | |
1482 | } else { | |
1483 | ret = s->rbr; | |
1484 | s->lsr &= ~(UART_LSR_DR | UART_LSR_BI); | |
1485 | serial_update_irq(); | |
1486 | } | |
1487 | break; | |
1488 | case 1: | |
1489 | if (s->lcr & UART_LCR_DLAB) { | |
1490 | ret = (s->divider >> 8) & 0xff; | |
1491 | } else { | |
1492 | ret = s->ier; | |
1493 | } | |
1494 | break; | |
1495 | case 2: | |
1496 | ret = s->iir; | |
7dea1da4 FB |
1497 | /* reset THR pending bit */ |
1498 | if ((ret & 0x7) == UART_IIR_THRI) | |
1499 | s->thr_ipending = 0; | |
1500 | serial_update_irq(); | |
0824d6fc FB |
1501 | break; |
1502 | case 3: | |
1503 | ret = s->lcr; | |
1504 | break; | |
1505 | case 4: | |
1506 | ret = s->mcr; | |
1507 | break; | |
1508 | case 5: | |
1509 | ret = s->lsr; | |
1510 | break; | |
1511 | case 6: | |
7dea1da4 FB |
1512 | if (s->mcr & UART_MCR_LOOP) { |
1513 | /* in loopback, the modem output pins are connected to the | |
1514 | inputs */ | |
1515 | ret = (s->mcr & 0x0c) << 4; | |
1516 | ret |= (s->mcr & 0x02) << 3; | |
1517 | ret |= (s->mcr & 0x01) << 5; | |
1518 | } else { | |
1519 | ret = s->msr; | |
1520 | } | |
0824d6fc FB |
1521 | break; |
1522 | case 7: | |
1523 | ret = s->scr; | |
1524 | break; | |
1525 | } | |
7dea1da4 FB |
1526 | #ifdef DEBUG_SERIAL |
1527 | printf("serial: read addr=0x%02x val=0x%02x\n", addr, ret); | |
1528 | #endif | |
0824d6fc FB |
1529 | return ret; |
1530 | } | |
1531 | ||
1532 | #define TERM_ESCAPE 0x01 /* ctrl-a is used for escape */ | |
c45886db FB |
1533 | static int term_got_escape, term_command; |
1534 | static unsigned char term_cmd_buf[128]; | |
1535 | ||
1536 | typedef struct term_cmd_t { | |
1537 | const unsigned char *name; | |
1538 | void (*handler)(unsigned char *params); | |
1539 | } term_cmd_t; | |
1540 | ||
1541 | static void do_change_cdrom (unsigned char *params); | |
1542 | static void do_change_fd0 (unsigned char *params); | |
1543 | static void do_change_fd1 (unsigned char *params); | |
1544 | ||
1545 | static term_cmd_t term_cmds[] = { | |
1546 | { "changecd", &do_change_cdrom, }, | |
1547 | { "changefd0", &do_change_fd0, }, | |
1548 | { "changefd1", &do_change_fd1, }, | |
1549 | { NULL, NULL, }, | |
1550 | }; | |
0824d6fc FB |
1551 | |
1552 | void term_print_help(void) | |
1553 | { | |
1554 | printf("\n" | |
1555 | "C-a h print this help\n" | |
1556 | "C-a x exit emulatior\n" | |
c45886db | 1557 | "C-a d switch on/off debug log\n" |
33e3963e | 1558 | "C-a s save disk data back to file (if -snapshot)\n" |
0824d6fc | 1559 | "C-a b send break (magic sysrq)\n" |
c45886db | 1560 | "C-a c send qemu internal command\n" |
0824d6fc FB |
1561 | "C-a C-a send C-a\n" |
1562 | ); | |
1563 | } | |
1564 | ||
c45886db FB |
1565 | static void do_change_cdrom (unsigned char *params) |
1566 | { | |
1567 | /* Dunno how to do it... */ | |
1568 | } | |
1569 | ||
1570 | static void do_change_fd (int fd, unsigned char *params) | |
1571 | { | |
1572 | unsigned char *name_start, *name_end, *ros; | |
1573 | int ro; | |
1574 | ||
1575 | for (name_start = params; | |
1576 | isspace(*name_start); name_start++) | |
1577 | continue; | |
1578 | if (*name_start == '\0') | |
1579 | return; | |
1580 | for (name_end = name_start; | |
1581 | !isspace(*name_end) && *name_end != '\0'; name_end++) | |
1582 | continue; | |
1583 | for (ros = name_end + 1; isspace(*ros); ros++) | |
1584 | continue; | |
1585 | if (ros[0] == 'r' && ros[1] == 'o') | |
1586 | ro = 1; | |
1587 | else | |
1588 | ro = 0; | |
1589 | *name_end = '\0'; | |
1590 | printf("Change fd %d to %s (%s)\n", fd, name_start, params); | |
1591 | fdctrl_disk_change(fd, name_start, ro); | |
1592 | } | |
1593 | ||
1594 | static void do_change_fd0 (unsigned char *params) | |
1595 | { | |
1596 | do_change_fd(0, params); | |
1597 | } | |
1598 | ||
1599 | static void do_change_fd1 (unsigned char *params) | |
1600 | { | |
1601 | do_change_fd(1, params); | |
1602 | } | |
1603 | ||
1604 | static void serial_treat_command () | |
1605 | { | |
1606 | unsigned char *cmd_start, *cmd_end; | |
1607 | int i; | |
1608 | ||
1609 | for (cmd_start = term_cmd_buf; isspace(*cmd_start); cmd_start++) | |
1610 | continue; | |
1611 | for (cmd_end = cmd_start; | |
1612 | !isspace(*cmd_end) && *cmd_end != '\0'; cmd_end++) | |
1613 | continue; | |
1614 | for (i = 0; term_cmds[i].name != NULL; i++) { | |
1615 | if (strlen(term_cmds[i].name) == (cmd_end - cmd_start) && | |
1616 | memcmp(term_cmds[i].name, cmd_start, cmd_end - cmd_start) == 0) { | |
1617 | (*term_cmds[i].handler)(cmd_end + 1); | |
1618 | return; | |
1619 | } | |
1620 | } | |
1621 | *cmd_end = '\0'; | |
1622 | printf("Unknown term command: %s\n", cmd_start); | |
1623 | } | |
1624 | ||
1625 | extern FILE *logfile; | |
1626 | ||
0824d6fc FB |
1627 | /* called when a char is received */ |
1628 | void serial_received_byte(SerialState *s, int ch) | |
1629 | { | |
c45886db FB |
1630 | if (term_command) { |
1631 | if (ch == '\n' || ch == '\r' || term_command == 127) { | |
1632 | printf("\n"); | |
1633 | serial_treat_command(); | |
1634 | term_command = 0; | |
1635 | } else { | |
1636 | if (ch == 0x7F || ch == 0x08) { | |
1637 | if (term_command > 1) { | |
1638 | term_cmd_buf[--term_command - 1] = '\0'; | |
1639 | printf("\r " | |
1640 | " "); | |
1641 | printf("\r> %s", term_cmd_buf); | |
1642 | } | |
1643 | } else if (ch > 0x1f) { | |
1644 | term_cmd_buf[term_command++ - 1] = ch; | |
1645 | term_cmd_buf[term_command - 1] = '\0'; | |
1646 | printf("\r> %s", term_cmd_buf); | |
1647 | } | |
1648 | fflush(stdout); | |
1649 | } | |
1650 | } else if (term_got_escape) { | |
0824d6fc FB |
1651 | term_got_escape = 0; |
1652 | switch(ch) { | |
1653 | case 'h': | |
1654 | term_print_help(); | |
1655 | break; | |
1656 | case 'x': | |
1657 | exit(0); | |
1658 | break; | |
33e3963e FB |
1659 | case 's': |
1660 | { | |
1661 | int i; | |
1662 | for (i = 0; i < MAX_DISKS; i++) { | |
1663 | if (bs_table[i]) | |
1664 | bdrv_commit(bs_table[i]); | |
1665 | } | |
1666 | } | |
1667 | break; | |
0824d6fc FB |
1668 | case 'b': |
1669 | /* send break */ | |
1670 | s->rbr = 0; | |
1671 | s->lsr |= UART_LSR_BI | UART_LSR_DR; | |
1672 | serial_update_irq(); | |
1673 | break; | |
c45886db FB |
1674 | case 'c': |
1675 | printf("> "); | |
1676 | fflush(stdout); | |
1677 | term_command = 1; | |
07ad1b93 | 1678 | break; |
6e44ba7f FB |
1679 | case 'd': |
1680 | cpu_set_log(CPU_LOG_ALL); | |
1681 | break; | |
0824d6fc FB |
1682 | case TERM_ESCAPE: |
1683 | goto send_char; | |
1684 | } | |
1685 | } else if (ch == TERM_ESCAPE) { | |
1686 | term_got_escape = 1; | |
1687 | } else { | |
1688 | send_char: | |
1689 | s->rbr = ch; | |
1690 | s->lsr |= UART_LSR_DR; | |
1691 | serial_update_irq(); | |
1692 | } | |
1693 | } | |
1694 | ||
0824d6fc FB |
1695 | void serial_init(void) |
1696 | { | |
1697 | SerialState *s = &serial_ports[0]; | |
1698 | ||
1699 | s->lsr = UART_LSR_TEMT | UART_LSR_THRE; | |
7dea1da4 FB |
1700 | s->iir = UART_IIR_NO_INT; |
1701 | ||
c45886db | 1702 | #if defined(TARGET_I386) || defined (TARGET_PPC) |
fc01f7e7 FB |
1703 | register_ioport_write(0x3f8, 8, serial_ioport_write, 1); |
1704 | register_ioport_read(0x3f8, 8, serial_ioport_read, 1); | |
c45886db | 1705 | #endif |
0824d6fc FB |
1706 | } |
1707 | ||
f1510b2c FB |
1708 | /***********************************************************/ |
1709 | /* ne2000 emulation */ | |
1710 | ||
c45886db | 1711 | #if defined (TARGET_I386) |
f1510b2c FB |
1712 | #define NE2000_IOPORT 0x300 |
1713 | #define NE2000_IRQ 9 | |
1714 | ||
1715 | #define MAX_ETH_FRAME_SIZE 1514 | |
1716 | ||
1717 | #define E8390_CMD 0x00 /* The command register (for all pages) */ | |
1718 | /* Page 0 register offsets. */ | |
1719 | #define EN0_CLDALO 0x01 /* Low byte of current local dma addr RD */ | |
1720 | #define EN0_STARTPG 0x01 /* Starting page of ring bfr WR */ | |
1721 | #define EN0_CLDAHI 0x02 /* High byte of current local dma addr RD */ | |
1722 | #define EN0_STOPPG 0x02 /* Ending page +1 of ring bfr WR */ | |
1723 | #define EN0_BOUNDARY 0x03 /* Boundary page of ring bfr RD WR */ | |
1724 | #define EN0_TSR 0x04 /* Transmit status reg RD */ | |
1725 | #define EN0_TPSR 0x04 /* Transmit starting page WR */ | |
1726 | #define EN0_NCR 0x05 /* Number of collision reg RD */ | |
1727 | #define EN0_TCNTLO 0x05 /* Low byte of tx byte count WR */ | |
1728 | #define EN0_FIFO 0x06 /* FIFO RD */ | |
1729 | #define EN0_TCNTHI 0x06 /* High byte of tx byte count WR */ | |
1730 | #define EN0_ISR 0x07 /* Interrupt status reg RD WR */ | |
1731 | #define EN0_CRDALO 0x08 /* low byte of current remote dma address RD */ | |
1732 | #define EN0_RSARLO 0x08 /* Remote start address reg 0 */ | |
1733 | #define EN0_CRDAHI 0x09 /* high byte, current remote dma address RD */ | |
1734 | #define EN0_RSARHI 0x09 /* Remote start address reg 1 */ | |
1735 | #define EN0_RCNTLO 0x0a /* Remote byte count reg WR */ | |
1736 | #define EN0_RCNTHI 0x0b /* Remote byte count reg WR */ | |
1737 | #define EN0_RSR 0x0c /* rx status reg RD */ | |
1738 | #define EN0_RXCR 0x0c /* RX configuration reg WR */ | |
1739 | #define EN0_TXCR 0x0d /* TX configuration reg WR */ | |
1740 | #define EN0_COUNTER0 0x0d /* Rcv alignment error counter RD */ | |
1741 | #define EN0_DCFG 0x0e /* Data configuration reg WR */ | |
1742 | #define EN0_COUNTER1 0x0e /* Rcv CRC error counter RD */ | |
1743 | #define EN0_IMR 0x0f /* Interrupt mask reg WR */ | |
1744 | #define EN0_COUNTER2 0x0f /* Rcv missed frame error counter RD */ | |
1745 | ||
1746 | #define EN1_PHYS 0x11 | |
1747 | #define EN1_CURPAG 0x17 | |
1748 | #define EN1_MULT 0x18 | |
1749 | ||
1750 | /* Register accessed at EN_CMD, the 8390 base addr. */ | |
1751 | #define E8390_STOP 0x01 /* Stop and reset the chip */ | |
1752 | #define E8390_START 0x02 /* Start the chip, clear reset */ | |
1753 | #define E8390_TRANS 0x04 /* Transmit a frame */ | |
1754 | #define E8390_RREAD 0x08 /* Remote read */ | |
1755 | #define E8390_RWRITE 0x10 /* Remote write */ | |
1756 | #define E8390_NODMA 0x20 /* Remote DMA */ | |
1757 | #define E8390_PAGE0 0x00 /* Select page chip registers */ | |
1758 | #define E8390_PAGE1 0x40 /* using the two high-order bits */ | |
1759 | #define E8390_PAGE2 0x80 /* Page 3 is invalid. */ | |
1760 | ||
1761 | /* Bits in EN0_ISR - Interrupt status register */ | |
1762 | #define ENISR_RX 0x01 /* Receiver, no error */ | |
1763 | #define ENISR_TX 0x02 /* Transmitter, no error */ | |
1764 | #define ENISR_RX_ERR 0x04 /* Receiver, with error */ | |
1765 | #define ENISR_TX_ERR 0x08 /* Transmitter, with error */ | |
1766 | #define ENISR_OVER 0x10 /* Receiver overwrote the ring */ | |
1767 | #define ENISR_COUNTERS 0x20 /* Counters need emptying */ | |
1768 | #define ENISR_RDC 0x40 /* remote dma complete */ | |
1769 | #define ENISR_RESET 0x80 /* Reset completed */ | |
1770 | #define ENISR_ALL 0x3f /* Interrupts we will enable */ | |
1771 | ||
1772 | /* Bits in received packet status byte and EN0_RSR*/ | |
1773 | #define ENRSR_RXOK 0x01 /* Received a good packet */ | |
1774 | #define ENRSR_CRC 0x02 /* CRC error */ | |
1775 | #define ENRSR_FAE 0x04 /* frame alignment error */ | |
1776 | #define ENRSR_FO 0x08 /* FIFO overrun */ | |
1777 | #define ENRSR_MPA 0x10 /* missed pkt */ | |
1778 | #define ENRSR_PHY 0x20 /* physical/multicast address */ | |
1779 | #define ENRSR_DIS 0x40 /* receiver disable. set in monitor mode */ | |
1780 | #define ENRSR_DEF 0x80 /* deferring */ | |
1781 | ||
1782 | /* Transmitted packet status, EN0_TSR. */ | |
1783 | #define ENTSR_PTX 0x01 /* Packet transmitted without error */ | |
1784 | #define ENTSR_ND 0x02 /* The transmit wasn't deferred. */ | |
1785 | #define ENTSR_COL 0x04 /* The transmit collided at least once. */ | |
1786 | #define ENTSR_ABT 0x08 /* The transmit collided 16 times, and was deferred. */ | |
1787 | #define ENTSR_CRS 0x10 /* The carrier sense was lost. */ | |
1788 | #define ENTSR_FU 0x20 /* A "FIFO underrun" occurred during transmit. */ | |
1789 | #define ENTSR_CDH 0x40 /* The collision detect "heartbeat" signal was lost. */ | |
1790 | #define ENTSR_OWC 0x80 /* There was an out-of-window collision. */ | |
1791 | ||
1792 | #define NE2000_MEM_SIZE 32768 | |
1793 | ||
1794 | typedef struct NE2000State { | |
1795 | uint8_t cmd; | |
1796 | uint32_t start; | |
1797 | uint32_t stop; | |
1798 | uint8_t boundary; | |
1799 | uint8_t tsr; | |
1800 | uint8_t tpsr; | |
1801 | uint16_t tcnt; | |
1802 | uint16_t rcnt; | |
1803 | uint32_t rsar; | |
1804 | uint8_t isr; | |
1805 | uint8_t dcfg; | |
1806 | uint8_t imr; | |
1807 | uint8_t phys[6]; /* mac address */ | |
1808 | uint8_t curpag; | |
1809 | uint8_t mult[8]; /* multicast mask array */ | |
1810 | uint8_t mem[NE2000_MEM_SIZE]; | |
1811 | } NE2000State; | |
1812 | ||
1813 | NE2000State ne2000_state; | |
1814 | int net_fd = -1; | |
1815 | char network_script[1024]; | |
1816 | ||
1817 | void ne2000_reset(void) | |
1818 | { | |
1819 | NE2000State *s = &ne2000_state; | |
1820 | int i; | |
1821 | ||
1822 | s->isr = ENISR_RESET; | |
1823 | s->mem[0] = 0x52; | |
1824 | s->mem[1] = 0x54; | |
1825 | s->mem[2] = 0x00; | |
1826 | s->mem[3] = 0x12; | |
1827 | s->mem[4] = 0x34; | |
1828 | s->mem[5] = 0x56; | |
1829 | s->mem[14] = 0x57; | |
1830 | s->mem[15] = 0x57; | |
1831 | ||
1832 | /* duplicate prom data */ | |
1833 | for(i = 15;i >= 0; i--) { | |
1834 | s->mem[2 * i] = s->mem[i]; | |
1835 | s->mem[2 * i + 1] = s->mem[i]; | |
1836 | } | |
1837 | } | |
1838 | ||
1839 | void ne2000_update_irq(NE2000State *s) | |
1840 | { | |
1841 | int isr; | |
1842 | isr = s->isr & s->imr; | |
1843 | if (isr) | |
1844 | pic_set_irq(NE2000_IRQ, 1); | |
1845 | else | |
1846 | pic_set_irq(NE2000_IRQ, 0); | |
1847 | } | |
1848 | ||
1849 | int net_init(void) | |
1850 | { | |
1851 | struct ifreq ifr; | |
1852 | int fd, ret, pid, status; | |
1853 | ||
1854 | fd = open("/dev/net/tun", O_RDWR); | |
1855 | if (fd < 0) { | |
1856 | fprintf(stderr, "warning: could not open /dev/net/tun: no virtual network emulation\n"); | |
1857 | return -1; | |
1858 | } | |
1859 | memset(&ifr, 0, sizeof(ifr)); | |
1860 | ifr.ifr_flags = IFF_TAP | IFF_NO_PI; | |
1861 | pstrcpy(ifr.ifr_name, IFNAMSIZ, "tun%d"); | |
1862 | ret = ioctl(fd, TUNSETIFF, (void *) &ifr); | |
1863 | if (ret != 0) { | |
1864 | fprintf(stderr, "warning: could not configure /dev/net/tun: no virtual network emulation\n"); | |
1865 | close(fd); | |
1866 | return -1; | |
1867 | } | |
fc01f7e7 | 1868 | printf("Connected to host network interface: %s\n", ifr.ifr_name); |
f1510b2c FB |
1869 | fcntl(fd, F_SETFL, O_NONBLOCK); |
1870 | net_fd = fd; | |
1871 | ||
1872 | /* try to launch network init script */ | |
1873 | pid = fork(); | |
1874 | if (pid >= 0) { | |
1875 | if (pid == 0) { | |
1876 | execl(network_script, network_script, ifr.ifr_name, NULL); | |
1877 | exit(1); | |
1878 | } | |
1879 | while (waitpid(pid, &status, 0) != pid); | |
1880 | if (!WIFEXITED(status) || | |
1881 | WEXITSTATUS(status) != 0) { | |
1882 | fprintf(stderr, "%s: could not launch network script for '%s'\n", | |
1883 | network_script, ifr.ifr_name); | |
1884 | } | |
1885 | } | |
1886 | return 0; | |
1887 | } | |
1888 | ||
1889 | void net_send_packet(NE2000State *s, const uint8_t *buf, int size) | |
1890 | { | |
1891 | #ifdef DEBUG_NE2000 | |
1892 | printf("NE2000: sending packet size=%d\n", size); | |
1893 | #endif | |
1894 | write(net_fd, buf, size); | |
1895 | } | |
1896 | ||
1897 | /* return true if the NE2000 can receive more data */ | |
1898 | int ne2000_can_receive(NE2000State *s) | |
1899 | { | |
1900 | int avail, index, boundary; | |
1901 | ||
1902 | if (s->cmd & E8390_STOP) | |
1903 | return 0; | |
1904 | index = s->curpag << 8; | |
1905 | boundary = s->boundary << 8; | |
1906 | if (index < boundary) | |
1907 | avail = boundary - index; | |
1908 | else | |
1909 | avail = (s->stop - s->start) - (index - boundary); | |
1910 | if (avail < (MAX_ETH_FRAME_SIZE + 4)) | |
1911 | return 0; | |
1912 | return 1; | |
1913 | } | |
1914 | ||
1915 | void ne2000_receive(NE2000State *s, uint8_t *buf, int size) | |
1916 | { | |
1917 | uint8_t *p; | |
1918 | int total_len, next, avail, len, index; | |
1919 | ||
1920 | #if defined(DEBUG_NE2000) | |
1921 | printf("NE2000: received len=%d\n", size); | |
1922 | #endif | |
1923 | ||
1924 | index = s->curpag << 8; | |
1925 | /* 4 bytes for header */ | |
1926 | total_len = size + 4; | |
1927 | /* address for next packet (4 bytes for CRC) */ | |
1928 | next = index + ((total_len + 4 + 255) & ~0xff); | |
1929 | if (next >= s->stop) | |
1930 | next -= (s->stop - s->start); | |
1931 | /* prepare packet header */ | |
1932 | p = s->mem + index; | |
1933 | p[0] = ENRSR_RXOK; /* receive status */ | |
1934 | p[1] = next >> 8; | |
1935 | p[2] = total_len; | |
1936 | p[3] = total_len >> 8; | |
1937 | index += 4; | |
1938 | ||
1939 | /* write packet data */ | |
1940 | while (size > 0) { | |
1941 | avail = s->stop - index; | |
1942 | len = size; | |
1943 | if (len > avail) | |
1944 | len = avail; | |
1945 | memcpy(s->mem + index, buf, len); | |
1946 | buf += len; | |
1947 | index += len; | |
1948 | if (index == s->stop) | |
1949 | index = s->start; | |
1950 | size -= len; | |
1951 | } | |
1952 | s->curpag = next >> 8; | |
1953 | ||
1954 | /* now we can signal we have receive something */ | |
1955 | s->isr |= ENISR_RX; | |
1956 | ne2000_update_irq(s); | |
1957 | } | |
1958 | ||
c45886db | 1959 | void ne2000_ioport_write(CPUState *env, uint32_t addr, uint32_t val) |
f1510b2c FB |
1960 | { |
1961 | NE2000State *s = &ne2000_state; | |
1962 | int offset, page; | |
1963 | ||
1964 | addr &= 0xf; | |
1965 | #ifdef DEBUG_NE2000 | |
1966 | printf("NE2000: write addr=0x%x val=0x%02x\n", addr, val); | |
1967 | #endif | |
1968 | if (addr == E8390_CMD) { | |
1969 | /* control register */ | |
1970 | s->cmd = val; | |
1971 | if (val & E8390_START) { | |
1972 | /* test specific case: zero length transfert */ | |
1973 | if ((val & (E8390_RREAD | E8390_RWRITE)) && | |
1974 | s->rcnt == 0) { | |
1975 | s->isr |= ENISR_RDC; | |
1976 | ne2000_update_irq(s); | |
1977 | } | |
1978 | if (val & E8390_TRANS) { | |
1979 | net_send_packet(s, s->mem + (s->tpsr << 8), s->tcnt); | |
1980 | /* signal end of transfert */ | |
1981 | s->tsr = ENTSR_PTX; | |
1982 | s->isr |= ENISR_TX; | |
1983 | ne2000_update_irq(s); | |
1984 | } | |
1985 | } | |
1986 | } else { | |
1987 | page = s->cmd >> 6; | |
1988 | offset = addr | (page << 4); | |
1989 | switch(offset) { | |
1990 | case EN0_STARTPG: | |
1991 | s->start = val << 8; | |
1992 | break; | |
1993 | case EN0_STOPPG: | |
1994 | s->stop = val << 8; | |
1995 | break; | |
1996 | case EN0_BOUNDARY: | |
1997 | s->boundary = val; | |
1998 | break; | |
1999 | case EN0_IMR: | |
2000 | s->imr = val; | |
2001 | ne2000_update_irq(s); | |
2002 | break; | |
2003 | case EN0_TPSR: | |
2004 | s->tpsr = val; | |
2005 | break; | |
2006 | case EN0_TCNTLO: | |
2007 | s->tcnt = (s->tcnt & 0xff00) | val; | |
2008 | break; | |
2009 | case EN0_TCNTHI: | |
2010 | s->tcnt = (s->tcnt & 0x00ff) | (val << 8); | |
2011 | break; | |
2012 | case EN0_RSARLO: | |
2013 | s->rsar = (s->rsar & 0xff00) | val; | |
2014 | break; | |
2015 | case EN0_RSARHI: | |
2016 | s->rsar = (s->rsar & 0x00ff) | (val << 8); | |
2017 | break; | |
2018 | case EN0_RCNTLO: | |
2019 | s->rcnt = (s->rcnt & 0xff00) | val; | |
2020 | break; | |
2021 | case EN0_RCNTHI: | |
2022 | s->rcnt = (s->rcnt & 0x00ff) | (val << 8); | |
2023 | break; | |
2024 | case EN0_DCFG: | |
2025 | s->dcfg = val; | |
2026 | break; | |
2027 | case EN0_ISR: | |
2028 | s->isr &= ~val; | |
2029 | ne2000_update_irq(s); | |
2030 | break; | |
2031 | case EN1_PHYS ... EN1_PHYS + 5: | |
2032 | s->phys[offset - EN1_PHYS] = val; | |
2033 | break; | |
2034 | case EN1_CURPAG: | |
2035 | s->curpag = val; | |
2036 | break; | |
2037 | case EN1_MULT ... EN1_MULT + 7: | |
2038 | s->mult[offset - EN1_MULT] = val; | |
2039 | break; | |
2040 | } | |
2041 | } | |
2042 | } | |
2043 | ||
c45886db | 2044 | uint32_t ne2000_ioport_read(CPUState *env, uint32_t addr) |
f1510b2c FB |
2045 | { |
2046 | NE2000State *s = &ne2000_state; | |
2047 | int offset, page, ret; | |
2048 | ||
2049 | addr &= 0xf; | |
2050 | if (addr == E8390_CMD) { | |
2051 | ret = s->cmd; | |
2052 | } else { | |
2053 | page = s->cmd >> 6; | |
2054 | offset = addr | (page << 4); | |
2055 | switch(offset) { | |
2056 | case EN0_TSR: | |
2057 | ret = s->tsr; | |
2058 | break; | |
2059 | case EN0_BOUNDARY: | |
2060 | ret = s->boundary; | |
2061 | break; | |
2062 | case EN0_ISR: | |
2063 | ret = s->isr; | |
2064 | break; | |
2065 | case EN1_PHYS ... EN1_PHYS + 5: | |
2066 | ret = s->phys[offset - EN1_PHYS]; | |
2067 | break; | |
2068 | case EN1_CURPAG: | |
2069 | ret = s->curpag; | |
2070 | break; | |
2071 | case EN1_MULT ... EN1_MULT + 7: | |
2072 | ret = s->mult[offset - EN1_MULT]; | |
2073 | break; | |
2074 | default: | |
2075 | ret = 0x00; | |
2076 | break; | |
2077 | } | |
2078 | } | |
2079 | #ifdef DEBUG_NE2000 | |
2080 | printf("NE2000: read addr=0x%x val=%02x\n", addr, ret); | |
2081 | #endif | |
2082 | return ret; | |
2083 | } | |
2084 | ||
c45886db | 2085 | void ne2000_asic_ioport_write(CPUState *env, uint32_t addr, uint32_t val) |
f1510b2c FB |
2086 | { |
2087 | NE2000State *s = &ne2000_state; | |
2088 | uint8_t *p; | |
2089 | ||
2090 | #ifdef DEBUG_NE2000 | |
2091 | printf("NE2000: asic write val=0x%04x\n", val); | |
2092 | #endif | |
2093 | p = s->mem + s->rsar; | |
2094 | if (s->dcfg & 0x01) { | |
2095 | /* 16 bit access */ | |
2096 | p[0] = val; | |
2097 | p[1] = val >> 8; | |
2098 | s->rsar += 2; | |
2099 | s->rcnt -= 2; | |
2100 | } else { | |
2101 | /* 8 bit access */ | |
2102 | p[0] = val; | |
2103 | s->rsar++; | |
2104 | s->rcnt--; | |
2105 | } | |
2106 | /* wrap */ | |
2107 | if (s->rsar == s->stop) | |
2108 | s->rsar = s->start; | |
2109 | if (s->rcnt == 0) { | |
2110 | /* signal end of transfert */ | |
2111 | s->isr |= ENISR_RDC; | |
2112 | ne2000_update_irq(s); | |
2113 | } | |
2114 | } | |
2115 | ||
c45886db | 2116 | uint32_t ne2000_asic_ioport_read(CPUState *env, uint32_t addr) |
f1510b2c FB |
2117 | { |
2118 | NE2000State *s = &ne2000_state; | |
2119 | uint8_t *p; | |
2120 | int ret; | |
2121 | ||
2122 | p = s->mem + s->rsar; | |
2123 | if (s->dcfg & 0x01) { | |
2124 | /* 16 bit access */ | |
2125 | ret = p[0] | (p[1] << 8); | |
2126 | s->rsar += 2; | |
2127 | s->rcnt -= 2; | |
2128 | } else { | |
2129 | /* 8 bit access */ | |
2130 | ret = p[0]; | |
2131 | s->rsar++; | |
2132 | s->rcnt--; | |
2133 | } | |
2134 | /* wrap */ | |
2135 | if (s->rsar == s->stop) | |
2136 | s->rsar = s->start; | |
2137 | if (s->rcnt == 0) { | |
2138 | /* signal end of transfert */ | |
2139 | s->isr |= ENISR_RDC; | |
2140 | ne2000_update_irq(s); | |
2141 | } | |
2142 | #ifdef DEBUG_NE2000 | |
2143 | printf("NE2000: asic read val=0x%04x\n", ret); | |
2144 | #endif | |
2145 | return ret; | |
2146 | } | |
2147 | ||
c45886db | 2148 | void ne2000_reset_ioport_write(CPUState *env, uint32_t addr, uint32_t val) |
f1510b2c FB |
2149 | { |
2150 | /* nothing to do (end of reset pulse) */ | |
2151 | } | |
2152 | ||
c45886db | 2153 | uint32_t ne2000_reset_ioport_read(CPUState *env, uint32_t addr) |
f1510b2c FB |
2154 | { |
2155 | ne2000_reset(); | |
2156 | return 0; | |
2157 | } | |
2158 | ||
2159 | void ne2000_init(void) | |
2160 | { | |
fc01f7e7 FB |
2161 | register_ioport_write(NE2000_IOPORT, 16, ne2000_ioport_write, 1); |
2162 | register_ioport_read(NE2000_IOPORT, 16, ne2000_ioport_read, 1); | |
f1510b2c | 2163 | |
fc01f7e7 FB |
2164 | register_ioport_write(NE2000_IOPORT + 0x10, 1, ne2000_asic_ioport_write, 1); |
2165 | register_ioport_read(NE2000_IOPORT + 0x10, 1, ne2000_asic_ioport_read, 1); | |
2166 | register_ioport_write(NE2000_IOPORT + 0x10, 2, ne2000_asic_ioport_write, 2); | |
2167 | register_ioport_read(NE2000_IOPORT + 0x10, 2, ne2000_asic_ioport_read, 2); | |
f1510b2c | 2168 | |
fc01f7e7 FB |
2169 | register_ioport_write(NE2000_IOPORT + 0x1f, 1, ne2000_reset_ioport_write, 1); |
2170 | register_ioport_read(NE2000_IOPORT + 0x1f, 1, ne2000_reset_ioport_read, 1); | |
f1510b2c FB |
2171 | ne2000_reset(); |
2172 | } | |
c45886db FB |
2173 | #endif |
2174 | ||
2175 | /***********************************************************/ | |
2176 | /* PC floppy disk controler emulation glue */ | |
2177 | #define PC_FDC_DMA 0x2 | |
2178 | #define PC_FDC_IRQ 0x6 | |
2179 | #define PC_FDC_BASE 0x3F0 | |
2180 | ||
2181 | static void fdctrl_register (unsigned char **disknames, int ro, | |
2182 | char boot_device) | |
2183 | { | |
2184 | int i; | |
2185 | ||
2186 | fdctrl_init(PC_FDC_IRQ, PC_FDC_DMA, 0, PC_FDC_BASE, boot_device); | |
2187 | for (i = 0; i < MAX_FD; i++) { | |
2188 | if (disknames[i] != NULL) | |
2189 | fdctrl_disk_change(i, disknames[i], ro); | |
2190 | } | |
2191 | } | |
f1510b2c | 2192 | |
cd4c3e88 | 2193 | /***********************************************************/ |
330d0414 FB |
2194 | /* keyboard emulation */ |
2195 | ||
2196 | /* Keyboard Controller Commands */ | |
2197 | #define KBD_CCMD_READ_MODE 0x20 /* Read mode bits */ | |
2198 | #define KBD_CCMD_WRITE_MODE 0x60 /* Write mode bits */ | |
2199 | #define KBD_CCMD_GET_VERSION 0xA1 /* Get controller version */ | |
2200 | #define KBD_CCMD_MOUSE_DISABLE 0xA7 /* Disable mouse interface */ | |
2201 | #define KBD_CCMD_MOUSE_ENABLE 0xA8 /* Enable mouse interface */ | |
2202 | #define KBD_CCMD_TEST_MOUSE 0xA9 /* Mouse interface test */ | |
2203 | #define KBD_CCMD_SELF_TEST 0xAA /* Controller self test */ | |
2204 | #define KBD_CCMD_KBD_TEST 0xAB /* Keyboard interface test */ | |
2205 | #define KBD_CCMD_KBD_DISABLE 0xAD /* Keyboard interface disable */ | |
2206 | #define KBD_CCMD_KBD_ENABLE 0xAE /* Keyboard interface enable */ | |
2207 | #define KBD_CCMD_READ_INPORT 0xC0 /* read input port */ | |
2208 | #define KBD_CCMD_READ_OUTPORT 0xD0 /* read output port */ | |
2209 | #define KBD_CCMD_WRITE_OUTPORT 0xD1 /* write output port */ | |
2210 | #define KBD_CCMD_WRITE_OBUF 0xD2 | |
2211 | #define KBD_CCMD_WRITE_AUX_OBUF 0xD3 /* Write to output buffer as if | |
2212 | initiated by the auxiliary device */ | |
2213 | #define KBD_CCMD_WRITE_MOUSE 0xD4 /* Write the following byte to the mouse */ | |
1f5476fc FB |
2214 | #define KBD_CCMD_DISABLE_A20 0xDD /* HP vectra only ? */ |
2215 | #define KBD_CCMD_ENABLE_A20 0xDF /* HP vectra only ? */ | |
330d0414 FB |
2216 | #define KBD_CCMD_RESET 0xFE |
2217 | ||
2218 | /* Keyboard Commands */ | |
2219 | #define KBD_CMD_SET_LEDS 0xED /* Set keyboard leds */ | |
2220 | #define KBD_CMD_ECHO 0xEE | |
07ad1b93 | 2221 | #define KBD_CMD_GET_ID 0xF2 /* get keyboard ID */ |
330d0414 FB |
2222 | #define KBD_CMD_SET_RATE 0xF3 /* Set typematic rate */ |
2223 | #define KBD_CMD_ENABLE 0xF4 /* Enable scanning */ | |
2224 | #define KBD_CMD_RESET_DISABLE 0xF5 /* reset and disable scanning */ | |
2225 | #define KBD_CMD_RESET_ENABLE 0xF6 /* reset and enable scanning */ | |
2226 | #define KBD_CMD_RESET 0xFF /* Reset */ | |
2227 | ||
2228 | /* Keyboard Replies */ | |
2229 | #define KBD_REPLY_POR 0xAA /* Power on reset */ | |
2230 | #define KBD_REPLY_ACK 0xFA /* Command ACK */ | |
2231 | #define KBD_REPLY_RESEND 0xFE /* Command NACK, send the cmd again */ | |
2232 | ||
2233 | /* Status Register Bits */ | |
2234 | #define KBD_STAT_OBF 0x01 /* Keyboard output buffer full */ | |
2235 | #define KBD_STAT_IBF 0x02 /* Keyboard input buffer full */ | |
2236 | #define KBD_STAT_SELFTEST 0x04 /* Self test successful */ | |
2237 | #define KBD_STAT_CMD 0x08 /* Last write was a command write (0=data) */ | |
2238 | #define KBD_STAT_UNLOCKED 0x10 /* Zero if keyboard locked */ | |
2239 | #define KBD_STAT_MOUSE_OBF 0x20 /* Mouse output buffer full */ | |
2240 | #define KBD_STAT_GTO 0x40 /* General receive/xmit timeout */ | |
2241 | #define KBD_STAT_PERR 0x80 /* Parity error */ | |
2242 | ||
2243 | /* Controller Mode Register Bits */ | |
2244 | #define KBD_MODE_KBD_INT 0x01 /* Keyboard data generate IRQ1 */ | |
2245 | #define KBD_MODE_MOUSE_INT 0x02 /* Mouse data generate IRQ12 */ | |
2246 | #define KBD_MODE_SYS 0x04 /* The system flag (?) */ | |
2247 | #define KBD_MODE_NO_KEYLOCK 0x08 /* The keylock doesn't affect the keyboard if set */ | |
2248 | #define KBD_MODE_DISABLE_KBD 0x10 /* Disable keyboard interface */ | |
2249 | #define KBD_MODE_DISABLE_MOUSE 0x20 /* Disable mouse interface */ | |
2250 | #define KBD_MODE_KCC 0x40 /* Scan code conversion to PC format */ | |
2251 | #define KBD_MODE_RFU 0x80 | |
2252 | ||
2253 | /* Mouse Commands */ | |
330d0414 FB |
2254 | #define AUX_SET_SCALE11 0xE6 /* Set 1:1 scaling */ |
2255 | #define AUX_SET_SCALE21 0xE7 /* Set 2:1 scaling */ | |
313aa567 | 2256 | #define AUX_SET_RES 0xE8 /* Set resolution */ |
330d0414 FB |
2257 | #define AUX_GET_SCALE 0xE9 /* Get scaling factor */ |
2258 | #define AUX_SET_STREAM 0xEA /* Set stream mode */ | |
313aa567 FB |
2259 | #define AUX_POLL 0xEB /* Poll */ |
2260 | #define AUX_RESET_WRAP 0xEC /* Reset wrap mode */ | |
2261 | #define AUX_SET_WRAP 0xEE /* Set wrap mode */ | |
2262 | #define AUX_SET_REMOTE 0xF0 /* Set remote mode */ | |
2263 | #define AUX_GET_TYPE 0xF2 /* Get type */ | |
330d0414 FB |
2264 | #define AUX_SET_SAMPLE 0xF3 /* Set sample rate */ |
2265 | #define AUX_ENABLE_DEV 0xF4 /* Enable aux device */ | |
2266 | #define AUX_DISABLE_DEV 0xF5 /* Disable aux device */ | |
313aa567 | 2267 | #define AUX_SET_DEFAULT 0xF6 |
330d0414 FB |
2268 | #define AUX_RESET 0xFF /* Reset aux device */ |
2269 | #define AUX_ACK 0xFA /* Command byte ACK. */ | |
2270 | ||
313aa567 FB |
2271 | #define MOUSE_STATUS_REMOTE 0x40 |
2272 | #define MOUSE_STATUS_ENABLED 0x20 | |
2273 | #define MOUSE_STATUS_SCALE21 0x10 | |
2274 | ||
2275 | #define KBD_QUEUE_SIZE 256 | |
330d0414 FB |
2276 | |
2277 | typedef struct { | |
2278 | uint8_t data[KBD_QUEUE_SIZE]; | |
2279 | int rptr, wptr, count; | |
2280 | } KBDQueue; | |
2281 | ||
330d0414 FB |
2282 | typedef struct KBDState { |
2283 | KBDQueue queues[2]; | |
2284 | uint8_t write_cmd; /* if non zero, write data to port 60 is expected */ | |
2285 | uint8_t status; | |
2286 | uint8_t mode; | |
313aa567 | 2287 | /* keyboard state */ |
330d0414 FB |
2288 | int kbd_write_cmd; |
2289 | int scan_enabled; | |
313aa567 FB |
2290 | /* mouse state */ |
2291 | int mouse_write_cmd; | |
2292 | uint8_t mouse_status; | |
2293 | uint8_t mouse_resolution; | |
2294 | uint8_t mouse_sample_rate; | |
2295 | uint8_t mouse_wrap; | |
2296 | uint8_t mouse_type; /* 0 = PS2, 3 = IMPS/2, 4 = IMEX */ | |
2297 | uint8_t mouse_detect_state; | |
2298 | int mouse_dx; /* current values, needed for 'poll' mode */ | |
2299 | int mouse_dy; | |
2300 | int mouse_dz; | |
2301 | uint8_t mouse_buttons; | |
330d0414 FB |
2302 | } KBDState; |
2303 | ||
2304 | KBDState kbd_state; | |
cd4c3e88 | 2305 | int reset_requested; |
330d0414 | 2306 | |
313aa567 | 2307 | /* update irq and KBD_STAT_[MOUSE_]OBF */ |
07ad1b93 FB |
2308 | /* XXX: not generating the irqs if KBD_MODE_DISABLE_KBD is set may be |
2309 | incorrect, but it avoids having to simulate exact delays */ | |
330d0414 FB |
2310 | static void kbd_update_irq(KBDState *s) |
2311 | { | |
313aa567 FB |
2312 | int irq12_level, irq1_level; |
2313 | ||
2314 | irq1_level = 0; | |
2315 | irq12_level = 0; | |
2316 | s->status &= ~(KBD_STAT_OBF | KBD_STAT_MOUSE_OBF); | |
2317 | if (s->queues[0].count != 0 || | |
2318 | s->queues[1].count != 0) { | |
2319 | s->status |= KBD_STAT_OBF; | |
2320 | if (s->queues[1].count != 0) { | |
2321 | s->status |= KBD_STAT_MOUSE_OBF; | |
2322 | if (s->mode & KBD_MODE_MOUSE_INT) | |
2323 | irq12_level = 1; | |
2324 | } else { | |
07ad1b93 FB |
2325 | if ((s->mode & KBD_MODE_KBD_INT) && |
2326 | !(s->mode & KBD_MODE_DISABLE_KBD)) | |
313aa567 FB |
2327 | irq1_level = 1; |
2328 | } | |
2329 | } | |
2330 | pic_set_irq(1, irq1_level); | |
2331 | pic_set_irq(12, irq12_level); | |
330d0414 FB |
2332 | } |
2333 | ||
2334 | static void kbd_queue(KBDState *s, int b, int aux) | |
2335 | { | |
2336 | KBDQueue *q = &kbd_state.queues[aux]; | |
2337 | ||
313aa567 FB |
2338 | #if defined(DEBUG_MOUSE) || defined(DEBUG_KBD) |
2339 | if (aux) | |
2340 | printf("mouse event: 0x%02x\n", b); | |
2341 | #ifdef DEBUG_KBD | |
2342 | else | |
2343 | printf("kbd event: 0x%02x\n", b); | |
2344 | #endif | |
2345 | #endif | |
330d0414 FB |
2346 | if (q->count >= KBD_QUEUE_SIZE) |
2347 | return; | |
2348 | q->data[q->wptr] = b; | |
2349 | if (++q->wptr == KBD_QUEUE_SIZE) | |
2350 | q->wptr = 0; | |
2351 | q->count++; | |
330d0414 FB |
2352 | kbd_update_irq(s); |
2353 | } | |
cd4c3e88 | 2354 | |
313aa567 FB |
2355 | void kbd_put_keycode(int keycode) |
2356 | { | |
2357 | KBDState *s = &kbd_state; | |
2358 | kbd_queue(s, keycode, 0); | |
2359 | } | |
2360 | ||
c45886db | 2361 | uint32_t kbd_read_status(CPUState *env, uint32_t addr) |
cd4c3e88 | 2362 | { |
330d0414 FB |
2363 | KBDState *s = &kbd_state; |
2364 | int val; | |
2365 | val = s->status; | |
c45886db | 2366 | #if defined(DEBUG_KBD) |
330d0414 FB |
2367 | printf("kbd: read status=0x%02x\n", val); |
2368 | #endif | |
2369 | return val; | |
cd4c3e88 FB |
2370 | } |
2371 | ||
c45886db | 2372 | void kbd_write_command(CPUState *env, uint32_t addr, uint32_t val) |
cd4c3e88 | 2373 | { |
330d0414 FB |
2374 | KBDState *s = &kbd_state; |
2375 | ||
2376 | #ifdef DEBUG_KBD | |
2377 | printf("kbd: write cmd=0x%02x\n", val); | |
2378 | #endif | |
cd4c3e88 | 2379 | switch(val) { |
330d0414 FB |
2380 | case KBD_CCMD_READ_MODE: |
2381 | kbd_queue(s, s->mode, 0); | |
2382 | break; | |
2383 | case KBD_CCMD_WRITE_MODE: | |
2384 | case KBD_CCMD_WRITE_OBUF: | |
2385 | case KBD_CCMD_WRITE_AUX_OBUF: | |
2386 | case KBD_CCMD_WRITE_MOUSE: | |
2387 | case KBD_CCMD_WRITE_OUTPORT: | |
2388 | s->write_cmd = val; | |
2389 | break; | |
2390 | case KBD_CCMD_MOUSE_DISABLE: | |
2391 | s->mode |= KBD_MODE_DISABLE_MOUSE; | |
2392 | break; | |
2393 | case KBD_CCMD_MOUSE_ENABLE: | |
2394 | s->mode &= ~KBD_MODE_DISABLE_MOUSE; | |
2395 | break; | |
2396 | case KBD_CCMD_TEST_MOUSE: | |
2397 | kbd_queue(s, 0x00, 0); | |
2398 | break; | |
2399 | case KBD_CCMD_SELF_TEST: | |
2400 | s->status |= KBD_STAT_SELFTEST; | |
2401 | kbd_queue(s, 0x55, 0); | |
2402 | break; | |
2403 | case KBD_CCMD_KBD_TEST: | |
2404 | kbd_queue(s, 0x00, 0); | |
2405 | break; | |
2406 | case KBD_CCMD_KBD_DISABLE: | |
2407 | s->mode |= KBD_MODE_DISABLE_KBD; | |
07ad1b93 | 2408 | kbd_update_irq(s); |
330d0414 FB |
2409 | break; |
2410 | case KBD_CCMD_KBD_ENABLE: | |
2411 | s->mode &= ~KBD_MODE_DISABLE_KBD; | |
07ad1b93 | 2412 | kbd_update_irq(s); |
330d0414 FB |
2413 | break; |
2414 | case KBD_CCMD_READ_INPORT: | |
2415 | kbd_queue(s, 0x00, 0); | |
2416 | break; | |
2417 | case KBD_CCMD_READ_OUTPORT: | |
2418 | /* XXX: check that */ | |
c45886db | 2419 | #ifdef TARGET_I386 |
415e561f | 2420 | val = 0x01 | (((cpu_single_env->a20_mask >> 20) & 1) << 1); |
c45886db FB |
2421 | #else |
2422 | val = 0x01; | |
2423 | #endif | |
330d0414 FB |
2424 | if (s->status & KBD_STAT_OBF) |
2425 | val |= 0x10; | |
2426 | if (s->status & KBD_STAT_MOUSE_OBF) | |
2427 | val |= 0x20; | |
2428 | kbd_queue(s, val, 0); | |
2429 | break; | |
c45886db | 2430 | #ifdef TARGET_I386 |
330d0414 | 2431 | case KBD_CCMD_ENABLE_A20: |
1f5476fc | 2432 | cpu_x86_set_a20(env, 1); |
330d0414 FB |
2433 | break; |
2434 | case KBD_CCMD_DISABLE_A20: | |
1f5476fc | 2435 | cpu_x86_set_a20(env, 0); |
330d0414 | 2436 | break; |
c45886db | 2437 | #endif |
330d0414 | 2438 | case KBD_CCMD_RESET: |
cd4c3e88 | 2439 | reset_requested = 1; |
c45886db | 2440 | cpu_interrupt(global_env, CPU_INTERRUPT_EXIT); |
cd4c3e88 | 2441 | break; |
27503323 FB |
2442 | case 0xff: |
2443 | /* ignore that - I don't know what is its use */ | |
2444 | break; | |
330d0414 | 2445 | default: |
36b486bb | 2446 | fprintf(stderr, "qemu: unsupported keyboard cmd=0x%02x\n", val); |
330d0414 FB |
2447 | break; |
2448 | } | |
2449 | } | |
2450 | ||
c45886db | 2451 | uint32_t kbd_read_data(CPUState *env, uint32_t addr) |
330d0414 FB |
2452 | { |
2453 | KBDState *s = &kbd_state; | |
2454 | KBDQueue *q; | |
7dea1da4 | 2455 | int val, index; |
330d0414 | 2456 | |
313aa567 | 2457 | q = &s->queues[0]; /* first check KBD data */ |
330d0414 | 2458 | if (q->count == 0) |
313aa567 | 2459 | q = &s->queues[1]; /* then check AUX data */ |
330d0414 | 2460 | if (q->count == 0) { |
7dea1da4 FB |
2461 | /* NOTE: if no data left, we return the last keyboard one |
2462 | (needed for EMM386) */ | |
2463 | /* XXX: need a timer to do things correctly */ | |
2464 | q = &s->queues[0]; | |
2465 | index = q->rptr - 1; | |
2466 | if (index < 0) | |
2467 | index = KBD_QUEUE_SIZE - 1; | |
2468 | val = q->data[index]; | |
330d0414 FB |
2469 | } else { |
2470 | val = q->data[q->rptr]; | |
2471 | if (++q->rptr == KBD_QUEUE_SIZE) | |
2472 | q->rptr = 0; | |
2473 | q->count--; | |
313aa567 FB |
2474 | /* reading deasserts IRQ */ |
2475 | if (q == &s->queues[0]) | |
2476 | pic_set_irq(1, 0); | |
2477 | else | |
2478 | pic_set_irq(12, 0); | |
330d0414 | 2479 | } |
313aa567 FB |
2480 | /* reassert IRQs if data left */ |
2481 | kbd_update_irq(s); | |
330d0414 FB |
2482 | #ifdef DEBUG_KBD |
2483 | printf("kbd: read data=0x%02x\n", val); | |
2484 | #endif | |
2485 | return val; | |
2486 | } | |
2487 | ||
2488 | static void kbd_reset_keyboard(KBDState *s) | |
2489 | { | |
2490 | s->scan_enabled = 1; | |
2491 | } | |
2492 | ||
2493 | static void kbd_write_keyboard(KBDState *s, int val) | |
2494 | { | |
2495 | switch(s->kbd_write_cmd) { | |
2496 | default: | |
2497 | case -1: | |
2498 | switch(val) { | |
2499 | case 0x00: | |
2500 | kbd_queue(s, KBD_REPLY_ACK, 0); | |
2501 | break; | |
2502 | case 0x05: | |
2503 | kbd_queue(s, KBD_REPLY_RESEND, 0); | |
2504 | break; | |
07ad1b93 FB |
2505 | case KBD_CMD_GET_ID: |
2506 | kbd_queue(s, KBD_REPLY_ACK, 0); | |
2507 | kbd_queue(s, 0xab, 0); | |
2508 | kbd_queue(s, 0x83, 0); | |
2509 | break; | |
330d0414 FB |
2510 | case KBD_CMD_ECHO: |
2511 | kbd_queue(s, KBD_CMD_ECHO, 0); | |
2512 | break; | |
2513 | case KBD_CMD_ENABLE: | |
2514 | s->scan_enabled = 1; | |
2515 | kbd_queue(s, KBD_REPLY_ACK, 0); | |
2516 | break; | |
2517 | case KBD_CMD_SET_LEDS: | |
2518 | case KBD_CMD_SET_RATE: | |
2519 | s->kbd_write_cmd = val; | |
1f5476fc | 2520 | kbd_queue(s, KBD_REPLY_ACK, 0); |
330d0414 FB |
2521 | break; |
2522 | case KBD_CMD_RESET_DISABLE: | |
2523 | kbd_reset_keyboard(s); | |
2524 | s->scan_enabled = 0; | |
2525 | kbd_queue(s, KBD_REPLY_ACK, 0); | |
2526 | break; | |
2527 | case KBD_CMD_RESET_ENABLE: | |
2528 | kbd_reset_keyboard(s); | |
2529 | s->scan_enabled = 1; | |
2530 | kbd_queue(s, KBD_REPLY_ACK, 0); | |
2531 | break; | |
2532 | case KBD_CMD_RESET: | |
2533 | kbd_reset_keyboard(s); | |
2534 | kbd_queue(s, KBD_REPLY_ACK, 0); | |
2535 | kbd_queue(s, KBD_REPLY_POR, 0); | |
2536 | break; | |
2537 | default: | |
2538 | kbd_queue(s, KBD_REPLY_ACK, 0); | |
2539 | break; | |
2540 | } | |
2541 | break; | |
2542 | case KBD_CMD_SET_LEDS: | |
2543 | kbd_queue(s, KBD_REPLY_ACK, 0); | |
313aa567 | 2544 | s->kbd_write_cmd = -1; |
330d0414 FB |
2545 | break; |
2546 | case KBD_CMD_SET_RATE: | |
2547 | kbd_queue(s, KBD_REPLY_ACK, 0); | |
313aa567 FB |
2548 | s->kbd_write_cmd = -1; |
2549 | break; | |
2550 | } | |
2551 | } | |
2552 | ||
2553 | static void kbd_mouse_send_packet(KBDState *s) | |
2554 | { | |
2555 | unsigned int b; | |
2556 | int dx1, dy1, dz1; | |
2557 | ||
2558 | dx1 = s->mouse_dx; | |
2559 | dy1 = s->mouse_dy; | |
2560 | dz1 = s->mouse_dz; | |
2561 | /* XXX: increase range to 8 bits ? */ | |
2562 | if (dx1 > 127) | |
2563 | dx1 = 127; | |
2564 | else if (dx1 < -127) | |
2565 | dx1 = -127; | |
2566 | if (dy1 > 127) | |
2567 | dy1 = 127; | |
2568 | else if (dy1 < -127) | |
2569 | dy1 = -127; | |
2570 | b = 0x08 | ((dx1 < 0) << 4) | ((dy1 < 0) << 5) | (s->mouse_buttons & 0x07); | |
2571 | kbd_queue(s, b, 1); | |
2572 | kbd_queue(s, dx1 & 0xff, 1); | |
2573 | kbd_queue(s, dy1 & 0xff, 1); | |
2574 | /* extra byte for IMPS/2 or IMEX */ | |
2575 | switch(s->mouse_type) { | |
2576 | default: | |
2577 | break; | |
2578 | case 3: | |
2579 | if (dz1 > 127) | |
2580 | dz1 = 127; | |
2581 | else if (dz1 < -127) | |
2582 | dz1 = -127; | |
2583 | kbd_queue(s, dz1 & 0xff, 1); | |
2584 | break; | |
2585 | case 4: | |
2586 | if (dz1 > 7) | |
2587 | dz1 = 7; | |
2588 | else if (dz1 < -7) | |
2589 | dz1 = -7; | |
2590 | b = (dz1 & 0x0f) | ((s->mouse_buttons & 0x18) << 1); | |
2591 | kbd_queue(s, b, 1); | |
2592 | break; | |
2593 | } | |
2594 | ||
2595 | /* update deltas */ | |
2596 | s->mouse_dx -= dx1; | |
2597 | s->mouse_dy -= dy1; | |
2598 | s->mouse_dz -= dz1; | |
2599 | } | |
2600 | ||
2601 | void kbd_mouse_event(int dx, int dy, int dz, int buttons_state) | |
2602 | { | |
2603 | KBDState *s = &kbd_state; | |
2604 | ||
2605 | /* check if deltas are recorded when disabled */ | |
2606 | if (!(s->mouse_status & MOUSE_STATUS_ENABLED)) | |
2607 | return; | |
2608 | ||
2609 | s->mouse_dx += dx; | |
2610 | s->mouse_dy -= dy; | |
2611 | s->mouse_dz += dz; | |
2612 | s->mouse_buttons = buttons_state; | |
2613 | ||
2614 | if (!(s->mouse_status & MOUSE_STATUS_REMOTE) && | |
2615 | (s->queues[1].count < (KBD_QUEUE_SIZE - 16))) { | |
2616 | for(;;) { | |
2617 | /* if not remote, send event. Multiple events are sent if | |
2618 | too big deltas */ | |
2619 | kbd_mouse_send_packet(s); | |
2620 | if (s->mouse_dx == 0 && s->mouse_dy == 0 && s->mouse_dz == 0) | |
2621 | break; | |
2622 | } | |
2623 | } | |
2624 | } | |
2625 | ||
2626 | static void kbd_write_mouse(KBDState *s, int val) | |
2627 | { | |
2628 | #ifdef DEBUG_MOUSE | |
2629 | printf("kbd: write mouse 0x%02x\n", val); | |
2630 | #endif | |
2631 | switch(s->mouse_write_cmd) { | |
2632 | default: | |
2633 | case -1: | |
2634 | /* mouse command */ | |
2635 | if (s->mouse_wrap) { | |
2636 | if (val == AUX_RESET_WRAP) { | |
2637 | s->mouse_wrap = 0; | |
2638 | kbd_queue(s, AUX_ACK, 1); | |
2639 | return; | |
2640 | } else if (val != AUX_RESET) { | |
2641 | kbd_queue(s, val, 1); | |
2642 | return; | |
2643 | } | |
2644 | } | |
2645 | switch(val) { | |
2646 | case AUX_SET_SCALE11: | |
2647 | s->mouse_status &= ~MOUSE_STATUS_SCALE21; | |
2648 | kbd_queue(s, AUX_ACK, 1); | |
2649 | break; | |
2650 | case AUX_SET_SCALE21: | |
2651 | s->mouse_status |= MOUSE_STATUS_SCALE21; | |
2652 | kbd_queue(s, AUX_ACK, 1); | |
2653 | break; | |
2654 | case AUX_SET_STREAM: | |
2655 | s->mouse_status &= ~MOUSE_STATUS_REMOTE; | |
2656 | kbd_queue(s, AUX_ACK, 1); | |
2657 | break; | |
2658 | case AUX_SET_WRAP: | |
2659 | s->mouse_wrap = 1; | |
2660 | kbd_queue(s, AUX_ACK, 1); | |
2661 | break; | |
2662 | case AUX_SET_REMOTE: | |
2663 | s->mouse_status |= MOUSE_STATUS_REMOTE; | |
2664 | kbd_queue(s, AUX_ACK, 1); | |
2665 | break; | |
2666 | case AUX_GET_TYPE: | |
2667 | kbd_queue(s, AUX_ACK, 1); | |
2668 | kbd_queue(s, s->mouse_type, 1); | |
2669 | break; | |
2670 | case AUX_SET_RES: | |
2671 | case AUX_SET_SAMPLE: | |
2672 | s->mouse_write_cmd = val; | |
2673 | kbd_queue(s, AUX_ACK, 1); | |
2674 | break; | |
2675 | case AUX_GET_SCALE: | |
2676 | kbd_queue(s, AUX_ACK, 1); | |
2677 | kbd_queue(s, s->mouse_status, 1); | |
2678 | kbd_queue(s, s->mouse_resolution, 1); | |
2679 | kbd_queue(s, s->mouse_sample_rate, 1); | |
2680 | break; | |
2681 | case AUX_POLL: | |
2682 | kbd_queue(s, AUX_ACK, 1); | |
2683 | kbd_mouse_send_packet(s); | |
2684 | break; | |
2685 | case AUX_ENABLE_DEV: | |
2686 | s->mouse_status |= MOUSE_STATUS_ENABLED; | |
2687 | kbd_queue(s, AUX_ACK, 1); | |
2688 | break; | |
2689 | case AUX_DISABLE_DEV: | |
2690 | s->mouse_status &= ~MOUSE_STATUS_ENABLED; | |
2691 | kbd_queue(s, AUX_ACK, 1); | |
2692 | break; | |
2693 | case AUX_SET_DEFAULT: | |
2694 | s->mouse_sample_rate = 100; | |
2695 | s->mouse_resolution = 2; | |
2696 | s->mouse_status = 0; | |
2697 | kbd_queue(s, AUX_ACK, 1); | |
2698 | break; | |
2699 | case AUX_RESET: | |
2700 | s->mouse_sample_rate = 100; | |
2701 | s->mouse_resolution = 2; | |
2702 | s->mouse_status = 0; | |
2703 | kbd_queue(s, AUX_ACK, 1); | |
2704 | kbd_queue(s, 0xaa, 1); | |
2705 | kbd_queue(s, s->mouse_type, 1); | |
2706 | break; | |
2707 | default: | |
2708 | break; | |
2709 | } | |
2710 | break; | |
2711 | case AUX_SET_SAMPLE: | |
2712 | s->mouse_sample_rate = val; | |
2713 | #if 0 | |
2714 | /* detect IMPS/2 or IMEX */ | |
2715 | switch(s->mouse_detect_state) { | |
2716 | default: | |
2717 | case 0: | |
2718 | if (val == 200) | |
2719 | s->mouse_detect_state = 1; | |
2720 | break; | |
2721 | case 1: | |
2722 | if (val == 100) | |
2723 | s->mouse_detect_state = 2; | |
2724 | else if (val == 200) | |
2725 | s->mouse_detect_state = 3; | |
2726 | else | |
2727 | s->mouse_detect_state = 0; | |
2728 | break; | |
2729 | case 2: | |
2730 | if (val == 80) | |
2731 | s->mouse_type = 3; /* IMPS/2 */ | |
2732 | s->mouse_detect_state = 0; | |
2733 | break; | |
2734 | case 3: | |
2735 | if (val == 80) | |
2736 | s->mouse_type = 4; /* IMEX */ | |
2737 | s->mouse_detect_state = 0; | |
2738 | break; | |
2739 | } | |
2740 | #endif | |
2741 | kbd_queue(s, AUX_ACK, 1); | |
2742 | s->mouse_write_cmd = -1; | |
2743 | break; | |
2744 | case AUX_SET_RES: | |
2745 | s->mouse_resolution = val; | |
2746 | kbd_queue(s, AUX_ACK, 1); | |
2747 | s->mouse_write_cmd = -1; | |
330d0414 FB |
2748 | break; |
2749 | } | |
330d0414 FB |
2750 | } |
2751 | ||
c45886db | 2752 | void kbd_write_data(CPUState *env, uint32_t addr, uint32_t val) |
330d0414 FB |
2753 | { |
2754 | KBDState *s = &kbd_state; | |
2755 | ||
2756 | #ifdef DEBUG_KBD | |
2757 | printf("kbd: write data=0x%02x\n", val); | |
2758 | #endif | |
2759 | ||
2760 | switch(s->write_cmd) { | |
2761 | case 0: | |
2762 | kbd_write_keyboard(s, val); | |
2763 | break; | |
2764 | case KBD_CCMD_WRITE_MODE: | |
2765 | s->mode = val; | |
2766 | kbd_update_irq(s); | |
2767 | break; | |
2768 | case KBD_CCMD_WRITE_OBUF: | |
2769 | kbd_queue(s, val, 0); | |
2770 | break; | |
2771 | case KBD_CCMD_WRITE_AUX_OBUF: | |
2772 | kbd_queue(s, val, 1); | |
2773 | break; | |
2774 | case KBD_CCMD_WRITE_OUTPORT: | |
c45886db | 2775 | #ifdef TARGET_I386 |
1f5476fc | 2776 | cpu_x86_set_a20(env, (val >> 1) & 1); |
c45886db | 2777 | #endif |
330d0414 FB |
2778 | if (!(val & 1)) { |
2779 | reset_requested = 1; | |
c45886db | 2780 | cpu_interrupt(global_env, CPU_INTERRUPT_EXIT); |
330d0414 FB |
2781 | } |
2782 | break; | |
313aa567 FB |
2783 | case KBD_CCMD_WRITE_MOUSE: |
2784 | kbd_write_mouse(s, val); | |
2785 | break; | |
cd4c3e88 FB |
2786 | default: |
2787 | break; | |
2788 | } | |
330d0414 FB |
2789 | s->write_cmd = 0; |
2790 | } | |
2791 | ||
2792 | void kbd_reset(KBDState *s) | |
2793 | { | |
2794 | KBDQueue *q; | |
2795 | int i; | |
2796 | ||
2797 | s->kbd_write_cmd = -1; | |
313aa567 | 2798 | s->mouse_write_cmd = -1; |
330d0414 | 2799 | s->mode = KBD_MODE_KBD_INT | KBD_MODE_MOUSE_INT; |
313aa567 | 2800 | s->status = KBD_STAT_CMD | KBD_STAT_UNLOCKED; |
330d0414 FB |
2801 | for(i = 0; i < 2; i++) { |
2802 | q = &s->queues[i]; | |
2803 | q->rptr = 0; | |
2804 | q->wptr = 0; | |
2805 | q->count = 0; | |
2806 | } | |
cd4c3e88 FB |
2807 | } |
2808 | ||
2809 | void kbd_init(void) | |
2810 | { | |
330d0414 | 2811 | kbd_reset(&kbd_state); |
c45886db | 2812 | #if defined (TARGET_I386) || defined (TARGET_PPC) |
330d0414 FB |
2813 | register_ioport_read(0x60, 1, kbd_read_data, 1); |
2814 | register_ioport_write(0x60, 1, kbd_write_data, 1); | |
cd4c3e88 FB |
2815 | register_ioport_read(0x64, 1, kbd_read_status, 1); |
2816 | register_ioport_write(0x64, 1, kbd_write_command, 1); | |
c45886db | 2817 | #endif |
cd4c3e88 FB |
2818 | } |
2819 | ||
330d0414 FB |
2820 | /***********************************************************/ |
2821 | /* Bochs BIOS debug ports */ | |
c45886db | 2822 | #ifdef TARGET_I386 |
330d0414 FB |
2823 | void bochs_bios_write(CPUX86State *env, uint32_t addr, uint32_t val) |
2824 | { | |
2825 | switch(addr) { | |
2826 | /* Bochs BIOS messages */ | |
2827 | case 0x400: | |
2828 | case 0x401: | |
2829 | fprintf(stderr, "BIOS panic at rombios.c, line %d\n", val); | |
2830 | exit(1); | |
2831 | case 0x402: | |
2832 | case 0x403: | |
2833 | #ifdef DEBUG_BIOS | |
2834 | fprintf(stderr, "%c", val); | |
2835 | #endif | |
2836 | break; | |
2837 | ||
2838 | /* LGPL'ed VGA BIOS messages */ | |
2839 | case 0x501: | |
2840 | case 0x502: | |
2841 | fprintf(stderr, "VGA BIOS panic, line %d\n", val); | |
2842 | exit(1); | |
2843 | case 0x500: | |
2844 | case 0x503: | |
2845 | #ifdef DEBUG_BIOS | |
2846 | fprintf(stderr, "%c", val); | |
2847 | #endif | |
2848 | break; | |
2849 | } | |
2850 | } | |
2851 | ||
2852 | void bochs_bios_init(void) | |
2853 | { | |
2854 | register_ioport_write(0x400, 1, bochs_bios_write, 2); | |
2855 | register_ioport_write(0x401, 1, bochs_bios_write, 2); | |
2856 | register_ioport_write(0x402, 1, bochs_bios_write, 1); | |
2857 | register_ioport_write(0x403, 1, bochs_bios_write, 1); | |
2858 | ||
2859 | register_ioport_write(0x501, 1, bochs_bios_write, 2); | |
2860 | register_ioport_write(0x502, 1, bochs_bios_write, 2); | |
2861 | register_ioport_write(0x500, 1, bochs_bios_write, 1); | |
2862 | register_ioport_write(0x503, 1, bochs_bios_write, 1); | |
2863 | } | |
c45886db | 2864 | #endif |
330d0414 | 2865 | |
313aa567 FB |
2866 | /***********************************************************/ |
2867 | /* dumb display */ | |
2868 | ||
2869 | /* init terminal so that we can grab keys */ | |
2870 | static struct termios oldtty; | |
2871 | ||
2872 | static void term_exit(void) | |
2873 | { | |
2874 | tcsetattr (0, TCSANOW, &oldtty); | |
2875 | } | |
2876 | ||
2877 | static void term_init(void) | |
2878 | { | |
2879 | struct termios tty; | |
2880 | ||
2881 | tcgetattr (0, &tty); | |
2882 | oldtty = tty; | |
2883 | ||
2884 | tty.c_iflag &= ~(IGNBRK|BRKINT|PARMRK|ISTRIP | |
2885 | |INLCR|IGNCR|ICRNL|IXON); | |
2886 | tty.c_oflag |= OPOST; | |
a20dd508 FB |
2887 | tty.c_lflag &= ~(ECHO|ECHONL|ICANON|IEXTEN); |
2888 | /* if graphical mode, we allow Ctrl-C handling */ | |
2889 | if (nographic) | |
2890 | tty.c_lflag &= ~ISIG; | |
313aa567 FB |
2891 | tty.c_cflag &= ~(CSIZE|PARENB); |
2892 | tty.c_cflag |= CS8; | |
2893 | tty.c_cc[VMIN] = 1; | |
2894 | tty.c_cc[VTIME] = 0; | |
2895 | ||
2896 | tcsetattr (0, TCSANOW, &tty); | |
2897 | ||
2898 | atexit(term_exit); | |
2899 | ||
2900 | fcntl(0, F_SETFL, O_NONBLOCK); | |
2901 | } | |
2902 | ||
2903 | static void dumb_update(DisplayState *ds, int x, int y, int w, int h) | |
2904 | { | |
2905 | } | |
2906 | ||
2907 | static void dumb_resize(DisplayState *ds, int w, int h) | |
2908 | { | |
2909 | } | |
2910 | ||
2911 | static void dumb_refresh(DisplayState *ds) | |
2912 | { | |
2913 | vga_update_display(); | |
2914 | } | |
2915 | ||
2916 | void dumb_display_init(DisplayState *ds) | |
2917 | { | |
2918 | ds->data = NULL; | |
2919 | ds->linesize = 0; | |
2920 | ds->depth = 0; | |
2921 | ds->dpy_update = dumb_update; | |
2922 | ds->dpy_resize = dumb_resize; | |
2923 | ds->dpy_refresh = dumb_refresh; | |
2924 | } | |
2925 | ||
3a51dee6 | 2926 | #if !defined(CONFIG_SOFTMMU) |
f1510b2c | 2927 | /***********************************************************/ |
0824d6fc FB |
2928 | /* cpu signal handler */ |
2929 | static void host_segv_handler(int host_signum, siginfo_t *info, | |
2930 | void *puc) | |
2931 | { | |
2932 | if (cpu_signal_handler(host_signum, info, puc)) | |
2933 | return; | |
2934 | term_exit(); | |
2935 | abort(); | |
2936 | } | |
3a51dee6 | 2937 | #endif |
0824d6fc FB |
2938 | |
2939 | static int timer_irq_pending; | |
87858c89 | 2940 | static int timer_irq_count; |
0824d6fc | 2941 | |
313aa567 FB |
2942 | static int timer_ms; |
2943 | static int gui_refresh_pending, gui_refresh_count; | |
2944 | ||
0824d6fc FB |
2945 | static void host_alarm_handler(int host_signum, siginfo_t *info, |
2946 | void *puc) | |
2947 | { | |
87858c89 FB |
2948 | /* NOTE: since usually the OS asks a 100 Hz clock, there can be |
2949 | some drift between cpu_get_ticks() and the interrupt time. So | |
2950 | we queue some interrupts to avoid missing some */ | |
2951 | timer_irq_count += pit_get_out_edges(&pit_channels[0]); | |
2952 | if (timer_irq_count) { | |
2953 | if (timer_irq_count > 2) | |
2954 | timer_irq_count = 2; | |
2955 | timer_irq_count--; | |
313aa567 FB |
2956 | timer_irq_pending = 1; |
2957 | } | |
2958 | gui_refresh_count += timer_ms; | |
2959 | if (gui_refresh_count >= GUI_REFRESH_INTERVAL) { | |
2960 | gui_refresh_count = 0; | |
2961 | gui_refresh_pending = 1; | |
2962 | } | |
2963 | ||
2964 | if (gui_refresh_pending || timer_irq_pending) { | |
87858c89 | 2965 | /* just exit from the cpu to have a chance to handle timers */ |
c45886db | 2966 | cpu_interrupt(global_env, CPU_INTERRUPT_EXIT); |
87858c89 | 2967 | } |
0824d6fc FB |
2968 | } |
2969 | ||
b4608c04 FB |
2970 | /* main execution loop */ |
2971 | ||
2972 | CPUState *cpu_gdbstub_get_env(void *opaque) | |
2973 | { | |
2974 | return global_env; | |
2975 | } | |
2976 | ||
4c3a88a2 | 2977 | int main_loop(void *opaque) |
b4608c04 | 2978 | { |
c45886db FB |
2979 | struct pollfd ufds[3], *pf, *serial_ufd, *gdb_ufd; |
2980 | #if defined (TARGET_I386) | |
2981 | struct pollfd *net_ufd; | |
2982 | #endif | |
27c3f2cb | 2983 | int ret, n, timeout, serial_ok; |
b4608c04 FB |
2984 | uint8_t ch; |
2985 | CPUState *env = global_env; | |
2986 | ||
a20dd508 | 2987 | if (!term_inited) { |
313aa567 FB |
2988 | /* initialize terminal only there so that the user has a |
2989 | chance to stop QEMU with Ctrl-C before the gdb connection | |
2990 | is launched */ | |
2991 | term_inited = 1; | |
2992 | term_init(); | |
2993 | } | |
2994 | ||
27c3f2cb | 2995 | serial_ok = 1; |
34865134 | 2996 | cpu_enable_ticks(); |
b4608c04 | 2997 | for(;;) { |
c45886db FB |
2998 | #if defined (DO_TB_FLUSH) |
2999 | tb_flush(); | |
3000 | #endif | |
3001 | ret = cpu_exec(env); | |
34865134 FB |
3002 | if (reset_requested) { |
3003 | ret = EXCP_INTERRUPT; | |
cd4c3e88 | 3004 | break; |
34865134 FB |
3005 | } |
3006 | if (ret == EXCP_DEBUG) { | |
3007 | ret = EXCP_DEBUG; | |
3008 | break; | |
3009 | } | |
b4608c04 FB |
3010 | /* if hlt instruction, we wait until the next IRQ */ |
3011 | if (ret == EXCP_HLT) | |
3012 | timeout = 10; | |
3013 | else | |
3014 | timeout = 0; | |
3015 | /* poll any events */ | |
3016 | serial_ufd = NULL; | |
3017 | pf = ufds; | |
27c3f2cb | 3018 | if (serial_ok && !(serial_ports[0].lsr & UART_LSR_DR)) { |
b4608c04 FB |
3019 | serial_ufd = pf; |
3020 | pf->fd = 0; | |
3021 | pf->events = POLLIN; | |
3022 | pf++; | |
3023 | } | |
c45886db | 3024 | #if defined (TARGET_I386) |
b4608c04 FB |
3025 | net_ufd = NULL; |
3026 | if (net_fd > 0 && ne2000_can_receive(&ne2000_state)) { | |
3027 | net_ufd = pf; | |
3028 | pf->fd = net_fd; | |
3029 | pf->events = POLLIN; | |
3030 | pf++; | |
3031 | } | |
c45886db | 3032 | #endif |
b4608c04 FB |
3033 | gdb_ufd = NULL; |
3034 | if (gdbstub_fd > 0) { | |
3035 | gdb_ufd = pf; | |
3036 | pf->fd = gdbstub_fd; | |
3037 | pf->events = POLLIN; | |
3038 | pf++; | |
3039 | } | |
3040 | ||
3041 | ret = poll(ufds, pf - ufds, timeout); | |
3042 | if (ret > 0) { | |
3043 | if (serial_ufd && (serial_ufd->revents & POLLIN)) { | |
3044 | n = read(0, &ch, 1); | |
3045 | if (n == 1) { | |
3046 | serial_received_byte(&serial_ports[0], ch); | |
27c3f2cb FB |
3047 | } else { |
3048 | /* Closed, stop polling. */ | |
3049 | serial_ok = 0; | |
b4608c04 FB |
3050 | } |
3051 | } | |
c45886db | 3052 | #if defined (TARGET_I386) |
b4608c04 FB |
3053 | if (net_ufd && (net_ufd->revents & POLLIN)) { |
3054 | uint8_t buf[MAX_ETH_FRAME_SIZE]; | |
3055 | ||
3056 | n = read(net_fd, buf, MAX_ETH_FRAME_SIZE); | |
3057 | if (n > 0) { | |
3058 | if (n < 60) { | |
3059 | memset(buf + n, 0, 60 - n); | |
3060 | n = 60; | |
3061 | } | |
3062 | ne2000_receive(&ne2000_state, buf, n); | |
3063 | } | |
3064 | } | |
c45886db | 3065 | #endif |
b4608c04 FB |
3066 | if (gdb_ufd && (gdb_ufd->revents & POLLIN)) { |
3067 | uint8_t buf[1]; | |
3068 | /* stop emulation if requested by gdb */ | |
3069 | n = read(gdbstub_fd, buf, 1); | |
34865134 FB |
3070 | if (n == 1) { |
3071 | ret = EXCP_INTERRUPT; | |
b4608c04 | 3072 | break; |
34865134 | 3073 | } |
b4608c04 FB |
3074 | } |
3075 | } | |
3076 | ||
3077 | /* timer IRQ */ | |
3078 | if (timer_irq_pending) { | |
c45886db | 3079 | #if defined (TARGET_I386) |
b4608c04 FB |
3080 | pic_set_irq(0, 1); |
3081 | pic_set_irq(0, 0); | |
3082 | timer_irq_pending = 0; | |
7dea1da4 | 3083 | /* XXX: RTC test */ |
8f2b1fb0 | 3084 | if (cmos_data[RTC_REG_B] & 0x50) { |
7dea1da4 FB |
3085 | pic_set_irq(8, 1); |
3086 | } | |
c45886db | 3087 | #endif |
b4608c04 | 3088 | } |
8dc75d75 FB |
3089 | /* XXX: add explicit timer */ |
3090 | SB16_run(); | |
3091 | ||
3092 | /* run dma transfers, if any */ | |
3093 | DMA_run(); | |
313aa567 FB |
3094 | |
3095 | /* VGA */ | |
3096 | if (gui_refresh_pending) { | |
3097 | display_state.dpy_refresh(&display_state); | |
3098 | gui_refresh_pending = 0; | |
3099 | } | |
b4608c04 | 3100 | } |
34865134 FB |
3101 | cpu_disable_ticks(); |
3102 | return ret; | |
b4608c04 FB |
3103 | } |
3104 | ||
0824d6fc FB |
3105 | void help(void) |
3106 | { | |
a20dd508 | 3107 | printf("QEMU PC emulator version " QEMU_VERSION ", Copyright (c) 2003 Fabrice Bellard\n" |
0db63474 | 3108 | "usage: %s [options] [disk_image]\n" |
0824d6fc | 3109 | "\n" |
a20dd508 | 3110 | "'disk_image' is a raw hard image image for IDE hard disk 0\n" |
fc01f7e7 | 3111 | "\n" |
a20dd508 | 3112 | "Standard options:\n" |
c45886db | 3113 | "-fda/-fdb file use 'file' as floppy disk 0/1 image\n" |
36b486bb FB |
3114 | "-hda/-hdb file use 'file' as IDE hard disk 0/1 image\n" |
3115 | "-hdc/-hdd file use 'file' as IDE hard disk 2/3 image\n" | |
3116 | "-cdrom file use 'file' as IDE cdrom 2 image\n" | |
6e44ba7f | 3117 | "-boot [a|b|c|d] boot on floppy (a, b), hard disk (c) or CD-ROM (d)\n" |
a20dd508 FB |
3118 | "-snapshot write to temporary files instead of disk image files\n" |
3119 | "-m megs set virtual RAM size to megs MB\n" | |
3120 | "-n script set network init script [default=%s]\n" | |
42f1e0e4 | 3121 | "-tun-fd fd this fd talks to tap/tun, use it.\n" |
a20dd508 FB |
3122 | "-nographic disable graphical output\n" |
3123 | "\n" | |
3124 | "Linux boot specific (does not require PC BIOS):\n" | |
3125 | "-kernel bzImage use 'bzImage' as kernel image\n" | |
3126 | "-append cmdline use 'cmdline' as kernel command line\n" | |
3127 | "-initrd file use 'file' as initial ram disk\n" | |
fc01f7e7 | 3128 | "\n" |
330d0414 | 3129 | "Debug/Expert options:\n" |
a20dd508 FB |
3130 | "-s wait gdb connection to port %d\n" |
3131 | "-p port change gdb connection port\n" | |
6e44ba7f | 3132 | "-d output log to %s\n" |
a20dd508 FB |
3133 | "-hdachs c,h,s force hard disk 0 geometry (usually qemu can guess it)\n" |
3134 | "-L path set the directory for the BIOS and VGA BIOS\n" | |
77fef8c1 FB |
3135 | #ifdef USE_CODE_COPY |
3136 | "-no-code-copy disable code copy acceleration\n" | |
3137 | #endif | |
3138 | ||
0824d6fc | 3139 | "\n" |
f1510b2c | 3140 | "During emulation, use C-a h to get terminal commands:\n", |
0db63474 FB |
3141 | #ifdef CONFIG_SOFTMMU |
3142 | "qemu", | |
3143 | #else | |
3144 | "qemu-fast", | |
3145 | #endif | |
3146 | DEFAULT_NETWORK_SCRIPT, | |
6e44ba7f FB |
3147 | DEFAULT_GDBSTUB_PORT, |
3148 | "/tmp/qemu.log"); | |
0824d6fc | 3149 | term_print_help(); |
0db63474 FB |
3150 | #ifndef CONFIG_SOFTMMU |
3151 | printf("\n" | |
3152 | "NOTE: this version of QEMU is faster but it needs slightly patched OSes to\n" | |
3153 | "work. Please use the 'qemu' executable to have a more accurate (but slower)\n" | |
3154 | "PC emulation.\n"); | |
3155 | #endif | |
0824d6fc FB |
3156 | exit(1); |
3157 | } | |
3158 | ||
fc01f7e7 FB |
3159 | struct option long_options[] = { |
3160 | { "initrd", 1, NULL, 0, }, | |
3161 | { "hda", 1, NULL, 0, }, | |
3162 | { "hdb", 1, NULL, 0, }, | |
33e3963e | 3163 | { "snapshot", 0, NULL, 0, }, |
330d0414 | 3164 | { "hdachs", 1, NULL, 0, }, |
a20dd508 FB |
3165 | { "nographic", 0, NULL, 0, }, |
3166 | { "kernel", 1, NULL, 0, }, | |
3167 | { "append", 1, NULL, 0, }, | |
42f1e0e4 | 3168 | { "tun-fd", 1, NULL, 0, }, |
36b486bb FB |
3169 | { "hdc", 1, NULL, 0, }, |
3170 | { "hdd", 1, NULL, 0, }, | |
3171 | { "cdrom", 1, NULL, 0, }, | |
3172 | { "boot", 1, NULL, 0, }, | |
c45886db FB |
3173 | { "fda", 1, NULL, 0, }, |
3174 | { "fdb", 1, NULL, 0, }, | |
77fef8c1 | 3175 | { "no-code-copy", 0, NULL, 0}, |
fc01f7e7 FB |
3176 | { NULL, 0, NULL, 0 }, |
3177 | }; | |
3178 | ||
a20dd508 FB |
3179 | #ifdef CONFIG_SDL |
3180 | /* SDL use the pthreads and they modify sigaction. We don't | |
3181 | want that. */ | |
dc887a4d | 3182 | #if __GLIBC__ > 2 || (__GLIBC__ == 2 && __GLIBC_MINOR__ >= 2) |
a20dd508 FB |
3183 | extern void __libc_sigaction(); |
3184 | #define sigaction(sig, act, oact) __libc_sigaction(sig, act, oact) | |
3185 | #else | |
3186 | extern void __sigaction(); | |
3187 | #define sigaction(sig, act, oact) __sigaction(sig, act, oact) | |
3188 | #endif | |
3189 | #endif /* CONFIG_SDL */ | |
3190 | ||
77fef8c1 FB |
3191 | #if defined (TARGET_I386) && defined(USE_CODE_COPY) |
3192 | ||
3193 | /* this stack is only used during signal handling */ | |
3194 | #define SIGNAL_STACK_SIZE 32768 | |
3195 | ||
3196 | static uint8_t *signal_stack; | |
3197 | ||
3198 | #endif | |
3199 | ||
0824d6fc FB |
3200 | int main(int argc, char **argv) |
3201 | { | |
fc01f7e7 | 3202 | int c, ret, initrd_size, i, use_gdbstub, gdbstub_port, long_index; |
1ccde1cb | 3203 | int snapshot, linux_boot; |
0824d6fc FB |
3204 | struct sigaction act; |
3205 | struct itimerval itv; | |
c45886db | 3206 | CPUState *env; |
7f7f9873 | 3207 | const char *initrd_filename; |
c45886db | 3208 | const char *hd_filename[MAX_DISKS], *fd_filename[MAX_FD]; |
a20dd508 | 3209 | const char *kernel_filename, *kernel_cmdline; |
77fef8c1 | 3210 | char buf[1024]; |
313aa567 FB |
3211 | DisplayState *ds = &display_state; |
3212 | ||
0824d6fc FB |
3213 | /* we never want that malloc() uses mmap() */ |
3214 | mallopt(M_MMAP_THRESHOLD, 4096 * 1024); | |
fc01f7e7 | 3215 | initrd_filename = NULL; |
c45886db FB |
3216 | for(i = 0; i < MAX_FD; i++) |
3217 | fd_filename[i] = NULL; | |
fc01f7e7 FB |
3218 | for(i = 0; i < MAX_DISKS; i++) |
3219 | hd_filename[i] = NULL; | |
1ccde1cb | 3220 | ram_size = 32 * 1024 * 1024; |
313aa567 | 3221 | vga_ram_size = VGA_RAM_SIZE; |
c45886db | 3222 | #if defined (TARGET_I386) |
f1510b2c | 3223 | pstrcpy(network_script, sizeof(network_script), DEFAULT_NETWORK_SCRIPT); |
c45886db | 3224 | #endif |
b4608c04 FB |
3225 | use_gdbstub = 0; |
3226 | gdbstub_port = DEFAULT_GDBSTUB_PORT; | |
33e3963e | 3227 | snapshot = 0; |
a20dd508 FB |
3228 | nographic = 0; |
3229 | kernel_filename = NULL; | |
3230 | kernel_cmdline = ""; | |
0824d6fc | 3231 | for(;;) { |
330d0414 | 3232 | c = getopt_long_only(argc, argv, "hm:dn:sp:L:", long_options, &long_index); |
0824d6fc FB |
3233 | if (c == -1) |
3234 | break; | |
3235 | switch(c) { | |
fc01f7e7 FB |
3236 | case 0: |
3237 | switch(long_index) { | |
3238 | case 0: | |
3239 | initrd_filename = optarg; | |
3240 | break; | |
3241 | case 1: | |
3242 | hd_filename[0] = optarg; | |
3243 | break; | |
3244 | case 2: | |
3245 | hd_filename[1] = optarg; | |
3246 | break; | |
33e3963e FB |
3247 | case 3: |
3248 | snapshot = 1; | |
3249 | break; | |
330d0414 FB |
3250 | case 4: |
3251 | { | |
3252 | int cyls, heads, secs; | |
3253 | const char *p; | |
3254 | p = optarg; | |
3255 | cyls = strtol(p, (char **)&p, 0); | |
3256 | if (*p != ',') | |
3257 | goto chs_fail; | |
3258 | p++; | |
3259 | heads = strtol(p, (char **)&p, 0); | |
3260 | if (*p != ',') | |
3261 | goto chs_fail; | |
3262 | p++; | |
3263 | secs = strtol(p, (char **)&p, 0); | |
3264 | if (*p != '\0') | |
3265 | goto chs_fail; | |
5391d806 | 3266 | ide_set_geometry(0, cyls, heads, secs); |
330d0414 FB |
3267 | chs_fail: ; |
3268 | } | |
3269 | break; | |
313aa567 | 3270 | case 5: |
a20dd508 FB |
3271 | nographic = 1; |
3272 | break; | |
3273 | case 6: | |
3274 | kernel_filename = optarg; | |
3275 | break; | |
3276 | case 7: | |
3277 | kernel_cmdline = optarg; | |
313aa567 | 3278 | break; |
c45886db | 3279 | #if defined (TARGET_I386) |
42f1e0e4 FB |
3280 | case 8: |
3281 | net_fd = atoi(optarg); | |
3282 | break; | |
c45886db | 3283 | #endif |
36b486bb FB |
3284 | case 9: |
3285 | hd_filename[2] = optarg; | |
3286 | break; | |
3287 | case 10: | |
3288 | hd_filename[3] = optarg; | |
3289 | break; | |
3290 | case 11: | |
3291 | hd_filename[2] = optarg; | |
5391d806 | 3292 | ide_set_cdrom(2, 1); |
36b486bb FB |
3293 | break; |
3294 | case 12: | |
3295 | boot_device = optarg[0]; | |
c45886db FB |
3296 | if (boot_device != 'a' && boot_device != 'b' && |
3297 | boot_device != 'c' && boot_device != 'd') { | |
36b486bb FB |
3298 | fprintf(stderr, "qemu: invalid boot device '%c'\n", boot_device); |
3299 | exit(1); | |
3300 | } | |
3301 | break; | |
c45886db FB |
3302 | case 13: |
3303 | fd_filename[0] = optarg; | |
3304 | break; | |
3305 | case 14: | |
3306 | fd_filename[1] = optarg; | |
3307 | break; | |
77fef8c1 FB |
3308 | case 15: |
3309 | code_copy_enabled = 0; | |
3310 | break; | |
fc01f7e7 FB |
3311 | } |
3312 | break; | |
0824d6fc FB |
3313 | case 'h': |
3314 | help(); | |
3315 | break; | |
3316 | case 'm': | |
1ccde1cb FB |
3317 | ram_size = atoi(optarg) * 1024 * 1024; |
3318 | if (ram_size <= 0) | |
0824d6fc | 3319 | help(); |
1ccde1cb | 3320 | if (ram_size > PHYS_RAM_MAX_SIZE) { |
36b486bb | 3321 | fprintf(stderr, "qemu: at most %d MB RAM can be simulated\n", |
7916e224 FB |
3322 | PHYS_RAM_MAX_SIZE / (1024 * 1024)); |
3323 | exit(1); | |
3324 | } | |
0824d6fc FB |
3325 | break; |
3326 | case 'd': | |
34865134 | 3327 | cpu_set_log(CPU_LOG_ALL); |
0824d6fc | 3328 | break; |
c45886db | 3329 | #if defined (TARGET_I386) |
f1510b2c FB |
3330 | case 'n': |
3331 | pstrcpy(network_script, sizeof(network_script), optarg); | |
3332 | break; | |
c45886db | 3333 | #endif |
b4608c04 FB |
3334 | case 's': |
3335 | use_gdbstub = 1; | |
3336 | break; | |
3337 | case 'p': | |
3338 | gdbstub_port = atoi(optarg); | |
3339 | break; | |
330d0414 | 3340 | case 'L': |
5a67135a | 3341 | bios_dir = optarg; |
330d0414 | 3342 | break; |
0824d6fc FB |
3343 | } |
3344 | } | |
330d0414 | 3345 | |
a20dd508 FB |
3346 | if (optind < argc) { |
3347 | hd_filename[0] = argv[optind++]; | |
3348 | } | |
3349 | ||
3350 | linux_boot = (kernel_filename != NULL); | |
330d0414 | 3351 | |
c45886db FB |
3352 | if (!linux_boot && hd_filename[0] == '\0' && hd_filename[2] == '\0' && |
3353 | fd_filename[0] == '\0') | |
0824d6fc | 3354 | help(); |
8f2b1fb0 FB |
3355 | |
3356 | /* boot to cd by default if no hard disk */ | |
d0309311 FB |
3357 | if (hd_filename[0] == '\0' && boot_device == 'c') { |
3358 | if (fd_filename[0] != '\0') | |
3359 | boot_device = 'a'; | |
3360 | else | |
3361 | boot_device = 'd'; | |
3362 | } | |
0824d6fc | 3363 | |
dc887a4d FB |
3364 | #if !defined(CONFIG_SOFTMMU) |
3365 | /* must avoid mmap() usage of glibc by setting a buffer "by hand" */ | |
3366 | { | |
3367 | static uint8_t stdout_buf[4096]; | |
3368 | setvbuf(stdout, stdout_buf, _IOLBF, sizeof(stdout_buf)); | |
3369 | } | |
3370 | #else | |
b118d61e | 3371 | setvbuf(stdout, NULL, _IOLBF, 0); |
dc887a4d | 3372 | #endif |
0824d6fc | 3373 | |
f1510b2c | 3374 | /* init network tun interface */ |
c45886db | 3375 | #if defined (TARGET_I386) |
42f1e0e4 FB |
3376 | if (net_fd < 0) |
3377 | net_init(); | |
c45886db | 3378 | #endif |
f1510b2c | 3379 | |
0824d6fc | 3380 | /* init the memory */ |
1ccde1cb | 3381 | phys_ram_size = ram_size + vga_ram_size; |
7f7f9873 FB |
3382 | |
3383 | #ifdef CONFIG_SOFTMMU | |
1ccde1cb | 3384 | phys_ram_base = memalign(TARGET_PAGE_SIZE, phys_ram_size); |
7f7f9873 FB |
3385 | if (!phys_ram_base) { |
3386 | fprintf(stderr, "Could not allocate physical memory\n"); | |
0824d6fc FB |
3387 | exit(1); |
3388 | } | |
7f7f9873 FB |
3389 | #else |
3390 | /* as we must map the same page at several addresses, we must use | |
3391 | a fd */ | |
3392 | { | |
3393 | const char *tmpdir; | |
3394 | ||
3395 | tmpdir = getenv("QEMU_TMPDIR"); | |
3396 | if (!tmpdir) | |
3397 | tmpdir = "/tmp"; | |
3398 | snprintf(phys_ram_file, sizeof(phys_ram_file), "%s/vlXXXXXX", tmpdir); | |
3399 | if (mkstemp(phys_ram_file) < 0) { | |
3400 | fprintf(stderr, "Could not create temporary memory file '%s'\n", | |
3401 | phys_ram_file); | |
3402 | exit(1); | |
3403 | } | |
3404 | phys_ram_fd = open(phys_ram_file, O_CREAT | O_TRUNC | O_RDWR, 0600); | |
3405 | if (phys_ram_fd < 0) { | |
3406 | fprintf(stderr, "Could not open temporary memory file '%s'\n", | |
3407 | phys_ram_file); | |
3408 | exit(1); | |
3409 | } | |
1ccde1cb | 3410 | ftruncate(phys_ram_fd, phys_ram_size); |
7f7f9873 | 3411 | unlink(phys_ram_file); |
1ccde1cb FB |
3412 | phys_ram_base = mmap(get_mmap_addr(phys_ram_size), |
3413 | phys_ram_size, | |
7f7f9873 FB |
3414 | PROT_WRITE | PROT_READ, MAP_SHARED | MAP_FIXED, |
3415 | phys_ram_fd, 0); | |
3416 | if (phys_ram_base == MAP_FAILED) { | |
3417 | fprintf(stderr, "Could not map physical memory\n"); | |
3418 | exit(1); | |
3419 | } | |
3420 | } | |
3421 | #endif | |
0824d6fc | 3422 | |
33e3963e FB |
3423 | /* open the virtual block devices */ |
3424 | for(i = 0; i < MAX_DISKS; i++) { | |
3425 | if (hd_filename[i]) { | |
3426 | bs_table[i] = bdrv_open(hd_filename[i], snapshot); | |
3427 | if (!bs_table[i]) { | |
36b486bb | 3428 | fprintf(stderr, "qemu: could not open hard disk image '%s\n", |
33e3963e FB |
3429 | hd_filename[i]); |
3430 | exit(1); | |
3431 | } | |
3432 | } | |
3433 | } | |
3434 | ||
330d0414 FB |
3435 | /* init CPU state */ |
3436 | env = cpu_init(); | |
3437 | global_env = env; | |
3438 | cpu_single_env = env; | |
3439 | ||
3440 | init_ioports(); | |
0824d6fc | 3441 | |
313aa567 | 3442 | /* allocate RAM */ |
1ccde1cb | 3443 | cpu_register_physical_memory(0, ram_size, 0); |
313aa567 | 3444 | |
77fef8c1 FB |
3445 | #if defined(TARGET_I386) |
3446 | /* RAW PC boot */ | |
3447 | ||
3448 | /* BIOS load */ | |
3449 | snprintf(buf, sizeof(buf), "%s/%s", bios_dir, BIOS_FILENAME); | |
3450 | ret = load_image(buf, phys_ram_base + 0x000f0000); | |
3451 | if (ret != 0x10000) { | |
3452 | fprintf(stderr, "qemu: could not load PC bios '%s'\n", buf); | |
3453 | exit(1); | |
3454 | } | |
3455 | ||
3456 | /* VGA BIOS load */ | |
3457 | snprintf(buf, sizeof(buf), "%s/%s", bios_dir, VGABIOS_FILENAME); | |
3458 | ret = load_image(buf, phys_ram_base + 0x000c0000); | |
3459 | ||
3460 | /* setup basic memory access */ | |
3461 | cpu_register_physical_memory(0xc0000, 0x10000, 0xc0000 | IO_MEM_ROM); | |
3462 | cpu_register_physical_memory(0xf0000, 0x10000, 0xf0000 | IO_MEM_ROM); | |
3463 | ||
3464 | bochs_bios_init(); | |
3465 | ||
330d0414 | 3466 | if (linux_boot) { |
a735aa31 | 3467 | uint8_t bootsect[512]; |
77fef8c1 FB |
3468 | |
3469 | if (bs_table[0] == NULL) { | |
3470 | fprintf(stderr, "A disk image must be given for 'hda' when booting a Linux kernel\n"); | |
3471 | exit(1); | |
3472 | } | |
a735aa31 FB |
3473 | snprintf(buf, sizeof(buf), "%s/%s", bios_dir, LINUX_BOOT_FILENAME); |
3474 | ret = load_image(buf, bootsect); | |
3475 | if (ret != sizeof(bootsect)) { | |
3476 | fprintf(stderr, "qemu: could not load linux boot sector '%s'\n", | |
3477 | buf); | |
3478 | exit(1); | |
3479 | } | |
3480 | ||
3481 | bdrv_set_boot_sector(bs_table[0], bootsect, sizeof(bootsect)); | |
77fef8c1 | 3482 | |
330d0414 | 3483 | /* now we can load the kernel */ |
77fef8c1 FB |
3484 | ret = load_kernel(kernel_filename, |
3485 | phys_ram_base + KERNEL_LOAD_ADDR, | |
3486 | phys_ram_base + KERNEL_PARAMS_ADDR); | |
330d0414 | 3487 | if (ret < 0) { |
36b486bb | 3488 | fprintf(stderr, "qemu: could not load kernel '%s'\n", |
a20dd508 | 3489 | kernel_filename); |
fc01f7e7 FB |
3490 | exit(1); |
3491 | } | |
330d0414 FB |
3492 | |
3493 | /* load initrd */ | |
3494 | initrd_size = 0; | |
3495 | if (initrd_filename) { | |
3496 | initrd_size = load_image(initrd_filename, phys_ram_base + INITRD_LOAD_ADDR); | |
3497 | if (initrd_size < 0) { | |
36b486bb | 3498 | fprintf(stderr, "qemu: could not load initial ram disk '%s'\n", |
330d0414 FB |
3499 | initrd_filename); |
3500 | exit(1); | |
3501 | } | |
3502 | } | |
330d0414 | 3503 | if (initrd_size > 0) { |
77fef8c1 FB |
3504 | stl_raw(phys_ram_base + KERNEL_PARAMS_ADDR + 0x218, INITRD_LOAD_ADDR); |
3505 | stl_raw(phys_ram_base + KERNEL_PARAMS_ADDR + 0x21c, initrd_size); | |
330d0414 | 3506 | } |
77fef8c1 FB |
3507 | pstrcpy(phys_ram_base + KERNEL_CMDLINE_ADDR, 4096, |
3508 | kernel_cmdline); | |
3509 | stw_raw(phys_ram_base + KERNEL_PARAMS_ADDR + 0x20, 0xA33F); | |
3510 | stw_raw(phys_ram_base + KERNEL_PARAMS_ADDR + 0x22, | |
3511 | KERNEL_CMDLINE_ADDR - KERNEL_PARAMS_ADDR); | |
3512 | /* loader type */ | |
3513 | stw_raw(phys_ram_base + KERNEL_PARAMS_ADDR + 0x210, 0x01); | |
3514 | } | |
c45886db | 3515 | #elif defined(TARGET_PPC) |
77fef8c1 FB |
3516 | /* allocate ROM */ |
3517 | // snprintf(buf, sizeof(buf), "%s/%s", bios_dir, BIOS_FILENAME); | |
3518 | snprintf(buf, sizeof(buf), "%s", BIOS_FILENAME); | |
3519 | printf("load BIOS at %p\n", phys_ram_base + 0x000f0000); | |
3520 | ret = load_image(buf, phys_ram_base + 0x000f0000); | |
3521 | if (ret != 0x10000) { | |
3522 | fprintf(stderr, "qemu: could not load PPC bios '%s' (%d)\n%m\n", | |
3523 | buf, ret); | |
3524 | exit(1); | |
0824d6fc | 3525 | } |
77fef8c1 | 3526 | #endif |
0824d6fc | 3527 | |
313aa567 | 3528 | /* terminal init */ |
a20dd508 | 3529 | if (nographic) { |
313aa567 FB |
3530 | dumb_display_init(ds); |
3531 | } else { | |
3532 | #ifdef CONFIG_SDL | |
3533 | sdl_display_init(ds); | |
313aa567 FB |
3534 | #else |
3535 | dumb_display_init(ds); | |
3536 | #endif | |
3537 | } | |
0824d6fc | 3538 | /* init basic PC hardware */ |
fc01f7e7 | 3539 | register_ioport_write(0x80, 1, ioport80_write, 1); |
0824d6fc | 3540 | |
1ccde1cb | 3541 | vga_initialize(ds, phys_ram_base + ram_size, ram_size, |
313aa567 | 3542 | vga_ram_size); |
c45886db | 3543 | #if defined (TARGET_I386) |
0824d6fc | 3544 | cmos_init(); |
c45886db | 3545 | #endif |
0824d6fc FB |
3546 | pic_init(); |
3547 | pit_init(); | |
3548 | serial_init(); | |
c45886db | 3549 | #if defined (TARGET_I386) |
f1510b2c | 3550 | ne2000_init(); |
c45886db | 3551 | #endif |
fc01f7e7 | 3552 | ide_init(); |
cd4c3e88 | 3553 | kbd_init(); |
27503323 FB |
3554 | AUD_init(); |
3555 | DMA_init(); | |
c45886db | 3556 | #if defined (TARGET_I386) |
27503323 | 3557 | SB16_init(); |
c45886db FB |
3558 | #endif |
3559 | #if defined (TARGET_PPC) | |
3560 | PPC_end_init(); | |
3561 | #endif | |
3562 | fdctrl_register((unsigned char **)fd_filename, snapshot, boot_device); | |
77fef8c1 | 3563 | |
0824d6fc | 3564 | /* setup cpu signal handlers for MMU / self modifying code handling */ |
77fef8c1 FB |
3565 | #if !defined(CONFIG_SOFTMMU) |
3566 | ||
3567 | #if defined (TARGET_I386) && defined(USE_CODE_COPY) | |
3568 | { | |
3569 | stack_t stk; | |
3570 | signal_stack = malloc(SIGNAL_STACK_SIZE); | |
3571 | stk.ss_sp = signal_stack; | |
3572 | stk.ss_size = SIGNAL_STACK_SIZE; | |
3573 | stk.ss_flags = 0; | |
3574 | ||
3575 | if (sigaltstack(&stk, NULL) < 0) { | |
3576 | perror("sigaltstack"); | |
3577 | exit(1); | |
3578 | } | |
3579 | } | |
3580 | #endif | |
3581 | ||
0824d6fc FB |
3582 | sigfillset(&act.sa_mask); |
3583 | act.sa_flags = SA_SIGINFO; | |
77fef8c1 FB |
3584 | #if defined (TARGET_I386) && defined(USE_CODE_COPY) |
3585 | act.sa_flags |= SA_ONSTACK; | |
3586 | #endif | |
0824d6fc FB |
3587 | act.sa_sigaction = host_segv_handler; |
3588 | sigaction(SIGSEGV, &act, NULL); | |
3589 | sigaction(SIGBUS, &act, NULL); | |
77fef8c1 FB |
3590 | #if defined (TARGET_I386) && defined(USE_CODE_COPY) |
3591 | sigaction(SIGFPE, &act, NULL); | |
3592 | #endif | |
3a51dee6 | 3593 | #endif |
0824d6fc | 3594 | |
77fef8c1 FB |
3595 | /* timer signal */ |
3596 | sigfillset(&act.sa_mask); | |
3597 | act.sa_flags = SA_SIGINFO; | |
3598 | #if defined (TARGET_I386) && defined(USE_CODE_COPY) | |
3599 | act.sa_flags |= SA_ONSTACK; | |
3600 | #endif | |
0824d6fc FB |
3601 | act.sa_sigaction = host_alarm_handler; |
3602 | sigaction(SIGALRM, &act, NULL); | |
3603 | ||
0824d6fc | 3604 | itv.it_interval.tv_sec = 0; |
87858c89 | 3605 | itv.it_interval.tv_usec = 1000; |
0824d6fc FB |
3606 | itv.it_value.tv_sec = 0; |
3607 | itv.it_value.tv_usec = 10 * 1000; | |
3608 | setitimer(ITIMER_REAL, &itv, NULL); | |
87858c89 FB |
3609 | /* we probe the tick duration of the kernel to inform the user if |
3610 | the emulated kernel requested a too high timer frequency */ | |
3611 | getitimer(ITIMER_REAL, &itv); | |
313aa567 | 3612 | timer_ms = itv.it_interval.tv_usec / 1000; |
87858c89 FB |
3613 | pit_min_timer_count = ((uint64_t)itv.it_interval.tv_usec * PIT_FREQ) / |
3614 | 1000000; | |
7f7f9873 | 3615 | |
b4608c04 FB |
3616 | if (use_gdbstub) { |
3617 | cpu_gdbstub(NULL, main_loop, gdbstub_port); | |
3618 | } else { | |
3619 | main_loop(NULL); | |
0824d6fc | 3620 | } |
0824d6fc FB |
3621 | return 0; |
3622 | } |