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0824d6fc 1/*
1df912cf 2 * QEMU PC System Emulator
0824d6fc 3 *
1df912cf 4 * Copyright (c) 2003 Fabrice Bellard
0824d6fc 5 *
1df912cf
FB		 6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
0824d6fc
FB		 23 */
24#include <stdlib.h>
25#include <stdio.h>
1df912cf 26#include <stdarg.h>
0824d6fc 27#include <string.h>
c45886db 28#include <ctype.h>
0824d6fc
FB		 29#include <getopt.h>
30#include <inttypes.h>
31#include <unistd.h>
32#include <sys/mman.h>
33#include <fcntl.h>
34#include <signal.h>
35#include <time.h>
36#include <sys/time.h>
37#include <malloc.h>
38#include <termios.h>
39#include <sys/poll.h>
40#include <errno.h>
f1510b2c
FB		 41#include <sys/wait.h>
42
43#include <sys/ioctl.h>
44#include <sys/socket.h>
45#include <linux/if.h>
46#include <linux/if_tun.h>
0824d6fc 47
a20dd508 48#include "cpu.h"
0824d6fc 49#include "disas.h"
fc01f7e7
FB		 50#include "thunk.h"
51
52#include "vl.h"
0824d6fc 53
5a67135a 54#define DEFAULT_NETWORK_SCRIPT "/etc/qemu-ifup"
330d0414
FB		 55#define BIOS_FILENAME "bios.bin"
56#define VGABIOS_FILENAME "vgabios.bin"
f1510b2c 57
0824d6fc 58//#define DEBUG_UNUSED_IOPORT
330d0414 59
c9159e53 60//#define DEBUG_IRQ_LATENCY
0824d6fc 61
330d0414
FB		 62/* output Bochs bios info messages */
63//#define DEBUG_BIOS
64
7dea1da4
FB		 65//#define DEBUG_CMOS
66
330d0414
FB		 67/* debug PIC */
68//#define DEBUG_PIC
69
70/* debug NE2000 card */
71//#define DEBUG_NE2000
72
73/* debug PC keyboard */
74//#define DEBUG_KBD
75
313aa567
FB		 76/* debug PC keyboard : only mouse */
77//#define DEBUG_MOUSE
78
7dea1da4
FB		 79//#define DEBUG_SERIAL
80
7916e224
FB		 81#define PHYS_RAM_BASE 0xac000000
82#define PHYS_RAM_MAX_SIZE (256 * 1024 * 1024)
83
c45886db 84#if defined (TARGET_I386)
0824d6fc 85#define KERNEL_LOAD_ADDR 0x00100000
c45886db
FB		 86#elif defined (TARGET_PPC)
87//#define USE_OPEN_FIRMWARE
88#if defined (USE_OPEN_FIRMWARE)
89#define KERNEL_LOAD_ADDR 0x01000000
90#define KERNEL_STACK_ADDR 0x01200000
91#else
92#define KERNEL_LOAD_ADDR 0x00000000
93#define KERNEL_STACK_ADDR 0x00400000
94#endif
95#endif
0824d6fc
FB		 96#define INITRD_LOAD_ADDR 0x00400000
97#define KERNEL_PARAMS_ADDR 0x00090000
98
313aa567
FB		 99#define GUI_REFRESH_INTERVAL 30
100
0824d6fc
FB		 101/* from plex86 (BSD license) */
102struct __attribute__ ((packed)) linux_params {
103 // For 0x00..0x3f, see 'struct screen_info' in linux/include/linux/tty.h.
104 // I just padded out the VESA parts, rather than define them.
105
106 /* 0x000 */ uint8_t orig_x;
107 /* 0x001 */ uint8_t orig_y;
108 /* 0x002 */ uint16_t ext_mem_k;
109 /* 0x004 */ uint16_t orig_video_page;
110 /* 0x006 */ uint8_t orig_video_mode;
111 /* 0x007 */ uint8_t orig_video_cols;
112 /* 0x008 */ uint16_t unused1;
113 /* 0x00a */ uint16_t orig_video_ega_bx;
114 /* 0x00c */ uint16_t unused2;
115 /* 0x00e */ uint8_t orig_video_lines;
116 /* 0x00f */ uint8_t orig_video_isVGA;
117 /* 0x010 */ uint16_t orig_video_points;
118 /* 0x012 */ uint8_t pad0[0x20 - 0x12]; // VESA info.
119 /* 0x020 */ uint16_t cl_magic; // Commandline magic number (0xA33F)
120 /* 0x022 */ uint16_t cl_offset; // Commandline offset. Address of commandline
121 // is calculated as 0x90000 + cl_offset, bu
122 // only if cl_magic == 0xA33F.
123 /* 0x024 */ uint8_t pad1[0x40 - 0x24]; // VESA info.
124
125 /* 0x040 */ uint8_t apm_bios_info[20]; // struct apm_bios_info
126 /* 0x054 */ uint8_t pad2[0x80 - 0x54];
127
128 // Following 2 from 'struct drive_info_struct' in drivers/block/cciss.h.
129 // Might be truncated?
130 /* 0x080 */ uint8_t hd0_info[16]; // hd0-disk-parameter from intvector 0x41
131 /* 0x090 */ uint8_t hd1_info[16]; // hd1-disk-parameter from intvector 0x46
132
133 // System description table truncated to 16 bytes
134 // From 'struct sys_desc_table_struct' in linux/arch/i386/kernel/setup.c.
135 /* 0x0a0 */ uint16_t sys_description_len;
136 /* 0x0a2 */ uint8_t sys_description_table[14];
137 // [0] machine id
138 // [1] machine submodel id
139 // [2] BIOS revision
140 // [3] bit1: MCA bus
141
142 /* 0x0b0 */ uint8_t pad3[0x1e0 - 0xb0];
143 /* 0x1e0 */ uint32_t alt_mem_k;
144 /* 0x1e4 */ uint8_t pad4[4];
145 /* 0x1e8 */ uint8_t e820map_entries;
146 /* 0x1e9 */ uint8_t eddbuf_entries; // EDD_NR
147 /* 0x1ea */ uint8_t pad5[0x1f1 - 0x1ea];
148 /* 0x1f1 */ uint8_t setup_sects; // size of setup.S, number of sectors
149 /* 0x1f2 */ uint16_t mount_root_rdonly; // MOUNT_ROOT_RDONLY (if !=0)
150 /* 0x1f4 */ uint16_t sys_size; // size of compressed kernel-part in the
151 // (b)zImage-file (in 16 byte units, rounded up)
152 /* 0x1f6 */ uint16_t swap_dev; // (unused AFAIK)
153 /* 0x1f8 */ uint16_t ramdisk_flags;
154 /* 0x1fa */ uint16_t vga_mode; // (old one)
155 /* 0x1fc */ uint16_t orig_root_dev; // (high=Major, low=minor)
156 /* 0x1fe */ uint8_t pad6[1];
157 /* 0x1ff */ uint8_t aux_device_info;
158 /* 0x200 */ uint16_t jump_setup; // Jump to start of setup code,
159 // aka "reserved" field.
160 /* 0x202 */ uint8_t setup_signature[4]; // Signature for SETUP-header, ="HdrS"
161 /* 0x206 */ uint16_t header_format_version; // Version number of header format;
162 /* 0x208 */ uint8_t setup_S_temp0[8]; // Used by setup.S for communication with
163 // boot loaders, look there.
164 /* 0x210 */ uint8_t loader_type;
165 // 0 for old one.
166 // else 0xTV:
167 // T=0: LILO
168 // T=1: Loadlin
169 // T=2: bootsect-loader
170 // T=3: SYSLINUX
171 // T=4: ETHERBOOT
172 // V=version
173 /* 0x211 */ uint8_t loadflags;
174 // bit0 = 1: kernel is loaded high (bzImage)
175 // bit7 = 1: Heap and pointer (see below) set by boot
176 // loader.
177 /* 0x212 */ uint16_t setup_S_temp1;
178 /* 0x214 */ uint32_t kernel_start;
179 /* 0x218 */ uint32_t initrd_start;
180 /* 0x21c */ uint32_t initrd_size;
181 /* 0x220 */ uint8_t setup_S_temp2[4];
182 /* 0x224 */ uint16_t setup_S_heap_end_pointer;
183 /* 0x226 */ uint8_t pad7[0x2d0 - 0x226];
184
185 /* 0x2d0 : Int 15, ax=e820 memory map. */
186 // (linux/include/asm-i386/e820.h, 'struct e820entry')
187#define E820MAX 32
188#define E820_RAM 1
189#define E820_RESERVED 2
190#define E820_ACPI 3 /* usable as RAM once ACPI tables have been read */
191#define E820_NVS 4
192 struct {
193 uint64_t addr;
194 uint64_t size;
195 uint32_t type;
196 } e820map[E820MAX];
197
198 /* 0x550 */ uint8_t pad8[0x600 - 0x550];
199
200 // BIOS Enhanced Disk Drive Services.
201 // (From linux/include/asm-i386/edd.h, 'struct edd_info')
202 // Each 'struct edd_info is 78 bytes, times a max of 6 structs in array.
203 /* 0x600 */ uint8_t eddbuf[0x7d4 - 0x600];
204
205 /* 0x7d4 */ uint8_t pad9[0x800 - 0x7d4];
206 /* 0x800 */ uint8_t commandline[0x800];
207
208 /* 0x1000 */
209 uint64_t gdt_table[256];
210 uint64_t idt_table[48];
211};
212
213#define KERNEL_CS 0x10
214#define KERNEL_DS 0x18
215
7dea1da4
FB		 216/* XXX: use a two level table to limit memory usage */
217#define MAX_IOPORTS 65536
0824d6fc 218
5a67135a 219static const char *bios_dir = CONFIG_QEMU_SHAREDIR;
0824d6fc 220char phys_ram_file[1024];
c45886db
FB		 221CPUState *global_env;
222CPUState *cpu_single_env;
fc01f7e7
FB		 223IOPortReadFunc *ioport_read_table[3][MAX_IOPORTS];
224IOPortWriteFunc *ioport_write_table[3][MAX_IOPORTS];
c45886db 225BlockDriverState *bs_table[MAX_DISKS], *fd_table[MAX_FD];
313aa567
FB		 226int vga_ram_size;
227static DisplayState display_state;
a20dd508 228int nographic;
313aa567
FB		 229int term_inited;
230int64_t ticks_per_sec;
36b486bb 231int boot_device = 'c';
0824d6fc
FB		 232
233/***********************************************************/
234/* x86 io ports */
235
c45886db 236uint32_t default_ioport_readb(CPUState *env, uint32_t address)
0824d6fc
FB		 237{
238#ifdef DEBUG_UNUSED_IOPORT
239 fprintf(stderr, "inb: port=0x%04x\n", address);
240#endif
fc01f7e7 241 return 0xff;
0824d6fc
FB		 242}
243
c45886db 244void default_ioport_writeb(CPUState *env, uint32_t address, uint32_t data)
0824d6fc
FB		 245{
246#ifdef DEBUG_UNUSED_IOPORT
247 fprintf(stderr, "outb: port=0x%04x data=0x%02x\n", address, data);
248#endif
249}
250
251/* default is to make two byte accesses */
c45886db 252uint32_t default_ioport_readw(CPUState *env, uint32_t address)
0824d6fc
FB		 253{
254 uint32_t data;
330d0414
FB		 255 data = ioport_read_table[0][address & (MAX_IOPORTS - 1)](env, address);
256 data |= ioport_read_table[0][(address + 1) & (MAX_IOPORTS - 1)](env, address + 1) << 8;
0824d6fc
FB		 257 return data;
258}
259
c45886db 260void default_ioport_writew(CPUState *env, uint32_t address, uint32_t data)
0824d6fc 261{
330d0414
FB		 262 ioport_write_table[0][address & (MAX_IOPORTS - 1)](env, address, data & 0xff);
263 ioport_write_table[0][(address + 1) & (MAX_IOPORTS - 1)](env, address + 1, (data >> 8) & 0xff);
0824d6fc
FB		 264}
265
c45886db 266uint32_t default_ioport_readl(CPUState *env, uint32_t address)
0824d6fc 267{
fc01f7e7
FB		 268#ifdef DEBUG_UNUSED_IOPORT
269 fprintf(stderr, "inl: port=0x%04x\n", address);
270#endif
271 return 0xffffffff;
0824d6fc
FB		 272}
273
c45886db 274void default_ioport_writel(CPUState *env, uint32_t address, uint32_t data)
0824d6fc 275{
fc01f7e7
FB		 276#ifdef DEBUG_UNUSED_IOPORT
277 fprintf(stderr, "outl: port=0x%04x data=0x%02x\n", address, data);
278#endif
0824d6fc
FB		 279}
280
fc01f7e7 281void init_ioports(void)
0824d6fc
FB		 282{
283 int i;
284
fc01f7e7
FB		 285 for(i = 0; i < MAX_IOPORTS; i++) {
286 ioport_read_table[0][i] = default_ioport_readb;
287 ioport_write_table[0][i] = default_ioport_writeb;
288 ioport_read_table[1][i] = default_ioport_readw;
289 ioport_write_table[1][i] = default_ioport_writew;
290 ioport_read_table[2][i] = default_ioport_readl;
291 ioport_write_table[2][i] = default_ioport_writel;
292 }
0824d6fc
FB		 293}
294
fc01f7e7
FB		 295/* size is the word size in byte */
296int register_ioport_read(int start, int length, IOPortReadFunc *func, int size)
f1510b2c 297{
fc01f7e7 298 int i, bsize;
f1510b2c 299
fc01f7e7
FB		 300 if (size == 1)
301 bsize = 0;
302 else if (size == 2)
303 bsize = 1;
304 else if (size == 4)
305 bsize = 2;
306 else
307 return -1;
308 for(i = start; i < start + length; i += size)
309 ioport_read_table[bsize][i] = func;
f1510b2c
FB		 310 return 0;
311}
312
fc01f7e7
FB		 313/* size is the word size in byte */
314int register_ioport_write(int start, int length, IOPortWriteFunc *func, int size)
f1510b2c 315{
fc01f7e7 316 int i, bsize;
f1510b2c 317
fc01f7e7
FB		 318 if (size == 1)
319 bsize = 0;
320 else if (size == 2)
321 bsize = 1;
322 else if (size == 4)
323 bsize = 2;
324 else
325 return -1;
326 for(i = start; i < start + length; i += size)
327 ioport_write_table[bsize][i] = func;
f1510b2c
FB		 328 return 0;
329}
330
0824d6fc
FB		 331void pstrcpy(char *buf, int buf_size, const char *str)
332{
333 int c;
334 char *q = buf;
335
336 if (buf_size <= 0)
337 return;
338
339 for(;;) {
340 c = *str++;
341 if (c == 0 || q >= buf + buf_size - 1)
342 break;
343 *q++ = c;
344 }
345 *q = '\0';
346}
347
348/* strcat and truncate. */
349char *pstrcat(char *buf, int buf_size, const char *s)
350{
351 int len;
352 len = strlen(buf);
353 if (len < buf_size)
354 pstrcpy(buf + len, buf_size - len, s);
355 return buf;
356}
357
358int load_kernel(const char *filename, uint8_t *addr)
359{
c45886db
FB		 360 int fd, size;
361#if defined (TARGET_I386)
362 int setup_sects;
0824d6fc 363 uint8_t bootsect[512];
c45886db 364#endif
0824d6fc 365
c45886db
FB		 366 printf("Load kernel at %p (0x%08x)\n", addr,
367 (uint32_t)addr - (uint32_t)phys_ram_base);
0824d6fc
FB		 368 fd = open(filename, O_RDONLY);
369 if (fd < 0)
370 return -1;
c45886db 371#if defined (TARGET_I386)
0824d6fc
FB		 372 if (read(fd, bootsect, 512) != 512)
373 goto fail;
374 setup_sects = bootsect[0x1F1];
375 if (!setup_sects)
376 setup_sects = 4;
377 /* skip 16 bit setup code */
378 lseek(fd, (setup_sects + 1) * 512, SEEK_SET);
c45886db 379#endif
0824d6fc
FB		 380 size = read(fd, addr, 16 * 1024 * 1024);
381 if (size < 0)
382 goto fail;
383 close(fd);
384 return size;
385 fail:
386 close(fd);
387 return -1;
388}
389
390/* return the size or -1 if error */
391int load_image(const char *filename, uint8_t *addr)
392{
393 int fd, size;
394 fd = open(filename, O_RDONLY);
395 if (fd < 0)
396 return -1;
397 size = lseek(fd, 0, SEEK_END);
398 lseek(fd, 0, SEEK_SET);
399 if (read(fd, addr, size) != size) {
400 close(fd);
401 return -1;
402 }
403 close(fd);
404 return size;
405}
406
c45886db 407void cpu_outb(CPUState *env, int addr, int val)
0824d6fc 408{
fc01f7e7 409 ioport_write_table[0][addr & (MAX_IOPORTS - 1)](env, addr, val);
0824d6fc
FB		 410}
411
c45886db 412void cpu_outw(CPUState *env, int addr, int val)
0824d6fc 413{
fc01f7e7 414 ioport_write_table[1][addr & (MAX_IOPORTS - 1)](env, addr, val);
0824d6fc
FB		 415}
416
c45886db 417void cpu_outl(CPUState *env, int addr, int val)
0824d6fc 418{
fc01f7e7 419 ioport_write_table[2][addr & (MAX_IOPORTS - 1)](env, addr, val);
0824d6fc
FB		 420}
421
c45886db 422int cpu_inb(CPUState *env, int addr)
0824d6fc 423{
fc01f7e7 424 return ioport_read_table[0][addr & (MAX_IOPORTS - 1)](env, addr);
0824d6fc
FB		 425}
426
c45886db 427int cpu_inw(CPUState *env, int addr)
0824d6fc 428{
fc01f7e7 429 return ioport_read_table[1][addr & (MAX_IOPORTS - 1)](env, addr);
0824d6fc
FB		 430}
431
c45886db 432int cpu_inl(CPUState *env, int addr)
0824d6fc 433{
fc01f7e7 434 return ioport_read_table[2][addr & (MAX_IOPORTS - 1)](env, addr);
0824d6fc
FB		 435}
436
437/***********************************************************/
c45886db 438void ioport80_write(CPUState *env, uint32_t addr, uint32_t data)
0824d6fc
FB		 439{
440}
441
442void hw_error(const char *fmt, ...)
443{
444 va_list ap;
445
446 va_start(ap, fmt);
447 fprintf(stderr, "qemu: hardware error: ");
448 vfprintf(stderr, fmt, ap);
449 fprintf(stderr, "\n");
450#ifdef TARGET_I386
451 cpu_x86_dump_state(global_env, stderr, X86_DUMP_FPU | X86_DUMP_CCOP);
c45886db
FB		 452#else
453 cpu_dump_state(global_env, stderr, 0);
0824d6fc
FB		 454#endif
455 va_end(ap);
456 abort();
457}
458
0824d6fc
FB		 459/***********************************************************/
460/* cmos emulation */
461
c45886db 462#if defined (TARGET_I386)
0824d6fc
FB		 463#define RTC_SECONDS 0
464#define RTC_SECONDS_ALARM 1
465#define RTC_MINUTES 2
466#define RTC_MINUTES_ALARM 3
467#define RTC_HOURS 4
468#define RTC_HOURS_ALARM 5
469#define RTC_ALARM_DONT_CARE 0xC0
470
471#define RTC_DAY_OF_WEEK 6
472#define RTC_DAY_OF_MONTH 7
473#define RTC_MONTH 8
474#define RTC_YEAR 9
475
476#define RTC_REG_A 10
477#define RTC_REG_B 11
478#define RTC_REG_C 12
479#define RTC_REG_D 13
480
481/* PC cmos mappings */
482#define REG_EQUIPMENT_BYTE 0x14
dc887a4d 483#define REG_IBM_CENTURY_BYTE 0x32
0824d6fc
FB		 484
485uint8_t cmos_data[128];
486uint8_t cmos_index;
487
c45886db 488void cmos_ioport_write(CPUState *env, uint32_t addr, uint32_t data)
0824d6fc
FB		 489{
490 if (addr == 0x70) {
491 cmos_index = data & 0x7f;
7dea1da4
FB		 492 } else {
493#ifdef DEBUG_CMOS
494 printf("cmos: write index=0x%02x val=0x%02x\n",
495 cmos_index, data);
496#endif
497 switch(addr) {
498 case RTC_SECONDS_ALARM:
499 case RTC_MINUTES_ALARM:
500 case RTC_HOURS_ALARM:
501 /* XXX: not supported */
502 cmos_data[cmos_index] = data;
503 break;
504 case RTC_SECONDS:
505 case RTC_MINUTES:
506 case RTC_HOURS:
507 case RTC_DAY_OF_WEEK:
508 case RTC_DAY_OF_MONTH:
509 case RTC_MONTH:
510 case RTC_YEAR:
511 cmos_data[cmos_index] = data;
512 break;
513 case RTC_REG_A:
514 case RTC_REG_B:
515 cmos_data[cmos_index] = data;
516 break;
517 case RTC_REG_C:
518 case RTC_REG_D:
519 /* cannot write to them */
520 break;
521 default:
522 cmos_data[cmos_index] = data;
523 break;
524 }
0824d6fc
FB		 525 }
526}
527
c45886db 528uint32_t cmos_ioport_read(CPUState *env, uint32_t addr)
0824d6fc
FB		 529{
530 int ret;
531
532 if (addr == 0x70) {
533 return 0xff;
534 } else {
0824d6fc 535 ret = cmos_data[cmos_index];
7dea1da4
FB		 536 switch(cmos_index) {
537 case RTC_REG_A:
538 /* toggle update-in-progress bit for Linux (same hack as
539 plex86) */
0824d6fc 540 cmos_data[RTC_REG_A] ^= 0x80;
7dea1da4
FB		 541 break;
542 case RTC_REG_C:
543 pic_set_irq(8, 0);
0824d6fc 544 cmos_data[RTC_REG_C] = 0x00;
7dea1da4
FB		 545 break;
546 }
547#ifdef DEBUG_CMOS
548 printf("cmos: read index=0x%02x val=0x%02x\n",
549 cmos_index, ret);
550#endif
0824d6fc
FB		 551 return ret;
552 }
553}
554
555
556static inline int to_bcd(int a)
557{
558 return ((a / 10) << 4) | (a % 10);
559}
560
561void cmos_init(void)
562{
563 struct tm *tm;
564 time_t ti;
330d0414 565 int val;
0824d6fc
FB		 566
567 ti = time(NULL);
568 tm = gmtime(&ti);
569 cmos_data[RTC_SECONDS] = to_bcd(tm->tm_sec);
570 cmos_data[RTC_MINUTES] = to_bcd(tm->tm_min);
571 cmos_data[RTC_HOURS] = to_bcd(tm->tm_hour);
572 cmos_data[RTC_DAY_OF_WEEK] = to_bcd(tm->tm_wday);
573 cmos_data[RTC_DAY_OF_MONTH] = to_bcd(tm->tm_mday);
abd0aaff 574 cmos_data[RTC_MONTH] = to_bcd(tm->tm_mon + 1);
0824d6fc
FB		 575 cmos_data[RTC_YEAR] = to_bcd(tm->tm_year % 100);
576
577 cmos_data[RTC_REG_A] = 0x26;
578 cmos_data[RTC_REG_B] = 0x02;
579 cmos_data[RTC_REG_C] = 0x00;
580 cmos_data[RTC_REG_D] = 0x80;
581
330d0414 582 /* various important CMOS locations needed by PC/Bochs bios */
dc887a4d 583 cmos_data[REG_IBM_CENTURY_BYTE] = to_bcd((tm->tm_year / 100) + 19);
330d0414 584
0824d6fc 585 cmos_data[REG_EQUIPMENT_BYTE] = 0x02; /* FPU is there */
313aa567 586 cmos_data[REG_EQUIPMENT_BYTE] |= 0x04; /* PS/2 mouse installed */
0824d6fc 587
330d0414
FB		 588 /* memory size */
589 val = (phys_ram_size / 1024) - 1024;
590 if (val > 65535)
591 val = 65535;
592 cmos_data[0x17] = val;
593 cmos_data[0x18] = val >> 8;
594 cmos_data[0x30] = val;
595 cmos_data[0x31] = val >> 8;
596
597 val = (phys_ram_size / 65536) - ((16 * 1024 * 1024) / 65536);
598 if (val > 65535)
599 val = 65535;
600 cmos_data[0x34] = val;
601 cmos_data[0x35] = val >> 8;
602
36b486bb
FB		 603 switch(boot_device) {
604 case 'a':
c45886db 605 case 'b':
36b486bb
FB		 606 cmos_data[0x3d] = 0x01; /* floppy boot */
607 break;
608 default:
609 case 'c':
610 cmos_data[0x3d] = 0x02; /* hard drive boot */
611 break;
612 case 'd':
613 cmos_data[0x3d] = 0x03; /* CD-ROM boot */
614 break;
615 }
616
fc01f7e7
FB		 617 register_ioport_write(0x70, 2, cmos_ioport_write, 1);
618 register_ioport_read(0x70, 2, cmos_ioport_read, 1);
0824d6fc
FB		 619}
620
c45886db
FB		 621void cmos_register_fd (uint8_t fd0, uint8_t fd1)
622{
623 int nb = 0;
624
625 cmos_data[0x10] = 0;
626 switch (fd0) {
627 case 0:
628 /* 1.44 Mb 3"5 drive */
629 cmos_data[0x10] |= 0x40;
630 break;
631 case 1:
632 /* 2.88 Mb 3"5 drive */
633 cmos_data[0x10] |= 0x60;
634 break;
635 case 2:
636 /* 1.2 Mb 5"5 drive */
637 cmos_data[0x10] |= 0x20;
638 break;
639 }
640 switch (fd1) {
641 case 0:
642 /* 1.44 Mb 3"5 drive */
643 cmos_data[0x10] |= 0x04;
644 break;
645 case 1:
646 /* 2.88 Mb 3"5 drive */
647 cmos_data[0x10] |= 0x06;
648 break;
649 case 2:
650 /* 1.2 Mb 5"5 drive */
651 cmos_data[0x10] |= 0x02;
652 break;
653 }
654 if (fd0 < 3)
655 nb++;
656 if (fd1 < 3)
657 nb++;
658 switch (nb) {
659 case 0:
660 break;
661 case 1:
662 cmos_data[REG_EQUIPMENT_BYTE] |= 0x01; /* 1 drive, ready for boot */
663 break;
664 case 2:
665 cmos_data[REG_EQUIPMENT_BYTE] |= 0x41; /* 2 drives, ready for boot */
666 break;
667 }
668}
669#endif /* TARGET_I386 */
670
0824d6fc
FB		 671/***********************************************************/
672/* 8259 pic emulation */
673
674typedef struct PicState {
675 uint8_t last_irr; /* edge detection */
676 uint8_t irr; /* interrupt request register */
677 uint8_t imr; /* interrupt mask register */
678 uint8_t isr; /* interrupt service register */
679 uint8_t priority_add; /* used to compute irq priority */
680 uint8_t irq_base;
681 uint8_t read_reg_select;
c45886db 682 uint8_t poll;
0824d6fc
FB		 683 uint8_t special_mask;
684 uint8_t init_state;
685 uint8_t auto_eoi;
686 uint8_t rotate_on_autoeoi;
687 uint8_t init4; /* true if 4 byte init */
688} PicState;
689
690/* 0 is master pic, 1 is slave pic */
691PicState pics[2];
692int pic_irq_requested;
693
694/* set irq level. If an edge is detected, then the IRR is set to 1 */
695static inline void pic_set_irq1(PicState *s, int irq, int level)
696{
697 int mask;
698 mask = 1 << irq;
699 if (level) {
700 if ((s->last_irr & mask) == 0)
701 s->irr |= mask;
702 s->last_irr |= mask;
703 } else {
704 s->last_irr &= ~mask;
705 }
706}
707
708static inline int get_priority(PicState *s, int mask)
709{
710 int priority;
711 if (mask == 0)
712 return -1;
713 priority = 7;
714 while ((mask & (1 << ((priority + s->priority_add) & 7))) == 0)
715 priority--;
716 return priority;
717}
718
719/* return the pic wanted interrupt. return -1 if none */
720static int pic_get_irq(PicState *s)
721{
722 int mask, cur_priority, priority;
723
724 mask = s->irr & ~s->imr;
725 priority = get_priority(s, mask);
726 if (priority < 0)
727 return -1;
728 /* compute current priority */
729 cur_priority = get_priority(s, s->isr);
730 if (priority > cur_priority) {
731 /* higher priority found: an irq should be generated */
732 return priority;
733 } else {
734 return -1;
735 }
736}
737
c9159e53
FB		 738/* raise irq to CPU if necessary. must be called every time the active
739 irq may change */
c45886db 740void pic_update_irq(void)
0824d6fc
FB		 741{
742 int irq2, irq;
743
744 /* first look at slave pic */
745 irq2 = pic_get_irq(&pics[1]);
746 if (irq2 >= 0) {
747 /* if irq request by slave pic, signal master PIC */
748 pic_set_irq1(&pics[0], 2, 1);
749 pic_set_irq1(&pics[0], 2, 0);
750 }
751 /* look at requested irq */
752 irq = pic_get_irq(&pics[0]);
753 if (irq >= 0) {
754 if (irq == 2) {
755 /* from slave pic */
756 pic_irq_requested = 8 + irq2;
757 } else {
758 /* from master pic */
759 pic_irq_requested = irq;
760 }
c45886db 761 cpu_interrupt(global_env, CPU_INTERRUPT_HARD);
0824d6fc
FB		 762 }
763}
764
c9159e53
FB		 765#ifdef DEBUG_IRQ_LATENCY
766int64_t irq_time[16];
767int64_t cpu_get_ticks(void);
768#endif
313aa567 769#if defined(DEBUG_PIC)
b118d61e
FB		 770int irq_level[16];
771#endif
c9159e53
FB		 772
773void pic_set_irq(int irq, int level)
774{
313aa567 775#if defined(DEBUG_PIC)
b118d61e
FB		 776 if (level != irq_level[irq]) {
777 printf("pic_set_irq: irq=%d level=%d\n", irq, level);
778 irq_level[irq] = level;
779 }
780#endif
c9159e53
FB		 781#ifdef DEBUG_IRQ_LATENCY
782 if (level) {
783 irq_time[irq] = cpu_get_ticks();
784 }
785#endif
786 pic_set_irq1(&pics[irq >> 3], irq & 7, level);
787 pic_update_irq();
788}
789
c45886db 790int cpu_x86_get_pic_interrupt(CPUState *env)
0824d6fc
FB		 791{
792 int irq, irq2, intno;
793
794 /* signal the pic that the irq was acked by the CPU */
795 irq = pic_irq_requested;
c9159e53 796#ifdef DEBUG_IRQ_LATENCY
313aa567
FB		 797 printf("IRQ%d latency=%0.3fus\n",
798 irq,
799 (double)(cpu_get_ticks() - irq_time[irq]) * 1000000.0 / ticks_per_sec);
c9159e53 800#endif
7dea1da4 801#if defined(DEBUG_PIC)
b118d61e
FB		 802 printf("pic_interrupt: irq=%d\n", irq);
803#endif
c9159e53 804
0824d6fc
FB		 805 if (irq >= 8) {
806 irq2 = irq & 7;
807 pics[1].isr |= (1 << irq2);
808 pics[1].irr &= ~(1 << irq2);
809 irq = 2;
810 intno = pics[1].irq_base + irq2;
811 } else {
812 intno = pics[0].irq_base + irq;
813 }
814 pics[0].isr |= (1 << irq);
815 pics[0].irr &= ~(1 << irq);
816 return intno;
817}
818
c45886db 819void pic_ioport_write(CPUState *env, uint32_t addr, uint32_t val)
0824d6fc
FB		 820{
821 PicState *s;
822 int priority;
823
b118d61e
FB		 824#ifdef DEBUG_PIC
825 printf("pic_write: addr=0x%02x val=0x%02x\n", addr, val);
826#endif
0824d6fc
FB		 827 s = &pics[addr >> 7];
828 addr &= 1;
829 if (addr == 0) {
830 if (val & 0x10) {
831 /* init */
832 memset(s, 0, sizeof(PicState));
833 s->init_state = 1;
834 s->init4 = val & 1;
835 if (val & 0x02)
836 hw_error("single mode not supported");
837 if (val & 0x08)
838 hw_error("level sensitive irq not supported");
839 } else if (val & 0x08) {
c45886db
FB		 840 if (val & 0x04) {
841 s->poll = 1;
842 } else {
0824d6fc
FB		 843 if (val & 0x02)
844 s->read_reg_select = val & 1;
845 if (val & 0x40)
846 s->special_mask = (val >> 5) & 1;
c45886db 847 }
0824d6fc
FB		 848 } else {
849 switch(val) {
850 case 0x00:
851 case 0x80:
852 s->rotate_on_autoeoi = val >> 7;
853 break;
854 case 0x20: /* end of interrupt */
855 case 0xa0:
856 priority = get_priority(s, s->isr);
857 if (priority >= 0) {
858 s->isr &= ~(1 << ((priority + s->priority_add) & 7));
859 }
860 if (val == 0xa0)
861 s->priority_add = (s->priority_add + 1) & 7;
313aa567 862 pic_update_irq();
0824d6fc
FB		 863 break;
864 case 0x60 ... 0x67:
865 priority = val & 7;
866 s->isr &= ~(1 << priority);
313aa567 867 pic_update_irq();
0824d6fc
FB		 868 break;
869 case 0xc0 ... 0xc7:
870 s->priority_add = (val + 1) & 7;
313aa567 871 pic_update_irq();
0824d6fc
FB		 872 break;
873 case 0xe0 ... 0xe7:
874 priority = val & 7;
875 s->isr &= ~(1 << priority);
876 s->priority_add = (priority + 1) & 7;
313aa567 877 pic_update_irq();
0824d6fc
FB		 878 break;
879 }
880 }
881 } else {
882 switch(s->init_state) {
883 case 0:
884 /* normal mode */
885 s->imr = val;
c9159e53 886 pic_update_irq();
0824d6fc
FB		 887 break;
888 case 1:
889 s->irq_base = val & 0xf8;
890 s->init_state = 2;
891 break;
892 case 2:
893 if (s->init4) {
894 s->init_state = 3;
895 } else {
896 s->init_state = 0;
897 }
898 break;
899 case 3:
900 s->auto_eoi = (val >> 1) & 1;
901 s->init_state = 0;
902 break;
903 }
904 }
905}
906
c45886db
FB		 907static uint32_t pic_poll_read (PicState *s, uint32_t addr1)
908{
909 int ret;
910
911 ret = pic_get_irq(s);
912 if (ret >= 0) {
913 if (addr1 >> 7) {
914 pics[0].isr &= ~(1 << 2);
915 pics[0].irr &= ~(1 << 2);
916 }
917 s->irr &= ~(1 << ret);
918 s->isr &= ~(1 << ret);
919 if (addr1 >> 7 || ret != 2)
920 pic_update_irq();
921 } else {
922 ret = 0x07;
923 pic_update_irq();
924 }
925
926 return ret;
927}
928
929uint32_t pic_ioport_read(CPUState *env, uint32_t addr1)
0824d6fc
FB		 930{
931 PicState *s;
b118d61e
FB		 932 unsigned int addr;
933 int ret;
934
935 addr = addr1;
0824d6fc
FB		 936 s = &pics[addr >> 7];
937 addr &= 1;
c45886db
FB		 938 if (s->poll == 1) {
939 ret = pic_poll_read(s, addr1);
940 s->poll = 0;
941 } else {
0824d6fc
FB		 942 if (addr == 0) {
943 if (s->read_reg_select)
b118d61e 944 ret = s->isr;
0824d6fc 945 else
b118d61e 946 ret = s->irr;
0824d6fc 947 } else {
b118d61e 948 ret = s->imr;
0824d6fc 949 }
c45886db 950 }
b118d61e
FB		 951#ifdef DEBUG_PIC
952 printf("pic_read: addr=0x%02x val=0x%02x\n", addr1, ret);
953#endif
954 return ret;
0824d6fc
FB		 955}
956
c45886db
FB		 957/* memory mapped interrupt status */
958uint32_t pic_intack_read(CPUState *env)
959{
960 int ret;
961
962 ret = pic_poll_read(&pics[0], 0x00);
963 if (ret == 2)
964 ret = pic_poll_read(&pics[1], 0x80) + 8;
965 /* Prepare for ISR read */
966 pics[0].read_reg_select = 1;
967
968 return ret;
969}
970
0824d6fc
FB		 971void pic_init(void)
972{
c45886db 973#if defined (TARGET_I386) || defined (TARGET_PPC)
fc01f7e7
FB		 974 register_ioport_write(0x20, 2, pic_ioport_write, 1);
975 register_ioport_read(0x20, 2, pic_ioport_read, 1);
976 register_ioport_write(0xa0, 2, pic_ioport_write, 1);
977 register_ioport_read(0xa0, 2, pic_ioport_read, 1);
c45886db 978#endif
0824d6fc
FB		 979}
980
981/***********************************************************/
982/* 8253 PIT emulation */
983
984#define PIT_FREQ 1193182
985
986#define RW_STATE_LSB 0
987#define RW_STATE_MSB 1
988#define RW_STATE_WORD0 2
989#define RW_STATE_WORD1 3
990#define RW_STATE_LATCHED_WORD0 4
991#define RW_STATE_LATCHED_WORD1 5
992
993typedef struct PITChannelState {
87858c89 994 int count; /* can be 65536 */
0824d6fc
FB		 995 uint16_t latched_count;
996 uint8_t rw_state;
997 uint8_t mode;
998 uint8_t bcd; /* not supported */
999 uint8_t gate; /* timer start */
1000 int64_t count_load_time;
87858c89 1001 int64_t count_last_edge_check_time;
0824d6fc
FB		 1002} PITChannelState;
1003
1004PITChannelState pit_channels[3];
1005int speaker_data_on;
61a2ad53 1006int dummy_refresh_clock;
87858c89 1007int pit_min_timer_count = 0;
0824d6fc 1008
34865134
FB		 1009
1010#if defined(__powerpc__)
1011
1012static inline uint32_t get_tbl(void)
0824d6fc 1013{
34865134
FB		 1014 uint32_t tbl;
1015 asm volatile("mftb %0" : "=r" (tbl));
1016 return tbl;
0824d6fc
FB		 1017}
1018
34865134
FB		 1019static inline uint32_t get_tbu(void)
1020{
1021 uint32_t tbl;
1022 asm volatile("mftbu %0" : "=r" (tbl));
1023 return tbl;
1024}
1025
1026int64_t cpu_get_real_ticks(void)
1027{
1028 uint32_t l, h, h1;
1029 /* NOTE: we test if wrapping has occurred */
1030 do {
1031 h = get_tbu();
1032 l = get_tbl();
1033 h1 = get_tbu();
1034 } while (h != h1);
1035 return ((int64_t)h << 32) | l;
1036}
1037
1038#elif defined(__i386__)
1039
1040int64_t cpu_get_real_ticks(void)
0824d6fc
FB		 1041{
1042 int64_t val;
1043 asm("rdtsc" : "=A" (val));
1044 return val;
1045}
1046
34865134
FB		 1047#else
1048#error unsupported CPU
1049#endif
1050
1051static int64_t cpu_ticks_offset;
1052static int64_t cpu_ticks_last;
1053
1054int64_t cpu_get_ticks(void)
1055{
1056 return cpu_get_real_ticks() + cpu_ticks_offset;
1057}
1058
1059/* enable cpu_get_ticks() */
1060void cpu_enable_ticks(void)
1061{
1062 cpu_ticks_offset = cpu_ticks_last - cpu_get_real_ticks();
1063}
1064
1065/* disable cpu_get_ticks() : the clock is stopped. You must not call
1066 cpu_get_ticks() after that. */
1067void cpu_disable_ticks(void)
1068{
1069 cpu_ticks_last = cpu_get_ticks();
1070}
1071
1072int64_t get_clock(void)
1073{
1074 struct timeval tv;
1075 gettimeofday(&tv, NULL);
1076 return tv.tv_sec * 1000000LL + tv.tv_usec;
1077}
1078
0824d6fc
FB		 1079void cpu_calibrate_ticks(void)
1080{
1081 int64_t usec, ticks;
1082
1083 usec = get_clock();
1084 ticks = cpu_get_ticks();
1085 usleep(50 * 1000);
1086 usec = get_clock() - usec;
1087 ticks = cpu_get_ticks() - ticks;
1088 ticks_per_sec = (ticks * 1000000LL + (usec >> 1)) / usec;
1089}
1090
87858c89
FB		 1091/* compute with 96 bit intermediate result: (a*b)/c */
1092static uint64_t muldiv64(uint64_t a, uint32_t b, uint32_t c)
1093{
1094 union {
1095 uint64_t ll;
1096 struct {
1097#ifdef WORDS_BIGENDIAN
1098 uint32_t high, low;
1099#else
1100 uint32_t low, high;
1101#endif
1102 } l;
1103 } u, res;
1104 uint64_t rl, rh;
1105
1106 u.ll = a;
1107 rl = (uint64_t)u.l.low * (uint64_t)b;
1108 rh = (uint64_t)u.l.high * (uint64_t)b;
1109 rh += (rl >> 32);
1110 res.l.high = rh / c;
1111 res.l.low = (((rh % c) << 32) + (rl & 0xffffffff)) / c;
1112 return res.ll;
1113}
1114
0824d6fc
FB		 1115static int pit_get_count(PITChannelState *s)
1116{
87858c89 1117 uint64_t d;
0824d6fc
FB		 1118 int counter;
1119
87858c89 1120 d = muldiv64(cpu_get_ticks() - s->count_load_time, PIT_FREQ, ticks_per_sec);
0824d6fc
FB		 1121 switch(s->mode) {
1122 case 0:
1123 case 1:
1124 case 4:
1125 case 5:
1126 counter = (s->count - d) & 0xffff;
1127 break;
c2655080
FB		 1128 case 3:
1129 /* XXX: may be incorrect for odd counts */
1130 counter = s->count - ((2 * d) % s->count);
1131 break;
0824d6fc
FB		 1132 default:
1133 counter = s->count - (d % s->count);
1134 break;
1135 }
1136 return counter;
1137}
1138
1139/* get pit output bit */
1140static int pit_get_out(PITChannelState *s)
1141{
87858c89 1142 uint64_t d;
0824d6fc
FB		 1143 int out;
1144
87858c89 1145 d = muldiv64(cpu_get_ticks() - s->count_load_time, PIT_FREQ, ticks_per_sec);
0824d6fc
FB		 1146 switch(s->mode) {
1147 default:
1148 case 0:
1149 out = (d >= s->count);
1150 break;
1151 case 1:
1152 out = (d < s->count);
1153 break;
1154 case 2:
1155 if ((d % s->count) == 0 && d != 0)
1156 out = 1;
1157 else
1158 out = 0;
1159 break;
1160 case 3:
c2655080 1161 out = (d % s->count) < ((s->count + 1) >> 1);
0824d6fc
FB		 1162 break;
1163 case 4:
1164 case 5:
1165 out = (d == s->count);
1166 break;
1167 }
1168 return out;
1169}
1170
87858c89
FB		 1171/* get the number of 0 to 1 transitions we had since we call this
1172 function */
1173/* XXX: maybe better to use ticks precision to avoid getting edges
1174 twice if checks are done at very small intervals */
1175static int pit_get_out_edges(PITChannelState *s)
1176{
1177 uint64_t d1, d2;
1178 int64_t ticks;
1179 int ret, v;
1180
1181 ticks = cpu_get_ticks();
1182 d1 = muldiv64(s->count_last_edge_check_time - s->count_load_time,
1183 PIT_FREQ, ticks_per_sec);
1184 d2 = muldiv64(ticks - s->count_load_time,
1185 PIT_FREQ, ticks_per_sec);
1186 s->count_last_edge_check_time = ticks;
1187 switch(s->mode) {
1188 default:
1189 case 0:
1190 if (d1 < s->count && d2 >= s->count)
1191 ret = 1;
1192 else
1193 ret = 0;
1194 break;
1195 case 1:
1196 ret = 0;
1197 break;
1198 case 2:
1199 d1 /= s->count;
1200 d2 /= s->count;
1201 ret = d2 - d1;
1202 break;
1203 case 3:
c2655080 1204 v = s->count - ((s->count + 1) >> 1);
87858c89
FB		 1205 d1 = (d1 + v) / s->count;
1206 d2 = (d2 + v) / s->count;
1207 ret = d2 - d1;
1208 break;
1209 case 4:
1210 case 5:
1211 if (d1 < s->count && d2 >= s->count)
1212 ret = 1;
1213 else
1214 ret = 0;
1215 break;
1216 }
1217 return ret;
1218}
1219
c2655080
FB		 1220/* val must be 0 or 1 */
1221static inline void pit_set_gate(PITChannelState *s, int val)
1222{
1223 switch(s->mode) {
1224 default:
1225 case 0:
1226 case 4:
1227 /* XXX: just disable/enable counting */
1228 break;
1229 case 1:
1230 case 5:
1231 if (s->gate < val) {
1232 /* restart counting on rising edge */
1233 s->count_load_time = cpu_get_ticks();
1234 s->count_last_edge_check_time = s->count_load_time;
1235 }
1236 break;
1237 case 2:
1238 case 3:
1239 if (s->gate < val) {
1240 /* restart counting on rising edge */
1241 s->count_load_time = cpu_get_ticks();
1242 s->count_last_edge_check_time = s->count_load_time;
1243 }
1244 /* XXX: disable/enable counting */
1245 break;
1246 }
1247 s->gate = val;
1248}
1249
87858c89
FB		 1250static inline void pit_load_count(PITChannelState *s, int val)
1251{
1252 if (val == 0)
1253 val = 0x10000;
1254 s->count_load_time = cpu_get_ticks();
1255 s->count_last_edge_check_time = s->count_load_time;
1256 s->count = val;
1257 if (s == &pit_channels[0] && val <= pit_min_timer_count) {
1258 fprintf(stderr,
36b486bb 1259 "\nWARNING: qemu: on your system, accurate timer emulation is impossible if its frequency is more than %d Hz. If using a 2.5.xx Linux kernel, you must patch asm/param.h to change HZ from 1000 to 100.\n\n",
87858c89
FB		 1260 PIT_FREQ / pit_min_timer_count);
1261 }
1262}
1263
c45886db 1264void pit_ioport_write(CPUState *env, uint32_t addr, uint32_t val)
0824d6fc
FB		 1265{
1266 int channel, access;
1267 PITChannelState *s;
87858c89 1268
0824d6fc
FB		 1269 addr &= 3;
1270 if (addr == 3) {
1271 channel = val >> 6;
1272 if (channel == 3)
1273 return;
1274 s = &pit_channels[channel];
1275 access = (val >> 4) & 3;
1276 switch(access) {
1277 case 0:
1278 s->latched_count = pit_get_count(s);
1279 s->rw_state = RW_STATE_LATCHED_WORD0;
1280 break;
1281 default:
87858c89
FB		 1282 s->mode = (val >> 1) & 7;
1283 s->bcd = val & 1;
0824d6fc
FB		 1284 s->rw_state = access - 1 + RW_STATE_LSB;
1285 break;
1286 }
0824d6fc
FB		 1287 } else {
1288 s = &pit_channels[addr];
1289 switch(s->rw_state) {
1290 case RW_STATE_LSB:
87858c89 1291 pit_load_count(s, val);
0824d6fc
FB		 1292 break;
1293 case RW_STATE_MSB:
87858c89 1294 pit_load_count(s, val << 8);
0824d6fc
FB		 1295 break;
1296 case RW_STATE_WORD0:
1297 case RW_STATE_WORD1:
1298 if (s->rw_state & 1) {
87858c89 1299 pit_load_count(s, (s->latched_count & 0xff) | (val << 8));
0824d6fc
FB		 1300 } else {
1301 s->latched_count = val;
1302 }
1303 s->rw_state ^= 1;
1304 break;
1305 }
1306 }
1307}
1308
c45886db 1309uint32_t pit_ioport_read(CPUState *env, uint32_t addr)
0824d6fc
FB		 1310{
1311 int ret, count;
1312 PITChannelState *s;
1313
1314 addr &= 3;
1315 s = &pit_channels[addr];
1316 switch(s->rw_state) {
1317 case RW_STATE_LSB:
1318 case RW_STATE_MSB:
1319 case RW_STATE_WORD0:
1320 case RW_STATE_WORD1:
1321 count = pit_get_count(s);
1322 if (s->rw_state & 1)
1323 ret = (count >> 8) & 0xff;
1324 else
1325 ret = count & 0xff;
1326 if (s->rw_state & 2)
1327 s->rw_state ^= 1;
1328 break;
1329 default:
1330 case RW_STATE_LATCHED_WORD0:
1331 case RW_STATE_LATCHED_WORD1:
1332 if (s->rw_state & 1)
1333 ret = s->latched_count >> 8;
1334 else
1335 ret = s->latched_count & 0xff;
1336 s->rw_state ^= 1;
1337 break;
1338 }
1339 return ret;
1340}
1341
c45886db
FB		 1342#if defined (TARGET_I386)
1343void speaker_ioport_write(CPUState *env, uint32_t addr, uint32_t val)
0824d6fc
FB		 1344{
1345 speaker_data_on = (val >> 1) & 1;
c2655080 1346 pit_set_gate(&pit_channels[2], val & 1);
0824d6fc
FB		 1347}
1348
c45886db 1349uint32_t speaker_ioport_read(CPUState *env, uint32_t addr)
0824d6fc
FB		 1350{
1351 int out;
1352 out = pit_get_out(&pit_channels[2]);
61a2ad53
FB		 1353 dummy_refresh_clock ^= 1;
1354 return (speaker_data_on << 1) | pit_channels[2].gate | (out << 5) |
1355 (dummy_refresh_clock << 4);
0824d6fc 1356}
c45886db 1357#endif
0824d6fc
FB		 1358
1359void pit_init(void)
1360{
87858c89
FB		 1361 PITChannelState *s;
1362 int i;
1363
1364 cpu_calibrate_ticks();
1365
1366 for(i = 0;i < 3; i++) {
1367 s = &pit_channels[i];
1368 s->mode = 3;
1369 s->gate = (i != 2);
1370 pit_load_count(s, 0);
1371 }
1372
fc01f7e7
FB		 1373 register_ioport_write(0x40, 4, pit_ioport_write, 1);
1374 register_ioport_read(0x40, 3, pit_ioport_read, 1);
0824d6fc 1375
c45886db 1376#if defined (TARGET_I386)
fc01f7e7
FB		 1377 register_ioport_read(0x61, 1, speaker_ioport_read, 1);
1378 register_ioport_write(0x61, 1, speaker_ioport_write, 1);
c45886db 1379#endif
0824d6fc
FB		 1380}
1381
1382/***********************************************************/
1383/* serial port emulation */
1384
1385#define UART_IRQ 4
1386
1387#define UART_LCR_DLAB 0x80 /* Divisor latch access bit */
1388
1389#define UART_IER_MSI 0x08 /* Enable Modem status interrupt */
1390#define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */
1391#define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */
1392#define UART_IER_RDI 0x01 /* Enable receiver data interrupt */
1393
1394#define UART_IIR_NO_INT 0x01 /* No interrupts pending */
1395#define UART_IIR_ID 0x06 /* Mask for the interrupt ID */
1396
1397#define UART_IIR_MSI 0x00 /* Modem status interrupt */
1398#define UART_IIR_THRI 0x02 /* Transmitter holding register empty */
1399#define UART_IIR_RDI 0x04 /* Receiver data interrupt */
1400#define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */
1401
7dea1da4
FB		 1402/*
1403 * These are the definitions for the Modem Control Register
1404 */
1405#define UART_MCR_LOOP 0x10 /* Enable loopback test mode */
1406#define UART_MCR_OUT2 0x08 /* Out2 complement */
1407#define UART_MCR_OUT1 0x04 /* Out1 complement */
1408#define UART_MCR_RTS 0x02 /* RTS complement */
1409#define UART_MCR_DTR 0x01 /* DTR complement */
1410
1411/*
1412 * These are the definitions for the Modem Status Register
1413 */
1414#define UART_MSR_DCD 0x80 /* Data Carrier Detect */
1415#define UART_MSR_RI 0x40 /* Ring Indicator */
1416#define UART_MSR_DSR 0x20 /* Data Set Ready */
1417#define UART_MSR_CTS 0x10 /* Clear to Send */
1418#define UART_MSR_DDCD 0x08 /* Delta DCD */
1419#define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */
1420#define UART_MSR_DDSR 0x02 /* Delta DSR */
1421#define UART_MSR_DCTS 0x01 /* Delta CTS */
1422#define UART_MSR_ANY_DELTA 0x0F /* Any of the delta bits! */
1423
0824d6fc
FB		 1424#define UART_LSR_TEMT 0x40 /* Transmitter empty */
1425#define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */
1426#define UART_LSR_BI 0x10 /* Break interrupt indicator */
1427#define UART_LSR_FE 0x08 /* Frame error indicator */
1428#define UART_LSR_PE 0x04 /* Parity error indicator */
1429#define UART_LSR_OE 0x02 /* Overrun error indicator */
1430#define UART_LSR_DR 0x01 /* Receiver data ready */
1431
1432typedef struct SerialState {
1433 uint8_t divider;
1434 uint8_t rbr; /* receive register */
1435 uint8_t ier;
1436 uint8_t iir; /* read only */
1437 uint8_t lcr;
1438 uint8_t mcr;
1439 uint8_t lsr; /* read only */
1440 uint8_t msr;
1441 uint8_t scr;
7dea1da4
FB		 1442 /* NOTE: this hidden state is necessary for tx irq generation as
1443 it can be reset while reading iir */
1444 int thr_ipending;
0824d6fc
FB		 1445} SerialState;
1446
1447SerialState serial_ports[1];
1448
1449void serial_update_irq(void)
1450{
1451 SerialState *s = &serial_ports[0];
1452
1453 if ((s->lsr & UART_LSR_DR) && (s->ier & UART_IER_RDI)) {
1454 s->iir = UART_IIR_RDI;
7dea1da4 1455 } else if (s->thr_ipending && (s->ier & UART_IER_THRI)) {
0824d6fc
FB		 1456 s->iir = UART_IIR_THRI;
1457 } else {
1458 s->iir = UART_IIR_NO_INT;
1459 }
1460 if (s->iir != UART_IIR_NO_INT) {
1461 pic_set_irq(UART_IRQ, 1);
1462 } else {
1463 pic_set_irq(UART_IRQ, 0);
1464 }
1465}
1466
c45886db 1467void serial_ioport_write(CPUState *env, uint32_t addr, uint32_t val)
0824d6fc
FB		 1468{
1469 SerialState *s = &serial_ports[0];
1470 unsigned char ch;
1471 int ret;
1472
1473 addr &= 7;
7dea1da4
FB		 1474#ifdef DEBUG_SERIAL
1475 printf("serial: write addr=0x%02x val=0x%02x\n", addr, val);
1476#endif
0824d6fc
FB		 1477 switch(addr) {
1478 default:
1479 case 0:
1480 if (s->lcr & UART_LCR_DLAB) {
1481 s->divider = (s->divider & 0xff00) | val;
1482 } else {
7dea1da4 1483 s->thr_ipending = 0;
0824d6fc
FB		 1484 s->lsr &= ~UART_LSR_THRE;
1485 serial_update_irq();
1486
1487 ch = val;
1488 do {
1489 ret = write(1, &ch, 1);
1490 } while (ret != 1);
7dea1da4 1491 s->thr_ipending = 1;
0824d6fc
FB		 1492 s->lsr |= UART_LSR_THRE;
1493 s->lsr |= UART_LSR_TEMT;
1494 serial_update_irq();
1495 }
1496 break;
1497 case 1:
1498 if (s->lcr & UART_LCR_DLAB) {
1499 s->divider = (s->divider & 0x00ff) | (val << 8);
1500 } else {
1501 s->ier = val;
1502 serial_update_irq();
1503 }
1504 break;
1505 case 2:
1506 break;
1507 case 3:
1508 s->lcr = val;
1509 break;
1510 case 4:
1511 s->mcr = val;
1512 break;
1513 case 5:
1514 break;
1515 case 6:
1516 s->msr = val;
1517 break;
1518 case 7:
1519 s->scr = val;
1520 break;
1521 }
1522}
1523
c45886db 1524uint32_t serial_ioport_read(CPUState *env, uint32_t addr)
0824d6fc
FB		 1525{
1526 SerialState *s = &serial_ports[0];
1527 uint32_t ret;
1528
1529 addr &= 7;
1530 switch(addr) {
1531 default:
1532 case 0:
1533 if (s->lcr & UART_LCR_DLAB) {
1534 ret = s->divider & 0xff;
1535 } else {
1536 ret = s->rbr;
1537 s->lsr &= ~(UART_LSR_DR | UART_LSR_BI);
1538 serial_update_irq();
1539 }
1540 break;
1541 case 1:
1542 if (s->lcr & UART_LCR_DLAB) {
1543 ret = (s->divider >> 8) & 0xff;
1544 } else {
1545 ret = s->ier;
1546 }
1547 break;
1548 case 2:
1549 ret = s->iir;
7dea1da4
FB		 1550 /* reset THR pending bit */
1551 if ((ret & 0x7) == UART_IIR_THRI)
1552 s->thr_ipending = 0;
1553 serial_update_irq();
0824d6fc
FB		 1554 break;
1555 case 3:
1556 ret = s->lcr;
1557 break;
1558 case 4:
1559 ret = s->mcr;
1560 break;
1561 case 5:
1562 ret = s->lsr;
1563 break;
1564 case 6:
7dea1da4
FB		 1565 if (s->mcr & UART_MCR_LOOP) {
1566 /* in loopback, the modem output pins are connected to the
1567 inputs */
1568 ret = (s->mcr & 0x0c) << 4;
1569 ret |= (s->mcr & 0x02) << 3;
1570 ret |= (s->mcr & 0x01) << 5;
1571 } else {
1572 ret = s->msr;
1573 }
0824d6fc
FB		 1574 break;
1575 case 7:
1576 ret = s->scr;
1577 break;
1578 }
7dea1da4
FB		 1579#ifdef DEBUG_SERIAL
1580 printf("serial: read addr=0x%02x val=0x%02x\n", addr, ret);
1581#endif
0824d6fc
FB		 1582 return ret;
1583}
1584
1585#define TERM_ESCAPE 0x01 /* ctrl-a is used for escape */
c45886db
FB		 1586static int term_got_escape, term_command;
1587static unsigned char term_cmd_buf[128];
1588
1589typedef struct term_cmd_t {
1590 const unsigned char *name;
1591 void (*handler)(unsigned char *params);
1592} term_cmd_t;
1593
1594static void do_change_cdrom (unsigned char *params);
1595static void do_change_fd0 (unsigned char *params);
1596static void do_change_fd1 (unsigned char *params);
1597
1598static term_cmd_t term_cmds[] = {
1599 { "changecd", &do_change_cdrom, },
1600 { "changefd0", &do_change_fd0, },
1601 { "changefd1", &do_change_fd1, },
1602 { NULL, NULL, },
1603};
0824d6fc
FB		 1604
1605void term_print_help(void)
1606{
1607 printf("\n"
1608 "C-a h print this help\n"
1609 "C-a x exit emulatior\n"
c45886db 1610 "C-a d switch on/off debug log\n"
33e3963e 1611 "C-a s save disk data back to file (if -snapshot)\n"
0824d6fc 1612 "C-a b send break (magic sysrq)\n"
c45886db 1613 "C-a c send qemu internal command\n"
0824d6fc
FB		 1614 "C-a C-a send C-a\n"
1615 );
1616}
1617
c45886db
FB		 1618static void do_change_cdrom (unsigned char *params)
1619{
1620 /* Dunno how to do it... */
1621}
1622
1623static void do_change_fd (int fd, unsigned char *params)
1624{
1625 unsigned char *name_start, *name_end, *ros;
1626 int ro;
1627
1628 for (name_start = params;
1629 isspace(*name_start); name_start++)
1630 continue;
1631 if (*name_start == '\0')
1632 return;
1633 for (name_end = name_start;
1634 !isspace(*name_end) && *name_end != '\0'; name_end++)
1635 continue;
1636 for (ros = name_end + 1; isspace(*ros); ros++)
1637 continue;
1638 if (ros[0] == 'r' && ros[1] == 'o')
1639 ro = 1;
1640 else
1641 ro = 0;
1642 *name_end = '\0';
1643 printf("Change fd %d to %s (%s)\n", fd, name_start, params);
1644 fdctrl_disk_change(fd, name_start, ro);
1645}
1646
1647static void do_change_fd0 (unsigned char *params)
1648{
1649 do_change_fd(0, params);
1650}
1651
1652static void do_change_fd1 (unsigned char *params)
1653{
1654 do_change_fd(1, params);
1655}
1656
1657static void serial_treat_command ()
1658{
1659 unsigned char *cmd_start, *cmd_end;
1660 int i;
1661
1662 for (cmd_start = term_cmd_buf; isspace(*cmd_start); cmd_start++)
1663 continue;
1664 for (cmd_end = cmd_start;
1665 !isspace(*cmd_end) && *cmd_end != '\0'; cmd_end++)
1666 continue;
1667 for (i = 0; term_cmds[i].name != NULL; i++) {
1668 if (strlen(term_cmds[i].name) == (cmd_end - cmd_start) &&
1669 memcmp(term_cmds[i].name, cmd_start, cmd_end - cmd_start) == 0) {
1670 (*term_cmds[i].handler)(cmd_end + 1);
1671 return;
1672 }
1673 }
1674 *cmd_end = '\0';
1675 printf("Unknown term command: %s\n", cmd_start);
1676}
1677
1678extern FILE *logfile;
1679
0824d6fc
FB		 1680/* called when a char is received */
1681void serial_received_byte(SerialState *s, int ch)
1682{
c45886db
FB		 1683 if (term_command) {
1684 if (ch == '\n' || ch == '\r' || term_command == 127) {
1685 printf("\n");
1686 serial_treat_command();
1687 term_command = 0;
1688 } else {
1689 if (ch == 0x7F || ch == 0x08) {
1690 if (term_command > 1) {
1691 term_cmd_buf[--term_command - 1] = '\0';
1692 printf("\r "
1693 " ");
1694 printf("\r> %s", term_cmd_buf);
1695 }
1696 } else if (ch > 0x1f) {
1697 term_cmd_buf[term_command++ - 1] = ch;
1698 term_cmd_buf[term_command - 1] = '\0';
1699 printf("\r> %s", term_cmd_buf);
1700 }
1701 fflush(stdout);
1702 }
1703 } else if (term_got_escape) {
0824d6fc
FB		 1704 term_got_escape = 0;
1705 switch(ch) {
1706 case 'h':
1707 term_print_help();
1708 break;
1709 case 'x':
1710 exit(0);
1711 break;
33e3963e
FB		 1712 case 's':
1713 {
1714 int i;
1715 for (i = 0; i < MAX_DISKS; i++) {
1716 if (bs_table[i])
1717 bdrv_commit(bs_table[i]);
1718 }
1719 }
1720 break;
0824d6fc
FB		 1721 case 'b':
1722 /* send break */
1723 s->rbr = 0;
1724 s->lsr |= UART_LSR_BI | UART_LSR_DR;
1725 serial_update_irq();
1726 break;
c45886db
FB		 1727 case 'c':
1728 printf("> ");
1729 fflush(stdout);
1730 term_command = 1;
07ad1b93 1731 break;
0824d6fc
FB		 1732 case TERM_ESCAPE:
1733 goto send_char;
1734 }
1735 } else if (ch == TERM_ESCAPE) {
1736 term_got_escape = 1;
1737 } else {
1738 send_char:
1739 s->rbr = ch;
1740 s->lsr |= UART_LSR_DR;
1741 serial_update_irq();
1742 }
1743}
1744
0824d6fc
FB		 1745void serial_init(void)
1746{
1747 SerialState *s = &serial_ports[0];
1748
1749 s->lsr = UART_LSR_TEMT | UART_LSR_THRE;
7dea1da4
FB		 1750 s->iir = UART_IIR_NO_INT;
1751
c45886db 1752#if defined(TARGET_I386) || defined (TARGET_PPC)
fc01f7e7
FB		 1753 register_ioport_write(0x3f8, 8, serial_ioport_write, 1);
1754 register_ioport_read(0x3f8, 8, serial_ioport_read, 1);
c45886db 1755#endif
0824d6fc
FB		 1756}
1757
f1510b2c
FB		 1758/***********************************************************/
1759/* ne2000 emulation */
1760
c45886db 1761#if defined (TARGET_I386)
f1510b2c
FB		 1762#define NE2000_IOPORT 0x300
1763#define NE2000_IRQ 9
1764
1765#define MAX_ETH_FRAME_SIZE 1514
1766
1767#define E8390_CMD 0x00 /* The command register (for all pages) */
1768/* Page 0 register offsets. */
1769#define EN0_CLDALO 0x01 /* Low byte of current local dma addr RD */
1770#define EN0_STARTPG 0x01 /* Starting page of ring bfr WR */
1771#define EN0_CLDAHI 0x02 /* High byte of current local dma addr RD */
1772#define EN0_STOPPG 0x02 /* Ending page +1 of ring bfr WR */
1773#define EN0_BOUNDARY 0x03 /* Boundary page of ring bfr RD WR */
1774#define EN0_TSR 0x04 /* Transmit status reg RD */
1775#define EN0_TPSR 0x04 /* Transmit starting page WR */
1776#define EN0_NCR 0x05 /* Number of collision reg RD */
1777#define EN0_TCNTLO 0x05 /* Low byte of tx byte count WR */
1778#define EN0_FIFO 0x06 /* FIFO RD */
1779#define EN0_TCNTHI 0x06 /* High byte of tx byte count WR */
1780#define EN0_ISR 0x07 /* Interrupt status reg RD WR */
1781#define EN0_CRDALO 0x08 /* low byte of current remote dma address RD */
1782#define EN0_RSARLO 0x08 /* Remote start address reg 0 */
1783#define EN0_CRDAHI 0x09 /* high byte, current remote dma address RD */
1784#define EN0_RSARHI 0x09 /* Remote start address reg 1 */
1785#define EN0_RCNTLO 0x0a /* Remote byte count reg WR */
1786#define EN0_RCNTHI 0x0b /* Remote byte count reg WR */
1787#define EN0_RSR 0x0c /* rx status reg RD */
1788#define EN0_RXCR 0x0c /* RX configuration reg WR */
1789#define EN0_TXCR 0x0d /* TX configuration reg WR */
1790#define EN0_COUNTER0 0x0d /* Rcv alignment error counter RD */
1791#define EN0_DCFG 0x0e /* Data configuration reg WR */
1792#define EN0_COUNTER1 0x0e /* Rcv CRC error counter RD */
1793#define EN0_IMR 0x0f /* Interrupt mask reg WR */
1794#define EN0_COUNTER2 0x0f /* Rcv missed frame error counter RD */
1795
1796#define EN1_PHYS 0x11
1797#define EN1_CURPAG 0x17
1798#define EN1_MULT 0x18
1799
1800/* Register accessed at EN_CMD, the 8390 base addr. */
1801#define E8390_STOP 0x01 /* Stop and reset the chip */
1802#define E8390_START 0x02 /* Start the chip, clear reset */
1803#define E8390_TRANS 0x04 /* Transmit a frame */
1804#define E8390_RREAD 0x08 /* Remote read */
1805#define E8390_RWRITE 0x10 /* Remote write */
1806#define E8390_NODMA 0x20 /* Remote DMA */
1807#define E8390_PAGE0 0x00 /* Select page chip registers */
1808#define E8390_PAGE1 0x40 /* using the two high-order bits */
1809#define E8390_PAGE2 0x80 /* Page 3 is invalid. */
1810
1811/* Bits in EN0_ISR - Interrupt status register */
1812#define ENISR_RX 0x01 /* Receiver, no error */
1813#define ENISR_TX 0x02 /* Transmitter, no error */
1814#define ENISR_RX_ERR 0x04 /* Receiver, with error */
1815#define ENISR_TX_ERR 0x08 /* Transmitter, with error */
1816#define ENISR_OVER 0x10 /* Receiver overwrote the ring */
1817#define ENISR_COUNTERS 0x20 /* Counters need emptying */
1818#define ENISR_RDC 0x40 /* remote dma complete */
1819#define ENISR_RESET 0x80 /* Reset completed */
1820#define ENISR_ALL 0x3f /* Interrupts we will enable */
1821
1822/* Bits in received packet status byte and EN0_RSR*/
1823#define ENRSR_RXOK 0x01 /* Received a good packet */
1824#define ENRSR_CRC 0x02 /* CRC error */
1825#define ENRSR_FAE 0x04 /* frame alignment error */
1826#define ENRSR_FO 0x08 /* FIFO overrun */
1827#define ENRSR_MPA 0x10 /* missed pkt */
1828#define ENRSR_PHY 0x20 /* physical/multicast address */
1829#define ENRSR_DIS 0x40 /* receiver disable. set in monitor mode */
1830#define ENRSR_DEF 0x80 /* deferring */
1831
1832/* Transmitted packet status, EN0_TSR. */
1833#define ENTSR_PTX 0x01 /* Packet transmitted without error */
1834#define ENTSR_ND 0x02 /* The transmit wasn't deferred. */
1835#define ENTSR_COL 0x04 /* The transmit collided at least once. */
1836#define ENTSR_ABT 0x08 /* The transmit collided 16 times, and was deferred. */
1837#define ENTSR_CRS 0x10 /* The carrier sense was lost. */
1838#define ENTSR_FU 0x20 /* A "FIFO underrun" occurred during transmit. */
1839#define ENTSR_CDH 0x40 /* The collision detect "heartbeat" signal was lost. */
1840#define ENTSR_OWC 0x80 /* There was an out-of-window collision. */
1841
1842#define NE2000_MEM_SIZE 32768
1843
1844typedef struct NE2000State {
1845 uint8_t cmd;
1846 uint32_t start;
1847 uint32_t stop;
1848 uint8_t boundary;
1849 uint8_t tsr;
1850 uint8_t tpsr;
1851 uint16_t tcnt;
1852 uint16_t rcnt;
1853 uint32_t rsar;
1854 uint8_t isr;
1855 uint8_t dcfg;
1856 uint8_t imr;
1857 uint8_t phys[6]; /* mac address */
1858 uint8_t curpag;
1859 uint8_t mult[8]; /* multicast mask array */
1860 uint8_t mem[NE2000_MEM_SIZE];
1861} NE2000State;
1862
1863NE2000State ne2000_state;
1864int net_fd = -1;
1865char network_script[1024];
1866
1867void ne2000_reset(void)
1868{
1869 NE2000State *s = &ne2000_state;
1870 int i;
1871
1872 s->isr = ENISR_RESET;
1873 s->mem[0] = 0x52;
1874 s->mem[1] = 0x54;
1875 s->mem[2] = 0x00;
1876 s->mem[3] = 0x12;
1877 s->mem[4] = 0x34;
1878 s->mem[5] = 0x56;
1879 s->mem[14] = 0x57;
1880 s->mem[15] = 0x57;
1881
1882 /* duplicate prom data */
1883 for(i = 15;i >= 0; i--) {
1884 s->mem[2 * i] = s->mem[i];
1885 s->mem[2 * i + 1] = s->mem[i];
1886 }
1887}
1888
1889void ne2000_update_irq(NE2000State *s)
1890{
1891 int isr;
1892 isr = s->isr & s->imr;
1893 if (isr)
1894 pic_set_irq(NE2000_IRQ, 1);
1895 else
1896 pic_set_irq(NE2000_IRQ, 0);
1897}
1898
1899int net_init(void)
1900{
1901 struct ifreq ifr;
1902 int fd, ret, pid, status;
1903
1904 fd = open("/dev/net/tun", O_RDWR);
1905 if (fd < 0) {
1906 fprintf(stderr, "warning: could not open /dev/net/tun: no virtual network emulation\n");
1907 return -1;
1908 }
1909 memset(&ifr, 0, sizeof(ifr));
1910 ifr.ifr_flags = IFF_TAP | IFF_NO_PI;
1911 pstrcpy(ifr.ifr_name, IFNAMSIZ, "tun%d");
1912 ret = ioctl(fd, TUNSETIFF, (void *) &ifr);
1913 if (ret != 0) {
1914 fprintf(stderr, "warning: could not configure /dev/net/tun: no virtual network emulation\n");
1915 close(fd);
1916 return -1;
1917 }
fc01f7e7 1918 printf("Connected to host network interface: %s\n", ifr.ifr_name);
f1510b2c
FB		 1919 fcntl(fd, F_SETFL, O_NONBLOCK);
1920 net_fd = fd;
1921
1922 /* try to launch network init script */
1923 pid = fork();
1924 if (pid >= 0) {
1925 if (pid == 0) {
1926 execl(network_script, network_script, ifr.ifr_name, NULL);
1927 exit(1);
1928 }
1929 while (waitpid(pid, &status, 0) != pid);
1930 if (!WIFEXITED(status) ||
1931 WEXITSTATUS(status) != 0) {
1932 fprintf(stderr, "%s: could not launch network script for '%s'\n",
1933 network_script, ifr.ifr_name);
1934 }
1935 }
1936 return 0;
1937}
1938
1939void net_send_packet(NE2000State *s, const uint8_t *buf, int size)
1940{
1941#ifdef DEBUG_NE2000
1942 printf("NE2000: sending packet size=%d\n", size);
1943#endif
1944 write(net_fd, buf, size);
1945}
1946
1947/* return true if the NE2000 can receive more data */
1948int ne2000_can_receive(NE2000State *s)
1949{
1950 int avail, index, boundary;
1951
1952 if (s->cmd & E8390_STOP)
1953 return 0;
1954 index = s->curpag << 8;
1955 boundary = s->boundary << 8;
1956 if (index < boundary)
1957 avail = boundary - index;
1958 else
1959 avail = (s->stop - s->start) - (index - boundary);
1960 if (avail < (MAX_ETH_FRAME_SIZE + 4))
1961 return 0;
1962 return 1;
1963}
1964
1965void ne2000_receive(NE2000State *s, uint8_t *buf, int size)
1966{
1967 uint8_t *p;
1968 int total_len, next, avail, len, index;
1969
1970#if defined(DEBUG_NE2000)
1971 printf("NE2000: received len=%d\n", size);
1972#endif
1973
1974 index = s->curpag << 8;
1975 /* 4 bytes for header */
1976 total_len = size + 4;
1977 /* address for next packet (4 bytes for CRC) */
1978 next = index + ((total_len + 4 + 255) & ~0xff);
1979 if (next >= s->stop)
1980 next -= (s->stop - s->start);
1981 /* prepare packet header */
1982 p = s->mem + index;
1983 p[0] = ENRSR_RXOK; /* receive status */
1984 p[1] = next >> 8;
1985 p[2] = total_len;
1986 p[3] = total_len >> 8;
1987 index += 4;
1988
1989 /* write packet data */
1990 while (size > 0) {
1991 avail = s->stop - index;
1992 len = size;
1993 if (len > avail)
1994 len = avail;
1995 memcpy(s->mem + index, buf, len);
1996 buf += len;
1997 index += len;
1998 if (index == s->stop)
1999 index = s->start;
2000 size -= len;
2001 }
2002 s->curpag = next >> 8;
2003
2004 /* now we can signal we have receive something */
2005 s->isr |= ENISR_RX;
2006 ne2000_update_irq(s);
2007}
2008
c45886db 2009void ne2000_ioport_write(CPUState *env, uint32_t addr, uint32_t val)
f1510b2c
FB		 2010{
2011 NE2000State *s = &ne2000_state;
2012 int offset, page;
2013
2014 addr &= 0xf;
2015#ifdef DEBUG_NE2000
2016 printf("NE2000: write addr=0x%x val=0x%02x\n", addr, val);
2017#endif
2018 if (addr == E8390_CMD) {
2019 /* control register */
2020 s->cmd = val;
2021 if (val & E8390_START) {
2022 /* test specific case: zero length transfert */
2023 if ((val & (E8390_RREAD | E8390_RWRITE)) &&
2024 s->rcnt == 0) {
2025 s->isr |= ENISR_RDC;
2026 ne2000_update_irq(s);
2027 }
2028 if (val & E8390_TRANS) {
2029 net_send_packet(s, s->mem + (s->tpsr << 8), s->tcnt);
2030 /* signal end of transfert */
2031 s->tsr = ENTSR_PTX;
2032 s->isr |= ENISR_TX;
2033 ne2000_update_irq(s);
2034 }
2035 }
2036 } else {
2037 page = s->cmd >> 6;
2038 offset = addr | (page << 4);
2039 switch(offset) {
2040 case EN0_STARTPG:
2041 s->start = val << 8;
2042 break;
2043 case EN0_STOPPG:
2044 s->stop = val << 8;
2045 break;
2046 case EN0_BOUNDARY:
2047 s->boundary = val;
2048 break;
2049 case EN0_IMR:
2050 s->imr = val;
2051 ne2000_update_irq(s);
2052 break;
2053 case EN0_TPSR:
2054 s->tpsr = val;
2055 break;
2056 case EN0_TCNTLO:
2057 s->tcnt = (s->tcnt & 0xff00) | val;
2058 break;
2059 case EN0_TCNTHI:
2060 s->tcnt = (s->tcnt & 0x00ff) | (val << 8);
2061 break;
2062 case EN0_RSARLO:
2063 s->rsar = (s->rsar & 0xff00) | val;
2064 break;
2065 case EN0_RSARHI:
2066 s->rsar = (s->rsar & 0x00ff) | (val << 8);
2067 break;
2068 case EN0_RCNTLO:
2069 s->rcnt = (s->rcnt & 0xff00) | val;
2070 break;
2071 case EN0_RCNTHI:
2072 s->rcnt = (s->rcnt & 0x00ff) | (val << 8);
2073 break;
2074 case EN0_DCFG:
2075 s->dcfg = val;
2076 break;
2077 case EN0_ISR:
2078 s->isr &= ~val;
2079 ne2000_update_irq(s);
2080 break;
2081 case EN1_PHYS ... EN1_PHYS + 5:
2082 s->phys[offset - EN1_PHYS] = val;
2083 break;
2084 case EN1_CURPAG:
2085 s->curpag = val;
2086 break;
2087 case EN1_MULT ... EN1_MULT + 7:
2088 s->mult[offset - EN1_MULT] = val;
2089 break;
2090 }
2091 }
2092}
2093
c45886db 2094uint32_t ne2000_ioport_read(CPUState *env, uint32_t addr)
f1510b2c
FB		 2095{
2096 NE2000State *s = &ne2000_state;
2097 int offset, page, ret;
2098
2099 addr &= 0xf;
2100 if (addr == E8390_CMD) {
2101 ret = s->cmd;
2102 } else {
2103 page = s->cmd >> 6;
2104 offset = addr | (page << 4);
2105 switch(offset) {
2106 case EN0_TSR:
2107 ret = s->tsr;
2108 break;
2109 case EN0_BOUNDARY:
2110 ret = s->boundary;
2111 break;
2112 case EN0_ISR:
2113 ret = s->isr;
2114 break;
2115 case EN1_PHYS ... EN1_PHYS + 5:
2116 ret = s->phys[offset - EN1_PHYS];
2117 break;
2118 case EN1_CURPAG:
2119 ret = s->curpag;
2120 break;
2121 case EN1_MULT ... EN1_MULT + 7:
2122 ret = s->mult[offset - EN1_MULT];
2123 break;
2124 default:
2125 ret = 0x00;
2126 break;
2127 }
2128 }
2129#ifdef DEBUG_NE2000
2130 printf("NE2000: read addr=0x%x val=%02x\n", addr, ret);
2131#endif
2132 return ret;
2133}
2134
c45886db 2135void ne2000_asic_ioport_write(CPUState *env, uint32_t addr, uint32_t val)
f1510b2c
FB		 2136{
2137 NE2000State *s = &ne2000_state;
2138 uint8_t *p;
2139
2140#ifdef DEBUG_NE2000
2141 printf("NE2000: asic write val=0x%04x\n", val);
2142#endif
2143 p = s->mem + s->rsar;
2144 if (s->dcfg & 0x01) {
2145 /* 16 bit access */
2146 p[0] = val;
2147 p[1] = val >> 8;
2148 s->rsar += 2;
2149 s->rcnt -= 2;
2150 } else {
2151 /* 8 bit access */
2152 p[0] = val;
2153 s->rsar++;
2154 s->rcnt--;
2155 }
2156 /* wrap */
2157 if (s->rsar == s->stop)
2158 s->rsar = s->start;
2159 if (s->rcnt == 0) {
2160 /* signal end of transfert */
2161 s->isr |= ENISR_RDC;
2162 ne2000_update_irq(s);
2163 }
2164}
2165
c45886db 2166uint32_t ne2000_asic_ioport_read(CPUState *env, uint32_t addr)
f1510b2c
FB		 2167{
2168 NE2000State *s = &ne2000_state;
2169 uint8_t *p;
2170 int ret;
2171
2172 p = s->mem + s->rsar;
2173 if (s->dcfg & 0x01) {
2174 /* 16 bit access */
2175 ret = p[0] | (p[1] << 8);
2176 s->rsar += 2;
2177 s->rcnt -= 2;
2178 } else {
2179 /* 8 bit access */
2180 ret = p[0];
2181 s->rsar++;
2182 s->rcnt--;
2183 }
2184 /* wrap */
2185 if (s->rsar == s->stop)
2186 s->rsar = s->start;
2187 if (s->rcnt == 0) {
2188 /* signal end of transfert */
2189 s->isr |= ENISR_RDC;
2190 ne2000_update_irq(s);
2191 }
2192#ifdef DEBUG_NE2000
2193 printf("NE2000: asic read val=0x%04x\n", ret);
2194#endif
2195 return ret;
2196}
2197
c45886db 2198void ne2000_reset_ioport_write(CPUState *env, uint32_t addr, uint32_t val)
f1510b2c
FB		 2199{
2200 /* nothing to do (end of reset pulse) */
2201}
2202
c45886db 2203uint32_t ne2000_reset_ioport_read(CPUState *env, uint32_t addr)
f1510b2c
FB		 2204{
2205 ne2000_reset();
2206 return 0;
2207}
2208
2209void ne2000_init(void)
2210{
fc01f7e7
FB		 2211 register_ioport_write(NE2000_IOPORT, 16, ne2000_ioport_write, 1);
2212 register_ioport_read(NE2000_IOPORT, 16, ne2000_ioport_read, 1);
f1510b2c 2213
fc01f7e7
FB		 2214 register_ioport_write(NE2000_IOPORT + 0x10, 1, ne2000_asic_ioport_write, 1);
2215 register_ioport_read(NE2000_IOPORT + 0x10, 1, ne2000_asic_ioport_read, 1);
2216 register_ioport_write(NE2000_IOPORT + 0x10, 2, ne2000_asic_ioport_write, 2);
2217 register_ioport_read(NE2000_IOPORT + 0x10, 2, ne2000_asic_ioport_read, 2);
f1510b2c 2218
fc01f7e7
FB		 2219 register_ioport_write(NE2000_IOPORT + 0x1f, 1, ne2000_reset_ioport_write, 1);
2220 register_ioport_read(NE2000_IOPORT + 0x1f, 1, ne2000_reset_ioport_read, 1);
f1510b2c
FB		 2221 ne2000_reset();
2222}
c45886db
FB		 2223#endif
2224
2225/***********************************************************/
2226/* PC floppy disk controler emulation glue */
2227#define PC_FDC_DMA 0x2
2228#define PC_FDC_IRQ 0x6
2229#define PC_FDC_BASE 0x3F0
2230
2231static void fdctrl_register (unsigned char **disknames, int ro,
2232 char boot_device)
2233{
2234 int i;
2235
2236 fdctrl_init(PC_FDC_IRQ, PC_FDC_DMA, 0, PC_FDC_BASE, boot_device);
2237 for (i = 0; i < MAX_FD; i++) {
2238 if (disknames[i] != NULL)
2239 fdctrl_disk_change(i, disknames[i], ro);
2240 }
2241}
f1510b2c 2242
cd4c3e88 2243/***********************************************************/
330d0414
FB		 2244/* keyboard emulation */
2245
2246/* Keyboard Controller Commands */
2247#define KBD_CCMD_READ_MODE 0x20 /* Read mode bits */
2248#define KBD_CCMD_WRITE_MODE 0x60 /* Write mode bits */
2249#define KBD_CCMD_GET_VERSION 0xA1 /* Get controller version */
2250#define KBD_CCMD_MOUSE_DISABLE 0xA7 /* Disable mouse interface */
2251#define KBD_CCMD_MOUSE_ENABLE 0xA8 /* Enable mouse interface */
2252#define KBD_CCMD_TEST_MOUSE 0xA9 /* Mouse interface test */
2253#define KBD_CCMD_SELF_TEST 0xAA /* Controller self test */
2254#define KBD_CCMD_KBD_TEST 0xAB /* Keyboard interface test */
2255#define KBD_CCMD_KBD_DISABLE 0xAD /* Keyboard interface disable */
2256#define KBD_CCMD_KBD_ENABLE 0xAE /* Keyboard interface enable */
2257#define KBD_CCMD_READ_INPORT 0xC0 /* read input port */
2258#define KBD_CCMD_READ_OUTPORT 0xD0 /* read output port */
2259#define KBD_CCMD_WRITE_OUTPORT 0xD1 /* write output port */
2260#define KBD_CCMD_WRITE_OBUF 0xD2
2261#define KBD_CCMD_WRITE_AUX_OBUF 0xD3 /* Write to output buffer as if
2262 initiated by the auxiliary device */
2263#define KBD_CCMD_WRITE_MOUSE 0xD4 /* Write the following byte to the mouse */
1f5476fc
FB		 2264#define KBD_CCMD_DISABLE_A20 0xDD /* HP vectra only ? */
2265#define KBD_CCMD_ENABLE_A20 0xDF /* HP vectra only ? */
330d0414
FB		 2266#define KBD_CCMD_RESET 0xFE
2267
2268/* Keyboard Commands */
2269#define KBD_CMD_SET_LEDS 0xED /* Set keyboard leds */
2270#define KBD_CMD_ECHO 0xEE
07ad1b93 2271#define KBD_CMD_GET_ID 0xF2 /* get keyboard ID */
330d0414
FB		 2272#define KBD_CMD_SET_RATE 0xF3 /* Set typematic rate */
2273#define KBD_CMD_ENABLE 0xF4 /* Enable scanning */
2274#define KBD_CMD_RESET_DISABLE 0xF5 /* reset and disable scanning */
2275#define KBD_CMD_RESET_ENABLE 0xF6 /* reset and enable scanning */
2276#define KBD_CMD_RESET 0xFF /* Reset */
2277
2278/* Keyboard Replies */
2279#define KBD_REPLY_POR 0xAA /* Power on reset */
2280#define KBD_REPLY_ACK 0xFA /* Command ACK */
2281#define KBD_REPLY_RESEND 0xFE /* Command NACK, send the cmd again */
2282
2283/* Status Register Bits */
2284#define KBD_STAT_OBF 0x01 /* Keyboard output buffer full */
2285#define KBD_STAT_IBF 0x02 /* Keyboard input buffer full */
2286#define KBD_STAT_SELFTEST 0x04 /* Self test successful */
2287#define KBD_STAT_CMD 0x08 /* Last write was a command write (0=data) */
2288#define KBD_STAT_UNLOCKED 0x10 /* Zero if keyboard locked */
2289#define KBD_STAT_MOUSE_OBF 0x20 /* Mouse output buffer full */
2290#define KBD_STAT_GTO 0x40 /* General receive/xmit timeout */
2291#define KBD_STAT_PERR 0x80 /* Parity error */
2292
2293/* Controller Mode Register Bits */
2294#define KBD_MODE_KBD_INT 0x01 /* Keyboard data generate IRQ1 */
2295#define KBD_MODE_MOUSE_INT 0x02 /* Mouse data generate IRQ12 */
2296#define KBD_MODE_SYS 0x04 /* The system flag (?) */
2297#define KBD_MODE_NO_KEYLOCK 0x08 /* The keylock doesn't affect the keyboard if set */
2298#define KBD_MODE_DISABLE_KBD 0x10 /* Disable keyboard interface */
2299#define KBD_MODE_DISABLE_MOUSE 0x20 /* Disable mouse interface */
2300#define KBD_MODE_KCC 0x40 /* Scan code conversion to PC format */
2301#define KBD_MODE_RFU 0x80
2302
2303/* Mouse Commands */
330d0414
FB		 2304#define AUX_SET_SCALE11 0xE6 /* Set 1:1 scaling */
2305#define AUX_SET_SCALE21 0xE7 /* Set 2:1 scaling */
313aa567 2306#define AUX_SET_RES 0xE8 /* Set resolution */
330d0414
FB		 2307#define AUX_GET_SCALE 0xE9 /* Get scaling factor */
2308#define AUX_SET_STREAM 0xEA /* Set stream mode */
313aa567
FB		 2309#define AUX_POLL 0xEB /* Poll */
2310#define AUX_RESET_WRAP 0xEC /* Reset wrap mode */
2311#define AUX_SET_WRAP 0xEE /* Set wrap mode */
2312#define AUX_SET_REMOTE 0xF0 /* Set remote mode */
2313#define AUX_GET_TYPE 0xF2 /* Get type */
330d0414
FB		 2314#define AUX_SET_SAMPLE 0xF3 /* Set sample rate */
2315#define AUX_ENABLE_DEV 0xF4 /* Enable aux device */
2316#define AUX_DISABLE_DEV 0xF5 /* Disable aux device */
313aa567 2317#define AUX_SET_DEFAULT 0xF6
330d0414
FB		 2318#define AUX_RESET 0xFF /* Reset aux device */
2319#define AUX_ACK 0xFA /* Command byte ACK. */
2320
313aa567
FB		 2321#define MOUSE_STATUS_REMOTE 0x40
2322#define MOUSE_STATUS_ENABLED 0x20
2323#define MOUSE_STATUS_SCALE21 0x10
2324
2325#define KBD_QUEUE_SIZE 256
330d0414
FB		 2326
2327typedef struct {
2328 uint8_t data[KBD_QUEUE_SIZE];
2329 int rptr, wptr, count;
2330} KBDQueue;
2331
330d0414
FB		 2332typedef struct KBDState {
2333 KBDQueue queues[2];
2334 uint8_t write_cmd; /* if non zero, write data to port 60 is expected */
2335 uint8_t status;
2336 uint8_t mode;
313aa567 2337 /* keyboard state */
330d0414
FB		 2338 int kbd_write_cmd;
2339 int scan_enabled;
313aa567
FB		 2340 /* mouse state */
2341 int mouse_write_cmd;
2342 uint8_t mouse_status;
2343 uint8_t mouse_resolution;
2344 uint8_t mouse_sample_rate;
2345 uint8_t mouse_wrap;
2346 uint8_t mouse_type; /* 0 = PS2, 3 = IMPS/2, 4 = IMEX */
2347 uint8_t mouse_detect_state;
2348 int mouse_dx; /* current values, needed for 'poll' mode */
2349 int mouse_dy;
2350 int mouse_dz;
2351 uint8_t mouse_buttons;
330d0414
FB		 2352} KBDState;
2353
2354KBDState kbd_state;
cd4c3e88 2355int reset_requested;
330d0414 2356
313aa567 2357/* update irq and KBD_STAT_[MOUSE_]OBF */
07ad1b93
FB		 2358/* XXX: not generating the irqs if KBD_MODE_DISABLE_KBD is set may be
2359 incorrect, but it avoids having to simulate exact delays */
330d0414
FB		 2360static void kbd_update_irq(KBDState *s)
2361{
313aa567
FB		 2362 int irq12_level, irq1_level;
2363
2364 irq1_level = 0;
2365 irq12_level = 0;
2366 s->status &= ~(KBD_STAT_OBF | KBD_STAT_MOUSE_OBF);
2367 if (s->queues[0].count != 0 ||
2368 s->queues[1].count != 0) {
2369 s->status |= KBD_STAT_OBF;
2370 if (s->queues[1].count != 0) {
2371 s->status |= KBD_STAT_MOUSE_OBF;
2372 if (s->mode & KBD_MODE_MOUSE_INT)
2373 irq12_level = 1;
2374 } else {
07ad1b93
FB		 2375 if ((s->mode & KBD_MODE_KBD_INT) &&
2376 !(s->mode & KBD_MODE_DISABLE_KBD))
313aa567
FB		 2377 irq1_level = 1;
2378 }
2379 }
2380 pic_set_irq(1, irq1_level);
2381 pic_set_irq(12, irq12_level);
330d0414
FB		 2382}
2383
2384static void kbd_queue(KBDState *s, int b, int aux)
2385{
2386 KBDQueue *q = &kbd_state.queues[aux];
2387
313aa567
FB		 2388#if defined(DEBUG_MOUSE) || defined(DEBUG_KBD)
2389 if (aux)
2390 printf("mouse event: 0x%02x\n", b);
2391#ifdef DEBUG_KBD
2392 else
2393 printf("kbd event: 0x%02x\n", b);
2394#endif
2395#endif
330d0414
FB		 2396 if (q->count >= KBD_QUEUE_SIZE)
2397 return;
2398 q->data[q->wptr] = b;
2399 if (++q->wptr == KBD_QUEUE_SIZE)
2400 q->wptr = 0;
2401 q->count++;
330d0414
FB		 2402 kbd_update_irq(s);
2403}
cd4c3e88 2404
313aa567
FB		 2405void kbd_put_keycode(int keycode)
2406{
2407 KBDState *s = &kbd_state;
2408 kbd_queue(s, keycode, 0);
2409}
2410
c45886db 2411uint32_t kbd_read_status(CPUState *env, uint32_t addr)
cd4c3e88 2412{
330d0414
FB		 2413 KBDState *s = &kbd_state;
2414 int val;
2415 val = s->status;
c45886db 2416#if defined(DEBUG_KBD)
330d0414
FB		 2417 printf("kbd: read status=0x%02x\n", val);
2418#endif
2419 return val;
cd4c3e88
FB		 2420}
2421
c45886db 2422void kbd_write_command(CPUState *env, uint32_t addr, uint32_t val)
cd4c3e88 2423{
330d0414
FB		 2424 KBDState *s = &kbd_state;
2425
2426#ifdef DEBUG_KBD
2427 printf("kbd: write cmd=0x%02x\n", val);
2428#endif
cd4c3e88 2429 switch(val) {
330d0414
FB		 2430 case KBD_CCMD_READ_MODE:
2431 kbd_queue(s, s->mode, 0);
2432 break;
2433 case KBD_CCMD_WRITE_MODE:
2434 case KBD_CCMD_WRITE_OBUF:
2435 case KBD_CCMD_WRITE_AUX_OBUF:
2436 case KBD_CCMD_WRITE_MOUSE:
2437 case KBD_CCMD_WRITE_OUTPORT:
2438 s->write_cmd = val;
2439 break;
2440 case KBD_CCMD_MOUSE_DISABLE:
2441 s->mode |= KBD_MODE_DISABLE_MOUSE;
2442 break;
2443 case KBD_CCMD_MOUSE_ENABLE:
2444 s->mode &= ~KBD_MODE_DISABLE_MOUSE;
2445 break;
2446 case KBD_CCMD_TEST_MOUSE:
2447 kbd_queue(s, 0x00, 0);
2448 break;
2449 case KBD_CCMD_SELF_TEST:
2450 s->status |= KBD_STAT_SELFTEST;
2451 kbd_queue(s, 0x55, 0);
2452 break;
2453 case KBD_CCMD_KBD_TEST:
2454 kbd_queue(s, 0x00, 0);
2455 break;
2456 case KBD_CCMD_KBD_DISABLE:
2457 s->mode |= KBD_MODE_DISABLE_KBD;
07ad1b93 2458 kbd_update_irq(s);
330d0414
FB		 2459 break;
2460 case KBD_CCMD_KBD_ENABLE:
2461 s->mode &= ~KBD_MODE_DISABLE_KBD;
07ad1b93 2462 kbd_update_irq(s);
330d0414
FB		 2463 break;
2464 case KBD_CCMD_READ_INPORT:
2465 kbd_queue(s, 0x00, 0);
2466 break;
2467 case KBD_CCMD_READ_OUTPORT:
2468 /* XXX: check that */
c45886db 2469#ifdef TARGET_I386
330d0414 2470 val = 0x01 | (a20_enabled << 1);
c45886db
FB		 2471#else
2472 val = 0x01;
2473#endif
330d0414
FB		 2474 if (s->status & KBD_STAT_OBF)
2475 val |= 0x10;
2476 if (s->status & KBD_STAT_MOUSE_OBF)
2477 val |= 0x20;
2478 kbd_queue(s, val, 0);
2479 break;
c45886db 2480#ifdef TARGET_I386
330d0414 2481 case KBD_CCMD_ENABLE_A20:
1f5476fc 2482 cpu_x86_set_a20(env, 1);
330d0414
FB		 2483 break;
2484 case KBD_CCMD_DISABLE_A20:
1f5476fc 2485 cpu_x86_set_a20(env, 0);
330d0414 2486 break;
c45886db 2487#endif
330d0414 2488 case KBD_CCMD_RESET:
cd4c3e88 2489 reset_requested = 1;
c45886db 2490 cpu_interrupt(global_env, CPU_INTERRUPT_EXIT);
cd4c3e88 2491 break;
27503323
FB		 2492 case 0xff:
2493 /* ignore that - I don't know what is its use */
2494 break;
330d0414 2495 default:
36b486bb 2496 fprintf(stderr, "qemu: unsupported keyboard cmd=0x%02x\n", val);
330d0414
FB		 2497 break;
2498 }
2499}
2500
c45886db 2501uint32_t kbd_read_data(CPUState *env, uint32_t addr)
330d0414
FB		 2502{
2503 KBDState *s = &kbd_state;
2504 KBDQueue *q;
7dea1da4 2505 int val, index;
330d0414 2506
313aa567 2507 q = &s->queues[0]; /* first check KBD data */
330d0414 2508 if (q->count == 0)
313aa567 2509 q = &s->queues[1]; /* then check AUX data */
330d0414 2510 if (q->count == 0) {
7dea1da4
FB		 2511 /* NOTE: if no data left, we return the last keyboard one
2512 (needed for EMM386) */
2513 /* XXX: need a timer to do things correctly */
2514 q = &s->queues[0];
2515 index = q->rptr - 1;
2516 if (index < 0)
2517 index = KBD_QUEUE_SIZE - 1;
2518 val = q->data[index];
330d0414
FB		 2519 } else {
2520 val = q->data[q->rptr];
2521 if (++q->rptr == KBD_QUEUE_SIZE)
2522 q->rptr = 0;
2523 q->count--;
313aa567
FB		 2524 /* reading deasserts IRQ */
2525 if (q == &s->queues[0])
2526 pic_set_irq(1, 0);
2527 else
2528 pic_set_irq(12, 0);
330d0414 2529 }
313aa567
FB		 2530 /* reassert IRQs if data left */
2531 kbd_update_irq(s);
330d0414
FB		 2532#ifdef DEBUG_KBD
2533 printf("kbd: read data=0x%02x\n", val);
2534#endif
2535 return val;
2536}
2537
2538static void kbd_reset_keyboard(KBDState *s)
2539{
2540 s->scan_enabled = 1;
2541}
2542
2543static void kbd_write_keyboard(KBDState *s, int val)
2544{
2545 switch(s->kbd_write_cmd) {
2546 default:
2547 case -1:
2548 switch(val) {
2549 case 0x00:
2550 kbd_queue(s, KBD_REPLY_ACK, 0);
2551 break;
2552 case 0x05:
2553 kbd_queue(s, KBD_REPLY_RESEND, 0);
2554 break;
07ad1b93
FB		 2555 case KBD_CMD_GET_ID:
2556 kbd_queue(s, KBD_REPLY_ACK, 0);
2557 kbd_queue(s, 0xab, 0);
2558 kbd_queue(s, 0x83, 0);
2559 break;
330d0414
FB		 2560 case KBD_CMD_ECHO:
2561 kbd_queue(s, KBD_CMD_ECHO, 0);
2562 break;
2563 case KBD_CMD_ENABLE:
2564 s->scan_enabled = 1;
2565 kbd_queue(s, KBD_REPLY_ACK, 0);
2566 break;
2567 case KBD_CMD_SET_LEDS:
2568 case KBD_CMD_SET_RATE:
2569 s->kbd_write_cmd = val;
1f5476fc 2570 kbd_queue(s, KBD_REPLY_ACK, 0);
330d0414
FB		 2571 break;
2572 case KBD_CMD_RESET_DISABLE:
2573 kbd_reset_keyboard(s);
2574 s->scan_enabled = 0;
2575 kbd_queue(s, KBD_REPLY_ACK, 0);
2576 break;
2577 case KBD_CMD_RESET_ENABLE:
2578 kbd_reset_keyboard(s);
2579 s->scan_enabled = 1;
2580 kbd_queue(s, KBD_REPLY_ACK, 0);
2581 break;
2582 case KBD_CMD_RESET:
2583 kbd_reset_keyboard(s);
2584 kbd_queue(s, KBD_REPLY_ACK, 0);
2585 kbd_queue(s, KBD_REPLY_POR, 0);
2586 break;
2587 default:
2588 kbd_queue(s, KBD_REPLY_ACK, 0);
2589 break;
2590 }
2591 break;
2592 case KBD_CMD_SET_LEDS:
2593 kbd_queue(s, KBD_REPLY_ACK, 0);
313aa567 2594 s->kbd_write_cmd = -1;
330d0414
FB		 2595 break;
2596 case KBD_CMD_SET_RATE:
2597 kbd_queue(s, KBD_REPLY_ACK, 0);
313aa567
FB		 2598 s->kbd_write_cmd = -1;
2599 break;
2600 }
2601}
2602
2603static void kbd_mouse_send_packet(KBDState *s)
2604{
2605 unsigned int b;
2606 int dx1, dy1, dz1;
2607
2608 dx1 = s->mouse_dx;
2609 dy1 = s->mouse_dy;
2610 dz1 = s->mouse_dz;
2611 /* XXX: increase range to 8 bits ? */
2612 if (dx1 > 127)
2613 dx1 = 127;
2614 else if (dx1 < -127)
2615 dx1 = -127;
2616 if (dy1 > 127)
2617 dy1 = 127;
2618 else if (dy1 < -127)
2619 dy1 = -127;
2620 b = 0x08 | ((dx1 < 0) << 4) | ((dy1 < 0) << 5) | (s->mouse_buttons & 0x07);
2621 kbd_queue(s, b, 1);
2622 kbd_queue(s, dx1 & 0xff, 1);
2623 kbd_queue(s, dy1 & 0xff, 1);
2624 /* extra byte for IMPS/2 or IMEX */
2625 switch(s->mouse_type) {
2626 default:
2627 break;
2628 case 3:
2629 if (dz1 > 127)
2630 dz1 = 127;
2631 else if (dz1 < -127)
2632 dz1 = -127;
2633 kbd_queue(s, dz1 & 0xff, 1);
2634 break;
2635 case 4:
2636 if (dz1 > 7)
2637 dz1 = 7;
2638 else if (dz1 < -7)
2639 dz1 = -7;
2640 b = (dz1 & 0x0f) | ((s->mouse_buttons & 0x18) << 1);
2641 kbd_queue(s, b, 1);
2642 break;
2643 }
2644
2645 /* update deltas */
2646 s->mouse_dx -= dx1;
2647 s->mouse_dy -= dy1;
2648 s->mouse_dz -= dz1;
2649}
2650
2651void kbd_mouse_event(int dx, int dy, int dz, int buttons_state)
2652{
2653 KBDState *s = &kbd_state;
2654
2655 /* check if deltas are recorded when disabled */
2656 if (!(s->mouse_status & MOUSE_STATUS_ENABLED))
2657 return;
2658
2659 s->mouse_dx += dx;
2660 s->mouse_dy -= dy;
2661 s->mouse_dz += dz;
2662 s->mouse_buttons = buttons_state;
2663
2664 if (!(s->mouse_status & MOUSE_STATUS_REMOTE) &&
2665 (s->queues[1].count < (KBD_QUEUE_SIZE - 16))) {
2666 for(;;) {
2667 /* if not remote, send event. Multiple events are sent if
2668 too big deltas */
2669 kbd_mouse_send_packet(s);
2670 if (s->mouse_dx == 0 && s->mouse_dy == 0 && s->mouse_dz == 0)
2671 break;
2672 }
2673 }
2674}
2675
2676static void kbd_write_mouse(KBDState *s, int val)
2677{
2678#ifdef DEBUG_MOUSE
2679 printf("kbd: write mouse 0x%02x\n", val);
2680#endif
2681 switch(s->mouse_write_cmd) {
2682 default:
2683 case -1:
2684 /* mouse command */
2685 if (s->mouse_wrap) {
2686 if (val == AUX_RESET_WRAP) {
2687 s->mouse_wrap = 0;
2688 kbd_queue(s, AUX_ACK, 1);
2689 return;
2690 } else if (val != AUX_RESET) {
2691 kbd_queue(s, val, 1);
2692 return;
2693 }
2694 }
2695 switch(val) {
2696 case AUX_SET_SCALE11:
2697 s->mouse_status &= ~MOUSE_STATUS_SCALE21;
2698 kbd_queue(s, AUX_ACK, 1);
2699 break;
2700 case AUX_SET_SCALE21:
2701 s->mouse_status |= MOUSE_STATUS_SCALE21;
2702 kbd_queue(s, AUX_ACK, 1);
2703 break;
2704 case AUX_SET_STREAM:
2705 s->mouse_status &= ~MOUSE_STATUS_REMOTE;
2706 kbd_queue(s, AUX_ACK, 1);
2707 break;
2708 case AUX_SET_WRAP:
2709 s->mouse_wrap = 1;
2710 kbd_queue(s, AUX_ACK, 1);
2711 break;
2712 case AUX_SET_REMOTE:
2713 s->mouse_status |= MOUSE_STATUS_REMOTE;
2714 kbd_queue(s, AUX_ACK, 1);
2715 break;
2716 case AUX_GET_TYPE:
2717 kbd_queue(s, AUX_ACK, 1);
2718 kbd_queue(s, s->mouse_type, 1);
2719 break;
2720 case AUX_SET_RES:
2721 case AUX_SET_SAMPLE:
2722 s->mouse_write_cmd = val;
2723 kbd_queue(s, AUX_ACK, 1);
2724 break;
2725 case AUX_GET_SCALE:
2726 kbd_queue(s, AUX_ACK, 1);
2727 kbd_queue(s, s->mouse_status, 1);
2728 kbd_queue(s, s->mouse_resolution, 1);
2729 kbd_queue(s, s->mouse_sample_rate, 1);
2730 break;
2731 case AUX_POLL:
2732 kbd_queue(s, AUX_ACK, 1);
2733 kbd_mouse_send_packet(s);
2734 break;
2735 case AUX_ENABLE_DEV:
2736 s->mouse_status |= MOUSE_STATUS_ENABLED;
2737 kbd_queue(s, AUX_ACK, 1);
2738 break;
2739 case AUX_DISABLE_DEV:
2740 s->mouse_status &= ~MOUSE_STATUS_ENABLED;
2741 kbd_queue(s, AUX_ACK, 1);
2742 break;
2743 case AUX_SET_DEFAULT:
2744 s->mouse_sample_rate = 100;
2745 s->mouse_resolution = 2;
2746 s->mouse_status = 0;
2747 kbd_queue(s, AUX_ACK, 1);
2748 break;
2749 case AUX_RESET:
2750 s->mouse_sample_rate = 100;
2751 s->mouse_resolution = 2;
2752 s->mouse_status = 0;
2753 kbd_queue(s, AUX_ACK, 1);
2754 kbd_queue(s, 0xaa, 1);
2755 kbd_queue(s, s->mouse_type, 1);
2756 break;
2757 default:
2758 break;
2759 }
2760 break;
2761 case AUX_SET_SAMPLE:
2762 s->mouse_sample_rate = val;
2763#if 0
2764 /* detect IMPS/2 or IMEX */
2765 switch(s->mouse_detect_state) {
2766 default:
2767 case 0:
2768 if (val == 200)
2769 s->mouse_detect_state = 1;
2770 break;
2771 case 1:
2772 if (val == 100)
2773 s->mouse_detect_state = 2;
2774 else if (val == 200)
2775 s->mouse_detect_state = 3;
2776 else
2777 s->mouse_detect_state = 0;
2778 break;
2779 case 2:
2780 if (val == 80)
2781 s->mouse_type = 3; /* IMPS/2 */
2782 s->mouse_detect_state = 0;
2783 break;
2784 case 3:
2785 if (val == 80)
2786 s->mouse_type = 4; /* IMEX */
2787 s->mouse_detect_state = 0;
2788 break;
2789 }
2790#endif
2791 kbd_queue(s, AUX_ACK, 1);
2792 s->mouse_write_cmd = -1;
2793 break;
2794 case AUX_SET_RES:
2795 s->mouse_resolution = val;
2796 kbd_queue(s, AUX_ACK, 1);
2797 s->mouse_write_cmd = -1;
330d0414
FB		 2798 break;
2799 }
330d0414
FB		 2800}
2801
c45886db 2802void kbd_write_data(CPUState *env, uint32_t addr, uint32_t val)
330d0414
FB		 2803{
2804 KBDState *s = &kbd_state;
2805
2806#ifdef DEBUG_KBD
2807 printf("kbd: write data=0x%02x\n", val);
2808#endif
2809
2810 switch(s->write_cmd) {
2811 case 0:
2812 kbd_write_keyboard(s, val);
2813 break;
2814 case KBD_CCMD_WRITE_MODE:
2815 s->mode = val;
2816 kbd_update_irq(s);
2817 break;
2818 case KBD_CCMD_WRITE_OBUF:
2819 kbd_queue(s, val, 0);
2820 break;
2821 case KBD_CCMD_WRITE_AUX_OBUF:
2822 kbd_queue(s, val, 1);
2823 break;
2824 case KBD_CCMD_WRITE_OUTPORT:
c45886db 2825#ifdef TARGET_I386
1f5476fc 2826 cpu_x86_set_a20(env, (val >> 1) & 1);
c45886db 2827#endif
330d0414
FB		 2828 if (!(val & 1)) {
2829 reset_requested = 1;
c45886db 2830 cpu_interrupt(global_env, CPU_INTERRUPT_EXIT);
330d0414
FB		 2831 }
2832 break;
313aa567
FB		 2833 case KBD_CCMD_WRITE_MOUSE:
2834 kbd_write_mouse(s, val);
2835 break;
cd4c3e88
FB		 2836 default:
2837 break;
2838 }
330d0414
FB		 2839 s->write_cmd = 0;
2840}
2841
2842void kbd_reset(KBDState *s)
2843{
2844 KBDQueue *q;
2845 int i;
2846
2847 s->kbd_write_cmd = -1;
313aa567 2848 s->mouse_write_cmd = -1;
330d0414 2849 s->mode = KBD_MODE_KBD_INT | KBD_MODE_MOUSE_INT;
313aa567 2850 s->status = KBD_STAT_CMD | KBD_STAT_UNLOCKED;
330d0414
FB		 2851 for(i = 0; i < 2; i++) {
2852 q = &s->queues[i];
2853 q->rptr = 0;
2854 q->wptr = 0;
2855 q->count = 0;
2856 }
cd4c3e88
FB		 2857}
2858
2859void kbd_init(void)
2860{
330d0414 2861 kbd_reset(&kbd_state);
c45886db 2862#if defined (TARGET_I386) || defined (TARGET_PPC)
330d0414
FB		 2863 register_ioport_read(0x60, 1, kbd_read_data, 1);
2864 register_ioport_write(0x60, 1, kbd_write_data, 1);
cd4c3e88
FB		 2865 register_ioport_read(0x64, 1, kbd_read_status, 1);
2866 register_ioport_write(0x64, 1, kbd_write_command, 1);
c45886db 2867#endif
cd4c3e88
FB		 2868}
2869
330d0414
FB		 2870/***********************************************************/
2871/* Bochs BIOS debug ports */
c45886db 2872#ifdef TARGET_I386
330d0414
FB		 2873void bochs_bios_write(CPUX86State *env, uint32_t addr, uint32_t val)
2874{
2875 switch(addr) {
2876 /* Bochs BIOS messages */
2877 case 0x400:
2878 case 0x401:
2879 fprintf(stderr, "BIOS panic at rombios.c, line %d\n", val);
2880 exit(1);
2881 case 0x402:
2882 case 0x403:
2883#ifdef DEBUG_BIOS
2884 fprintf(stderr, "%c", val);
2885#endif
2886 break;
2887
2888 /* LGPL'ed VGA BIOS messages */
2889 case 0x501:
2890 case 0x502:
2891 fprintf(stderr, "VGA BIOS panic, line %d\n", val);
2892 exit(1);
2893 case 0x500:
2894 case 0x503:
2895#ifdef DEBUG_BIOS
2896 fprintf(stderr, "%c", val);
2897#endif
2898 break;
2899 }
2900}
2901
2902void bochs_bios_init(void)
2903{
2904 register_ioport_write(0x400, 1, bochs_bios_write, 2);
2905 register_ioport_write(0x401, 1, bochs_bios_write, 2);
2906 register_ioport_write(0x402, 1, bochs_bios_write, 1);
2907 register_ioport_write(0x403, 1, bochs_bios_write, 1);
2908
2909 register_ioport_write(0x501, 1, bochs_bios_write, 2);
2910 register_ioport_write(0x502, 1, bochs_bios_write, 2);
2911 register_ioport_write(0x500, 1, bochs_bios_write, 1);
2912 register_ioport_write(0x503, 1, bochs_bios_write, 1);
2913}
c45886db 2914#endif
330d0414 2915
313aa567
FB		 2916/***********************************************************/
2917/* dumb display */
2918
2919/* init terminal so that we can grab keys */
2920static struct termios oldtty;
2921
2922static void term_exit(void)
2923{
2924 tcsetattr (0, TCSANOW, &oldtty);
2925}
2926
2927static void term_init(void)
2928{
2929 struct termios tty;
2930
2931 tcgetattr (0, &tty);
2932 oldtty = tty;
2933
2934 tty.c_iflag &= ~(IGNBRK|BRKINT|PARMRK|ISTRIP
2935 |INLCR|IGNCR|ICRNL|IXON);
2936 tty.c_oflag |= OPOST;
a20dd508
FB		 2937 tty.c_lflag &= ~(ECHO|ECHONL|ICANON|IEXTEN);
2938 /* if graphical mode, we allow Ctrl-C handling */
2939 if (nographic)
2940 tty.c_lflag &= ~ISIG;
313aa567
FB		 2941 tty.c_cflag &= ~(CSIZE|PARENB);
2942 tty.c_cflag |= CS8;
2943 tty.c_cc[VMIN] = 1;
2944 tty.c_cc[VTIME] = 0;
2945
2946 tcsetattr (0, TCSANOW, &tty);
2947
2948 atexit(term_exit);
2949
2950 fcntl(0, F_SETFL, O_NONBLOCK);
2951}
2952
2953static void dumb_update(DisplayState *ds, int x, int y, int w, int h)
2954{
2955}
2956
2957static void dumb_resize(DisplayState *ds, int w, int h)
2958{
2959}
2960
2961static void dumb_refresh(DisplayState *ds)
2962{
2963 vga_update_display();
2964}
2965
2966void dumb_display_init(DisplayState *ds)
2967{
2968 ds->data = NULL;
2969 ds->linesize = 0;
2970 ds->depth = 0;
2971 ds->dpy_update = dumb_update;
2972 ds->dpy_resize = dumb_resize;
2973 ds->dpy_refresh = dumb_refresh;
2974}
2975
3a51dee6 2976#if !defined(CONFIG_SOFTMMU)
f1510b2c 2977/***********************************************************/
0824d6fc
FB		 2978/* cpu signal handler */
2979static void host_segv_handler(int host_signum, siginfo_t *info,
2980 void *puc)
2981{
2982 if (cpu_signal_handler(host_signum, info, puc))
2983 return;
2984 term_exit();
2985 abort();
2986}
3a51dee6 2987#endif
0824d6fc
FB		 2988
2989static int timer_irq_pending;
87858c89 2990static int timer_irq_count;
0824d6fc 2991
313aa567
FB		 2992static int timer_ms;
2993static int gui_refresh_pending, gui_refresh_count;
2994
0824d6fc
FB		 2995static void host_alarm_handler(int host_signum, siginfo_t *info,
2996 void *puc)
2997{
87858c89
FB		 2998 /* NOTE: since usually the OS asks a 100 Hz clock, there can be
2999 some drift between cpu_get_ticks() and the interrupt time. So
3000 we queue some interrupts to avoid missing some */
3001 timer_irq_count += pit_get_out_edges(&pit_channels[0]);
3002 if (timer_irq_count) {
3003 if (timer_irq_count > 2)
3004 timer_irq_count = 2;
3005 timer_irq_count--;
313aa567
FB		 3006 timer_irq_pending = 1;
3007 }
3008 gui_refresh_count += timer_ms;
3009 if (gui_refresh_count >= GUI_REFRESH_INTERVAL) {
3010 gui_refresh_count = 0;
3011 gui_refresh_pending = 1;
3012 }
3013
27503323
FB		 3014 /* XXX: seems dangerous to run that here. */
3015 DMA_run();
3016 SB16_run();
3017
313aa567 3018 if (gui_refresh_pending || timer_irq_pending) {
87858c89 3019 /* just exit from the cpu to have a chance to handle timers */
c45886db 3020 cpu_interrupt(global_env, CPU_INTERRUPT_EXIT);
87858c89 3021 }
0824d6fc
FB		 3022}
3023
7f7f9873
FB		 3024#ifdef CONFIG_SOFTMMU
3025void *get_mmap_addr(unsigned long size)
3026{
3027 return NULL;
3028}
3029#else
33e3963e
FB		 3030unsigned long mmap_addr = PHYS_RAM_BASE;
3031
3032void *get_mmap_addr(unsigned long size)
3033{
3034 unsigned long addr;
3035 addr = mmap_addr;
3036 mmap_addr += ((size + 4095) & ~4095) + 4096;
3037 return (void *)addr;
3038}
7f7f9873 3039#endif
33e3963e 3040
b4608c04
FB		 3041/* main execution loop */
3042
3043CPUState *cpu_gdbstub_get_env(void *opaque)
3044{
3045 return global_env;
3046}
3047
4c3a88a2 3048int main_loop(void *opaque)
b4608c04 3049{
c45886db
FB		 3050 struct pollfd ufds[3], *pf, *serial_ufd, *gdb_ufd;
3051#if defined (TARGET_I386)
3052 struct pollfd *net_ufd;
3053#endif
27c3f2cb 3054 int ret, n, timeout, serial_ok;
b4608c04
FB		 3055 uint8_t ch;
3056 CPUState *env = global_env;
3057
a20dd508 3058 if (!term_inited) {
313aa567
FB		 3059 /* initialize terminal only there so that the user has a
3060 chance to stop QEMU with Ctrl-C before the gdb connection
3061 is launched */
3062 term_inited = 1;
3063 term_init();
3064 }
3065
27c3f2cb 3066 serial_ok = 1;
34865134 3067 cpu_enable_ticks();
b4608c04 3068 for(;;) {
c45886db
FB		 3069#if defined (DO_TB_FLUSH)
3070 tb_flush();
3071#endif
3072 ret = cpu_exec(env);
34865134
FB		 3073 if (reset_requested) {
3074 ret = EXCP_INTERRUPT;
cd4c3e88 3075 break;
34865134
FB		 3076 }
3077 if (ret == EXCP_DEBUG) {
3078 ret = EXCP_DEBUG;
3079 break;
3080 }
b4608c04
FB		 3081 /* if hlt instruction, we wait until the next IRQ */
3082 if (ret == EXCP_HLT)
3083 timeout = 10;
3084 else
3085 timeout = 0;
3086 /* poll any events */
3087 serial_ufd = NULL;
3088 pf = ufds;
27c3f2cb 3089 if (serial_ok && !(serial_ports[0].lsr & UART_LSR_DR)) {
b4608c04
FB		 3090 serial_ufd = pf;
3091 pf->fd = 0;
3092 pf->events = POLLIN;
3093 pf++;
3094 }
c45886db 3095#if defined (TARGET_I386)
b4608c04
FB		 3096 net_ufd = NULL;
3097 if (net_fd > 0 && ne2000_can_receive(&ne2000_state)) {
3098 net_ufd = pf;
3099 pf->fd = net_fd;
3100 pf->events = POLLIN;
3101 pf++;
3102 }
c45886db 3103#endif
b4608c04
FB		 3104 gdb_ufd = NULL;
3105 if (gdbstub_fd > 0) {
3106 gdb_ufd = pf;
3107 pf->fd = gdbstub_fd;
3108 pf->events = POLLIN;
3109 pf++;
3110 }
3111
3112 ret = poll(ufds, pf - ufds, timeout);
3113 if (ret > 0) {
3114 if (serial_ufd && (serial_ufd->revents & POLLIN)) {
3115 n = read(0, &ch, 1);
3116 if (n == 1) {
3117 serial_received_byte(&serial_ports[0], ch);
27c3f2cb
FB		 3118 } else {
3119 /* Closed, stop polling. */
3120 serial_ok = 0;
b4608c04
FB		 3121 }
3122 }
c45886db 3123#if defined (TARGET_I386)
b4608c04
FB		 3124 if (net_ufd && (net_ufd->revents & POLLIN)) {
3125 uint8_t buf[MAX_ETH_FRAME_SIZE];
3126
3127 n = read(net_fd, buf, MAX_ETH_FRAME_SIZE);
3128 if (n > 0) {
3129 if (n < 60) {
3130 memset(buf + n, 0, 60 - n);
3131 n = 60;
3132 }
3133 ne2000_receive(&ne2000_state, buf, n);
3134 }
3135 }
c45886db 3136#endif
b4608c04
FB		 3137 if (gdb_ufd && (gdb_ufd->revents & POLLIN)) {
3138 uint8_t buf[1];
3139 /* stop emulation if requested by gdb */
3140 n = read(gdbstub_fd, buf, 1);
34865134
FB		 3141 if (n == 1) {
3142 ret = EXCP_INTERRUPT;
b4608c04 3143 break;
34865134 3144 }
b4608c04
FB		 3145 }
3146 }
3147
3148 /* timer IRQ */
3149 if (timer_irq_pending) {
c45886db 3150#if defined (TARGET_I386)
b4608c04
FB		 3151 pic_set_irq(0, 1);
3152 pic_set_irq(0, 0);
3153 timer_irq_pending = 0;
7dea1da4 3154 /* XXX: RTC test */
8f2b1fb0 3155 if (cmos_data[RTC_REG_B] & 0x50) {
7dea1da4
FB		 3156 pic_set_irq(8, 1);
3157 }
c45886db 3158#endif
b4608c04 3159 }
313aa567
FB		 3160
3161 /* VGA */
3162 if (gui_refresh_pending) {
3163 display_state.dpy_refresh(&display_state);
3164 gui_refresh_pending = 0;
3165 }
b4608c04 3166 }
34865134
FB		 3167 cpu_disable_ticks();
3168 return ret;
b4608c04
FB		 3169}
3170
0824d6fc
FB		 3171void help(void)
3172{
a20dd508 3173 printf("QEMU PC emulator version " QEMU_VERSION ", Copyright (c) 2003 Fabrice Bellard\n"
0db63474 3174 "usage: %s [options] [disk_image]\n"
0824d6fc 3175 "\n"
a20dd508 3176 "'disk_image' is a raw hard image image for IDE hard disk 0\n"
fc01f7e7 3177 "\n"
a20dd508 3178 "Standard options:\n"
c45886db 3179 "-fda/-fdb file use 'file' as floppy disk 0/1 image\n"
36b486bb
FB		 3180 "-hda/-hdb file use 'file' as IDE hard disk 0/1 image\n"
3181 "-hdc/-hdd file use 'file' as IDE hard disk 2/3 image\n"
3182 "-cdrom file use 'file' as IDE cdrom 2 image\n"
27503323 3183 "-boot [c|d] boot on hard disk (c) or CD-ROM (d)\n"
a20dd508
FB		 3184 "-snapshot write to temporary files instead of disk image files\n"
3185 "-m megs set virtual RAM size to megs MB\n"
3186 "-n script set network init script [default=%s]\n"
42f1e0e4 3187 "-tun-fd fd this fd talks to tap/tun, use it.\n"
a20dd508
FB		 3188 "-nographic disable graphical output\n"
3189 "\n"
3190 "Linux boot specific (does not require PC BIOS):\n"
3191 "-kernel bzImage use 'bzImage' as kernel image\n"
3192 "-append cmdline use 'cmdline' as kernel command line\n"
3193 "-initrd file use 'file' as initial ram disk\n"
fc01f7e7 3194 "\n"
330d0414 3195 "Debug/Expert options:\n"
a20dd508
FB		 3196 "-s wait gdb connection to port %d\n"
3197 "-p port change gdb connection port\n"
3198 "-d output log in /tmp/vl.log\n"
3199 "-hdachs c,h,s force hard disk 0 geometry (usually qemu can guess it)\n"
3200 "-L path set the directory for the BIOS and VGA BIOS\n"
0824d6fc 3201 "\n"
f1510b2c 3202 "During emulation, use C-a h to get terminal commands:\n",
0db63474
FB		 3203#ifdef CONFIG_SOFTMMU
3204 "qemu",
3205#else
3206 "qemu-fast",
3207#endif
3208 DEFAULT_NETWORK_SCRIPT,
3209 DEFAULT_GDBSTUB_PORT);
0824d6fc 3210 term_print_help();
0db63474
FB		 3211#ifndef CONFIG_SOFTMMU
3212 printf("\n"
3213 "NOTE: this version of QEMU is faster but it needs slightly patched OSes to\n"
3214 "work. Please use the 'qemu' executable to have a more accurate (but slower)\n"
3215 "PC emulation.\n");
3216#endif
0824d6fc
FB		 3217 exit(1);
3218}
3219
fc01f7e7
FB		 3220struct option long_options[] = {
3221 { "initrd", 1, NULL, 0, },
3222 { "hda", 1, NULL, 0, },
3223 { "hdb", 1, NULL, 0, },
33e3963e 3224 { "snapshot", 0, NULL, 0, },
330d0414 3225 { "hdachs", 1, NULL, 0, },
a20dd508
FB		 3226 { "nographic", 0, NULL, 0, },
3227 { "kernel", 1, NULL, 0, },
3228 { "append", 1, NULL, 0, },
42f1e0e4 3229 { "tun-fd", 1, NULL, 0, },
36b486bb
FB		 3230 { "hdc", 1, NULL, 0, },
3231 { "hdd", 1, NULL, 0, },
3232 { "cdrom", 1, NULL, 0, },
3233 { "boot", 1, NULL, 0, },
c45886db
FB		 3234 { "fda", 1, NULL, 0, },
3235 { "fdb", 1, NULL, 0, },
fc01f7e7
FB		 3236 { NULL, 0, NULL, 0 },
3237};
3238
a20dd508
FB		 3239#ifdef CONFIG_SDL
3240/* SDL use the pthreads and they modify sigaction. We don't
3241 want that. */
dc887a4d 3242#if __GLIBC__ > 2 || (__GLIBC__ == 2 && __GLIBC_MINOR__ >= 2)
a20dd508
FB		 3243extern void __libc_sigaction();
3244#define sigaction(sig, act, oact) __libc_sigaction(sig, act, oact)
3245#else
3246extern void __sigaction();
3247#define sigaction(sig, act, oact) __sigaction(sig, act, oact)
3248#endif
3249#endif /* CONFIG_SDL */
3250
0824d6fc
FB		 3251int main(int argc, char **argv)
3252{
fc01f7e7 3253 int c, ret, initrd_size, i, use_gdbstub, gdbstub_port, long_index;
313aa567 3254 int snapshot, linux_boot, total_ram_size;
c45886db 3255#if defined (TARGET_I386)
0824d6fc 3256 struct linux_params *params;
c45886db 3257#endif
0824d6fc
FB		 3258 struct sigaction act;
3259 struct itimerval itv;
c45886db 3260 CPUState *env;
7f7f9873 3261 const char *initrd_filename;
c45886db 3262 const char *hd_filename[MAX_DISKS], *fd_filename[MAX_FD];
a20dd508 3263 const char *kernel_filename, *kernel_cmdline;
313aa567
FB		 3264 DisplayState *ds = &display_state;
3265
0824d6fc
FB		 3266 /* we never want that malloc() uses mmap() */
3267 mallopt(M_MMAP_THRESHOLD, 4096 * 1024);
fc01f7e7 3268 initrd_filename = NULL;
c45886db
FB		 3269 for(i = 0; i < MAX_FD; i++)
3270 fd_filename[i] = NULL;
fc01f7e7
FB		 3271 for(i = 0; i < MAX_DISKS; i++)
3272 hd_filename[i] = NULL;
0824d6fc 3273 phys_ram_size = 32 * 1024 * 1024;
313aa567 3274 vga_ram_size = VGA_RAM_SIZE;
c45886db 3275#if defined (TARGET_I386)
f1510b2c 3276 pstrcpy(network_script, sizeof(network_script), DEFAULT_NETWORK_SCRIPT);
c45886db 3277#endif
b4608c04
FB		 3278 use_gdbstub = 0;
3279 gdbstub_port = DEFAULT_GDBSTUB_PORT;
33e3963e 3280 snapshot = 0;
a20dd508
FB		 3281 nographic = 0;
3282 kernel_filename = NULL;
3283 kernel_cmdline = "";
0824d6fc 3284 for(;;) {
330d0414 3285 c = getopt_long_only(argc, argv, "hm:dn:sp:L:", long_options, &long_index);
0824d6fc
FB		 3286 if (c == -1)
3287 break;
3288 switch(c) {
fc01f7e7
FB		 3289 case 0:
3290 switch(long_index) {
3291 case 0:
3292 initrd_filename = optarg;
3293 break;
3294 case 1:
3295 hd_filename[0] = optarg;
3296 break;
3297 case 2:
3298 hd_filename[1] = optarg;
3299 break;
33e3963e
FB		 3300 case 3:
3301 snapshot = 1;
3302 break;
330d0414
FB		 3303 case 4:
3304 {
3305 int cyls, heads, secs;
3306 const char *p;
3307 p = optarg;
3308 cyls = strtol(p, (char **)&p, 0);
3309 if (*p != ',')
3310 goto chs_fail;
3311 p++;
3312 heads = strtol(p, (char **)&p, 0);
3313 if (*p != ',')
3314 goto chs_fail;
3315 p++;
3316 secs = strtol(p, (char **)&p, 0);
3317 if (*p != '\0')
3318 goto chs_fail;
5391d806 3319 ide_set_geometry(0, cyls, heads, secs);
330d0414
FB		 3320 chs_fail: ;
3321 }
3322 break;
313aa567 3323 case 5:
a20dd508
FB		 3324 nographic = 1;
3325 break;
3326 case 6:
3327 kernel_filename = optarg;
3328 break;
3329 case 7:
3330 kernel_cmdline = optarg;
313aa567 3331 break;
c45886db 3332#if defined (TARGET_I386)
42f1e0e4
FB		 3333 case 8:
3334 net_fd = atoi(optarg);
3335 break;
c45886db 3336#endif
36b486bb
FB		 3337 case 9:
3338 hd_filename[2] = optarg;
3339 break;
3340 case 10:
3341 hd_filename[3] = optarg;
3342 break;
3343 case 11:
3344 hd_filename[2] = optarg;
5391d806 3345 ide_set_cdrom(2, 1);
36b486bb
FB		 3346 break;
3347 case 12:
3348 boot_device = optarg[0];
c45886db
FB		 3349 if (boot_device != 'a' && boot_device != 'b' &&
3350 boot_device != 'c' && boot_device != 'd') {
36b486bb
FB		 3351 fprintf(stderr, "qemu: invalid boot device '%c'\n", boot_device);
3352 exit(1);
3353 }
3354 break;
c45886db
FB		 3355 case 13:
3356 fd_filename[0] = optarg;
3357 break;
3358 case 14:
3359 fd_filename[1] = optarg;
3360 break;
fc01f7e7
FB		 3361 }
3362 break;
0824d6fc
FB		 3363 case 'h':
3364 help();
3365 break;
3366 case 'm':
3367 phys_ram_size = atoi(optarg) * 1024 * 1024;
3368 if (phys_ram_size <= 0)
3369 help();
7916e224 3370 if (phys_ram_size > PHYS_RAM_MAX_SIZE) {
36b486bb 3371 fprintf(stderr, "qemu: at most %d MB RAM can be simulated\n",
7916e224
FB		 3372 PHYS_RAM_MAX_SIZE / (1024 * 1024));
3373 exit(1);
3374 }
0824d6fc
FB		 3375 break;
3376 case 'd':
34865134 3377 cpu_set_log(CPU_LOG_ALL);
0824d6fc 3378 break;
c45886db 3379#if defined (TARGET_I386)
f1510b2c
FB		 3380 case 'n':
3381 pstrcpy(network_script, sizeof(network_script), optarg);
3382 break;
c45886db 3383#endif
b4608c04
FB		 3384 case 's':
3385 use_gdbstub = 1;
3386 break;
3387 case 'p':
3388 gdbstub_port = atoi(optarg);
3389 break;
330d0414 3390 case 'L':
5a67135a 3391 bios_dir = optarg;
330d0414 3392 break;
0824d6fc
FB		 3393 }
3394 }
330d0414 3395
a20dd508
FB		 3396 if (optind < argc) {
3397 hd_filename[0] = argv[optind++];
3398 }
3399
3400 linux_boot = (kernel_filename != NULL);
330d0414 3401
c45886db
FB		 3402 if (!linux_boot && hd_filename[0] == '\0' && hd_filename[2] == '\0' &&
3403 fd_filename[0] == '\0')
0824d6fc 3404 help();
8f2b1fb0
FB		 3405
3406 /* boot to cd by default if no hard disk */
3407 if (hd_filename[0] == '\0' && boot_device == 'c')
3408 boot_device = 'd';
0824d6fc 3409
dc887a4d
FB		 3410#if !defined(CONFIG_SOFTMMU)
3411 /* must avoid mmap() usage of glibc by setting a buffer "by hand" */
3412 {
3413 static uint8_t stdout_buf[4096];
3414 setvbuf(stdout, stdout_buf, _IOLBF, sizeof(stdout_buf));
3415 }
3416#else
b118d61e 3417 setvbuf(stdout, NULL, _IOLBF, 0);
dc887a4d 3418#endif
0824d6fc 3419
f1510b2c 3420 /* init network tun interface */
c45886db 3421#if defined (TARGET_I386)
42f1e0e4
FB		 3422 if (net_fd < 0)
3423 net_init();
c45886db 3424#endif
f1510b2c 3425
0824d6fc 3426 /* init the memory */
313aa567 3427 total_ram_size = phys_ram_size + vga_ram_size;
7f7f9873
FB		 3428
3429#ifdef CONFIG_SOFTMMU
3430 phys_ram_base = malloc(total_ram_size);
3431 if (!phys_ram_base) {
3432 fprintf(stderr, "Could not allocate physical memory\n");
0824d6fc
FB		 3433 exit(1);
3434 }
7f7f9873
FB		 3435#else
3436 /* as we must map the same page at several addresses, we must use
3437 a fd */
3438 {
3439 const char *tmpdir;
3440
3441 tmpdir = getenv("QEMU_TMPDIR");
3442 if (!tmpdir)
3443 tmpdir = "/tmp";
3444 snprintf(phys_ram_file, sizeof(phys_ram_file), "%s/vlXXXXXX", tmpdir);
3445 if (mkstemp(phys_ram_file) < 0) {
3446 fprintf(stderr, "Could not create temporary memory file '%s'\n",
3447 phys_ram_file);
3448 exit(1);
3449 }
3450 phys_ram_fd = open(phys_ram_file, O_CREAT | O_TRUNC | O_RDWR, 0600);
3451 if (phys_ram_fd < 0) {
3452 fprintf(stderr, "Could not open temporary memory file '%s'\n",
3453 phys_ram_file);
3454 exit(1);
3455 }
3456 ftruncate(phys_ram_fd, total_ram_size);
3457 unlink(phys_ram_file);
3458 phys_ram_base = mmap(get_mmap_addr(total_ram_size),
3459 total_ram_size,
3460 PROT_WRITE | PROT_READ, MAP_SHARED | MAP_FIXED,
3461 phys_ram_fd, 0);
3462 if (phys_ram_base == MAP_FAILED) {
3463 fprintf(stderr, "Could not map physical memory\n");
3464 exit(1);
3465 }
3466 }
3467#endif
0824d6fc 3468
33e3963e
FB		 3469 /* open the virtual block devices */
3470 for(i = 0; i < MAX_DISKS; i++) {
3471 if (hd_filename[i]) {
3472 bs_table[i] = bdrv_open(hd_filename[i], snapshot);
3473 if (!bs_table[i]) {
36b486bb 3474 fprintf(stderr, "qemu: could not open hard disk image '%s\n",
33e3963e
FB		 3475 hd_filename[i]);
3476 exit(1);
3477 }
3478 }
3479 }
3480
330d0414
FB		 3481 /* init CPU state */
3482 env = cpu_init();
3483 global_env = env;
3484 cpu_single_env = env;
3485
3486 init_ioports();
0824d6fc 3487
313aa567
FB		 3488 /* allocate RAM */
3489 cpu_register_physical_memory(0, phys_ram_size, 0);
3490
330d0414
FB		 3491 if (linux_boot) {
3492 /* now we can load the kernel */
a20dd508 3493 ret = load_kernel(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR);
330d0414 3494 if (ret < 0) {
36b486bb 3495 fprintf(stderr, "qemu: could not load kernel '%s'\n",
a20dd508 3496 kernel_filename);
fc01f7e7
FB		 3497 exit(1);
3498 }
330d0414
FB		 3499
3500 /* load initrd */
3501 initrd_size = 0;
3502 if (initrd_filename) {
3503 initrd_size = load_image(initrd_filename, phys_ram_base + INITRD_LOAD_ADDR);
3504 if (initrd_size < 0) {
36b486bb 3505 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
330d0414
FB		 3506 initrd_filename);
3507 exit(1);
3508 }
3509 }
3510
3511 /* init kernel params */
c45886db 3512#ifdef TARGET_I386
330d0414
FB		 3513 params = (void *)(phys_ram_base + KERNEL_PARAMS_ADDR);
3514 memset(params, 0, sizeof(struct linux_params));
3515 params->mount_root_rdonly = 0;
7f7f9873
FB		 3516 stw_raw(&params->cl_magic, 0xA33F);
3517 stw_raw(&params->cl_offset, params->commandline - (uint8_t *)params);
3518 stl_raw(&params->alt_mem_k, (phys_ram_size / 1024) - 1024);
a20dd508 3519 pstrcat(params->commandline, sizeof(params->commandline), kernel_cmdline);
330d0414
FB		 3520 params->loader_type = 0x01;
3521 if (initrd_size > 0) {
7f7f9873
FB		 3522 stl_raw(&params->initrd_start, INITRD_LOAD_ADDR);
3523 stl_raw(&params->initrd_size, initrd_size);
330d0414
FB		 3524 }
3525 params->orig_video_lines = 25;
3526 params->orig_video_cols = 80;
3527
3528 /* setup basic memory access */
3529 env->cr[0] = 0x00000033;
dc887a4d 3530 env->hflags |= HF_PE_MASK;
330d0414
FB		 3531 cpu_x86_init_mmu(env);
3532
3533 memset(params->idt_table, 0, sizeof(params->idt_table));
3534
7f7f9873
FB		 3535 stq_raw(&params->gdt_table[2], 0x00cf9a000000ffffLL); /* KERNEL_CS */
3536 stq_raw(&params->gdt_table[3], 0x00cf92000000ffffLL); /* KERNEL_DS */
dd6ee15c 3537 /* for newer kernels (2.6.0) CS/DS are at different addresses */
7f7f9873
FB		 3538 stq_raw(&params->gdt_table[12], 0x00cf9a000000ffffLL); /* KERNEL_CS */
3539 stq_raw(&params->gdt_table[13], 0x00cf92000000ffffLL); /* KERNEL_DS */
330d0414 3540
dd6ee15c 3541 env->idt.base = (void *)((uint8_t *)params->idt_table - phys_ram_base);
330d0414 3542 env->idt.limit = sizeof(params->idt_table) - 1;
dd6ee15c 3543 env->gdt.base = (void *)((uint8_t *)params->gdt_table - phys_ram_base);
330d0414
FB		 3544 env->gdt.limit = sizeof(params->gdt_table) - 1;
3545
2e255c6b
FB		 3546 cpu_x86_load_seg_cache(env, R_CS, KERNEL_CS, NULL, 0xffffffff, 0x00cf9a00);
3547 cpu_x86_load_seg_cache(env, R_DS, KERNEL_DS, NULL, 0xffffffff, 0x00cf9200);
3548 cpu_x86_load_seg_cache(env, R_ES, KERNEL_DS, NULL, 0xffffffff, 0x00cf9200);
3549 cpu_x86_load_seg_cache(env, R_SS, KERNEL_DS, NULL, 0xffffffff, 0x00cf9200);
3550 cpu_x86_load_seg_cache(env, R_FS, KERNEL_DS, NULL, 0xffffffff, 0x00cf9200);
3551 cpu_x86_load_seg_cache(env, R_GS, KERNEL_DS, NULL, 0xffffffff, 0x00cf9200);
330d0414
FB		 3552
3553 env->eip = KERNEL_LOAD_ADDR;
3554 env->regs[R_ESI] = KERNEL_PARAMS_ADDR;
3555 env->eflags = 0x2;
c45886db
FB		 3556#elif defined (TARGET_PPC)
3557 cpu_x86_init_mmu(env);
3558 PPC_init_hw(env, phys_ram_size, KERNEL_LOAD_ADDR, ret,
3559 KERNEL_STACK_ADDR, boot_device);
3560#endif
330d0414
FB		 3561 } else {
3562 char buf[1024];
a20dd508 3563
330d0414 3564 /* RAW PC boot */
c45886db 3565#if defined(TARGET_I386)
330d0414 3566 /* BIOS load */
5a67135a 3567 snprintf(buf, sizeof(buf), "%s/%s", bios_dir, BIOS_FILENAME);
330d0414
FB		 3568 ret = load_image(buf, phys_ram_base + 0x000f0000);
3569 if (ret != 0x10000) {
36b486bb 3570 fprintf(stderr, "qemu: could not load PC bios '%s'\n", buf);
330d0414
FB		 3571 exit(1);
3572 }
3573
3574 /* VGA BIOS load */
5a67135a 3575 snprintf(buf, sizeof(buf), "%s/%s", bios_dir, VGABIOS_FILENAME);
330d0414
FB		 3576 ret = load_image(buf, phys_ram_base + 0x000c0000);
3577
3578 /* setup basic memory access */
3579 env->cr[0] = 0x60000010;
3580 cpu_x86_init_mmu(env);
3581
dc887a4d
FB		 3582 cpu_register_physical_memory(0xc0000, 0x10000, 0xc0000 | IO_MEM_ROM);
3583 cpu_register_physical_memory(0xf0000, 0x10000, 0xf0000 | IO_MEM_ROM);
3584
330d0414
FB		 3585 env->idt.limit = 0xffff;
3586 env->gdt.limit = 0xffff;
3587 env->ldt.limit = 0xffff;
7dea1da4
FB		 3588 env->ldt.flags = DESC_P_MASK;
3589 env->tr.limit = 0xffff;
3590 env->tr.flags = DESC_P_MASK;
330d0414
FB		 3591
3592 /* not correct (CS base=0xffff0000) */
2e255c6b
FB		 3593 cpu_x86_load_seg_cache(env, R_CS, 0xf000, (uint8_t *)0x000f0000, 0xffff, 0);
3594 cpu_x86_load_seg_cache(env, R_DS, 0, NULL, 0xffff, 0);
3595 cpu_x86_load_seg_cache(env, R_ES, 0, NULL, 0xffff, 0);
3596 cpu_x86_load_seg_cache(env, R_SS, 0, NULL, 0xffff, 0);
3597 cpu_x86_load_seg_cache(env, R_FS, 0, NULL, 0xffff, 0);
3598 cpu_x86_load_seg_cache(env, R_GS, 0, NULL, 0xffff, 0);
330d0414
FB		 3599
3600 env->eip = 0xfff0;
3601 env->regs[R_EDX] = 0x600; /* indicate P6 processor */
3602
3603 env->eflags = 0x2;
3604
3605 bochs_bios_init();
c45886db
FB		 3606#elif defined(TARGET_PPC)
3607 cpu_x86_init_mmu(env);
3608 /* allocate ROM */
3609 // snprintf(buf, sizeof(buf), "%s/%s", bios_dir, BIOS_FILENAME);
3610 snprintf(buf, sizeof(buf), "%s", BIOS_FILENAME);
3611 printf("load BIOS at %p\n", phys_ram_base + 0x000f0000);
3612 ret = load_image(buf, phys_ram_base + 0x000f0000);
3613 if (ret != 0x10000) {
3614 fprintf(stderr, "qemu: could not load PPC bios '%s' (%d)\n%m\n",
3615 buf, ret);
3616 exit(1);
3617 }
3618#endif
0824d6fc 3619 }
0824d6fc 3620
313aa567 3621 /* terminal init */
a20dd508 3622 if (nographic) {
313aa567
FB		 3623 dumb_display_init(ds);
3624 } else {
3625#ifdef CONFIG_SDL
3626 sdl_display_init(ds);
313aa567
FB		 3627#else
3628 dumb_display_init(ds);
3629#endif
3630 }
0824d6fc 3631 /* init basic PC hardware */
fc01f7e7 3632 register_ioport_write(0x80, 1, ioport80_write, 1);
0824d6fc 3633
c45886db 3634 vga_initialize(ds, phys_ram_base + phys_ram_size, phys_ram_size,
313aa567 3635 vga_ram_size);
c45886db 3636#if defined (TARGET_I386)
0824d6fc 3637 cmos_init();
c45886db 3638#endif
0824d6fc
FB		 3639 pic_init();
3640 pit_init();
3641 serial_init();
c45886db 3642#if defined (TARGET_I386)
f1510b2c 3643 ne2000_init();
c45886db 3644#endif
fc01f7e7 3645 ide_init();
cd4c3e88 3646 kbd_init();
27503323
FB		 3647 AUD_init();
3648 DMA_init();
c45886db 3649#if defined (TARGET_I386)
27503323 3650 SB16_init();
c45886db
FB		 3651#endif
3652#if defined (TARGET_PPC)
3653 PPC_end_init();
3654#endif
3655 fdctrl_register((unsigned char **)fd_filename, snapshot, boot_device);
0824d6fc
FB		 3656 /* setup cpu signal handlers for MMU / self modifying code handling */
3657 sigfillset(&act.sa_mask);
3658 act.sa_flags = SA_SIGINFO;
3a51dee6 3659#if !defined(CONFIG_SOFTMMU)
0824d6fc
FB		 3660 act.sa_sigaction = host_segv_handler;
3661 sigaction(SIGSEGV, &act, NULL);
3662 sigaction(SIGBUS, &act, NULL);
3a51dee6 3663#endif
0824d6fc
FB		 3664
3665 act.sa_sigaction = host_alarm_handler;
3666 sigaction(SIGALRM, &act, NULL);
3667
0824d6fc 3668 itv.it_interval.tv_sec = 0;
87858c89 3669 itv.it_interval.tv_usec = 1000;
0824d6fc
FB		 3670 itv.it_value.tv_sec = 0;
3671 itv.it_value.tv_usec = 10 * 1000;
3672 setitimer(ITIMER_REAL, &itv, NULL);
87858c89
FB		 3673 /* we probe the tick duration of the kernel to inform the user if
3674 the emulated kernel requested a too high timer frequency */
3675 getitimer(ITIMER_REAL, &itv);
313aa567 3676 timer_ms = itv.it_interval.tv_usec / 1000;
87858c89
FB		 3677 pit_min_timer_count = ((uint64_t)itv.it_interval.tv_usec * PIT_FREQ) /
3678 1000000;
7f7f9873 3679
b4608c04
FB		 3680 if (use_gdbstub) {
3681 cpu_gdbstub(NULL, main_loop, gdbstub_port);
3682 } else {
3683 main_loop(NULL);
0824d6fc 3684 }
0824d6fc
FB		 3685 return 0;
3686}
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