UefiCpuPkg: Move AsmRelocateApLoopStart from Mpfuncs.nasm to AmdSev.nasm

[mirror_edk2.git] / ArmPkg / Include / Chipset / ArmV7.h

/** @file\r
\r
  Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
  Copyright (c) 2011-2015, ARM Ltd. All rights reserved.<BR>\r
\r
  SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
**/\r
\r
#ifndef __ARM_V7_H__\r
#define __ARM_V7_H__\r
\r
#include <Chipset/ArmV7Mmu.h>\r
\r
// ARM Interrupt ID in Exception Table\r
#define ARM_ARCH_EXCEPTION_IRQ            EXCEPT_ARM_IRQ\r
\r
// ID_PFR1 - ARM Processor Feature Register 1 definitions\r
#define ARM_PFR1_SEC        (0xFUL << 4)\r
#define ARM_PFR1_TIMER      (0xFUL << 16)\r
#define ARM_PFR1_GIC        (0xFUL << 28)\r
\r
// Domain Access Control Register\r
#define DOMAIN_ACCESS_CONTROL_MASK(a)     (3UL << (2 * (a)))\r
#define DOMAIN_ACCESS_CONTROL_NONE(a)     (0UL << (2 * (a)))\r
#define DOMAIN_ACCESS_CONTROL_CLIENT(a)   (1UL << (2 * (a)))\r
#define DOMAIN_ACCESS_CONTROL_RESERVED(a) (2UL << (2 * (a)))\r
#define DOMAIN_ACCESS_CONTROL_MANAGER(a)  (3UL << (2 * (a)))\r
\r
// CPSR - Coprocessor Status Register definitions\r
#define CPSR_MODE_USER       0x10\r
#define CPSR_MODE_FIQ        0x11\r
#define CPSR_MODE_IRQ        0x12\r
#define CPSR_MODE_SVC        0x13\r
#define CPSR_MODE_ABORT      0x17\r
#define CPSR_MODE_HYP        0x1A\r
#define CPSR_MODE_UNDEFINED  0x1B\r
#define CPSR_MODE_SYSTEM     0x1F\r
#define CPSR_MODE_MASK       0x1F\r
#define CPSR_ASYNC_ABORT     (1 << 8)\r
#define CPSR_IRQ             (1 << 7)\r
#define CPSR_FIQ             (1 << 6)\r
\r
\r
// CPACR - Coprocessor Access Control Register definitions\r
#define CPACR_CP_DENIED(cp)     0x00\r
#define CPACR_CP_PRIV(cp)       ((0x1 << ((cp) << 1)) & 0x0FFFFFFF)\r
#define CPACR_CP_FULL(cp)       ((0x3 << ((cp) << 1)) & 0x0FFFFFFF)\r
#define CPACR_ASEDIS            (1 << 31)\r
#define CPACR_D32DIS            (1 << 30)\r
#define CPACR_CP_FULL_ACCESS    0x0FFFFFFF\r
\r
// NSACR - Non-Secure Access Control Register definitions\r
#define NSACR_CP(cp)            ((1 << (cp)) & 0x3FFF)\r
#define NSACR_NSD32DIS          (1 << 14)\r
#define NSACR_NSASEDIS          (1 << 15)\r
#define NSACR_PLE               (1 << 16)\r
#define NSACR_TL                (1 << 17)\r
#define NSACR_NS_SMP            (1 << 18)\r
#define NSACR_RFR               (1 << 19)\r
\r
// SCR - Secure Configuration Register definitions\r
#define SCR_NS                  (1 << 0)\r
#define SCR_IRQ                 (1 << 1)\r
#define SCR_FIQ                 (1 << 2)\r
#define SCR_EA                  (1 << 3)\r
#define SCR_FW                  (1 << 4)\r
#define SCR_AW                  (1 << 5)\r
\r
// MIDR - Main ID Register definitions\r
#define ARM_CPU_TYPE_SHIFT      4\r
#define ARM_CPU_TYPE_MASK       0xFFF\r
#define ARM_CPU_TYPE_AEMv8      0xD0F\r
#define ARM_CPU_TYPE_A53        0xD03\r
#define ARM_CPU_TYPE_A57        0xD07\r
#define ARM_CPU_TYPE_A15        0xC0F\r
#define ARM_CPU_TYPE_A12        0xC0D\r
#define ARM_CPU_TYPE_A9         0xC09\r
#define ARM_CPU_TYPE_A7         0xC07\r
#define ARM_CPU_TYPE_A5         0xC05\r
\r
#define ARM_CPU_REV_MASK        ((0xF << 20) | (0xF) )\r
#define ARM_CPU_REV(rn, pn)     ((((rn) & 0xF) << 20) | ((pn) & 0xF))\r
\r
#define ARM_VECTOR_TABLE_ALIGNMENT ((1 << 5)-1)\r
\r
VOID\r
EFIAPI\r
ArmEnableSWPInstruction (\r
  VOID\r
  );\r
\r
UINTN\r
EFIAPI\r
ArmReadCbar (\r
  VOID\r
  );\r
\r
UINTN\r
EFIAPI\r
ArmReadTpidrurw (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmWriteTpidrurw (\r
  UINTN Value\r
  );\r
\r
UINT32\r
EFIAPI\r
ArmReadNsacr (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmWriteNsacr (\r
  IN  UINT32   Nsacr\r
  );\r
\r
#endif // __ARM_V7_H__\r