| | 1 | #------------------------------------------------------------------------------\r |
| | 2 | #\r |
| | 3 | # Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r |
| | 4 | # Copyright (c) 2011 - 2014, ARM Limited. All rights reserved.\r |
| | 5 | # Copyright (c) 2016, Linaro Limited. All rights reserved.\r |
| | 6 | #\r |
| | 7 | # This program and the accompanying materials\r |
| | 8 | # are licensed and made available under the terms and conditions of the BSD License\r |
| | 9 | # which accompanies this distribution. The full text of the license may be found at\r |
| | 10 | # http://opensource.org/licenses/bsd-license.php\r |
| | 11 | #\r |
| | 12 | # THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r |
| | 13 | # WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r |
| | 14 | #\r |
| | 15 | #------------------------------------------------------------------------------\r |
| | 16 | \r |
| | 17 | #include <AsmMacroIoLibV8.h>\r |
| | 18 | \r |
| | 19 | .set MPIDR_U_BIT, (30)\r |
| | 20 | .set MPIDR_U_MASK, (1 << MPIDR_U_BIT)\r |
| | 21 | \r |
| | 22 | // DAIF bit definitions for writing through msr daifclr/sr daifset\r |
| | 23 | .set DAIF_WR_FIQ_BIT, (1 << 0)\r |
| | 24 | .set DAIF_WR_IRQ_BIT, (1 << 1)\r |
| | 25 | .set DAIF_WR_ABORT_BIT, (1 << 2)\r |
| | 26 | .set DAIF_WR_DEBUG_BIT, (1 << 3)\r |
| | 27 | .set DAIF_WR_INT_BITS, (DAIF_WR_FIQ_BIT | DAIF_WR_IRQ_BIT)\r |
| | 28 | .set DAIF_WR_ALL, (DAIF_WR_DEBUG_BIT | DAIF_WR_ABORT_BIT | DAIF_WR_INT_BITS)\r |
| | 29 | \r |
| | 30 | \r |
| | 31 | ASM_FUNC(ArmIsMpCore)\r |
| | 32 | mrs x0, mpidr_el1 // Read EL1 Mutliprocessor Affinty Reg (MPIDR)\r |
| | 33 | and x0, x0, #MPIDR_U_MASK // U Bit clear, the processor is part of a multiprocessor system\r |
| | 34 | lsr x0, x0, #MPIDR_U_BIT\r |
| | 35 | eor x0, x0, #1\r |
| | 36 | ret\r |
| | 37 | \r |
| | 38 | \r |
| | 39 | ASM_FUNC(ArmEnableAsynchronousAbort)\r |
| | 40 | msr daifclr, #DAIF_WR_ABORT_BIT\r |
| | 41 | isb\r |
| | 42 | ret\r |
| | 43 | \r |
| | 44 | \r |
| | 45 | ASM_FUNC(ArmDisableAsynchronousAbort)\r |
| | 46 | msr daifset, #DAIF_WR_ABORT_BIT\r |
| | 47 | isb\r |
| | 48 | ret\r |
| | 49 | \r |
| | 50 | \r |
| | 51 | ASM_FUNC(ArmEnableIrq)\r |
| | 52 | msr daifclr, #DAIF_WR_IRQ_BIT\r |
| | 53 | isb\r |
| | 54 | ret\r |
| | 55 | \r |
| | 56 | \r |
| | 57 | ASM_FUNC(ArmDisableIrq)\r |
| | 58 | msr daifset, #DAIF_WR_IRQ_BIT\r |
| | 59 | isb\r |
| | 60 | ret\r |
| | 61 | \r |
| | 62 | \r |
| | 63 | ASM_FUNC(ArmEnableFiq)\r |
| | 64 | msr daifclr, #DAIF_WR_FIQ_BIT\r |
| | 65 | isb\r |
| | 66 | ret\r |
| | 67 | \r |
| | 68 | \r |
| | 69 | ASM_FUNC(ArmDisableFiq)\r |
| | 70 | msr daifset, #DAIF_WR_FIQ_BIT\r |
| | 71 | isb\r |
| | 72 | ret\r |
| | 73 | \r |
| | 74 | \r |
| | 75 | ASM_FUNC(ArmEnableInterrupts)\r |
| | 76 | msr daifclr, #DAIF_WR_INT_BITS\r |
| | 77 | isb\r |
| | 78 | ret\r |
| | 79 | \r |
| | 80 | \r |
| | 81 | ASM_FUNC(ArmDisableInterrupts)\r |
| | 82 | msr daifset, #DAIF_WR_INT_BITS\r |
| | 83 | isb\r |
| | 84 | ret\r |
| | 85 | \r |
| | 86 | \r |
| | 87 | ASM_FUNC(ArmDisableAllExceptions)\r |
| | 88 | msr daifset, #DAIF_WR_ALL\r |
| | 89 | isb\r |
| | 90 | ret\r |
| | 91 | \r |
| | 92 | \r |
| | 93 | // UINT32\r |
| | 94 | // ReadCCSIDR (\r |
| | 95 | // IN UINT32 CSSELR\r |
| | 96 | // )\r |
| | 97 | ASM_FUNC(ReadCCSIDR)\r |
| | 98 | msr csselr_el1, x0 // Write Cache Size Selection Register (CSSELR)\r |
| | 99 | isb\r |
| | 100 | mrs x0, ccsidr_el1 // Read current Cache Size ID Register (CCSIDR)\r |
| | 101 | ret\r |
| | 102 | \r |
| | 103 | \r |
| | 104 | // UINT32\r |
| | 105 | // ReadCLIDR (\r |
| | 106 | // IN UINT32 CSSELR\r |
| | 107 | // )\r |
| | 108 | ASM_FUNC(ReadCLIDR)\r |
| | 109 | mrs x0, clidr_el1 // Read Cache Level ID Register\r |
| | 110 | ret\r |
| | 111 | \r |
| | 112 | ASM_FUNCTION_REMOVE_IF_UNREFERENCED\r |
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