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1 | /** @file | |
2 | ||
3 | Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR> | |
4 | ||
5 | This program and the accompanying materials | |
6 | are licensed and made available under the terms and conditions of the BSD License | |
7 | which accompanies this distribution. The full text of the license may be found at | |
8 | http://opensource.org/licenses/bsd-license.php | |
9 | ||
10 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, | |
11 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. | |
12 | ||
13 | **/ | |
14 | #include <Uefi.h> | |
15 | #include <Chipset/ArmV7.h> | |
16 | #include <Library/ArmLib.h> | |
17 | #include <Library/BaseLib.h> | |
18 | #include <Library/IoLib.h> | |
19 | #include "ArmV7Lib.h" | |
20 | #include "ArmLibPrivate.h" | |
21 | ||
22 | ARM_CACHE_TYPE | |
23 | EFIAPI | |
24 | ArmCacheType ( | |
25 | VOID | |
26 | ) | |
27 | { | |
28 | return ARM_CACHE_TYPE_WRITE_BACK; | |
29 | } | |
30 | ||
31 | ARM_CACHE_ARCHITECTURE | |
32 | EFIAPI | |
33 | ArmCacheArchitecture ( | |
34 | VOID | |
35 | ) | |
36 | { | |
37 | UINT32 CLIDR = ReadCLIDR (); | |
38 | ||
39 | return (ARM_CACHE_ARCHITECTURE)CLIDR; // BugBug Fix Me | |
40 | } | |
41 | ||
42 | BOOLEAN | |
43 | EFIAPI | |
44 | ArmDataCachePresent ( | |
45 | VOID | |
46 | ) | |
47 | { | |
48 | UINT32 CLIDR = ReadCLIDR (); | |
49 | ||
50 | if ((CLIDR & 0x2) == 0x2) { | |
51 | // Instruction cache exists | |
52 | return TRUE; | |
53 | } | |
54 | if ((CLIDR & 0x7) == 0x4) { | |
55 | // Unified cache | |
56 | return TRUE; | |
57 | } | |
58 | ||
59 | return FALSE; | |
60 | } | |
61 | ||
62 | UINTN | |
63 | EFIAPI | |
64 | ArmDataCacheSize ( | |
65 | VOID | |
66 | ) | |
67 | { | |
68 | UINT32 NumSets; | |
69 | UINT32 Associativity; | |
70 | UINT32 LineSize; | |
71 | UINT32 CCSIDR = ReadCCSIDR (0); | |
72 | ||
73 | LineSize = (1 << ((CCSIDR & 0x7) + 2)); | |
74 | Associativity = ((CCSIDR >> 3) & 0x3ff) + 1; | |
75 | NumSets = ((CCSIDR >> 13) & 0x7fff) + 1; | |
76 | ||
77 | // LineSize is in words (4 byte chunks) | |
78 | return NumSets * Associativity * LineSize * 4; | |
79 | } | |
80 | ||
81 | UINTN | |
82 | EFIAPI | |
83 | ArmDataCacheAssociativity ( | |
84 | VOID | |
85 | ) | |
86 | { | |
87 | UINT32 CCSIDR = ReadCCSIDR (0); | |
88 | ||
89 | return ((CCSIDR >> 3) & 0x3ff) + 1; | |
90 | } | |
91 | ||
92 | UINTN | |
93 | ArmDataCacheSets ( | |
94 | VOID | |
95 | ) | |
96 | { | |
97 | UINT32 CCSIDR = ReadCCSIDR (0); | |
98 | ||
99 | return ((CCSIDR >> 13) & 0x7fff) + 1; | |
100 | } | |
101 | ||
102 | UINTN | |
103 | EFIAPI | |
104 | ArmDataCacheLineLength ( | |
105 | VOID | |
106 | ) | |
107 | { | |
108 | UINT32 CCSIDR = ReadCCSIDR (0) & 7; | |
109 | ||
110 | // * 4 converts to bytes | |
111 | return (1 << (CCSIDR + 2)) * 4; | |
112 | } | |
113 | ||
114 | BOOLEAN | |
115 | EFIAPI | |
116 | ArmInstructionCachePresent ( | |
117 | VOID | |
118 | ) | |
119 | { | |
120 | UINT32 CLIDR = ReadCLIDR (); | |
121 | ||
122 | if ((CLIDR & 1) == 1) { | |
123 | // Instruction cache exists | |
124 | return TRUE; | |
125 | } | |
126 | if ((CLIDR & 0x7) == 0x4) { | |
127 | // Unified cache | |
128 | return TRUE; | |
129 | } | |
130 | ||
131 | return FALSE; | |
132 | } | |
133 | ||
134 | UINTN | |
135 | EFIAPI | |
136 | ArmInstructionCacheSize ( | |
137 | VOID | |
138 | ) | |
139 | { | |
140 | UINT32 NumSets; | |
141 | UINT32 Associativity; | |
142 | UINT32 LineSize; | |
143 | UINT32 CCSIDR = ReadCCSIDR (1); | |
144 | ||
145 | LineSize = (1 << ((CCSIDR & 0x7) + 2)); | |
146 | Associativity = ((CCSIDR >> 3) & 0x3ff) + 1; | |
147 | NumSets = ((CCSIDR >> 13) & 0x7fff) + 1; | |
148 | ||
149 | // LineSize is in words (4 byte chunks) | |
150 | return NumSets * Associativity * LineSize * 4; | |
151 | } | |
152 | ||
153 | UINTN | |
154 | EFIAPI | |
155 | ArmInstructionCacheAssociativity ( | |
156 | VOID | |
157 | ) | |
158 | { | |
159 | UINT32 CCSIDR = ReadCCSIDR (1); | |
160 | ||
161 | return ((CCSIDR >> 3) & 0x3ff) + 1; | |
162 | // return 4; | |
163 | } | |
164 | ||
165 | UINTN | |
166 | EFIAPI | |
167 | ArmInstructionCacheSets ( | |
168 | VOID | |
169 | ) | |
170 | { | |
171 | UINT32 CCSIDR = ReadCCSIDR (1); | |
172 | ||
173 | return ((CCSIDR >> 13) & 0x7fff) + 1; | |
174 | } | |
175 | ||
176 | UINTN | |
177 | EFIAPI | |
178 | ArmInstructionCacheLineLength ( | |
179 | VOID | |
180 | ) | |
181 | { | |
182 | UINT32 CCSIDR = ReadCCSIDR (1) & 7; | |
183 | ||
184 | // * 4 converts to bytes | |
185 | return (1 << (CCSIDR + 2)) * 4; | |
186 | ||
187 | // return 64; | |
188 | } | |
189 | ||
190 | ||
191 | VOID | |
192 | ArmV7DataCacheOperation ( | |
193 | IN ARM_V7_CACHE_OPERATION DataCacheOperation | |
194 | ) | |
195 | { | |
196 | UINTN SavedInterruptState; | |
197 | ||
198 | SavedInterruptState = ArmGetInterruptState (); | |
199 | ArmDisableInterrupts(); | |
200 | ||
201 | ||
202 | ArmV7AllDataCachesOperation (DataCacheOperation); | |
203 | ||
204 | ArmDrainWriteBuffer (); | |
205 | ||
206 | if (SavedInterruptState) { | |
207 | ArmEnableInterrupts (); | |
208 | } | |
209 | } | |
210 | ||
211 | VOID | |
212 | EFIAPI | |
213 | ArmInvalidateDataCache ( | |
214 | VOID | |
215 | ) | |
216 | { | |
217 | ArmV7DataCacheOperation (ArmInvalidateDataCacheEntryBySetWay); | |
218 | } | |
219 | ||
220 | VOID | |
221 | EFIAPI | |
222 | ArmCleanInvalidateDataCache ( | |
223 | VOID | |
224 | ) | |
225 | { | |
226 | ArmV7DataCacheOperation (ArmCleanInvalidateDataCacheEntryBySetWay); | |
227 | } | |
228 | ||
229 | VOID | |
230 | EFIAPI | |
231 | ArmCleanDataCache ( | |
232 | VOID | |
233 | ) | |
234 | { | |
235 | ArmV7DataCacheOperation (ArmCleanDataCacheEntryBySetWay); | |
236 | } | |
237 | ||
238 | VOID | |
239 | EFIAPI | |
240 | ArmSetAuxCrBit ( | |
241 | IN UINT32 Bits | |
242 | ) | |
243 | { | |
244 | UINT32 val = ArmReadAuxCr(); | |
245 | val |= Bits; | |
246 | ArmWriteAuxCr(val); | |
247 | } |