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1 | #------------------------------------------------------------------------------\r | |
2 | #\r | |
3 | # Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>\r | |
4 | # Copyright (c) 2011 - 2012, ARM Ltd. All rights reserved.<BR>\r | |
5 | #\r | |
6 | # This program and the accompanying materials\r | |
7 | # are licensed and made available under the terms and conditions of the BSD License\r | |
8 | # which accompanies this distribution. The full text of the license may be found at\r | |
9 | # http://opensource.org/licenses/bsd-license.php\r | |
10 | #\r | |
11 | # THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
12 | # WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
13 | #\r | |
14 | #------------------------------------------------------------------------------\r | |
15 | \r | |
16 | #include <Library/PcdLib.h>\r | |
17 | \r | |
18 | /*\r | |
19 | \r | |
20 | This is the stack constructed by the exception handler (low address to high address)\r | |
21 | # R0 - IFAR is EFI_SYSTEM_CONTEXT for ARM\r | |
22 | Reg Offset\r | |
23 | === ======\r | |
24 | R0 0x00 # stmfd SP!,{R0-R12}\r | |
25 | R1 0x04\r | |
26 | R2 0x08\r | |
27 | R3 0x0c\r | |
28 | R4 0x10\r | |
29 | R5 0x14\r | |
30 | R6 0x18\r | |
31 | R7 0x1c\r | |
32 | R8 0x20\r | |
33 | R9 0x24\r | |
34 | R10 0x28\r | |
35 | R11 0x2c\r | |
36 | R12 0x30\r | |
37 | SP 0x34 # reserved via adding 0x20 (32) to the SP\r | |
38 | LR 0x38\r | |
39 | PC 0x3c\r | |
40 | CPSR 0x40\r | |
41 | DFSR 0x44\r | |
42 | DFAR 0x48\r | |
43 | IFSR 0x4c\r | |
44 | IFAR 0x50\r | |
45 | \r | |
46 | LR 0x54 # SVC Link register (we need to restore it)\r | |
47 | \r | |
48 | LR 0x58 # pushed by srsfd\r | |
49 | CPSR 0x5c\r | |
50 | \r | |
51 | */\r | |
52 | \r | |
53 | GCC_ASM_EXPORT(DebugAgentVectorTable)\r | |
54 | GCC_ASM_IMPORT(DefaultExceptionHandler)\r | |
55 | \r | |
56 | .text\r | |
57 | #if !defined(__APPLE__)\r | |
58 | .fpu neon @ makes vpush/vpop assemble\r | |
59 | #endif\r | |
60 | .align 5\r | |
61 | \r | |
62 | \r | |
63 | //\r | |
64 | // This code gets copied to the ARM vector table\r | |
65 | // ExceptionHandlersStart - ExceptionHandlersEnd gets copied\r | |
66 | //\r | |
67 | ASM_PFX(DebugAgentVectorTable):\r | |
68 | b ASM_PFX(ResetEntry)\r | |
69 | b ASM_PFX(UndefinedInstructionEntry)\r | |
70 | b ASM_PFX(SoftwareInterruptEntry)\r | |
71 | b ASM_PFX(PrefetchAbortEntry)\r | |
72 | b ASM_PFX(DataAbortEntry)\r | |
73 | b ASM_PFX(ReservedExceptionEntry)\r | |
74 | b ASM_PFX(IrqEntry)\r | |
75 | b ASM_PFX(FiqEntry)\r | |
76 | \r | |
77 | ASM_PFX(ResetEntry):\r | |
78 | srsdb #0x13! @ Store return state on SVC stack\r | |
79 | @ We are already in SVC mode\r | |
80 | \r | |
81 | stmfd SP!,{LR} @ Store the link register for the current mode\r | |
82 | sub SP,SP,#0x20 @ Save space for SP, LR, PC, IFAR - CPSR\r | |
83 | stmfd SP!,{R0-R12} @ Store the register state\r | |
84 | \r | |
85 | mov R0,#0 @ ExceptionType\r | |
86 | ldr R1,ASM_PFX(CommonExceptionEntry)\r | |
87 | bx R1\r | |
88 | \r | |
89 | ASM_PFX(UndefinedInstructionEntry):\r | |
90 | sub LR, LR, #4 @ Only -2 for Thumb, adjust in CommonExceptionEntry\r | |
91 | srsdb #0x13! @ Store return state on SVC stack\r | |
92 | cps #0x13 @ Switch to SVC for common stack\r | |
93 | stmfd SP!,{LR} @ Store the link register for the current mode\r | |
94 | sub SP,SP,#0x20 @ Save space for SP, LR, PC, IFAR - CPSR\r | |
95 | stmfd SP!,{R0-R12} @ Store the register state\r | |
96 | \r | |
97 | mov R0,#1 @ ExceptionType\r | |
98 | ldr R1,ASM_PFX(CommonExceptionEntry)\r | |
99 | bx R1\r | |
100 | \r | |
101 | ASM_PFX(SoftwareInterruptEntry):\r | |
102 | sub LR, LR, #4 @ Only -2 for Thumb, adjust in CommonExceptionEntry\r | |
103 | srsdb #0x13! @ Store return state on SVC stack\r | |
104 | @ We are already in SVC mode\r | |
105 | stmfd SP!,{LR} @ Store the link register for the current mode\r | |
106 | sub SP,SP,#0x20 @ Save space for SP, LR, PC, IFAR - CPSR\r | |
107 | stmfd SP!,{R0-R12} @ Store the register state\r | |
108 | \r | |
109 | mov R0,#2 @ ExceptionType\r | |
110 | ldr R1,ASM_PFX(CommonExceptionEntry)\r | |
111 | bx R1\r | |
112 | \r | |
113 | ASM_PFX(PrefetchAbortEntry):\r | |
114 | sub LR,LR,#4\r | |
115 | srsdb #0x13! @ Store return state on SVC stack\r | |
116 | cps #0x13 @ Switch to SVC for common stack\r | |
117 | stmfd SP!,{LR} @ Store the link register for the current mode\r | |
118 | sub SP,SP,#0x20 @ Save space for SP, LR, PC, IFAR - CPSR\r | |
119 | stmfd SP!,{R0-R12} @ Store the register state\r | |
120 | \r | |
121 | mov R0,#3 @ ExceptionType\r | |
122 | ldr R1,ASM_PFX(CommonExceptionEntry)\r | |
123 | bx R1\r | |
124 | \r | |
125 | ASM_PFX(DataAbortEntry):\r | |
126 | sub LR,LR,#8\r | |
127 | srsdb #0x13! @ Store return state on SVC stack\r | |
128 | cps #0x13 @ Switch to SVC for common stack\r | |
129 | stmfd SP!,{LR} @ Store the link register for the current mode\r | |
130 | sub SP,SP,#0x20 @ Save space for SP, LR, PC, IFAR - CPSR\r | |
131 | stmfd SP!,{R0-R12} @ Store the register state\r | |
132 | \r | |
133 | mov R0,#4\r | |
134 | ldr R1,ASM_PFX(CommonExceptionEntry)\r | |
135 | bx R1\r | |
136 | \r | |
137 | ASM_PFX(ReservedExceptionEntry):\r | |
138 | srsdb #0x13! @ Store return state on SVC stack\r | |
139 | cps #0x13 @ Switch to SVC for common stack\r | |
140 | stmfd SP!,{LR} @ Store the link register for the current mode\r | |
141 | sub SP,SP,#0x20 @ Save space for SP, LR, PC, IFAR - CPSR\r | |
142 | stmfd SP!,{R0-R12} @ Store the register state\r | |
143 | \r | |
144 | mov R0,#5\r | |
145 | ldr R1,ASM_PFX(CommonExceptionEntry)\r | |
146 | bx R1\r | |
147 | \r | |
148 | ASM_PFX(IrqEntry):\r | |
149 | sub LR,LR,#4\r | |
150 | srsdb #0x13! @ Store return state on SVC stack\r | |
151 | cps #0x13 @ Switch to SVC for common stack\r | |
152 | stmfd SP!,{LR} @ Store the link register for the current mode\r | |
153 | sub SP,SP,#0x20 @ Save space for SP, LR, PC, IFAR - CPSR\r | |
154 | stmfd SP!,{R0-R12} @ Store the register state\r | |
155 | \r | |
156 | mov R0,#6 @ ExceptionType\r | |
157 | ldr R1,ASM_PFX(CommonExceptionEntry)\r | |
158 | bx R1\r | |
159 | \r | |
160 | ASM_PFX(FiqEntry):\r | |
161 | sub LR,LR,#4\r | |
162 | srsdb #0x13! @ Store return state on SVC stack\r | |
163 | cps #0x13 @ Switch to SVC for common stack\r | |
164 | stmfd SP!,{LR} @ Store the link register for the current mode\r | |
165 | sub SP,SP,#0x20 @ Save space for SP, LR, PC, IFAR - CPSR\r | |
166 | stmfd SP!,{R0-R12} @ Store the register state\r | |
167 | @ Since we have already switch to SVC R8_fiq - R12_fiq\r | |
168 | @ never get used or saved\r | |
169 | mov R0,#7 @ ExceptionType\r | |
170 | ldr R1,ASM_PFX(CommonExceptionEntry)\r | |
171 | bx R1\r | |
172 | \r | |
173 | //\r | |
174 | // This gets patched by the C code that patches in the vector table\r | |
175 | //\r | |
176 | ASM_PFX(CommonExceptionEntry):\r | |
177 | .word ASM_PFX(AsmCommonExceptionEntry)\r | |
178 | \r | |
179 | ASM_PFX(ExceptionHandlersEnd):\r | |
180 | \r | |
181 | //\r | |
182 | // This code runs from CpuDxe driver loaded address. It is patched into\r | |
183 | // CommonExceptionEntry.\r | |
184 | //\r | |
185 | ASM_PFX(AsmCommonExceptionEntry):\r | |
186 | mrc p15, 0, R1, c6, c0, 2 @ Read IFAR\r | |
187 | str R1, [SP, #0x50] @ Store it in EFI_SYSTEM_CONTEXT_ARM.IFAR\r | |
188 | \r | |
189 | mrc p15, 0, R1, c5, c0, 1 @ Read IFSR\r | |
190 | str R1, [SP, #0x4c] @ Store it in EFI_SYSTEM_CONTEXT_ARM.IFSR\r | |
191 | \r | |
192 | mrc p15, 0, R1, c6, c0, 0 @ Read DFAR\r | |
193 | str R1, [SP, #0x48] @ Store it in EFI_SYSTEM_CONTEXT_ARM.DFAR\r | |
194 | \r | |
195 | mrc p15, 0, R1, c5, c0, 0 @ Read DFSR\r | |
196 | str R1, [SP, #0x44] @ Store it in EFI_SYSTEM_CONTEXT_ARM.DFSR\r | |
197 | \r | |
198 | ldr R1, [SP, #0x5c] @ srsdb saved pre-exception CPSR on the stack\r | |
199 | str R1, [SP, #0x40] @ Store it in EFI_SYSTEM_CONTEXT_ARM.CPSR\r | |
200 | \r | |
201 | add R2, SP, #0x38 @ Make R2 point to EFI_SYSTEM_CONTEXT_ARM.LR\r | |
202 | and R3, R1, #0x1f @ Check CPSR to see if User or System Mode\r | |
203 | cmp R3, #0x1f @ if ((CPSR == 0x10) || (CPSR == 0x1df))\r | |
204 | cmpne R3, #0x10 @\r | |
205 | stmeqed R2, {lr}^ @ save unbanked lr\r | |
206 | @ else\r | |
207 | stmneed R2, {lr} @ save SVC lr\r | |
208 | \r | |
209 | \r | |
210 | ldr R5, [SP, #0x58] @ PC is the LR pushed by srsfd\r | |
211 | @ Check to see if we have to adjust for Thumb entry\r | |
212 | sub r4, r0, #1 @ if (ExceptionType == 1 || ExceptionType ==2)) {\r | |
213 | cmp r4, #1 @ // UND & SVC have differnt LR adjust for Thumb\r | |
214 | bhi NoAdjustNeeded\r | |
215 | \r | |
216 | tst r1, #0x20 @ if ((CPSR & T)) == T) { // Thumb Mode on entry\r | |
217 | addne R5, R5, #2 @ PC += 2@\r | |
218 | str R5,[SP,#0x58] @ Update LR value pused by srsfd\r | |
219 | \r | |
220 | NoAdjustNeeded:\r | |
221 | \r | |
222 | str R5, [SP, #0x3c] @ Store it in EFI_SYSTEM_CONTEXT_ARM.PC\r | |
223 | \r | |
224 | sub R1, SP, #0x60 @ We pused 0x60 bytes on the stack\r | |
225 | str R1, [SP, #0x34] @ Store it in EFI_SYSTEM_CONTEXT_ARM.SP\r | |
226 | \r | |
227 | @ R0 is ExceptionType\r | |
228 | mov R1,SP @ R1 is SystemContext\r | |
229 | \r | |
230 | #if (FixedPcdGet32(PcdVFPEnabled))\r | |
231 | vpush {d0-d15} @ save vstm registers in case they are used in optimizations\r | |
232 | #endif\r | |
233 | \r | |
234 | /*\r | |
235 | VOID\r | |
236 | EFIAPI\r | |
237 | DefaultExceptionHandler (\r | |
238 | IN EFI_EXCEPTION_TYPE ExceptionType, R0\r | |
239 | IN OUT EFI_SYSTEM_CONTEXT SystemContext R1\r | |
240 | )\r | |
241 | \r | |
242 | */\r | |
243 | blx ASM_PFX(DefaultExceptionHandler) @ Call exception handler\r | |
244 | \r | |
245 | #if (FixedPcdGet32(PcdVFPEnabled))\r | |
246 | vpop {d0-d15}\r | |
247 | #endif\r | |
248 | \r | |
249 | ldr R1, [SP, #0x4c] @ Restore EFI_SYSTEM_CONTEXT_ARM.IFSR\r | |
250 | mcr p15, 0, R1, c5, c0, 1 @ Write IFSR\r | |
251 | \r | |
252 | ldr R1, [SP, #0x44] @ sRestore EFI_SYSTEM_CONTEXT_ARM.DFSR\r | |
253 | mcr p15, 0, R1, c5, c0, 0 @ Write DFSR\r | |
254 | \r | |
255 | ldr R1,[SP,#0x3c] @ EFI_SYSTEM_CONTEXT_ARM.PC\r | |
256 | str R1,[SP,#0x58] @ Store it back to srsfd stack slot so it can be restored\r | |
257 | \r | |
258 | ldr R1,[SP,#0x40] @ EFI_SYSTEM_CONTEXT_ARM.CPSR\r | |
259 | str R1,[SP,#0x5c] @ Store it back to srsfd stack slot so it can be restored\r | |
260 | \r | |
261 | add R3, SP, #0x54 @ Make R3 point to SVC LR saved on entry\r | |
262 | add R2, SP, #0x38 @ Make R2 point to EFI_SYSTEM_CONTEXT_ARM.LR\r | |
263 | and R1, R1, #0x1f @ Check to see if User or System Mode\r | |
264 | cmp R1, #0x1f @ if ((CPSR == 0x10) || (CPSR == 0x1f))\r | |
265 | cmpne R1, #0x10 @\r | |
266 | ldmeqed R2, {lr}^ @ restore unbanked lr\r | |
267 | @ else\r | |
268 | ldmneed R3, {lr} @ restore SVC lr, via ldmfd SP!, {LR}\r | |
269 | \r | |
270 | ldmfd SP!,{R0-R12} @ Restore general purpose registers\r | |
271 | @ Exception handler can not change SP\r | |
272 | \r | |
273 | add SP,SP,#0x20 @ Clear out the remaining stack space\r | |
274 | ldmfd SP!,{LR} @ restore the link register for this context\r | |
275 | rfefd SP! @ return from exception via srsfd stack slot\r | |
276 | \r |