]> git.proxmox.com Git - mirror_edk2.git/blame_incremental - ArmPlatformPkg/ArmPlatformPkg.dec
ShellPkg: UefiShellBcfgCommandLib: drop unused string tokens
[mirror_edk2.git] / ArmPlatformPkg / ArmPlatformPkg.dec
... / ...
CommitLineData
1#/** @file\r
2#\r
3# Copyright (c) 2011-2015, ARM Limited. All rights reserved.\r
4# Copyright (c) 2015, Intel Corporation. All rights reserved.\r
5#\r
6# This program and the accompanying materials\r
7# are licensed and made available under the terms and conditions of the BSD License\r
8# which accompanies this distribution. The full text of the license may be found at\r
9# http://opensource.org/licenses/bsd-license.php\r
10#\r
11# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
12# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
13#\r
14#**/\r
15\r
16[Defines]\r
17 DEC_SPECIFICATION = 0x00010005\r
18 PACKAGE_NAME = ArmPlatformPkg\r
19 PACKAGE_GUID = 3308e0a0-1d94-11e0-915c-0002a5d5c51b\r
20 PACKAGE_VERSION = 0.1\r
21\r
22################################################################################\r
23#\r
24# Include Section - list of Include Paths that are provided by this package.\r
25# Comments are used for Keywords and Module Types.\r
26#\r
27# Supported Module Types:\r
28# BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION\r
29#\r
30################################################################################\r
31[Includes.common]\r
32 Include # Root include for the package\r
33\r
34[Guids.common]\r
35 gArmPlatformTokenSpaceGuid = { 0x9c0aaed4, 0x74c5, 0x4043, { 0xb4, 0x17, 0xa3, 0x22, 0x38, 0x14, 0xce, 0x76 } }\r
36 #\r
37 # Following Guid must match FILE_GUID in MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf\r
38 #\r
39 gVariableRuntimeDxeFileGuid = { 0xcbd2e4d5, 0x7068, 0x4ff5, { 0xb4, 0x62, 0x98, 0x22, 0xb4, 0xad, 0x8d, 0x60 } }\r
40\r
41 gArmBootMonFsFileInfoGuid = { 0x41e26b9c, 0xada6, 0x45b3, { 0x80, 0x8e, 0x23, 0x57, 0xa3, 0x5b, 0x60, 0xd6 } }\r
42\r
43[PcdsFeatureFlag.common]\r
44 # Set this PCD to TRUE to map NORFlash at 0x0. FALSE means the DRAM is mapped at 0x0.\r
45 gArmPlatformTokenSpaceGuid.PcdNorFlashRemapping|FALSE|BOOLEAN|0x00000012\r
46\r
47 gArmPlatformTokenSpaceGuid.PcdStandalone|TRUE|BOOLEAN|0x00000001\r
48 gArmPlatformTokenSpaceGuid.PcdSystemMemoryInitializeInSec|FALSE|BOOLEAN|0x00000002\r
49 gArmPlatformTokenSpaceGuid.PcdSendSgiToBringUpSecondaryCores|FALSE|BOOLEAN|0x00000004\r
50\r
51 gArmPlatformTokenSpaceGuid.PcdNorFlashCheckBlockLocked|FALSE|BOOLEAN|0x0000003C\r
52\r
53 # Disable the GOP controller on ExitBootServices(). By default the value is FALSE,\r
54 # we assume the OS will handle the FrameBuffer from the UEFI GOP information.\r
55 gArmPlatformTokenSpaceGuid.PcdGopDisableOnExitBootServices|FALSE|BOOLEAN|0x0000003D\r
56\r
57 # Enable Legacy Linux support in the BDS\r
58 gArmPlatformTokenSpaceGuid.PcdBdsLinuxSupport|TRUE|BOOLEAN|0x0000002E\r
59\r
60[PcdsFixedAtBuild.common]\r
61 gArmPlatformTokenSpaceGuid.PcdCoreCount|1|UINT32|0x00000039\r
62 gArmPlatformTokenSpaceGuid.PcdClusterCount|1|UINT32|0x00000038\r
63\r
64 # Stack for CPU Cores in Secure Mode\r
65 gArmPlatformTokenSpaceGuid.PcdCPUCoresSecStackBase|0|UINT32|0x00000005\r
66 gArmPlatformTokenSpaceGuid.PcdCPUCoreSecPrimaryStackSize|0x10000|UINT32|0x00000036\r
67 gArmPlatformTokenSpaceGuid.PcdCPUCoreSecSecondaryStackSize|0x1000|UINT32|0x00000006\r
68\r
69 # Stack for CPU Cores in Non Secure Mode\r
70 gArmPlatformTokenSpaceGuid.PcdCPUCoresStackBase|0|UINT64|0x00000009\r
71 gArmPlatformTokenSpaceGuid.PcdCPUCorePrimaryStackSize|0x10000|UINT32|0x00000037\r
72 gArmPlatformTokenSpaceGuid.PcdCPUCoreSecondaryStackSize|0x1000|UINT32|0x0000000A\r
73\r
74 # Size of the region used by UEFI in permanent memory (Reserved 128MB by default)\r
75 gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize|0x08000000|UINT32|0x00000015\r
76\r
77 # Boot Monitor FileSystem\r
78 gArmPlatformTokenSpaceGuid.PcdBootMonFsSupportedDevicePaths|L""|VOID*|0x0000003A\r
79\r
80 #\r
81 # ARM Primecells\r
82 #\r
83\r
84 ## SP804 DualTimer\r
85 gArmPlatformTokenSpaceGuid.PcdSP804TimerFrequencyInMHz|1|UINT32|0x0000001D\r
86 gArmPlatformTokenSpaceGuid.PcdSP804TimerPeriodicInterruptNum|0|UINT32|0x0000001E\r
87 gArmPlatformTokenSpaceGuid.PcdSP804TimerPeriodicBase|0|UINT32|0x0000002A\r
88 gArmPlatformTokenSpaceGuid.PcdSP804TimerPerformanceBase|0|UINT32|0x0000002B\r
89 gArmPlatformTokenSpaceGuid.PcdSP804TimerMetronomeBase|0|UINT32|0x0000002C\r
90\r
91 ## SP805 Watchdog\r
92 gArmPlatformTokenSpaceGuid.PcdSP805WatchdogBase|0x0|UINT32|0x00000023\r
93 gArmPlatformTokenSpaceGuid.PcdSP805WatchdogClockFrequencyInHz|32000|UINT32|0x00000021\r
94\r
95 ## PL011 UART\r
96 gArmPlatformTokenSpaceGuid.PL011UartClkInHz|24000000|UINT32|0x0000001F\r
97 gArmPlatformTokenSpaceGuid.PL011UartInteger|0|UINT32|0x00000020\r
98 gArmPlatformTokenSpaceGuid.PL011UartFractional|0|UINT32|0x0000002D\r
99\r
100 ## PL061 GPIO\r
101 gArmPlatformTokenSpaceGuid.PcdPL061GpioBase|0x0|UINT32|0x00000025\r
102\r
103 ## PL111 Lcd & HdLcd\r
104 gArmPlatformTokenSpaceGuid.PcdPL111LcdBase|0x0|UINT32|0x00000026\r
105 gArmPlatformTokenSpaceGuid.PcdArmHdLcdBase|0x0|UINT32|0x00000027\r
106\r
107 ## PL180 MCI\r
108 gArmPlatformTokenSpaceGuid.PcdPL180SysMciRegAddress|0x00000000|UINT32|0x00000028\r
109 gArmPlatformTokenSpaceGuid.PcdPL180MciBaseAddress|0x00000000|UINT32|0x00000029\r
110\r
111 #\r
112 # BDS - Boot Manager\r
113 #\r
114 gArmPlatformTokenSpaceGuid.PcdFirmwareVendor|"ARM Platform"|VOID*|0x00000019\r
115 gArmPlatformTokenSpaceGuid.PcdDefaultBootDescription|L"Default Boot Device"|VOID*|0x0000000C\r
116 gArmPlatformTokenSpaceGuid.PcdDefaultBootDevicePath|L""|VOID*|0x0000000D\r
117 gArmPlatformTokenSpaceGuid.PcdDefaultBootArgument|L""|VOID*|0x000000F\r
118\r
119 gArmPlatformTokenSpaceGuid.PcdDefaultConInPaths|L""|VOID*|0x0000001B\r
120 gArmPlatformTokenSpaceGuid.PcdDefaultConOutPaths|L""|VOID*|0x0000001C\r
121\r
122[PcdsFixedAtBuild.common,PcdsDynamic.common]\r
123 ## PL031 RealTimeClock\r
124 gArmPlatformTokenSpaceGuid.PcdPL031RtcBase|0x0|UINT32|0x00000024\r
125 gArmPlatformTokenSpaceGuid.PcdPL031RtcPpmAccuracy|300000000|UINT32|0x00000022\r
126\r
127 #\r
128 # Inclusive range of allowed PCI buses.\r
129 #\r
130 gArmPlatformTokenSpaceGuid.PcdPciBusMin|0x0|UINT32|0x0000003E\r
131 gArmPlatformTokenSpaceGuid.PcdPciBusMax|0x0|UINT32|0x0000003F\r
132\r
133 #\r
134 # Bases, sizes and translation offsets of IO and MMIO spaces, respectively.\r
135 # Note that "IO" is just another MMIO range that simulates IO space; there\r
136 # are no special instructions to access it.\r
137 #\r
138 # The base addresses PcdPciIoBase, PcdPciMmio32Base and PcdPciMmio64Base are\r
139 # specific to their containing address spaces. In order to get the physical\r
140 # address for the CPU, for a given access, the respective translation value\r
141 # has to be added.\r
142 #\r
143 # The translations always have to be initialized like this, using UINT64:\r
144 #\r
145 # UINT64 IoCpuBase; // mapping target in 64-bit cpu-physical space\r
146 # UINT64 Mmio32CpuBase; // mapping target in 64-bit cpu-physical space\r
147 # UINT64 Mmio64CpuBase; // mapping target in 64-bit cpu-physical space\r
148 #\r
149 # PcdPciIoTranslation = IoCpuBase - PcdPciIoBase;\r
150 # PcdPciMmio32Translation = Mmio32CpuBase - (UINT64)PcdPciMmio32Base;\r
151 # PcdPciMmio64Translation = Mmio64CpuBase - PcdPciMmio64Base;\r
152 #\r
153 # because (a) the target address space (ie. the cpu-physical space) is\r
154 # 64-bit, and (b) the translation values are meant as offsets for *modular*\r
155 # arithmetic.\r
156 #\r
157 # Accordingly, the translation itself needs to be implemented as:\r
158 #\r
159 # UINT64 UntranslatedIoAddress; // input parameter\r
160 # UINT32 UntranslatedMmio32Address; // input parameter\r
161 # UINT64 UntranslatedMmio64Address; // input parameter\r
162 #\r
163 # UINT64 TranslatedIoAddress; // output parameter\r
164 # UINT64 TranslatedMmio32Address; // output parameter\r
165 # UINT64 TranslatedMmio64Address; // output parameter\r
166 #\r
167 # TranslatedIoAddress = UntranslatedIoAddress +\r
168 # PcdPciIoTranslation;\r
169 # TranslatedMmio32Address = (UINT64)UntranslatedMmio32Address +\r
170 # PcdPciMmio32Translation;\r
171 # TranslatedMmio64Address = UntranslatedMmio64Address +\r
172 # PcdPciMmio64Translation;\r
173 #\r
174 # The modular arithmetic performed in UINT64 ensures that the translation\r
175 # works correctly regardless of the relation between IoCpuBase and\r
176 # PcdPciIoBase, Mmio32CpuBase and PcdPciMmio32Base, and Mmio64CpuBase and\r
177 # PcdPciMmio64Base.\r
178 #\r
179 gArmPlatformTokenSpaceGuid.PcdPciIoBase|0x0|UINT64|0x00000040\r
180 gArmPlatformTokenSpaceGuid.PcdPciIoSize|0x0|UINT64|0x00000041\r
181 gArmPlatformTokenSpaceGuid.PcdPciIoTranslation|0x0|UINT64|0x00000042\r
182 gArmPlatformTokenSpaceGuid.PcdPciMmio32Base|0x0|UINT32|0x00000043\r
183 gArmPlatformTokenSpaceGuid.PcdPciMmio32Size|0x0|UINT32|0x00000044\r
184 gArmPlatformTokenSpaceGuid.PcdPciMmio32Translation|0x0|UINT64|0x00000045\r
185 gArmPlatformTokenSpaceGuid.PcdPciMmio64Base|0x0|UINT64|0x00000046\r
186 gArmPlatformTokenSpaceGuid.PcdPciMmio64Size|0x0|UINT64|0x00000047\r
187 gArmPlatformTokenSpaceGuid.PcdPciMmio64Translation|0x0|UINT64|0x00000048\r
188\r
189[PcdsFixedAtBuild.ARM]\r
190 # Stack for CPU Cores in Secure Monitor Mode\r
191 gArmPlatformTokenSpaceGuid.PcdCPUCoresSecMonStackBase|0|UINT32|0x00000007\r
192 gArmPlatformTokenSpaceGuid.PcdCPUCoreSecMonStackSize|0x1000|UINT32|0x00000008\r
193\r
194[PcdsFixedAtBuild.AARCH64]\r
195 # The Secure World is only running in EL3. Only one set of stacks is needed for AArch64.\r
196 # The Secure stacks are described by PcdCPUCoresSecStackBase, PcdCPUCoreSecPrimaryStackSize\r
197 # and PcdCPUCoreSecSecondaryStackSize\r
198 gArmPlatformTokenSpaceGuid.PcdCPUCoresSecMonStackBase|0|UINT32|0x00000007\r
199 gArmPlatformTokenSpaceGuid.PcdCPUCoreSecMonStackSize|0x0|UINT32|0x00000008\r
200\r