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1 | /** @file\r | |
2 | *\r | |
3 | * Copyright (c) 2011, ARM Limited. All rights reserved.\r | |
4 | *\r | |
5 | * This program and the accompanying materials\r | |
6 | * are licensed and made available under the terms and conditions of the BSD License\r | |
7 | * which accompanies this distribution. The full text of the license may be found at\r | |
8 | * http://opensource.org/licenses/bsd-license.php\r | |
9 | *\r | |
10 | * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
11 | * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
12 | *\r | |
13 | **/\r | |
14 | \r | |
15 | #include "PrePi.h"\r | |
16 | \r | |
17 | #include <Library/ArmGicLib.h>\r | |
18 | \r | |
19 | #include <Ppi/ArmMpCoreInfo.h>\r | |
20 | \r | |
21 | EFI_STATUS\r | |
22 | GetPlatformPpi (\r | |
23 | IN EFI_GUID *PpiGuid,\r | |
24 | OUT VOID **Ppi\r | |
25 | )\r | |
26 | {\r | |
27 | UINTN PpiListSize;\r | |
28 | UINTN PpiListCount;\r | |
29 | EFI_PEI_PPI_DESCRIPTOR *PpiList;\r | |
30 | UINTN Index;\r | |
31 | \r | |
32 | PpiListSize = 0;\r | |
33 | ArmPlatformGetPlatformPpiList (&PpiListSize, &PpiList);\r | |
34 | PpiListCount = PpiListSize / sizeof(EFI_PEI_PPI_DESCRIPTOR);\r | |
35 | for (Index = 0; Index < PpiListCount; Index++, PpiList++) {\r | |
36 | if (CompareGuid (PpiList->Guid, PpiGuid) == TRUE) {\r | |
37 | *Ppi = PpiList->Ppi;\r | |
38 | return EFI_SUCCESS;\r | |
39 | }\r | |
40 | }\r | |
41 | \r | |
42 | return EFI_NOT_FOUND;\r | |
43 | }\r | |
44 | \r | |
45 | VOID\r | |
46 | PrimaryMain (\r | |
47 | IN UINTN UefiMemoryBase,\r | |
48 | IN UINTN StacksBase,\r | |
49 | IN UINTN GlobalVariableBase,\r | |
50 | IN UINT64 StartTimeStamp\r | |
51 | )\r | |
52 | {\r | |
53 | // On MP Core Platform we must implement the ARM MP Core Info PPI (gArmMpCoreInfoPpiGuid)\r | |
54 | DEBUG_CODE_BEGIN();\r | |
55 | EFI_STATUS Status;\r | |
56 | ARM_MP_CORE_INFO_PPI *ArmMpCoreInfoPpi;\r | |
57 | \r | |
58 | Status = GetPlatformPpi (&gArmMpCoreInfoPpiGuid, (VOID**)&ArmMpCoreInfoPpi);\r | |
59 | ASSERT_EFI_ERROR (Status);\r | |
60 | DEBUG_CODE_END();\r | |
61 | \r | |
62 | // Enable the GIC Distributor\r | |
63 | ArmGicEnableDistributor(PcdGet32(PcdGicDistributorBase));\r | |
64 | \r | |
65 | // In some cases, the secondary cores are waiting for an SGI from the next stage boot loader toresume their initialization\r | |
66 | if (!FixedPcdGet32(PcdSendSgiToBringUpSecondaryCores)) {\r | |
67 | // Sending SGI to all the Secondary CPU interfaces\r | |
68 | ArmGicSendSgiTo (PcdGet32(PcdGicDistributorBase), ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E);\r | |
69 | }\r | |
70 | \r | |
71 | PrePiMain (UefiMemoryBase, StacksBase, GlobalVariableBase, StartTimeStamp);\r | |
72 | \r | |
73 | // We must never return\r | |
74 | ASSERT(FALSE);\r | |
75 | }\r | |
76 | \r | |
77 | VOID\r | |
78 | SecondaryMain (\r | |
79 | IN UINTN MpId\r | |
80 | )\r | |
81 | {\r | |
82 | EFI_STATUS Status;\r | |
83 | ARM_MP_CORE_INFO_PPI *ArmMpCoreInfoPpi;\r | |
84 | UINTN Index;\r | |
85 | UINTN ArmCoreCount;\r | |
86 | ARM_CORE_INFO *ArmCoreInfoTable;\r | |
87 | UINT32 ClusterId;\r | |
88 | UINT32 CoreId;\r | |
89 | VOID (*SecondaryStart)(VOID);\r | |
90 | UINTN SecondaryEntryAddr;\r | |
91 | \r | |
92 | ClusterId = GET_CLUSTER_ID(MpId);\r | |
93 | CoreId = GET_CORE_ID(MpId);\r | |
94 | \r | |
95 | // On MP Core Platform we must implement the ARM MP Core Info PPI (gArmMpCoreInfoPpiGuid)\r | |
96 | Status = GetPlatformPpi (&gArmMpCoreInfoPpiGuid, (VOID**)&ArmMpCoreInfoPpi);\r | |
97 | ASSERT_EFI_ERROR (Status);\r | |
98 | \r | |
99 | ArmCoreCount = 0;\r | |
100 | Status = ArmMpCoreInfoPpi->GetMpCoreInfo (&ArmCoreCount, &ArmCoreInfoTable);\r | |
101 | ASSERT_EFI_ERROR (Status);\r | |
102 | \r | |
103 | // Find the core in the ArmCoreTable\r | |
104 | for (Index = 0; Index < ArmCoreCount; Index++) {\r | |
105 | if ((ArmCoreInfoTable[Index].ClusterId == ClusterId) && (ArmCoreInfoTable[Index].CoreId == CoreId)) {\r | |
106 | break;\r | |
107 | }\r | |
108 | }\r | |
109 | \r | |
110 | // The ARM Core Info Table must define every core\r | |
111 | ASSERT (Index != ArmCoreCount);\r | |
112 | \r | |
113 | // Clear Secondary cores MailBox\r | |
114 | MmioWrite32 (ArmCoreInfoTable[Index].MailboxClearAddress, ArmCoreInfoTable[Index].MailboxClearValue);\r | |
115 | \r | |
116 | SecondaryEntryAddr = 0;\r | |
117 | while (SecondaryEntryAddr = MmioRead32 (ArmCoreInfoTable[Index].MailboxGetAddress), SecondaryEntryAddr == 0) {\r | |
118 | ArmCallWFI ();\r | |
119 | // Acknowledge the interrupt and send End of Interrupt signal.\r | |
120 | ArmGicAcknowledgeSgiFrom (PcdGet32(PcdGicInterruptInterfaceBase), PRIMARY_CORE_ID);\r | |
121 | }\r | |
122 | \r | |
123 | // Jump to secondary core entry point.\r | |
124 | SecondaryStart = (VOID (*)())SecondaryEntryAddr;\r | |
125 | SecondaryStart();\r | |
126 | \r | |
127 | // The secondaries shouldn't reach here\r | |
128 | ASSERT(FALSE);\r | |
129 | }\r |