UefiCpuPkg: Move AsmRelocateApLoopStart from Mpfuncs.nasm to AmdSev.nasm

[mirror_edk2.git] / ArmPlatformPkg / PrePi / MainMPCore.c

/** @file\r
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  Copyright (c) 2011-2014, ARM Limited. All rights reserved.\r
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  SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
**/\r
\r
#include "PrePi.h"\r
\r
#include <Library/ArmGicLib.h>\r
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#include <Ppi/ArmMpCoreInfo.h>\r
\r
VOID\r
PrimaryMain (\r
  IN  UINTN   UefiMemoryBase,\r
  IN  UINTN   StacksBase,\r
  IN  UINT64  StartTimeStamp\r
  )\r
{\r
  // Enable the GIC Distributor\r
  ArmGicEnableDistributor (PcdGet64 (PcdGicDistributorBase));\r
\r
  // In some cases, the secondary cores are waiting for an SGI from the next stage boot loader to resume their initialization\r
  if (!FixedPcdGet32 (PcdSendSgiToBringUpSecondaryCores)) {\r
    // Sending SGI to all the Secondary CPU interfaces\r
    ArmGicSendSgiTo (PcdGet64 (PcdGicDistributorBase), ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E, PcdGet32 (PcdGicSgiIntId));\r
  }\r
\r
  PrePiMain (UefiMemoryBase, StacksBase, StartTimeStamp);\r
\r
  // We must never return\r
  ASSERT (FALSE);\r
}\r
\r
VOID\r
SecondaryMain (\r
  IN  UINTN  MpId\r
  )\r
{\r
  EFI_STATUS            Status;\r
  ARM_MP_CORE_INFO_PPI  *ArmMpCoreInfoPpi;\r
  UINTN                 Index;\r
  UINTN                 ArmCoreCount;\r
  ARM_CORE_INFO         *ArmCoreInfoTable;\r
  UINT32                ClusterId;\r
  UINT32                CoreId;\r
\r
  VOID  (*SecondaryStart)(\r
    VOID\r
    );\r
  UINTN  SecondaryEntryAddr;\r
  UINTN  AcknowledgeInterrupt;\r
  UINTN  InterruptId;\r
\r
  ClusterId = GET_CLUSTER_ID (MpId);\r
  CoreId    = GET_CORE_ID (MpId);\r
\r
  // On MP Core Platform we must implement the ARM MP Core Info PPI (gArmMpCoreInfoPpiGuid)\r
  Status = GetPlatformPpi (&gArmMpCoreInfoPpiGuid, (VOID **)&ArmMpCoreInfoPpi);\r
  ASSERT_EFI_ERROR (Status);\r
\r
  ArmCoreCount = 0;\r
  Status       = ArmMpCoreInfoPpi->GetMpCoreInfo (&ArmCoreCount, &ArmCoreInfoTable);\r
  ASSERT_EFI_ERROR (Status);\r
\r
  // Find the core in the ArmCoreTable\r
  for (Index = 0; Index < ArmCoreCount; Index++) {\r
    if ((GET_MPIDR_AFF1 (ArmCoreInfoTable[Index].Mpidr) == ClusterId) &&\r
        (GET_MPIDR_AFF0 (ArmCoreInfoTable[Index].Mpidr) == CoreId))\r
    {\r
      break;\r
    }\r
  }\r
\r
  // The ARM Core Info Table must define every core\r
  ASSERT (Index != ArmCoreCount);\r
\r
  // Clear Secondary cores MailBox\r
  MmioWrite32 (ArmCoreInfoTable[Index].MailboxClearAddress, ArmCoreInfoTable[Index].MailboxClearValue);\r
\r
  do {\r
    ArmCallWFI ();\r
\r
    // Read the Mailbox\r
    SecondaryEntryAddr = MmioRead32 (ArmCoreInfoTable[Index].MailboxGetAddress);\r
\r
    // Acknowledge the interrupt and send End of Interrupt signal.\r
    AcknowledgeInterrupt = ArmGicAcknowledgeInterrupt (PcdGet64 (PcdGicInterruptInterfaceBase), &InterruptId);\r
    // Check if it is a valid interrupt ID\r
    if (InterruptId < ArmGicGetMaxNumInterrupts (PcdGet64 (PcdGicDistributorBase))) {\r
      // Got a valid SGI number hence signal End of Interrupt\r
      ArmGicEndOfInterrupt (PcdGet64 (PcdGicInterruptInterfaceBase), AcknowledgeInterrupt);\r
    }\r
  } while (SecondaryEntryAddr == 0);\r
\r
  // Jump to secondary core entry point.\r
  SecondaryStart = (VOID (*)()) SecondaryEntryAddr;\r
  SecondaryStart ();\r
\r
  // The secondaries shouldn't reach here\r
  ASSERT (FALSE);\r
}\r