]>
Commit | Line | Data |
---|---|---|
1 | /** @file | |
2 | * Main file supporting the SEC Phase on ARM Platforms | |
3 | * | |
4 | * Copyright (c) 2011-2012, ARM Limited. All rights reserved. | |
5 | * | |
6 | * This program and the accompanying materials | |
7 | * are licensed and made available under the terms and conditions of the BSD License | |
8 | * which accompanies this distribution. The full text of the license may be found at | |
9 | * http://opensource.org/licenses/bsd-license.php | |
10 | * | |
11 | * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, | |
12 | * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. | |
13 | * | |
14 | **/ | |
15 | ||
16 | #include <Library/ArmTrustedMonitorLib.h> | |
17 | #include <Library/DebugAgentLib.h> | |
18 | #include <Library/PrintLib.h> | |
19 | #include <Library/BaseMemoryLib.h> | |
20 | #include <Library/SerialPortLib.h> | |
21 | #include <Library/ArmGicLib.h> | |
22 | #include <Library/ArmCpuLib.h> | |
23 | ||
24 | #include "SecInternal.h" | |
25 | ||
26 | #define SerialPrint(txt) SerialPortWrite ((UINT8*)txt, AsciiStrLen(txt)+1); | |
27 | ||
28 | VOID | |
29 | CEntryPoint ( | |
30 | IN UINTN MpId | |
31 | ) | |
32 | { | |
33 | CHAR8 Buffer[100]; | |
34 | UINTN CharCount; | |
35 | UINTN JumpAddress; | |
36 | ||
37 | // Invalidate the data cache. Doesn't have to do the Data cache clean. | |
38 | ArmInvalidateDataCache(); | |
39 | ||
40 | // Invalidate Instruction Cache | |
41 | ArmInvalidateInstructionCache(); | |
42 | ||
43 | // Invalidate I & D TLBs | |
44 | ArmInvalidateInstructionAndDataTlb(); | |
45 | ||
46 | // CPU specific settings | |
47 | ArmCpuSetup (MpId); | |
48 | ||
49 | // Enable Floating Point Coprocessor if supported by the platform | |
50 | if (FixedPcdGet32 (PcdVFPEnabled)) { | |
51 | ArmEnableVFP(); | |
52 | } | |
53 | ||
54 | // Primary CPU clears out the SCU tag RAMs, secondaries wait | |
55 | if (IS_PRIMARY_CORE(MpId)) { | |
56 | if (ArmIsMpCore()) { | |
57 | ArmCpuSynchronizeSignal (ARM_CPU_EVENT_BOOT_MEM_INIT); | |
58 | } | |
59 | ||
60 | // SEC phase needs to run library constructors by hand. This assumes we are linked against the SerialLib | |
61 | // In non SEC modules the init call is in autogenerated code. | |
62 | SerialPortInitialize (); | |
63 | ||
64 | // Start talking | |
65 | CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"UEFI firmware built at %a on %a\n\r",__TIME__, __DATE__); | |
66 | SerialPortWrite ((UINT8 *) Buffer, CharCount); | |
67 | ||
68 | // Initialize the Debug Agent for Source Level Debugging | |
69 | InitializeDebugAgent (DEBUG_AGENT_INIT_PREMEM_SEC, NULL, NULL); | |
70 | SaveAndSetDebugTimerInterrupt (TRUE); | |
71 | ||
72 | // Now we've got UART, make the check: | |
73 | // - The Vector table must be 32-byte aligned | |
74 | ASSERT(((UINT32)SecVectorTable & ((1 << 5)-1)) == 0); | |
75 | ||
76 | // Enable the GIC distributor and CPU Interface | |
77 | // - no other Interrupts are enabled, doesn't have to worry about the priority. | |
78 | // - all the cores are in secure state, use secure SGI's | |
79 | ArmGicEnableDistributor (PcdGet32(PcdGicDistributorBase)); | |
80 | ArmGicEnableInterruptInterface (PcdGet32(PcdGicInterruptInterfaceBase)); | |
81 | } else { | |
82 | // Enable the GIC CPU Interface | |
83 | ArmGicEnableInterruptInterface (PcdGet32(PcdGicInterruptInterfaceBase)); | |
84 | } | |
85 | ||
86 | // Enable Full Access to CoProcessors | |
87 | ArmWriteCPACR (CPACR_CP_FULL_ACCESS); | |
88 | ||
89 | if (IS_PRIMARY_CORE(MpId)) { | |
90 | // Initialize peripherals that must be done at the early stage | |
91 | // Example: Some L2x0 controllers must be initialized in Secure World | |
92 | ArmPlatformSecInitialize (); | |
93 | ||
94 | // If we skip the PEI Core we could want to initialize the DRAM in the SEC phase. | |
95 | // If we are in standalone, we need the initialization to copy the UEFI firmware into DRAM | |
96 | if (FeaturePcdGet (PcdSystemMemoryInitializeInSec)) { | |
97 | // Initialize system memory (DRAM) | |
98 | ArmPlatformInitializeSystemMemory (); | |
99 | } | |
100 | } | |
101 | ||
102 | // Test if Trustzone is supported on this platform | |
103 | if (FixedPcdGetBool (PcdTrustzoneSupport)) { | |
104 | if (ArmIsMpCore()) { | |
105 | // Setup SMP in Non Secure world | |
106 | ArmCpuSetupSmpNonSecure (GET_CORE_ID(MpId)); | |
107 | } | |
108 | ||
109 | // Enter Monitor Mode | |
110 | enter_monitor_mode ((UINTN)TrustedWorldInitialization, MpId, (VOID*)(PcdGet32(PcdCPUCoresSecMonStackBase) + (PcdGet32(PcdCPUCoreSecMonStackSize) * (GET_CORE_POS(MpId) + 1)))); | |
111 | } else { | |
112 | if (IS_PRIMARY_CORE(MpId)) { | |
113 | SerialPrint ("Trust Zone Configuration is disabled\n\r"); | |
114 | } | |
115 | ||
116 | // With Trustzone support the transition from Sec to Normal world is done by return_from_exception(). | |
117 | // If we want to keep this function call we need to ensure the SVC's SPSR point to the same Program | |
118 | // Status Register as the the current one (CPSR). | |
119 | copy_cpsr_into_spsr (); | |
120 | ||
121 | // Call the Platform specific function to execute additional actions if required | |
122 | JumpAddress = PcdGet32 (PcdFvBaseAddress); | |
123 | ArmPlatformSecExtraAction (MpId, &JumpAddress); | |
124 | ||
125 | NonTrustedWorldTransition (MpId, JumpAddress); | |
126 | } | |
127 | ASSERT (0); // We must never return from the above function | |
128 | } | |
129 | ||
130 | VOID | |
131 | TrustedWorldInitialization ( | |
132 | IN UINTN MpId | |
133 | ) | |
134 | { | |
135 | UINTN JumpAddress; | |
136 | ||
137 | //-------------------- Monitor Mode --------------------- | |
138 | ||
139 | // Set up Monitor World (Vector Table, etc) | |
140 | ArmSecureMonitorWorldInitialize (); | |
141 | ||
142 | // Setup the Trustzone Chipsets | |
143 | if (IS_PRIMARY_CORE(MpId)) { | |
144 | ArmPlatformTrustzoneInit (); | |
145 | ||
146 | if (ArmIsMpCore()) { | |
147 | // Waiting for the Primary Core to have finished to initialize the Secure World | |
148 | ArmCpuSynchronizeSignal (ARM_CPU_EVENT_SECURE_INIT); | |
149 | } | |
150 | } else { | |
151 | // The secondary cores need to wait until the Trustzone chipsets configuration is done | |
152 | // before switching to Non Secure World | |
153 | ||
154 | // Waiting for the Primary Core to have finished to initialize the Secure World | |
155 | ArmCpuSynchronizeWait (ARM_CPU_EVENT_SECURE_INIT); | |
156 | } | |
157 | ||
158 | // Transfer the interrupt to Non-secure World | |
159 | ArmGicSetupNonSecure (PcdGet32(PcdGicDistributorBase), PcdGet32(PcdGicInterruptInterfaceBase)); | |
160 | ||
161 | // Call the Platform specific fucntion to execute additional actions if required | |
162 | JumpAddress = PcdGet32 (PcdFvBaseAddress); | |
163 | ArmPlatformSecExtraAction (MpId, &JumpAddress); | |
164 | ||
165 | // Write to CP15 Non-secure Access Control Register | |
166 | ArmWriteNsacr (PcdGet32 (PcdArmNsacr)); | |
167 | ||
168 | // CP15 Secure Configuration Register | |
169 | ArmWriteScr (PcdGet32 (PcdArmScr)); | |
170 | ||
171 | NonTrustedWorldTransition (MpId, JumpAddress); | |
172 | } | |
173 | ||
174 | VOID | |
175 | NonTrustedWorldTransition ( | |
176 | IN UINTN MpId, | |
177 | IN UINTN JumpAddress | |
178 | ) | |
179 | { | |
180 | // If PcdArmNonSecModeTransition is defined then set this specific mode to CPSR before the transition | |
181 | // By not set, the mode for Non Secure World is SVC | |
182 | if (PcdGet32 (PcdArmNonSecModeTransition) != 0) { | |
183 | set_non_secure_mode ((ARM_PROCESSOR_MODE)PcdGet32 (PcdArmNonSecModeTransition)); | |
184 | } | |
185 | ||
186 | return_from_exception (JumpAddress); | |
187 | //-------------------- Non Secure Mode --------------------- | |
188 | ||
189 | // PEI Core should always load and never return | |
190 | ASSERT (FALSE); | |
191 | } | |
192 | ||
193 | VOID | |
194 | SecCommonExceptionEntry ( | |
195 | IN UINT32 Entry, | |
196 | IN UINT32 LR | |
197 | ) | |
198 | { | |
199 | CHAR8 Buffer[100]; | |
200 | UINTN CharCount; | |
201 | ||
202 | switch (Entry) { | |
203 | case 0: | |
204 | CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"Reset Exception at 0x%X\n\r",LR); | |
205 | break; | |
206 | case 1: | |
207 | CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"Undefined Exception at 0x%X\n\r",LR); | |
208 | break; | |
209 | case 2: | |
210 | CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"SWI Exception at 0x%X\n\r",LR); | |
211 | break; | |
212 | case 3: | |
213 | CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"PrefetchAbort Exception at 0x%X\n\r",LR); | |
214 | break; | |
215 | case 4: | |
216 | CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"DataAbort Exception at 0x%X\n\r",LR); | |
217 | break; | |
218 | case 5: | |
219 | CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"Reserved Exception at 0x%X\n\r",LR); | |
220 | break; | |
221 | case 6: | |
222 | CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"IRQ Exception at 0x%X\n\r",LR); | |
223 | break; | |
224 | case 7: | |
225 | CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"FIQ Exception at 0x%X\n\r",LR); | |
226 | break; | |
227 | default: | |
228 | CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"Unknown Exception at 0x%X\n\r",LR); | |
229 | break; | |
230 | } | |
231 | SerialPortWrite ((UINT8 *) Buffer, CharCount); | |
232 | while(1); | |
233 | } |