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1 | /** @file\r | |
2 | Private Header file for Usb Host Controller PEIM\r | |
3 | \r | |
4 | Copyright (c) 2010 - 2018, Intel Corporation. All rights reserved.<BR>\r | |
5 | Copyright (c) Microsoft Corporation.<BR>\r | |
6 | \r | |
7 | SPDX-License-Identifier: BSD-2-Clause-Patent\r | |
8 | \r | |
9 | **/\r | |
10 | \r | |
11 | #ifndef _RECOVERY_EHC_H_\r | |
12 | #define _RECOVERY_EHC_H_\r | |
13 | \r | |
14 | #include <PiPei.h>\r | |
15 | \r | |
16 | #include <Ppi/UsbController.h>\r | |
17 | #include <Ppi/Usb2HostController.h>\r | |
18 | #include <Ppi/IoMmu.h>\r | |
19 | #include <Ppi/EndOfPeiPhase.h>\r | |
20 | \r | |
21 | #include <Library/BaseLib.h>\r | |
22 | #include <Library/DebugLib.h>\r | |
23 | #include <Library/PeimEntryPoint.h>\r | |
24 | #include <Library/PeiServicesLib.h>\r | |
25 | #include <Library/BaseMemoryLib.h>\r | |
26 | #include <Library/TimerLib.h>\r | |
27 | #include <Library/IoLib.h>\r | |
28 | \r | |
29 | typedef struct _PEI_USB2_HC_DEV PEI_USB2_HC_DEV;\r | |
30 | \r | |
31 | #define EFI_LIST_ENTRY LIST_ENTRY\r | |
32 | \r | |
33 | #include "UsbHcMem.h"\r | |
34 | #include "EhciReg.h"\r | |
35 | #include "EhciUrb.h"\r | |
36 | #include "EhciSched.h"\r | |
37 | \r | |
38 | #define EFI_USB_SPEED_FULL 0x0000\r | |
39 | #define EFI_USB_SPEED_LOW 0x0001\r | |
40 | #define EFI_USB_SPEED_HIGH 0x0002\r | |
41 | \r | |
42 | #define PAGESIZE 4096\r | |
43 | \r | |
44 | #define EHC_1_MICROSECOND 1\r | |
45 | #define EHC_1_MILLISECOND (1000 * EHC_1_MICROSECOND)\r | |
46 | #define EHC_1_SECOND (1000 * EHC_1_MILLISECOND)\r | |
47 | \r | |
48 | //\r | |
49 | // EHCI register operation timeout, set by experience\r | |
50 | //\r | |
51 | #define EHC_RESET_TIMEOUT (1 * EHC_1_SECOND)\r | |
52 | #define EHC_GENERIC_TIMEOUT (10 * EHC_1_MILLISECOND)\r | |
53 | \r | |
54 | //\r | |
55 | // Wait for roothub port power stable, refers to Spec[EHCI1.0-2.3.9]\r | |
56 | //\r | |
57 | #define EHC_ROOT_PORT_RECOVERY_STALL (20 * EHC_1_MILLISECOND)\r | |
58 | \r | |
59 | //\r | |
60 | // Sync transfer polling interval, set by experience.\r | |
61 | //\r | |
62 | #define EHC_SYNC_POLL_INTERVAL (6 * EHC_1_MILLISECOND)\r | |
63 | \r | |
64 | #define EFI_LIST_CONTAINER(Entry, Type, Field) BASE_CR(Entry, Type, Field)\r | |
65 | \r | |
66 | #define EHC_LOW_32BIT(Addr64) ((UINT32)(((UINTN)(Addr64)) & 0XFFFFFFFF))\r | |
67 | #define EHC_HIGH_32BIT(Addr64) ((UINT32)(RShiftU64((UINTN)(Addr64), 32) & 0XFFFFFFFF))\r | |
68 | #define EHC_BIT_IS_SET(Data, Bit) ((BOOLEAN)(((Data) & (Bit)) == (Bit)))\r | |
69 | \r | |
70 | #define EHC_REG_BIT_IS_SET(Ehc, Offset, Bit) \\r | |
71 | (EHC_BIT_IS_SET(EhcReadOpReg ((Ehc), (Offset)), (Bit)))\r | |
72 | \r | |
73 | #define USB2_HC_DEV_SIGNATURE SIGNATURE_32 ('e', 'h', 'c', 'i')\r | |
74 | \r | |
75 | struct _PEI_USB2_HC_DEV {\r | |
76 | UINTN Signature;\r | |
77 | PEI_USB2_HOST_CONTROLLER_PPI Usb2HostControllerPpi;\r | |
78 | EDKII_IOMMU_PPI *IoMmu;\r | |
79 | EFI_PEI_PPI_DESCRIPTOR PpiDescriptor;\r | |
80 | //\r | |
81 | // EndOfPei callback is used to stop the EHC DMA operation\r | |
82 | // after exit PEI phase.\r | |
83 | //\r | |
84 | EFI_PEI_NOTIFY_DESCRIPTOR EndOfPeiNotifyList;\r | |
85 | UINT32 UsbHostControllerBaseAddress;\r | |
86 | PEI_URB *Urb;\r | |
87 | USBHC_MEM_POOL *MemPool;\r | |
88 | \r | |
89 | //\r | |
90 | // Schedule data shared between asynchronous and periodic\r | |
91 | // transfers:\r | |
92 | // ShortReadStop, as its name indicates, is used to terminate\r | |
93 | // the short read except the control transfer. EHCI follows\r | |
94 | // the alternative next QTD point when a short read happens.\r | |
95 | // For control transfer, even the short read happens, try the\r | |
96 | // status stage.\r | |
97 | //\r | |
98 | PEI_EHC_QTD *ShortReadStop;\r | |
99 | EFI_EVENT PollTimer;\r | |
100 | \r | |
101 | //\r | |
102 | // Asynchronous(bulk and control) transfer schedule data:\r | |
103 | // ReclaimHead is used as the head of the asynchronous transfer\r | |
104 | // list. It acts as the reclamation header.\r | |
105 | //\r | |
106 | PEI_EHC_QH *ReclaimHead;\r | |
107 | \r | |
108 | //\r | |
109 | // Periodic (interrupt) transfer schedule data:\r | |
110 | //\r | |
111 | VOID *PeriodFrame; // Mapped as common buffer\r | |
112 | VOID *PeriodFrameMap;\r | |
113 | \r | |
114 | PEI_EHC_QH *PeriodOne;\r | |
115 | EFI_LIST_ENTRY AsyncIntTransfers;\r | |
116 | \r | |
117 | //\r | |
118 | // EHCI configuration data\r | |
119 | //\r | |
120 | UINT32 HcStructParams; // Cache of HC structure parameter, EHC_HCSPARAMS_OFFSET\r | |
121 | UINT32 HcCapParams; // Cache of HC capability parameter, HCCPARAMS\r | |
122 | UINT32 CapLen; // Capability length\r | |
123 | UINT32 High32bitAddr;\r | |
124 | };\r | |
125 | \r | |
126 | #define PEI_RECOVERY_USB_EHC_DEV_FROM_EHCI_THIS(a) CR (a, PEI_USB2_HC_DEV, Usb2HostControllerPpi, USB2_HC_DEV_SIGNATURE)\r | |
127 | #define PEI_RECOVERY_USB_EHC_DEV_FROM_THIS_NOTIFY(a) CR (a, PEI_USB2_HC_DEV, EndOfPeiNotifyList, USB2_HC_DEV_SIGNATURE)\r | |
128 | \r | |
129 | /**\r | |
130 | @param EhcDev EHCI Device.\r | |
131 | \r | |
132 | @retval EFI_SUCCESS EHCI successfully initialized.\r | |
133 | @retval EFI_ABORTED EHCI was failed to be initialized.\r | |
134 | \r | |
135 | **/\r | |
136 | EFI_STATUS\r | |
137 | InitializeUsbHC (\r | |
138 | IN PEI_USB2_HC_DEV *EhcDev\r | |
139 | );\r | |
140 | \r | |
141 | /**\r | |
142 | Initialize the memory management pool for the host controller.\r | |
143 | \r | |
144 | @param Ehc The EHCI device.\r | |
145 | @param Check4G Whether the host controller requires allocated memory\r | |
146 | from one 4G address space.\r | |
147 | @param Which4G The 4G memory area each memory allocated should be from.\r | |
148 | \r | |
149 | @retval EFI_SUCCESS The memory pool is initialized.\r | |
150 | @retval EFI_OUT_OF_RESOURCE Fail to init the memory pool.\r | |
151 | \r | |
152 | **/\r | |
153 | USBHC_MEM_POOL *\r | |
154 | UsbHcInitMemPool (\r | |
155 | IN PEI_USB2_HC_DEV *Ehc,\r | |
156 | IN BOOLEAN Check4G,\r | |
157 | IN UINT32 Which4G\r | |
158 | )\r | |
159 | ;\r | |
160 | \r | |
161 | /**\r | |
162 | Release the memory management pool.\r | |
163 | \r | |
164 | @param Ehc The EHCI device.\r | |
165 | @param Pool The USB memory pool to free.\r | |
166 | \r | |
167 | @retval EFI_DEVICE_ERROR Fail to free the memory pool.\r | |
168 | @retval EFI_SUCCESS The memory pool is freed.\r | |
169 | \r | |
170 | **/\r | |
171 | EFI_STATUS\r | |
172 | UsbHcFreeMemPool (\r | |
173 | IN PEI_USB2_HC_DEV *Ehc,\r | |
174 | IN USBHC_MEM_POOL *Pool\r | |
175 | )\r | |
176 | ;\r | |
177 | \r | |
178 | /**\r | |
179 | Allocate some memory from the host controller's memory pool\r | |
180 | which can be used to communicate with host controller.\r | |
181 | \r | |
182 | @param Ehc The EHCI device.\r | |
183 | @param Pool The host controller's memory pool.\r | |
184 | @param Size Size of the memory to allocate.\r | |
185 | \r | |
186 | @return The allocated memory or NULL.\r | |
187 | \r | |
188 | **/\r | |
189 | VOID *\r | |
190 | UsbHcAllocateMem (\r | |
191 | IN PEI_USB2_HC_DEV *Ehc,\r | |
192 | IN USBHC_MEM_POOL *Pool,\r | |
193 | IN UINTN Size\r | |
194 | )\r | |
195 | ;\r | |
196 | \r | |
197 | /**\r | |
198 | Free the allocated memory back to the memory pool.\r | |
199 | \r | |
200 | @param Ehc The EHCI device.\r | |
201 | @param Pool The memory pool of the host controller.\r | |
202 | @param Mem The memory to free.\r | |
203 | @param Size The size of the memory to free.\r | |
204 | \r | |
205 | **/\r | |
206 | VOID\r | |
207 | UsbHcFreeMem (\r | |
208 | IN PEI_USB2_HC_DEV *Ehc,\r | |
209 | IN USBHC_MEM_POOL *Pool,\r | |
210 | IN VOID *Mem,\r | |
211 | IN UINTN Size\r | |
212 | )\r | |
213 | ;\r | |
214 | \r | |
215 | /**\r | |
216 | Provides the controller-specific addresses required to access system memory from a\r | |
217 | DMA bus master.\r | |
218 | \r | |
219 | @param IoMmu Pointer to IOMMU PPI.\r | |
220 | @param Operation Indicates if the bus master is going to read or write to system memory.\r | |
221 | @param HostAddress The system memory address to map to the PCI controller.\r | |
222 | @param NumberOfBytes On input the number of bytes to map. On output the number of bytes\r | |
223 | that were mapped.\r | |
224 | @param DeviceAddress The resulting map address for the bus master PCI controller to use to\r | |
225 | access the hosts HostAddress.\r | |
226 | @param Mapping A resulting value to pass to Unmap().\r | |
227 | \r | |
228 | @retval EFI_SUCCESS The range was mapped for the returned NumberOfBytes.\r | |
229 | @retval EFI_UNSUPPORTED The HostAddress cannot be mapped as a common buffer.\r | |
230 | @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r | |
231 | @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r | |
232 | @retval EFI_DEVICE_ERROR The system hardware could not map the requested address.\r | |
233 | \r | |
234 | **/\r | |
235 | EFI_STATUS\r | |
236 | IoMmuMap (\r | |
237 | IN EDKII_IOMMU_PPI *IoMmu,\r | |
238 | IN EDKII_IOMMU_OPERATION Operation,\r | |
239 | IN VOID *HostAddress,\r | |
240 | IN OUT UINTN *NumberOfBytes,\r | |
241 | OUT EFI_PHYSICAL_ADDRESS *DeviceAddress,\r | |
242 | OUT VOID **Mapping\r | |
243 | );\r | |
244 | \r | |
245 | /**\r | |
246 | Completes the Map() operation and releases any corresponding resources.\r | |
247 | \r | |
248 | @param IoMmu Pointer to IOMMU PPI.\r | |
249 | @param Mapping The mapping value returned from Map().\r | |
250 | \r | |
251 | **/\r | |
252 | VOID\r | |
253 | IoMmuUnmap (\r | |
254 | IN EDKII_IOMMU_PPI *IoMmu,\r | |
255 | IN VOID *Mapping\r | |
256 | );\r | |
257 | \r | |
258 | /**\r | |
259 | Allocates pages that are suitable for an OperationBusMasterCommonBuffer or\r | |
260 | OperationBusMasterCommonBuffer64 mapping.\r | |
261 | \r | |
262 | @param IoMmu Pointer to IOMMU PPI.\r | |
263 | @param Pages The number of pages to allocate.\r | |
264 | @param HostAddress A pointer to store the base system memory address of the\r | |
265 | allocated range.\r | |
266 | @param DeviceAddress The resulting map address for the bus master PCI controller to use to\r | |
267 | access the hosts HostAddress.\r | |
268 | @param Mapping A resulting value to pass to Unmap().\r | |
269 | \r | |
270 | @retval EFI_SUCCESS The requested memory pages were allocated.\r | |
271 | @retval EFI_UNSUPPORTED Attributes is unsupported. The only legal attribute bits are\r | |
272 | MEMORY_WRITE_COMBINE and MEMORY_CACHED.\r | |
273 | @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r | |
274 | @retval EFI_OUT_OF_RESOURCES The memory pages could not be allocated.\r | |
275 | \r | |
276 | **/\r | |
277 | EFI_STATUS\r | |
278 | IoMmuAllocateBuffer (\r | |
279 | IN EDKII_IOMMU_PPI *IoMmu,\r | |
280 | IN UINTN Pages,\r | |
281 | OUT VOID **HostAddress,\r | |
282 | OUT EFI_PHYSICAL_ADDRESS *DeviceAddress,\r | |
283 | OUT VOID **Mapping\r | |
284 | );\r | |
285 | \r | |
286 | /**\r | |
287 | Frees memory that was allocated with AllocateBuffer().\r | |
288 | \r | |
289 | @param IoMmu Pointer to IOMMU PPI.\r | |
290 | @param Pages The number of pages to free.\r | |
291 | @param HostAddress The base system memory address of the allocated range.\r | |
292 | @param Mapping The mapping value returned from Map().\r | |
293 | \r | |
294 | **/\r | |
295 | VOID\r | |
296 | IoMmuFreeBuffer (\r | |
297 | IN EDKII_IOMMU_PPI *IoMmu,\r | |
298 | IN UINTN Pages,\r | |
299 | IN VOID *HostAddress,\r | |
300 | IN VOID *Mapping\r | |
301 | );\r | |
302 | \r | |
303 | /**\r | |
304 | Initialize IOMMU.\r | |
305 | \r | |
306 | @param IoMmu Pointer to pointer to IOMMU PPI.\r | |
307 | \r | |
308 | **/\r | |
309 | VOID\r | |
310 | IoMmuInit (\r | |
311 | OUT EDKII_IOMMU_PPI **IoMmu\r | |
312 | );\r | |
313 | \r | |
314 | #endif\r |