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[mirror_edk2.git] / MdeModulePkg / Bus / Pci / PciBusDxe / PciIo.c
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1/** @file\r
2 EFI PCI IO protocol functions implementation for PCI Bus module.\r
3\r
4Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR>\r
5SPDX-License-Identifier: BSD-2-Clause-Patent\r
6\r
7**/\r
8\r
9#include "PciBus.h"\r
10\r
11extern EDKII_IOMMU_PROTOCOL *mIoMmuProtocol;\r
12\r
13//\r
14// Pci Io Protocol Interface\r
15//\r
16EFI_PCI_IO_PROTOCOL mPciIoInterface = {\r
17 PciIoPollMem,\r
18 PciIoPollIo,\r
19 {\r
20 PciIoMemRead,\r
21 PciIoMemWrite\r
22 },\r
23 {\r
24 PciIoIoRead,\r
25 PciIoIoWrite\r
26 },\r
27 {\r
28 PciIoConfigRead,\r
29 PciIoConfigWrite\r
30 },\r
31 PciIoCopyMem,\r
32 PciIoMap,\r
33 PciIoUnmap,\r
34 PciIoAllocateBuffer,\r
35 PciIoFreeBuffer,\r
36 PciIoFlush,\r
37 PciIoGetLocation,\r
38 PciIoAttributes,\r
39 PciIoGetBarAttributes,\r
40 PciIoSetBarAttributes,\r
41 0,\r
42 NULL\r
43};\r
44\r
45/**\r
46 Initializes a PCI I/O Instance.\r
47\r
48 @param PciIoDevice Pci device instance.\r
49\r
50**/\r
51VOID\r
52InitializePciIoInstance (\r
53 IN PCI_IO_DEVICE *PciIoDevice\r
54 )\r
55{\r
56 CopyMem (&PciIoDevice->PciIo, &mPciIoInterface, sizeof (EFI_PCI_IO_PROTOCOL));\r
57}\r
58\r
59/**\r
60 Verifies access to a PCI Base Address Register (BAR).\r
61\r
62 @param PciIoDevice Pci device instance.\r
63 @param BarIndex The BAR index of the standard PCI Configuration header to use as the\r
64 base address for the memory or I/O operation to perform.\r
65 @param Type Operation type could be memory or I/O.\r
66 @param Width Signifies the width of the memory or I/O operations.\r
67 @param Count The number of memory or I/O operations to perform.\r
68 @param Offset The offset within the PCI configuration space for the PCI controller.\r
69\r
70 @retval EFI_INVALID_PARAMETER Invalid Width/BarIndex or Bar type.\r
71 @retval EFI_SUCCESS Successfully verified.\r
72\r
73**/\r
74EFI_STATUS\r
75PciIoVerifyBarAccess (\r
76 IN PCI_IO_DEVICE *PciIoDevice,\r
77 IN UINT8 BarIndex,\r
78 IN PCI_BAR_TYPE Type,\r
79 IN IN EFI_PCI_IO_PROTOCOL_WIDTH Width,\r
80 IN IN UINTN Count,\r
81 IN UINT64 *Offset\r
82 )\r
83{\r
84 if ((UINT32)Width >= EfiPciIoWidthMaximum) {\r
85 return EFI_INVALID_PARAMETER;\r
86 }\r
87\r
88 if (BarIndex == EFI_PCI_IO_PASS_THROUGH_BAR) {\r
89 return EFI_SUCCESS;\r
90 }\r
91\r
92 //\r
93 // BarIndex 0-5 is legal\r
94 //\r
95 if (BarIndex >= PCI_MAX_BAR) {\r
96 return EFI_INVALID_PARAMETER;\r
97 }\r
98\r
99 if (!CheckBarType (PciIoDevice, BarIndex, Type)) {\r
100 return EFI_INVALID_PARAMETER;\r
101 }\r
102\r
103 //\r
104 // If Width is EfiPciIoWidthFifoUintX then convert to EfiPciIoWidthUintX\r
105 // If Width is EfiPciIoWidthFillUintX then convert to EfiPciIoWidthUintX\r
106 //\r
107 if ((Width >= EfiPciIoWidthFifoUint8) && (Width <= EfiPciIoWidthFifoUint64)) {\r
108 Count = 1;\r
109 }\r
110\r
111 Width = (EFI_PCI_IO_PROTOCOL_WIDTH)(Width & 0x03);\r
112\r
113 if ((*Offset + Count * (UINTN)(1 << Width)) - 1 >= PciIoDevice->PciBar[BarIndex].Length) {\r
114 return EFI_INVALID_PARAMETER;\r
115 }\r
116\r
117 *Offset = *Offset + PciIoDevice->PciBar[BarIndex].BaseAddress;\r
118\r
119 return EFI_SUCCESS;\r
120}\r
121\r
122/**\r
123 Verifies access to a PCI Configuration Header.\r
124\r
125 @param PciIoDevice Pci device instance.\r
126 @param Width Signifies the width of the memory or I/O operations.\r
127 @param Count The number of memory or I/O operations to perform.\r
128 @param Offset The offset within the PCI configuration space for the PCI controller.\r
129\r
130 @retval EFI_INVALID_PARAMETER Invalid Width\r
131 @retval EFI_UNSUPPORTED Offset overflowed.\r
132 @retval EFI_SUCCESS Successfully verified.\r
133\r
134**/\r
135EFI_STATUS\r
136PciIoVerifyConfigAccess (\r
137 IN PCI_IO_DEVICE *PciIoDevice,\r
138 IN EFI_PCI_IO_PROTOCOL_WIDTH Width,\r
139 IN UINTN Count,\r
140 IN UINT64 *Offset\r
141 )\r
142{\r
143 UINT64 ExtendOffset;\r
144\r
145 if ((UINT32)Width >= EfiPciIoWidthMaximum) {\r
146 return EFI_INVALID_PARAMETER;\r
147 }\r
148\r
149 //\r
150 // If Width is EfiPciIoWidthFillUintX then convert to EfiPciIoWidthUintX\r
151 //\r
152 Width = (EFI_PCI_IO_PROTOCOL_WIDTH)(Width & 0x03);\r
153\r
154 if (PciIoDevice->IsPciExp) {\r
155 if ((*Offset + Count * (UINTN)(1 << Width)) - 1 >= PCI_EXP_MAX_CONFIG_OFFSET) {\r
156 return EFI_UNSUPPORTED;\r
157 }\r
158\r
159 ExtendOffset = LShiftU64 (*Offset, 32);\r
160 *Offset = EFI_PCI_ADDRESS (PciIoDevice->BusNumber, PciIoDevice->DeviceNumber, PciIoDevice->FunctionNumber, 0);\r
161 *Offset = (*Offset) | ExtendOffset;\r
162 } else {\r
163 if ((*Offset + Count * (UINTN)(1 << Width)) - 1 >= PCI_MAX_CONFIG_OFFSET) {\r
164 return EFI_UNSUPPORTED;\r
165 }\r
166\r
167 *Offset = EFI_PCI_ADDRESS (PciIoDevice->BusNumber, PciIoDevice->DeviceNumber, PciIoDevice->FunctionNumber, *Offset);\r
168 }\r
169\r
170 return EFI_SUCCESS;\r
171}\r
172\r
173/**\r
174 Reads from the memory space of a PCI controller. Returns either when the polling exit criteria is\r
175 satisfied or after a defined duration.\r
176\r
177 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
178 @param Width Signifies the width of the memory or I/O operations.\r
179 @param BarIndex The BAR index of the standard PCI Configuration header to use as the\r
180 base address for the memory operation to perform.\r
181 @param Offset The offset within the selected BAR to start the memory operation.\r
182 @param Mask Mask used for the polling criteria.\r
183 @param Value The comparison value used for the polling exit criteria.\r
184 @param Delay The number of 100 ns units to poll.\r
185 @param Result Pointer to the last value read from the memory location.\r
186\r
187 @retval EFI_SUCCESS The last data returned from the access matched the poll exit criteria.\r
188 @retval EFI_UNSUPPORTED BarIndex not valid for this PCI controller.\r
189 @retval EFI_UNSUPPORTED Offset is not valid for the BarIndex of this PCI controller.\r
190 @retval EFI_TIMEOUT Delay expired before a match occurred.\r
191 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
192 @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r
193\r
194**/\r
195EFI_STATUS\r
196EFIAPI\r
197PciIoPollMem (\r
198 IN EFI_PCI_IO_PROTOCOL *This,\r
199 IN EFI_PCI_IO_PROTOCOL_WIDTH Width,\r
200 IN UINT8 BarIndex,\r
201 IN UINT64 Offset,\r
202 IN UINT64 Mask,\r
203 IN UINT64 Value,\r
204 IN UINT64 Delay,\r
205 OUT UINT64 *Result\r
206 )\r
207{\r
208 EFI_STATUS Status;\r
209 PCI_IO_DEVICE *PciIoDevice;\r
210\r
211 PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);\r
212\r
213 if ((UINT32)Width >= EfiPciIoWidthMaximum) {\r
214 return EFI_INVALID_PARAMETER;\r
215 }\r
216\r
217 Status = PciIoVerifyBarAccess (PciIoDevice, BarIndex, PciBarTypeMem, Width, 1, &Offset);\r
218 if (EFI_ERROR (Status)) {\r
219 return EFI_UNSUPPORTED;\r
220 }\r
221\r
222 if (Width > EfiPciIoWidthUint64) {\r
223 return EFI_INVALID_PARAMETER;\r
224 }\r
225\r
226 //\r
227 // If request is not aligned, then convert request to EfiPciIoWithXXXUint8\r
228 //\r
229 if (FeaturePcdGet (PcdUnalignedPciIoEnable)) {\r
230 if ((Offset & ((1 << (Width & 0x03)) - 1)) != 0) {\r
231 Status = PciIoMemRead (This, Width, BarIndex, Offset, 1, Result);\r
232 if (EFI_ERROR (Status)) {\r
233 return Status;\r
234 }\r
235\r
236 if (((*Result & Mask) == Value) || (Delay == 0)) {\r
237 return EFI_SUCCESS;\r
238 }\r
239\r
240 do {\r
241 //\r
242 // Stall 10 us = 100 * 100ns\r
243 //\r
244 gBS->Stall (10);\r
245\r
246 Status = PciIoMemRead (This, Width, BarIndex, Offset, 1, Result);\r
247 if (EFI_ERROR (Status)) {\r
248 return Status;\r
249 }\r
250\r
251 if ((*Result & Mask) == Value) {\r
252 return EFI_SUCCESS;\r
253 }\r
254\r
255 if (Delay <= 100) {\r
256 return EFI_TIMEOUT;\r
257 }\r
258\r
259 Delay -= 100;\r
260 } while (TRUE);\r
261 }\r
262 }\r
263\r
264 Status = PciIoDevice->PciRootBridgeIo->PollMem (\r
265 PciIoDevice->PciRootBridgeIo,\r
266 (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH)Width,\r
267 Offset,\r
268 Mask,\r
269 Value,\r
270 Delay,\r
271 Result\r
272 );\r
273\r
274 if (EFI_ERROR (Status)) {\r
275 REPORT_STATUS_CODE_WITH_DEVICE_PATH (\r
276 EFI_ERROR_CODE | EFI_ERROR_MINOR,\r
277 EFI_IO_BUS_PCI | EFI_IOB_EC_CONTROLLER_ERROR,\r
278 PciIoDevice->DevicePath\r
279 );\r
280 }\r
281\r
282 return Status;\r
283}\r
284\r
285/**\r
286 Reads from the memory space of a PCI controller. Returns either when the polling exit criteria is\r
287 satisfied or after a defined duration.\r
288\r
289 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
290 @param Width Signifies the width of the memory or I/O operations.\r
291 @param BarIndex The BAR index of the standard PCI Configuration header to use as the\r
292 base address for the memory operation to perform.\r
293 @param Offset The offset within the selected BAR to start the memory operation.\r
294 @param Mask Mask used for the polling criteria.\r
295 @param Value The comparison value used for the polling exit criteria.\r
296 @param Delay The number of 100 ns units to poll.\r
297 @param Result Pointer to the last value read from the memory location.\r
298\r
299 @retval EFI_SUCCESS The last data returned from the access matched the poll exit criteria.\r
300 @retval EFI_UNSUPPORTED BarIndex not valid for this PCI controller.\r
301 @retval EFI_UNSUPPORTED Offset is not valid for the BarIndex of this PCI controller.\r
302 @retval EFI_TIMEOUT Delay expired before a match occurred.\r
303 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
304 @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r
305\r
306**/\r
307EFI_STATUS\r
308EFIAPI\r
309PciIoPollIo (\r
310 IN EFI_PCI_IO_PROTOCOL *This,\r
311 IN EFI_PCI_IO_PROTOCOL_WIDTH Width,\r
312 IN UINT8 BarIndex,\r
313 IN UINT64 Offset,\r
314 IN UINT64 Mask,\r
315 IN UINT64 Value,\r
316 IN UINT64 Delay,\r
317 OUT UINT64 *Result\r
318 )\r
319{\r
320 EFI_STATUS Status;\r
321 PCI_IO_DEVICE *PciIoDevice;\r
322\r
323 PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);\r
324\r
325 if ((UINT32)Width > EfiPciIoWidthUint64) {\r
326 return EFI_INVALID_PARAMETER;\r
327 }\r
328\r
329 Status = PciIoVerifyBarAccess (PciIoDevice, BarIndex, PciBarTypeIo, Width, 1, &Offset);\r
330 if (EFI_ERROR (Status)) {\r
331 return EFI_UNSUPPORTED;\r
332 }\r
333\r
334 //\r
335 // If request is not aligned, then convert request to EfiPciIoWithXXXUint8\r
336 //\r
337 if (FeaturePcdGet (PcdUnalignedPciIoEnable)) {\r
338 if ((Offset & ((1 << (Width & 0x03)) - 1)) != 0) {\r
339 Status = PciIoIoRead (This, Width, BarIndex, Offset, 1, Result);\r
340 if (EFI_ERROR (Status)) {\r
341 return Status;\r
342 }\r
343\r
344 if (((*Result & Mask) == Value) || (Delay == 0)) {\r
345 return EFI_SUCCESS;\r
346 }\r
347\r
348 do {\r
349 //\r
350 // Stall 10 us = 100 * 100ns\r
351 //\r
352 gBS->Stall (10);\r
353\r
354 Status = PciIoIoRead (This, Width, BarIndex, Offset, 1, Result);\r
355 if (EFI_ERROR (Status)) {\r
356 return Status;\r
357 }\r
358\r
359 if ((*Result & Mask) == Value) {\r
360 return EFI_SUCCESS;\r
361 }\r
362\r
363 if (Delay <= 100) {\r
364 return EFI_TIMEOUT;\r
365 }\r
366\r
367 Delay -= 100;\r
368 } while (TRUE);\r
369 }\r
370 }\r
371\r
372 Status = PciIoDevice->PciRootBridgeIo->PollIo (\r
373 PciIoDevice->PciRootBridgeIo,\r
374 (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH)Width,\r
375 Offset,\r
376 Mask,\r
377 Value,\r
378 Delay,\r
379 Result\r
380 );\r
381\r
382 if (EFI_ERROR (Status)) {\r
383 REPORT_STATUS_CODE_WITH_DEVICE_PATH (\r
384 EFI_ERROR_CODE | EFI_ERROR_MINOR,\r
385 EFI_IO_BUS_PCI | EFI_IOB_EC_CONTROLLER_ERROR,\r
386 PciIoDevice->DevicePath\r
387 );\r
388 }\r
389\r
390 return Status;\r
391}\r
392\r
393/**\r
394 Enable a PCI driver to access PCI controller registers in the PCI memory or I/O space.\r
395\r
396 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
397 @param Width Signifies the width of the memory or I/O operations.\r
398 @param BarIndex The BAR index of the standard PCI Configuration header to use as the\r
399 base address for the memory or I/O operation to perform.\r
400 @param Offset The offset within the selected BAR to start the memory or I/O operation.\r
401 @param Count The number of memory or I/O operations to perform.\r
402 @param Buffer For read operations, the destination buffer to store the results. For write\r
403 operations, the source buffer to write data from.\r
404\r
405 @retval EFI_SUCCESS The data was read from or written to the PCI controller.\r
406 @retval EFI_UNSUPPORTED BarIndex not valid for this PCI controller.\r
407 @retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not\r
408 valid for the PCI BAR specified by BarIndex.\r
409 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
410 @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r
411\r
412**/\r
413EFI_STATUS\r
414EFIAPI\r
415PciIoMemRead (\r
416 IN EFI_PCI_IO_PROTOCOL *This,\r
417 IN EFI_PCI_IO_PROTOCOL_WIDTH Width,\r
418 IN UINT8 BarIndex,\r
419 IN UINT64 Offset,\r
420 IN UINTN Count,\r
421 IN OUT VOID *Buffer\r
422 )\r
423{\r
424 EFI_STATUS Status;\r
425 PCI_IO_DEVICE *PciIoDevice;\r
426\r
427 PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);\r
428\r
429 if ((UINT32)Width >= EfiPciIoWidthMaximum) {\r
430 return EFI_INVALID_PARAMETER;\r
431 }\r
432\r
433 if (Buffer == NULL) {\r
434 return EFI_INVALID_PARAMETER;\r
435 }\r
436\r
437 Status = PciIoVerifyBarAccess (PciIoDevice, BarIndex, PciBarTypeMem, Width, Count, &Offset);\r
438 if (EFI_ERROR (Status)) {\r
439 return EFI_UNSUPPORTED;\r
440 }\r
441\r
442 //\r
443 // If request is not aligned, then convert request to EfiPciIoWithXXXUint8\r
444 //\r
445 if (FeaturePcdGet (PcdUnalignedPciIoEnable)) {\r
446 if ((Offset & ((1 << (Width & 0x03)) - 1)) != 0) {\r
447 Count *= (UINTN)(1 << (Width & 0x03));\r
448 Width = (EFI_PCI_IO_PROTOCOL_WIDTH)(Width & (~0x03));\r
449 }\r
450 }\r
451\r
452 Status = PciIoDevice->PciRootBridgeIo->Mem.Read (\r
453 PciIoDevice->PciRootBridgeIo,\r
454 (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH)Width,\r
455 Offset,\r
456 Count,\r
457 Buffer\r
458 );\r
459\r
460 if (EFI_ERROR (Status)) {\r
461 REPORT_STATUS_CODE_WITH_DEVICE_PATH (\r
462 EFI_ERROR_CODE | EFI_ERROR_MINOR,\r
463 EFI_IO_BUS_PCI | EFI_IOB_EC_READ_ERROR,\r
464 PciIoDevice->DevicePath\r
465 );\r
466 }\r
467\r
468 return Status;\r
469}\r
470\r
471/**\r
472 Enable a PCI driver to access PCI controller registers in the PCI memory or I/O space.\r
473\r
474 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
475 @param Width Signifies the width of the memory or I/O operations.\r
476 @param BarIndex The BAR index of the standard PCI Configuration header to use as the\r
477 base address for the memory or I/O operation to perform.\r
478 @param Offset The offset within the selected BAR to start the memory or I/O operation.\r
479 @param Count The number of memory or I/O operations to perform.\r
480 @param Buffer For read operations, the destination buffer to store the results. For write\r
481 operations, the source buffer to write data from.\r
482\r
483 @retval EFI_SUCCESS The data was read from or written to the PCI controller.\r
484 @retval EFI_UNSUPPORTED BarIndex not valid for this PCI controller.\r
485 @retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not\r
486 valid for the PCI BAR specified by BarIndex.\r
487 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
488 @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r
489\r
490**/\r
491EFI_STATUS\r
492EFIAPI\r
493PciIoMemWrite (\r
494 IN EFI_PCI_IO_PROTOCOL *This,\r
495 IN EFI_PCI_IO_PROTOCOL_WIDTH Width,\r
496 IN UINT8 BarIndex,\r
497 IN UINT64 Offset,\r
498 IN UINTN Count,\r
499 IN OUT VOID *Buffer\r
500 )\r
501{\r
502 EFI_STATUS Status;\r
503 PCI_IO_DEVICE *PciIoDevice;\r
504\r
505 PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);\r
506\r
507 if ((UINT32)Width >= EfiPciIoWidthMaximum) {\r
508 return EFI_INVALID_PARAMETER;\r
509 }\r
510\r
511 if (Buffer == NULL) {\r
512 return EFI_INVALID_PARAMETER;\r
513 }\r
514\r
515 Status = PciIoVerifyBarAccess (PciIoDevice, BarIndex, PciBarTypeMem, Width, Count, &Offset);\r
516 if (EFI_ERROR (Status)) {\r
517 return EFI_UNSUPPORTED;\r
518 }\r
519\r
520 //\r
521 // If request is not aligned, then convert request to EfiPciIoWithXXXUint8\r
522 //\r
523 if (FeaturePcdGet (PcdUnalignedPciIoEnable)) {\r
524 if ((Offset & ((1 << (Width & 0x03)) - 1)) != 0) {\r
525 Count *= (UINTN)(1 << (Width & 0x03));\r
526 Width = (EFI_PCI_IO_PROTOCOL_WIDTH)(Width & (~0x03));\r
527 }\r
528 }\r
529\r
530 Status = PciIoDevice->PciRootBridgeIo->Mem.Write (\r
531 PciIoDevice->PciRootBridgeIo,\r
532 (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH)Width,\r
533 Offset,\r
534 Count,\r
535 Buffer\r
536 );\r
537\r
538 if (EFI_ERROR (Status)) {\r
539 REPORT_STATUS_CODE_WITH_DEVICE_PATH (\r
540 EFI_ERROR_CODE | EFI_ERROR_MINOR,\r
541 EFI_IO_BUS_PCI | EFI_IOB_EC_WRITE_ERROR,\r
542 PciIoDevice->DevicePath\r
543 );\r
544 }\r
545\r
546 return Status;\r
547}\r
548\r
549/**\r
550 Enable a PCI driver to access PCI controller registers in the PCI memory or I/O space.\r
551\r
552 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
553 @param Width Signifies the width of the memory or I/O operations.\r
554 @param BarIndex The BAR index of the standard PCI Configuration header to use as the\r
555 base address for the memory or I/O operation to perform.\r
556 @param Offset The offset within the selected BAR to start the memory or I/O operation.\r
557 @param Count The number of memory or I/O operations to perform.\r
558 @param Buffer For read operations, the destination buffer to store the results. For write\r
559 operations, the source buffer to write data from.\r
560\r
561 @retval EFI_SUCCESS The data was read from or written to the PCI controller.\r
562 @retval EFI_UNSUPPORTED BarIndex not valid for this PCI controller.\r
563 @retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not\r
564 valid for the PCI BAR specified by BarIndex.\r
565 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
566 @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r
567\r
568**/\r
569EFI_STATUS\r
570EFIAPI\r
571PciIoIoRead (\r
572 IN EFI_PCI_IO_PROTOCOL *This,\r
573 IN EFI_PCI_IO_PROTOCOL_WIDTH Width,\r
574 IN UINT8 BarIndex,\r
575 IN UINT64 Offset,\r
576 IN UINTN Count,\r
577 IN OUT VOID *Buffer\r
578 )\r
579{\r
580 EFI_STATUS Status;\r
581 PCI_IO_DEVICE *PciIoDevice;\r
582\r
583 PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);\r
584\r
585 if ((UINT32)Width >= EfiPciIoWidthMaximum) {\r
586 return EFI_INVALID_PARAMETER;\r
587 }\r
588\r
589 if (Buffer == NULL) {\r
590 return EFI_INVALID_PARAMETER;\r
591 }\r
592\r
593 Status = PciIoVerifyBarAccess (PciIoDevice, BarIndex, PciBarTypeIo, Width, Count, &Offset);\r
594 if (EFI_ERROR (Status)) {\r
595 return EFI_UNSUPPORTED;\r
596 }\r
597\r
598 //\r
599 // If request is not aligned, then convert request to EfiPciIoWithXXXUint8\r
600 //\r
601 if (FeaturePcdGet (PcdUnalignedPciIoEnable)) {\r
602 if ((Offset & ((1 << (Width & 0x03)) - 1)) != 0) {\r
603 Count *= (UINTN)(1 << (Width & 0x03));\r
604 Width = (EFI_PCI_IO_PROTOCOL_WIDTH)(Width & (~0x03));\r
605 }\r
606 }\r
607\r
608 Status = PciIoDevice->PciRootBridgeIo->Io.Read (\r
609 PciIoDevice->PciRootBridgeIo,\r
610 (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH)Width,\r
611 Offset,\r
612 Count,\r
613 Buffer\r
614 );\r
615\r
616 if (EFI_ERROR (Status)) {\r
617 REPORT_STATUS_CODE_WITH_DEVICE_PATH (\r
618 EFI_ERROR_CODE | EFI_ERROR_MINOR,\r
619 EFI_IO_BUS_PCI | EFI_IOB_EC_READ_ERROR,\r
620 PciIoDevice->DevicePath\r
621 );\r
622 }\r
623\r
624 return Status;\r
625}\r
626\r
627/**\r
628 Enable a PCI driver to access PCI controller registers in the PCI memory or I/O space.\r
629\r
630 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
631 @param Width Signifies the width of the memory or I/O operations.\r
632 @param BarIndex The BAR index of the standard PCI Configuration header to use as the\r
633 base address for the memory or I/O operation to perform.\r
634 @param Offset The offset within the selected BAR to start the memory or I/O operation.\r
635 @param Count The number of memory or I/O operations to perform.\r
636 @param Buffer For read operations, the destination buffer to store the results. For write\r
637 operations, the source buffer to write data from.\r
638\r
639 @retval EFI_SUCCESS The data was read from or written to the PCI controller.\r
640 @retval EFI_UNSUPPORTED BarIndex not valid for this PCI controller.\r
641 @retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not\r
642 valid for the PCI BAR specified by BarIndex.\r
643 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
644 @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r
645\r
646**/\r
647EFI_STATUS\r
648EFIAPI\r
649PciIoIoWrite (\r
650 IN EFI_PCI_IO_PROTOCOL *This,\r
651 IN EFI_PCI_IO_PROTOCOL_WIDTH Width,\r
652 IN UINT8 BarIndex,\r
653 IN UINT64 Offset,\r
654 IN UINTN Count,\r
655 IN OUT VOID *Buffer\r
656 )\r
657{\r
658 EFI_STATUS Status;\r
659 PCI_IO_DEVICE *PciIoDevice;\r
660\r
661 PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);\r
662\r
663 if ((UINT32)Width >= EfiPciIoWidthMaximum) {\r
664 return EFI_INVALID_PARAMETER;\r
665 }\r
666\r
667 if (Buffer == NULL) {\r
668 return EFI_INVALID_PARAMETER;\r
669 }\r
670\r
671 Status = PciIoVerifyBarAccess (PciIoDevice, BarIndex, PciBarTypeIo, Width, Count, &Offset);\r
672 if (EFI_ERROR (Status)) {\r
673 return EFI_UNSUPPORTED;\r
674 }\r
675\r
676 //\r
677 // If request is not aligned, then convert request to EfiPciIoWithXXXUint8\r
678 //\r
679 if (FeaturePcdGet (PcdUnalignedPciIoEnable)) {\r
680 if ((Offset & ((1 << (Width & 0x03)) - 1)) != 0) {\r
681 Count *= (UINTN)(1 << (Width & 0x03));\r
682 Width = (EFI_PCI_IO_PROTOCOL_WIDTH)(Width & (~0x03));\r
683 }\r
684 }\r
685\r
686 Status = PciIoDevice->PciRootBridgeIo->Io.Write (\r
687 PciIoDevice->PciRootBridgeIo,\r
688 (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH)Width,\r
689 Offset,\r
690 Count,\r
691 Buffer\r
692 );\r
693\r
694 if (EFI_ERROR (Status)) {\r
695 REPORT_STATUS_CODE_WITH_DEVICE_PATH (\r
696 EFI_ERROR_CODE | EFI_ERROR_MINOR,\r
697 EFI_IO_BUS_PCI | EFI_IOB_EC_WRITE_ERROR,\r
698 PciIoDevice->DevicePath\r
699 );\r
700 }\r
701\r
702 return Status;\r
703}\r
704\r
705/**\r
706 Enable a PCI driver to access PCI controller registers in PCI configuration space.\r
707\r
708 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
709 @param Width Signifies the width of the memory operations.\r
710 @param Offset The offset within the PCI configuration space for the PCI controller.\r
711 @param Count The number of PCI configuration operations to perform.\r
712 @param Buffer For read operations, the destination buffer to store the results. For write\r
713 operations, the source buffer to write data from.\r
714\r
715\r
716 @retval EFI_SUCCESS The data was read from or written to the PCI controller.\r
717 @retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not\r
718 valid for the PCI configuration header of the PCI controller.\r
719 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
720 @retval EFI_INVALID_PARAMETER Buffer is NULL or Width is invalid.\r
721\r
722**/\r
723EFI_STATUS\r
724EFIAPI\r
725PciIoConfigRead (\r
726 IN EFI_PCI_IO_PROTOCOL *This,\r
727 IN EFI_PCI_IO_PROTOCOL_WIDTH Width,\r
728 IN UINT32 Offset,\r
729 IN UINTN Count,\r
730 IN OUT VOID *Buffer\r
731 )\r
732{\r
733 EFI_STATUS Status;\r
734 PCI_IO_DEVICE *PciIoDevice;\r
735 UINT64 Address;\r
736\r
737 PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);\r
738\r
739 Address = Offset;\r
740 Status = PciIoVerifyConfigAccess (PciIoDevice, Width, Count, &Address);\r
741 if (EFI_ERROR (Status)) {\r
742 return Status;\r
743 }\r
744\r
745 //\r
746 // If request is not aligned, then convert request to EfiPciIoWithXXXUint8\r
747 //\r
748 if (FeaturePcdGet (PcdUnalignedPciIoEnable)) {\r
749 if ((Offset & ((1 << (Width & 0x03)) - 1)) != 0) {\r
750 Count *= (UINTN)(1 << (Width & 0x03));\r
751 Width = (EFI_PCI_IO_PROTOCOL_WIDTH)(Width & (~0x03));\r
752 }\r
753 }\r
754\r
755 Status = PciIoDevice->PciRootBridgeIo->Pci.Read (\r
756 PciIoDevice->PciRootBridgeIo,\r
757 (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH)Width,\r
758 Address,\r
759 Count,\r
760 Buffer\r
761 );\r
762\r
763 if (EFI_ERROR (Status)) {\r
764 REPORT_STATUS_CODE_WITH_DEVICE_PATH (\r
765 EFI_ERROR_CODE | EFI_ERROR_MINOR,\r
766 EFI_IO_BUS_PCI | EFI_IOB_EC_READ_ERROR,\r
767 PciIoDevice->DevicePath\r
768 );\r
769 }\r
770\r
771 return Status;\r
772}\r
773\r
774/**\r
775 Enable a PCI driver to access PCI controller registers in PCI configuration space.\r
776\r
777 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
778 @param Width Signifies the width of the memory operations.\r
779 @param Offset The offset within the PCI configuration space for the PCI controller.\r
780 @param Count The number of PCI configuration operations to perform.\r
781 @param Buffer For read operations, the destination buffer to store the results. For write\r
782 operations, the source buffer to write data from.\r
783\r
784\r
785 @retval EFI_SUCCESS The data was read from or written to the PCI controller.\r
786 @retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not\r
787 valid for the PCI configuration header of the PCI controller.\r
788 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
789 @retval EFI_INVALID_PARAMETER Buffer is NULL or Width is invalid.\r
790\r
791**/\r
792EFI_STATUS\r
793EFIAPI\r
794PciIoConfigWrite (\r
795 IN EFI_PCI_IO_PROTOCOL *This,\r
796 IN EFI_PCI_IO_PROTOCOL_WIDTH Width,\r
797 IN UINT32 Offset,\r
798 IN UINTN Count,\r
799 IN OUT VOID *Buffer\r
800 )\r
801{\r
802 EFI_STATUS Status;\r
803 PCI_IO_DEVICE *PciIoDevice;\r
804 UINT64 Address;\r
805\r
806 PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);\r
807\r
808 Address = Offset;\r
809 Status = PciIoVerifyConfigAccess (PciIoDevice, Width, Count, &Address);\r
810 if (EFI_ERROR (Status)) {\r
811 return Status;\r
812 }\r
813\r
814 //\r
815 // If request is not aligned, then convert request to EfiPciIoWithXXXUint8\r
816 //\r
817 if (FeaturePcdGet (PcdUnalignedPciIoEnable)) {\r
818 if ((Offset & ((1 << (Width & 0x03)) - 1)) != 0) {\r
819 Count *= (UINTN)(1 << (Width & 0x03));\r
820 Width = (EFI_PCI_IO_PROTOCOL_WIDTH)(Width & (~0x03));\r
821 }\r
822 }\r
823\r
824 Status = PciIoDevice->PciRootBridgeIo->Pci.Write (\r
825 PciIoDevice->PciRootBridgeIo,\r
826 (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH)Width,\r
827 Address,\r
828 Count,\r
829 Buffer\r
830 );\r
831\r
832 if (EFI_ERROR (Status)) {\r
833 REPORT_STATUS_CODE_WITH_DEVICE_PATH (\r
834 EFI_ERROR_CODE | EFI_ERROR_MINOR,\r
835 EFI_IO_BUS_PCI | EFI_IOB_EC_WRITE_ERROR,\r
836 PciIoDevice->DevicePath\r
837 );\r
838 }\r
839\r
840 return Status;\r
841}\r
842\r
843/**\r
844 Enables a PCI driver to copy one region of PCI memory space to another region of PCI\r
845 memory space.\r
846\r
847 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
848 @param Width Signifies the width of the memory operations.\r
849 @param DestBarIndex The BAR index in the standard PCI Configuration header to use as the\r
850 base address for the memory operation to perform.\r
851 @param DestOffset The destination offset within the BAR specified by DestBarIndex to\r
852 start the memory writes for the copy operation.\r
853 @param SrcBarIndex The BAR index in the standard PCI Configuration header to use as the\r
854 base address for the memory operation to perform.\r
855 @param SrcOffset The source offset within the BAR specified by SrcBarIndex to start\r
856 the memory reads for the copy operation.\r
857 @param Count The number of memory operations to perform. Bytes moved is Width\r
858 size * Count, starting at DestOffset and SrcOffset.\r
859\r
860 @retval EFI_SUCCESS The data was copied from one memory region to another memory region.\r
861 @retval EFI_UNSUPPORTED DestBarIndex not valid for this PCI controller.\r
862 @retval EFI_UNSUPPORTED SrcBarIndex not valid for this PCI controller.\r
863 @retval EFI_UNSUPPORTED The address range specified by DestOffset, Width, and Count\r
864 is not valid for the PCI BAR specified by DestBarIndex.\r
865 @retval EFI_UNSUPPORTED The address range specified by SrcOffset, Width, and Count is\r
866 not valid for the PCI BAR specified by SrcBarIndex.\r
867 @retval EFI_INVALID_PARAMETER Width is invalid.\r
868 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
869\r
870**/\r
871EFI_STATUS\r
872EFIAPI\r
873PciIoCopyMem (\r
874 IN EFI_PCI_IO_PROTOCOL *This,\r
875 IN EFI_PCI_IO_PROTOCOL_WIDTH Width,\r
876 IN UINT8 DestBarIndex,\r
877 IN UINT64 DestOffset,\r
878 IN UINT8 SrcBarIndex,\r
879 IN UINT64 SrcOffset,\r
880 IN UINTN Count\r
881 )\r
882{\r
883 EFI_STATUS Status;\r
884 PCI_IO_DEVICE *PciIoDevice;\r
885\r
886 PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);\r
887\r
888 if ((UINT32)Width >= EfiPciIoWidthMaximum) {\r
889 return EFI_INVALID_PARAMETER;\r
890 }\r
891\r
892 if ((Width == EfiPciIoWidthFifoUint8) ||\r
893 (Width == EfiPciIoWidthFifoUint16) ||\r
894 (Width == EfiPciIoWidthFifoUint32) ||\r
895 (Width == EfiPciIoWidthFifoUint64) ||\r
896 (Width == EfiPciIoWidthFillUint8) ||\r
897 (Width == EfiPciIoWidthFillUint16) ||\r
898 (Width == EfiPciIoWidthFillUint32) ||\r
899 (Width == EfiPciIoWidthFillUint64))\r
900 {\r
901 return EFI_INVALID_PARAMETER;\r
902 }\r
903\r
904 Status = PciIoVerifyBarAccess (PciIoDevice, DestBarIndex, PciBarTypeMem, Width, Count, &DestOffset);\r
905 if (EFI_ERROR (Status)) {\r
906 return EFI_UNSUPPORTED;\r
907 }\r
908\r
909 Status = PciIoVerifyBarAccess (PciIoDevice, SrcBarIndex, PciBarTypeMem, Width, Count, &SrcOffset);\r
910 if (EFI_ERROR (Status)) {\r
911 return EFI_UNSUPPORTED;\r
912 }\r
913\r
914 //\r
915 // If request is not aligned, then convert request to EfiPciIoWithXXXUint8\r
916 //\r
917 if (FeaturePcdGet (PcdUnalignedPciIoEnable)) {\r
918 if (((SrcOffset & ((1 << (Width & 0x03)) - 1)) != 0) || ((DestOffset & ((1 << (Width & 0x03)) - 1)) != 0)) {\r
919 Count *= (UINTN)(1 << (Width & 0x03));\r
920 Width = (EFI_PCI_IO_PROTOCOL_WIDTH)(Width & (~0x03));\r
921 }\r
922 }\r
923\r
924 Status = PciIoDevice->PciRootBridgeIo->CopyMem (\r
925 PciIoDevice->PciRootBridgeIo,\r
926 (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH)Width,\r
927 DestOffset,\r
928 SrcOffset,\r
929 Count\r
930 );\r
931\r
932 if (EFI_ERROR (Status)) {\r
933 REPORT_STATUS_CODE_WITH_DEVICE_PATH (\r
934 EFI_ERROR_CODE | EFI_ERROR_MINOR,\r
935 EFI_IO_BUS_PCI | EFI_IOB_EC_CONTROLLER_ERROR,\r
936 PciIoDevice->DevicePath\r
937 );\r
938 }\r
939\r
940 return Status;\r
941}\r
942\r
943/**\r
944 Provides the PCI controller-specific addresses needed to access system memory.\r
945\r
946 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
947 @param Operation Indicates if the bus master is going to read or write to system memory.\r
948 @param HostAddress The system memory address to map to the PCI controller.\r
949 @param NumberOfBytes On input the number of bytes to map. On output the number of bytes\r
950 that were mapped.\r
951 @param DeviceAddress The resulting map address for the bus master PCI controller to use to\r
952 access the hosts HostAddress.\r
953 @param Mapping A resulting value to pass to Unmap().\r
954\r
955 @retval EFI_SUCCESS The range was mapped for the returned NumberOfBytes.\r
956 @retval EFI_UNSUPPORTED The HostAddress cannot be mapped as a common buffer.\r
957 @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r
958 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
959 @retval EFI_DEVICE_ERROR The system hardware could not map the requested address.\r
960\r
961**/\r
962EFI_STATUS\r
963EFIAPI\r
964PciIoMap (\r
965 IN EFI_PCI_IO_PROTOCOL *This,\r
966 IN EFI_PCI_IO_PROTOCOL_OPERATION Operation,\r
967 IN VOID *HostAddress,\r
968 IN OUT UINTN *NumberOfBytes,\r
969 OUT EFI_PHYSICAL_ADDRESS *DeviceAddress,\r
970 OUT VOID **Mapping\r
971 )\r
972{\r
973 EFI_STATUS Status;\r
974 PCI_IO_DEVICE *PciIoDevice;\r
975 UINT64 IoMmuAttribute;\r
976 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION RootBridgeIoOperation;\r
977\r
978 PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);\r
979\r
980 if ((UINT32)Operation >= EfiPciIoOperationMaximum) {\r
981 return EFI_INVALID_PARAMETER;\r
982 }\r
983\r
984 if ((HostAddress == NULL) || (NumberOfBytes == NULL) || (DeviceAddress == NULL) || (Mapping == NULL)) {\r
985 return EFI_INVALID_PARAMETER;\r
986 }\r
987\r
988 RootBridgeIoOperation = (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION)Operation;\r
989 if ((PciIoDevice->Attributes & EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE) != 0) {\r
990 RootBridgeIoOperation = (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION)(Operation + EfiPciOperationBusMasterRead64);\r
991 }\r
992\r
993 Status = PciIoDevice->PciRootBridgeIo->Map (\r
994 PciIoDevice->PciRootBridgeIo,\r
995 RootBridgeIoOperation,\r
996 HostAddress,\r
997 NumberOfBytes,\r
998 DeviceAddress,\r
999 Mapping\r
1000 );\r
1001\r
1002 if (EFI_ERROR (Status)) {\r
1003 REPORT_STATUS_CODE_WITH_DEVICE_PATH (\r
1004 EFI_ERROR_CODE | EFI_ERROR_MINOR,\r
1005 EFI_IO_BUS_PCI | EFI_IOB_EC_CONTROLLER_ERROR,\r
1006 PciIoDevice->DevicePath\r
1007 );\r
1008 }\r
1009\r
1010 if (mIoMmuProtocol != NULL) {\r
1011 if (!EFI_ERROR (Status)) {\r
1012 switch (Operation) {\r
1013 case EfiPciIoOperationBusMasterRead:\r
1014 IoMmuAttribute = EDKII_IOMMU_ACCESS_READ;\r
1015 break;\r
1016 case EfiPciIoOperationBusMasterWrite:\r
1017 IoMmuAttribute = EDKII_IOMMU_ACCESS_WRITE;\r
1018 break;\r
1019 case EfiPciIoOperationBusMasterCommonBuffer:\r
1020 IoMmuAttribute = EDKII_IOMMU_ACCESS_READ | EDKII_IOMMU_ACCESS_WRITE;\r
1021 break;\r
1022 default:\r
1023 ASSERT (FALSE);\r
1024 return EFI_INVALID_PARAMETER;\r
1025 }\r
1026\r
1027 mIoMmuProtocol->SetAttribute (\r
1028 mIoMmuProtocol,\r
1029 PciIoDevice->Handle,\r
1030 *Mapping,\r
1031 IoMmuAttribute\r
1032 );\r
1033 }\r
1034 }\r
1035\r
1036 return Status;\r
1037}\r
1038\r
1039/**\r
1040 Completes the Map() operation and releases any corresponding resources.\r
1041\r
1042 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
1043 @param Mapping The mapping value returned from Map().\r
1044\r
1045 @retval EFI_SUCCESS The range was unmapped.\r
1046 @retval EFI_DEVICE_ERROR The data was not committed to the target system memory.\r
1047\r
1048**/\r
1049EFI_STATUS\r
1050EFIAPI\r
1051PciIoUnmap (\r
1052 IN EFI_PCI_IO_PROTOCOL *This,\r
1053 IN VOID *Mapping\r
1054 )\r
1055{\r
1056 EFI_STATUS Status;\r
1057 PCI_IO_DEVICE *PciIoDevice;\r
1058\r
1059 PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);\r
1060\r
1061 if (mIoMmuProtocol != NULL) {\r
1062 mIoMmuProtocol->SetAttribute (\r
1063 mIoMmuProtocol,\r
1064 PciIoDevice->Handle,\r
1065 Mapping,\r
1066 0\r
1067 );\r
1068 }\r
1069\r
1070 Status = PciIoDevice->PciRootBridgeIo->Unmap (\r
1071 PciIoDevice->PciRootBridgeIo,\r
1072 Mapping\r
1073 );\r
1074\r
1075 if (EFI_ERROR (Status)) {\r
1076 REPORT_STATUS_CODE_WITH_DEVICE_PATH (\r
1077 EFI_ERROR_CODE | EFI_ERROR_MINOR,\r
1078 EFI_IO_BUS_PCI | EFI_IOB_EC_CONTROLLER_ERROR,\r
1079 PciIoDevice->DevicePath\r
1080 );\r
1081 }\r
1082\r
1083 return Status;\r
1084}\r
1085\r
1086/**\r
1087 Allocates pages that are suitable for an EfiPciIoOperationBusMasterCommonBuffer\r
1088 or EfiPciOperationBusMasterCommonBuffer64 mapping.\r
1089\r
1090 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
1091 @param Type This parameter is not used and must be ignored.\r
1092 @param MemoryType The type of memory to allocate, EfiBootServicesData or\r
1093 EfiRuntimeServicesData.\r
1094 @param Pages The number of pages to allocate.\r
1095 @param HostAddress A pointer to store the base system memory address of the\r
1096 allocated range.\r
1097 @param Attributes The requested bit mask of attributes for the allocated range.\r
1098\r
1099 @retval EFI_SUCCESS The requested memory pages were allocated.\r
1100 @retval EFI_UNSUPPORTED Attributes is unsupported. The only legal attribute bits are\r
1101 MEMORY_WRITE_COMBINE, MEMORY_CACHED and DUAL_ADDRESS_CYCLE.\r
1102 @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r
1103 @retval EFI_OUT_OF_RESOURCES The memory pages could not be allocated.\r
1104\r
1105**/\r
1106EFI_STATUS\r
1107EFIAPI\r
1108PciIoAllocateBuffer (\r
1109 IN EFI_PCI_IO_PROTOCOL *This,\r
1110 IN EFI_ALLOCATE_TYPE Type,\r
1111 IN EFI_MEMORY_TYPE MemoryType,\r
1112 IN UINTN Pages,\r
1113 OUT VOID **HostAddress,\r
1114 IN UINT64 Attributes\r
1115 )\r
1116{\r
1117 EFI_STATUS Status;\r
1118 PCI_IO_DEVICE *PciIoDevice;\r
1119\r
1120 if ((Attributes &\r
1121 (~(EFI_PCI_ATTRIBUTE_MEMORY_WRITE_COMBINE | EFI_PCI_ATTRIBUTE_MEMORY_CACHED))) != 0)\r
1122 {\r
1123 return EFI_UNSUPPORTED;\r
1124 }\r
1125\r
1126 PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);\r
1127\r
1128 if ((PciIoDevice->Attributes & EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE) != 0) {\r
1129 Attributes |= EFI_PCI_ATTRIBUTE_DUAL_ADDRESS_CYCLE;\r
1130 }\r
1131\r
1132 Status = PciIoDevice->PciRootBridgeIo->AllocateBuffer (\r
1133 PciIoDevice->PciRootBridgeIo,\r
1134 Type,\r
1135 MemoryType,\r
1136 Pages,\r
1137 HostAddress,\r
1138 Attributes\r
1139 );\r
1140\r
1141 if (EFI_ERROR (Status)) {\r
1142 REPORT_STATUS_CODE_WITH_DEVICE_PATH (\r
1143 EFI_ERROR_CODE | EFI_ERROR_MINOR,\r
1144 EFI_IO_BUS_PCI | EFI_IOB_EC_CONTROLLER_ERROR,\r
1145 PciIoDevice->DevicePath\r
1146 );\r
1147 }\r
1148\r
1149 return Status;\r
1150}\r
1151\r
1152/**\r
1153 Frees memory that was allocated with AllocateBuffer().\r
1154\r
1155 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
1156 @param Pages The number of pages to free.\r
1157 @param HostAddress The base system memory address of the allocated range.\r
1158\r
1159 @retval EFI_SUCCESS The requested memory pages were freed.\r
1160 @retval EFI_INVALID_PARAMETER The memory range specified by HostAddress and Pages\r
1161 was not allocated with AllocateBuffer().\r
1162\r
1163**/\r
1164EFI_STATUS\r
1165EFIAPI\r
1166PciIoFreeBuffer (\r
1167 IN EFI_PCI_IO_PROTOCOL *This,\r
1168 IN UINTN Pages,\r
1169 IN VOID *HostAddress\r
1170 )\r
1171{\r
1172 EFI_STATUS Status;\r
1173 PCI_IO_DEVICE *PciIoDevice;\r
1174\r
1175 PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);\r
1176\r
1177 Status = PciIoDevice->PciRootBridgeIo->FreeBuffer (\r
1178 PciIoDevice->PciRootBridgeIo,\r
1179 Pages,\r
1180 HostAddress\r
1181 );\r
1182\r
1183 if (EFI_ERROR (Status)) {\r
1184 REPORT_STATUS_CODE_WITH_DEVICE_PATH (\r
1185 EFI_ERROR_CODE | EFI_ERROR_MINOR,\r
1186 EFI_IO_BUS_PCI | EFI_IOB_EC_CONTROLLER_ERROR,\r
1187 PciIoDevice->DevicePath\r
1188 );\r
1189 }\r
1190\r
1191 return Status;\r
1192}\r
1193\r
1194/**\r
1195 Flushes all PCI posted write transactions from a PCI host bridge to system memory.\r
1196\r
1197 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
1198\r
1199 @retval EFI_SUCCESS The PCI posted write transactions were flushed from the PCI host\r
1200 bridge to system memory.\r
1201 @retval EFI_DEVICE_ERROR The PCI posted write transactions were not flushed from the PCI\r
1202 host bridge due to a hardware error.\r
1203\r
1204**/\r
1205EFI_STATUS\r
1206EFIAPI\r
1207PciIoFlush (\r
1208 IN EFI_PCI_IO_PROTOCOL *This\r
1209 )\r
1210{\r
1211 EFI_STATUS Status;\r
1212 PCI_IO_DEVICE *PciIoDevice;\r
1213\r
1214 PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);\r
1215\r
1216 Status = PciIoDevice->PciRootBridgeIo->Flush (\r
1217 PciIoDevice->PciRootBridgeIo\r
1218 );\r
1219 if (EFI_ERROR (Status)) {\r
1220 REPORT_STATUS_CODE_WITH_DEVICE_PATH (\r
1221 EFI_ERROR_CODE | EFI_ERROR_MINOR,\r
1222 EFI_IO_BUS_PCI | EFI_IOB_EC_CONTROLLER_ERROR,\r
1223 PciIoDevice->DevicePath\r
1224 );\r
1225 }\r
1226\r
1227 return Status;\r
1228}\r
1229\r
1230/**\r
1231 Retrieves this PCI controller's current PCI bus number, device number, and function number.\r
1232\r
1233 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
1234 @param SegmentNumber The PCI controller's current PCI segment number.\r
1235 @param BusNumber The PCI controller's current PCI bus number.\r
1236 @param DeviceNumber The PCI controller's current PCI device number.\r
1237 @param FunctionNumber The PCI controller's current PCI function number.\r
1238\r
1239 @retval EFI_SUCCESS The PCI controller location was returned.\r
1240 @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r
1241\r
1242**/\r
1243EFI_STATUS\r
1244EFIAPI\r
1245PciIoGetLocation (\r
1246 IN EFI_PCI_IO_PROTOCOL *This,\r
1247 OUT UINTN *Segment,\r
1248 OUT UINTN *Bus,\r
1249 OUT UINTN *Device,\r
1250 OUT UINTN *Function\r
1251 )\r
1252{\r
1253 PCI_IO_DEVICE *PciIoDevice;\r
1254\r
1255 PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);\r
1256\r
1257 if ((Segment == NULL) || (Bus == NULL) || (Device == NULL) || (Function == NULL)) {\r
1258 return EFI_INVALID_PARAMETER;\r
1259 }\r
1260\r
1261 *Segment = PciIoDevice->PciRootBridgeIo->SegmentNumber;\r
1262 *Bus = PciIoDevice->BusNumber;\r
1263 *Device = PciIoDevice->DeviceNumber;\r
1264 *Function = PciIoDevice->FunctionNumber;\r
1265\r
1266 return EFI_SUCCESS;\r
1267}\r
1268\r
1269/**\r
1270 Check BAR type for PCI resource.\r
1271\r
1272 @param PciIoDevice PCI device instance.\r
1273 @param BarIndex The BAR index of the standard PCI Configuration header to use as the\r
1274 base address for the memory or I/O operation to perform.\r
1275 @param BarType Memory or I/O.\r
1276\r
1277 @retval TRUE Pci device's bar type is same with input BarType.\r
1278 @retval TRUE Pci device's bar type is not same with input BarType.\r
1279\r
1280**/\r
1281BOOLEAN\r
1282CheckBarType (\r
1283 IN PCI_IO_DEVICE *PciIoDevice,\r
1284 IN UINT8 BarIndex,\r
1285 IN PCI_BAR_TYPE BarType\r
1286 )\r
1287{\r
1288 switch (BarType) {\r
1289 case PciBarTypeMem:\r
1290\r
1291 if ((PciIoDevice->PciBar[BarIndex].BarType != PciBarTypeMem32) &&\r
1292 (PciIoDevice->PciBar[BarIndex].BarType != PciBarTypePMem32) &&\r
1293 (PciIoDevice->PciBar[BarIndex].BarType != PciBarTypePMem64) &&\r
1294 (PciIoDevice->PciBar[BarIndex].BarType != PciBarTypeMem64))\r
1295 {\r
1296 return FALSE;\r
1297 }\r
1298\r
1299 return TRUE;\r
1300\r
1301 case PciBarTypeIo:\r
1302 if ((PciIoDevice->PciBar[BarIndex].BarType != PciBarTypeIo32) &&\r
1303 (PciIoDevice->PciBar[BarIndex].BarType != PciBarTypeIo16))\r
1304 {\r
1305 return FALSE;\r
1306 }\r
1307\r
1308 return TRUE;\r
1309\r
1310 default:\r
1311 break;\r
1312 }\r
1313\r
1314 return FALSE;\r
1315}\r
1316\r
1317/**\r
1318 Set/Disable new attributes to a Root Bridge.\r
1319\r
1320 @param PciIoDevice Pci device instance.\r
1321 @param Attributes New attribute want to be set.\r
1322 @param Operation Set or Disable.\r
1323\r
1324 @retval EFI_UNSUPPORTED If root bridge does not support change attribute.\r
1325 @retval EFI_SUCCESS Successfully set new attributes.\r
1326\r
1327**/\r
1328EFI_STATUS\r
1329ModifyRootBridgeAttributes (\r
1330 IN PCI_IO_DEVICE *PciIoDevice,\r
1331 IN UINT64 Attributes,\r
1332 IN EFI_PCI_IO_PROTOCOL_ATTRIBUTE_OPERATION Operation\r
1333 )\r
1334{\r
1335 UINT64 PciRootBridgeSupports;\r
1336 UINT64 PciRootBridgeAttributes;\r
1337 UINT64 NewPciRootBridgeAttributes;\r
1338 EFI_STATUS Status;\r
1339\r
1340 //\r
1341 // Get the current attributes of this PCI device's PCI Root Bridge\r
1342 //\r
1343 Status = PciIoDevice->PciRootBridgeIo->GetAttributes (\r
1344 PciIoDevice->PciRootBridgeIo,\r
1345 &PciRootBridgeSupports,\r
1346 &PciRootBridgeAttributes\r
1347 );\r
1348 if (EFI_ERROR (Status)) {\r
1349 return EFI_UNSUPPORTED;\r
1350 }\r
1351\r
1352 //\r
1353 // Mask off attributes not supported by PCI root bridge.\r
1354 //\r
1355 Attributes &= ~(UINT64)(EFI_PCI_IO_ATTRIBUTE_EMBEDDED_DEVICE |\r
1356 EFI_PCI_IO_ATTRIBUTE_EMBEDDED_ROM |\r
1357 EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE);\r
1358\r
1359 //\r
1360 // Record the new attribute of the Root Bridge\r
1361 //\r
1362 if (Operation == EfiPciIoAttributeOperationEnable) {\r
1363 NewPciRootBridgeAttributes = PciRootBridgeAttributes | Attributes;\r
1364 } else {\r
1365 NewPciRootBridgeAttributes = PciRootBridgeAttributes & (~Attributes);\r
1366 }\r
1367\r
1368 //\r
1369 // Call the PCI Root Bridge to attempt to modify the attributes\r
1370 //\r
1371 if ((NewPciRootBridgeAttributes ^ PciRootBridgeAttributes) != 0) {\r
1372 Status = PciIoDevice->PciRootBridgeIo->SetAttributes (\r
1373 PciIoDevice->PciRootBridgeIo,\r
1374 NewPciRootBridgeAttributes,\r
1375 NULL,\r
1376 NULL\r
1377 );\r
1378 if (EFI_ERROR (Status)) {\r
1379 //\r
1380 // The PCI Root Bridge could not modify the attributes, so return the error.\r
1381 //\r
1382 return EFI_UNSUPPORTED;\r
1383 }\r
1384 }\r
1385\r
1386 //\r
1387 // Also update the attributes for this Root Bridge structure\r
1388 //\r
1389 PciIoDevice->Attributes = NewPciRootBridgeAttributes;\r
1390\r
1391 return EFI_SUCCESS;\r
1392}\r
1393\r
1394/**\r
1395 Check whether this device can be enable/disable to snoop.\r
1396\r
1397 @param PciIoDevice Pci device instance.\r
1398 @param Operation Enable/Disable.\r
1399\r
1400 @retval EFI_UNSUPPORTED Pci device is not GFX device or not support snoop.\r
1401 @retval EFI_SUCCESS Snoop can be supported.\r
1402\r
1403**/\r
1404EFI_STATUS\r
1405SupportPaletteSnoopAttributes (\r
1406 IN PCI_IO_DEVICE *PciIoDevice,\r
1407 IN EFI_PCI_IO_PROTOCOL_ATTRIBUTE_OPERATION Operation\r
1408 )\r
1409{\r
1410 PCI_IO_DEVICE *Temp;\r
1411 UINT16 VGACommand;\r
1412\r
1413 //\r
1414 // Snoop attribute can be only modified by GFX\r
1415 //\r
1416 if (!IS_PCI_GFX (&PciIoDevice->Pci)) {\r
1417 return EFI_UNSUPPORTED;\r
1418 }\r
1419\r
1420 //\r
1421 // Get the boot VGA on the same Host Bridge\r
1422 //\r
1423 Temp = LocateVgaDeviceOnHostBridge (PciIoDevice->PciRootBridgeIo->ParentHandle);\r
1424\r
1425 if (Temp == NULL) {\r
1426 //\r
1427 // If there is no VGA device on the segment, set\r
1428 // this graphics card to decode the palette range\r
1429 //\r
1430 return EFI_SUCCESS;\r
1431 }\r
1432\r
1433 //\r
1434 // Check these two agents are on the same path\r
1435 //\r
1436 if (!PciDevicesOnTheSamePath (Temp, PciIoDevice)) {\r
1437 //\r
1438 // they are not on the same path, so snoop can be enabled or disabled\r
1439 //\r
1440 return EFI_SUCCESS;\r
1441 }\r
1442\r
1443 //\r
1444 // Check if they are on the same bus\r
1445 //\r
1446 if (Temp->Parent == PciIoDevice->Parent) {\r
1447 PCI_READ_COMMAND_REGISTER (Temp, &VGACommand);\r
1448\r
1449 //\r
1450 // If they are on the same bus, either one can\r
1451 // be set to snoop, the other set to decode\r
1452 //\r
1453 if ((VGACommand & EFI_PCI_COMMAND_VGA_PALETTE_SNOOP) != 0) {\r
1454 //\r
1455 // VGA has set to snoop, so GFX can be only set to disable snoop\r
1456 //\r
1457 if (Operation == EfiPciIoAttributeOperationEnable) {\r
1458 return EFI_UNSUPPORTED;\r
1459 }\r
1460 } else {\r
1461 //\r
1462 // VGA has disabled to snoop, so GFX can be only enabled\r
1463 //\r
1464 if (Operation == EfiPciIoAttributeOperationDisable) {\r
1465 return EFI_UNSUPPORTED;\r
1466 }\r
1467 }\r
1468\r
1469 return EFI_SUCCESS;\r
1470 }\r
1471\r
1472 //\r
1473 // If they are on the same path but on the different bus\r
1474 // The first agent is set to snoop, the second one set to\r
1475 // decode\r
1476 //\r
1477\r
1478 if (Temp->BusNumber < PciIoDevice->BusNumber) {\r
1479 //\r
1480 // GFX should be set to decode\r
1481 //\r
1482 if (Operation == EfiPciIoAttributeOperationDisable) {\r
1483 PCI_ENABLE_COMMAND_REGISTER (Temp, EFI_PCI_COMMAND_VGA_PALETTE_SNOOP);\r
1484 Temp->Attributes |= EFI_PCI_COMMAND_VGA_PALETTE_SNOOP;\r
1485 } else {\r
1486 return EFI_UNSUPPORTED;\r
1487 }\r
1488 } else {\r
1489 //\r
1490 // GFX should be set to snoop\r
1491 //\r
1492 if (Operation == EfiPciIoAttributeOperationEnable) {\r
1493 PCI_DISABLE_COMMAND_REGISTER (Temp, EFI_PCI_COMMAND_VGA_PALETTE_SNOOP);\r
1494 Temp->Attributes &= (~(UINT64)EFI_PCI_COMMAND_VGA_PALETTE_SNOOP);\r
1495 } else {\r
1496 return EFI_UNSUPPORTED;\r
1497 }\r
1498 }\r
1499\r
1500 return EFI_SUCCESS;\r
1501}\r
1502\r
1503/**\r
1504 Performs an operation on the attributes that this PCI controller supports. The operations include\r
1505 getting the set of supported attributes, retrieving the current attributes, setting the current\r
1506 attributes, enabling attributes, and disabling attributes.\r
1507\r
1508 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
1509 @param Operation The operation to perform on the attributes for this PCI controller.\r
1510 @param Attributes The mask of attributes that are used for Set, Enable, and Disable\r
1511 operations.\r
1512 @param Result A pointer to the result mask of attributes that are returned for the Get\r
1513 and Supported operations.\r
1514\r
1515 @retval EFI_SUCCESS The operation on the PCI controller's attributes was completed.\r
1516 @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r
1517 @retval EFI_UNSUPPORTED one or more of the bits set in\r
1518 Attributes are not supported by this PCI controller or one of\r
1519 its parent bridges when Operation is Set, Enable or Disable.\r
1520\r
1521**/\r
1522EFI_STATUS\r
1523EFIAPI\r
1524PciIoAttributes (\r
1525 IN EFI_PCI_IO_PROTOCOL *This,\r
1526 IN EFI_PCI_IO_PROTOCOL_ATTRIBUTE_OPERATION Operation,\r
1527 IN UINT64 Attributes,\r
1528 OUT UINT64 *Result OPTIONAL\r
1529 )\r
1530{\r
1531 EFI_STATUS Status;\r
1532\r
1533 PCI_IO_DEVICE *PciIoDevice;\r
1534 PCI_IO_DEVICE *UpStreamBridge;\r
1535 PCI_IO_DEVICE *Temp;\r
1536\r
1537 UINT64 Supports;\r
1538 UINT64 UpStreamAttributes;\r
1539 UINT16 BridgeControl;\r
1540 UINT16 Command;\r
1541\r
1542 PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);\r
1543\r
1544 switch (Operation) {\r
1545 case EfiPciIoAttributeOperationGet:\r
1546 if (Result == NULL) {\r
1547 return EFI_INVALID_PARAMETER;\r
1548 }\r
1549\r
1550 *Result = PciIoDevice->Attributes;\r
1551 return EFI_SUCCESS;\r
1552\r
1553 case EfiPciIoAttributeOperationSupported:\r
1554 if (Result == NULL) {\r
1555 return EFI_INVALID_PARAMETER;\r
1556 }\r
1557\r
1558 *Result = PciIoDevice->Supports;\r
1559 return EFI_SUCCESS;\r
1560\r
1561 case EfiPciIoAttributeOperationSet:\r
1562 Status = PciIoDevice->PciIo.Attributes (\r
1563 &(PciIoDevice->PciIo),\r
1564 EfiPciIoAttributeOperationEnable,\r
1565 Attributes,\r
1566 NULL\r
1567 );\r
1568 if (EFI_ERROR (Status)) {\r
1569 return EFI_UNSUPPORTED;\r
1570 }\r
1571\r
1572 Status = PciIoDevice->PciIo.Attributes (\r
1573 &(PciIoDevice->PciIo),\r
1574 EfiPciIoAttributeOperationDisable,\r
1575 (~Attributes) & (PciIoDevice->Supports),\r
1576 NULL\r
1577 );\r
1578 if (EFI_ERROR (Status)) {\r
1579 return EFI_UNSUPPORTED;\r
1580 }\r
1581\r
1582 return EFI_SUCCESS;\r
1583\r
1584 case EfiPciIoAttributeOperationEnable:\r
1585 case EfiPciIoAttributeOperationDisable:\r
1586 break;\r
1587\r
1588 default:\r
1589 return EFI_INVALID_PARAMETER;\r
1590 }\r
1591\r
1592 //\r
1593 // Just a trick for ENABLE attribute\r
1594 // EFI_PCI_DEVICE_ENABLE is not defined in UEFI spec, which is the internal usage.\r
1595 // So, this logic doesn't conform to UEFI spec, which should be removed.\r
1596 // But this trick logic is still kept for some binary drivers that depend on it.\r
1597 //\r
1598 if ((Attributes & EFI_PCI_DEVICE_ENABLE) == EFI_PCI_DEVICE_ENABLE) {\r
1599 Attributes &= (PciIoDevice->Supports);\r
1600\r
1601 //\r
1602 // Raise the EFI_P_PC_ENABLE Status code\r
1603 //\r
1604 REPORT_STATUS_CODE_WITH_DEVICE_PATH (\r
1605 EFI_PROGRESS_CODE,\r
1606 EFI_IO_BUS_PCI | EFI_P_PC_ENABLE,\r
1607 PciIoDevice->DevicePath\r
1608 );\r
1609 }\r
1610\r
1611 //\r
1612 // Check VGA and VGA16, they can not be set at the same time\r
1613 //\r
1614 if ((Attributes & (EFI_PCI_IO_ATTRIBUTE_VGA_IO | EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO)) != 0) {\r
1615 if ((Attributes & (EFI_PCI_IO_ATTRIBUTE_VGA_IO_16 | EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO_16)) != 0) {\r
1616 return EFI_UNSUPPORTED;\r
1617 }\r
1618 }\r
1619\r
1620 //\r
1621 // If no attributes can be supported, then return.\r
1622 // Otherwise, set the attributes that it can support.\r
1623 //\r
1624 Supports = (PciIoDevice->Supports) & Attributes;\r
1625 if (Supports != Attributes) {\r
1626 return EFI_UNSUPPORTED;\r
1627 }\r
1628\r
1629 //\r
1630 // For Root Bridge, just call RootBridgeIo to set attributes;\r
1631 //\r
1632 if (PciIoDevice->Parent == NULL) {\r
1633 Status = ModifyRootBridgeAttributes (PciIoDevice, Attributes, Operation);\r
1634 return Status;\r
1635 }\r
1636\r
1637 Command = 0;\r
1638 BridgeControl = 0;\r
1639\r
1640 //\r
1641 // For PPB & P2C, set relevant attribute bits\r
1642 //\r
1643 if (IS_PCI_BRIDGE (&PciIoDevice->Pci) || IS_CARDBUS_BRIDGE (&PciIoDevice->Pci)) {\r
1644 if ((Attributes & (EFI_PCI_IO_ATTRIBUTE_VGA_IO | EFI_PCI_IO_ATTRIBUTE_VGA_IO_16)) != 0) {\r
1645 BridgeControl |= EFI_PCI_BRIDGE_CONTROL_VGA;\r
1646 }\r
1647\r
1648 if ((Attributes & EFI_PCI_IO_ATTRIBUTE_ISA_IO) != 0) {\r
1649 BridgeControl |= EFI_PCI_BRIDGE_CONTROL_ISA;\r
1650 }\r
1651\r
1652 if ((Attributes & (EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO | EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO_16)) != 0) {\r
1653 Command |= EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO;\r
1654 }\r
1655\r
1656 if ((Attributes & (EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO_16 | EFI_PCI_IO_ATTRIBUTE_VGA_IO_16)) != 0) {\r
1657 BridgeControl |= EFI_PCI_BRIDGE_CONTROL_VGA_16;\r
1658 }\r
1659 } else {\r
1660 //\r
1661 // Do with the attributes on VGA\r
1662 // Only for VGA's legacy resource, we just can enable once.\r
1663 //\r
1664 if ((Attributes &\r
1665 (EFI_PCI_IO_ATTRIBUTE_VGA_IO |\r
1666 EFI_PCI_IO_ATTRIBUTE_VGA_IO_16 |\r
1667 EFI_PCI_IO_ATTRIBUTE_VGA_MEMORY)) != 0)\r
1668 {\r
1669 //\r
1670 // Check if a VGA has been enabled before enabling a new one\r
1671 //\r
1672 if (Operation == EfiPciIoAttributeOperationEnable) {\r
1673 //\r
1674 // Check if there have been an active VGA device on the same Host Bridge\r
1675 //\r
1676 Temp = LocateVgaDeviceOnHostBridge (PciIoDevice->PciRootBridgeIo->ParentHandle);\r
1677 if ((Temp != NULL) && (Temp != PciIoDevice)) {\r
1678 //\r
1679 // An active VGA has been detected, so can not enable another\r
1680 //\r
1681 return EFI_UNSUPPORTED;\r
1682 }\r
1683 }\r
1684 }\r
1685\r
1686 //\r
1687 // Do with the attributes on GFX\r
1688 //\r
1689 if ((Attributes & (EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO | EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO_16)) != 0) {\r
1690 if (Operation == EfiPciIoAttributeOperationEnable) {\r
1691 //\r
1692 // Check if snoop can be enabled in current configuration\r
1693 //\r
1694 Status = SupportPaletteSnoopAttributes (PciIoDevice, Operation);\r
1695\r
1696 if (EFI_ERROR (Status)) {\r
1697 //\r
1698 // Enable operation is forbidden, so mask the bit in attributes\r
1699 // so as to keep consistent with the actual Status\r
1700 //\r
1701 // Attributes &= (~EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO);\r
1702 //\r
1703 //\r
1704 //\r
1705 return EFI_UNSUPPORTED;\r
1706 }\r
1707 }\r
1708\r
1709 //\r
1710 // It can be supported, so get ready to set the bit\r
1711 //\r
1712 Command |= EFI_PCI_COMMAND_VGA_PALETTE_SNOOP;\r
1713 }\r
1714 }\r
1715\r
1716 if ((Attributes & EFI_PCI_IO_ATTRIBUTE_IO) != 0) {\r
1717 Command |= EFI_PCI_COMMAND_IO_SPACE;\r
1718 }\r
1719\r
1720 if ((Attributes & EFI_PCI_IO_ATTRIBUTE_MEMORY) != 0) {\r
1721 Command |= EFI_PCI_COMMAND_MEMORY_SPACE;\r
1722 }\r
1723\r
1724 if ((Attributes & EFI_PCI_IO_ATTRIBUTE_BUS_MASTER) != 0) {\r
1725 Command |= EFI_PCI_COMMAND_BUS_MASTER;\r
1726 }\r
1727\r
1728 //\r
1729 // The upstream bridge should be also set to relevant attribute\r
1730 // expect for IO, Mem and BusMaster\r
1731 //\r
1732 UpStreamAttributes = Attributes &\r
1733 (~(EFI_PCI_IO_ATTRIBUTE_IO |\r
1734 EFI_PCI_IO_ATTRIBUTE_MEMORY |\r
1735 EFI_PCI_IO_ATTRIBUTE_BUS_MASTER\r
1736 )\r
1737 );\r
1738 UpStreamBridge = PciIoDevice->Parent;\r
1739\r
1740 if (Operation == EfiPciIoAttributeOperationEnable) {\r
1741 //\r
1742 // Enable relevant attributes to command register and bridge control register\r
1743 //\r
1744 Status = PCI_ENABLE_COMMAND_REGISTER (PciIoDevice, Command);\r
1745 if (BridgeControl != 0) {\r
1746 Status = PCI_ENABLE_BRIDGE_CONTROL_REGISTER (PciIoDevice, BridgeControl);\r
1747 }\r
1748\r
1749 PciIoDevice->Attributes |= Attributes;\r
1750\r
1751 //\r
1752 // Enable attributes of the upstream bridge\r
1753 //\r
1754 Status = UpStreamBridge->PciIo.Attributes (\r
1755 &(UpStreamBridge->PciIo),\r
1756 EfiPciIoAttributeOperationEnable,\r
1757 UpStreamAttributes,\r
1758 NULL\r
1759 );\r
1760 } else {\r
1761 //\r
1762 // Disable relevant attributes to command register and bridge control register\r
1763 //\r
1764 Status = PCI_DISABLE_COMMAND_REGISTER (PciIoDevice, Command);\r
1765 if (BridgeControl != 0) {\r
1766 Status = PCI_DISABLE_BRIDGE_CONTROL_REGISTER (PciIoDevice, BridgeControl);\r
1767 }\r
1768\r
1769 PciIoDevice->Attributes &= (~Attributes);\r
1770 Status = EFI_SUCCESS;\r
1771 }\r
1772\r
1773 if (EFI_ERROR (Status)) {\r
1774 REPORT_STATUS_CODE_WITH_DEVICE_PATH (\r
1775 EFI_ERROR_CODE | EFI_ERROR_MINOR,\r
1776 EFI_IO_BUS_PCI | EFI_IOB_EC_CONTROLLER_ERROR,\r
1777 PciIoDevice->DevicePath\r
1778 );\r
1779 }\r
1780\r
1781 return Status;\r
1782}\r
1783\r
1784/**\r
1785 Retrieve the AddrTranslationOffset from RootBridgeIo for the\r
1786 specified range.\r
1787\r
1788 @param RootBridgeIo Root Bridge IO instance.\r
1789 @param AddrRangeMin The base address of the MMIO.\r
1790 @param AddrLen The length of the MMIO.\r
1791\r
1792 @retval The AddrTranslationOffset from RootBridgeIo for the\r
1793 specified range, or (UINT64) -1 if the range is not\r
1794 found in RootBridgeIo.\r
1795**/\r
1796UINT64\r
1797GetMmioAddressTranslationOffset (\r
1798 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *RootBridgeIo,\r
1799 UINT64 AddrRangeMin,\r
1800 UINT64 AddrLen\r
1801 )\r
1802{\r
1803 EFI_STATUS Status;\r
1804 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Configuration;\r
1805\r
1806 Status = RootBridgeIo->Configuration (\r
1807 RootBridgeIo,\r
1808 (VOID **)&Configuration\r
1809 );\r
1810 if (EFI_ERROR (Status)) {\r
1811 return (UINT64)-1;\r
1812 }\r
1813\r
1814 // According to UEFI 2.7, EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL::Configuration()\r
1815 // returns host address instead of device address, while AddrTranslationOffset\r
1816 // is not zero, and device address = host address + AddrTranslationOffset, so\r
1817 // we convert host address to device address for range compare.\r
1818 while (Configuration->Desc == ACPI_ADDRESS_SPACE_DESCRIPTOR) {\r
1819 if ((Configuration->ResType == ACPI_ADDRESS_SPACE_TYPE_MEM) &&\r
1820 (Configuration->AddrRangeMin + Configuration->AddrTranslationOffset <= AddrRangeMin) &&\r
1821 (Configuration->AddrRangeMin + Configuration->AddrLen + Configuration->AddrTranslationOffset >= AddrRangeMin + AddrLen)\r
1822 )\r
1823 {\r
1824 return Configuration->AddrTranslationOffset;\r
1825 }\r
1826\r
1827 Configuration++;\r
1828 }\r
1829\r
1830 //\r
1831 // The resource occupied by BAR should be in the range reported by RootBridge.\r
1832 //\r
1833 ASSERT (FALSE);\r
1834 return (UINT64)-1;\r
1835}\r
1836\r
1837/**\r
1838 Gets the attributes that this PCI controller supports setting on a BAR using\r
1839 SetBarAttributes(), and retrieves the list of resource descriptors for a BAR.\r
1840\r
1841 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
1842 @param BarIndex The BAR index of the standard PCI Configuration header to use as the\r
1843 base address for resource range. The legal range for this field is 0..5.\r
1844 @param Supports A pointer to the mask of attributes that this PCI controller supports\r
1845 setting for this BAR with SetBarAttributes().\r
1846 @param Resources A pointer to the resource descriptors that describe the current\r
1847 configuration of this BAR of the PCI controller.\r
1848\r
1849 @retval EFI_SUCCESS If Supports is not NULL, then the attributes that the PCI\r
1850 controller supports are returned in Supports. If Resources\r
1851 is not NULL, then the resource descriptors that the PCI\r
1852 controller is currently using are returned in Resources.\r
1853 @retval EFI_INVALID_PARAMETER Both Supports and Attributes are NULL.\r
1854 @retval EFI_UNSUPPORTED BarIndex not valid for this PCI controller.\r
1855 @retval EFI_OUT_OF_RESOURCES There are not enough resources available to allocate\r
1856 Resources.\r
1857\r
1858**/\r
1859EFI_STATUS\r
1860EFIAPI\r
1861PciIoGetBarAttributes (\r
1862 IN EFI_PCI_IO_PROTOCOL *This,\r
1863 IN UINT8 BarIndex,\r
1864 OUT UINT64 *Supports OPTIONAL,\r
1865 OUT VOID **Resources OPTIONAL\r
1866 )\r
1867{\r
1868 PCI_IO_DEVICE *PciIoDevice;\r
1869 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptor;\r
1870 EFI_ACPI_END_TAG_DESCRIPTOR *End;\r
1871\r
1872 PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);\r
1873\r
1874 if ((Supports == NULL) && (Resources == NULL)) {\r
1875 return EFI_INVALID_PARAMETER;\r
1876 }\r
1877\r
1878 if ((BarIndex >= PCI_MAX_BAR) || (PciIoDevice->PciBar[BarIndex].BarType == PciBarTypeUnknown)) {\r
1879 return EFI_UNSUPPORTED;\r
1880 }\r
1881\r
1882 //\r
1883 // This driver does not support modifications to the WRITE_COMBINE or\r
1884 // CACHED attributes for BAR ranges.\r
1885 //\r
1886 if (Supports != NULL) {\r
1887 *Supports = PciIoDevice->Supports & EFI_PCI_IO_ATTRIBUTE_MEMORY_CACHED & EFI_PCI_IO_ATTRIBUTE_MEMORY_WRITE_COMBINE;\r
1888 }\r
1889\r
1890 if (Resources != NULL) {\r
1891 Descriptor = AllocateZeroPool (sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) + sizeof (EFI_ACPI_END_TAG_DESCRIPTOR));\r
1892 if (Descriptor == NULL) {\r
1893 return EFI_OUT_OF_RESOURCES;\r
1894 }\r
1895\r
1896 *Resources = Descriptor;\r
1897\r
1898 Descriptor->Desc = ACPI_ADDRESS_SPACE_DESCRIPTOR;\r
1899 Descriptor->Len = (UINT16)(sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) - 3);\r
1900 Descriptor->AddrRangeMin = PciIoDevice->PciBar[BarIndex].BaseAddress;\r
1901 Descriptor->AddrLen = PciIoDevice->PciBar[BarIndex].Length;\r
1902 Descriptor->AddrRangeMax = PciIoDevice->PciBar[BarIndex].Alignment;\r
1903\r
1904 switch (PciIoDevice->PciBar[BarIndex].BarType) {\r
1905 case PciBarTypeIo16:\r
1906 case PciBarTypeIo32:\r
1907 //\r
1908 // Io\r
1909 //\r
1910 Descriptor->ResType = ACPI_ADDRESS_SPACE_TYPE_IO;\r
1911 break;\r
1912\r
1913 case PciBarTypePMem32:\r
1914 //\r
1915 // prefetchable\r
1916 //\r
1917 Descriptor->SpecificFlag = EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE;\r
1918 //\r
1919 // Fall through\r
1920 //\r
1921 case PciBarTypeMem32:\r
1922 //\r
1923 // Mem\r
1924 //\r
1925 Descriptor->ResType = ACPI_ADDRESS_SPACE_TYPE_MEM;\r
1926 //\r
1927 // 32 bit\r
1928 //\r
1929 Descriptor->AddrSpaceGranularity = 32;\r
1930 break;\r
1931\r
1932 case PciBarTypePMem64:\r
1933 //\r
1934 // prefetchable\r
1935 //\r
1936 Descriptor->SpecificFlag = EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE;\r
1937 //\r
1938 // Fall through\r
1939 //\r
1940 case PciBarTypeMem64:\r
1941 //\r
1942 // Mem\r
1943 //\r
1944 Descriptor->ResType = ACPI_ADDRESS_SPACE_TYPE_MEM;\r
1945 //\r
1946 // 64 bit\r
1947 //\r
1948 Descriptor->AddrSpaceGranularity = 64;\r
1949 break;\r
1950\r
1951 default:\r
1952 break;\r
1953 }\r
1954\r
1955 //\r
1956 // put the checksum\r
1957 //\r
1958 End = (EFI_ACPI_END_TAG_DESCRIPTOR *)(Descriptor + 1);\r
1959 End->Desc = ACPI_END_TAG_DESCRIPTOR;\r
1960 End->Checksum = 0;\r
1961\r
1962 //\r
1963 // Get the Address Translation Offset\r
1964 //\r
1965 if (Descriptor->ResType == ACPI_ADDRESS_SPACE_TYPE_MEM) {\r
1966 Descriptor->AddrTranslationOffset = GetMmioAddressTranslationOffset (\r
1967 PciIoDevice->PciRootBridgeIo,\r
1968 Descriptor->AddrRangeMin,\r
1969 Descriptor->AddrLen\r
1970 );\r
1971 if (Descriptor->AddrTranslationOffset == (UINT64)-1) {\r
1972 FreePool (Descriptor);\r
1973 return EFI_UNSUPPORTED;\r
1974 }\r
1975 }\r
1976\r
1977 // According to UEFI spec 2.7, we need return host address for\r
1978 // PciIo->GetBarAttributes, and host address = device address - translation.\r
1979 Descriptor->AddrRangeMin -= Descriptor->AddrTranslationOffset;\r
1980 }\r
1981\r
1982 return EFI_SUCCESS;\r
1983}\r
1984\r
1985/**\r
1986 Sets the attributes for a range of a BAR on a PCI controller.\r
1987\r
1988 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
1989 @param Attributes The mask of attributes to set for the resource range specified by\r
1990 BarIndex, Offset, and Length.\r
1991 @param BarIndex The BAR index of the standard PCI Configuration header to use as the\r
1992 base address for resource range. The legal range for this field is 0..5.\r
1993 @param Offset A pointer to the BAR relative base address of the resource range to be\r
1994 modified by the attributes specified by Attributes.\r
1995 @param Length A pointer to the length of the resource range to be modified by the\r
1996 attributes specified by Attributes.\r
1997\r
1998 @retval EFI_SUCCESS The set of attributes specified by Attributes for the resource\r
1999 range specified by BarIndex, Offset, and Length were\r
2000 set on the PCI controller, and the actual resource range is returned\r
2001 in Offset and Length.\r
2002 @retval EFI_INVALID_PARAMETER Offset or Length is NULL.\r
2003 @retval EFI_UNSUPPORTED BarIndex not valid for this PCI controller.\r
2004 @retval EFI_OUT_OF_RESOURCES There are not enough resources to set the attributes on the\r
2005 resource range specified by BarIndex, Offset, and\r
2006 Length.\r
2007\r
2008**/\r
2009EFI_STATUS\r
2010EFIAPI\r
2011PciIoSetBarAttributes (\r
2012 IN EFI_PCI_IO_PROTOCOL *This,\r
2013 IN UINT64 Attributes,\r
2014 IN UINT8 BarIndex,\r
2015 IN OUT UINT64 *Offset,\r
2016 IN OUT UINT64 *Length\r
2017 )\r
2018{\r
2019 EFI_STATUS Status;\r
2020 PCI_IO_DEVICE *PciIoDevice;\r
2021 UINT64 NonRelativeOffset;\r
2022 UINT64 Supports;\r
2023\r
2024 PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);\r
2025\r
2026 //\r
2027 // Make sure Offset and Length are not NULL\r
2028 //\r
2029 if ((Offset == NULL) || (Length == NULL)) {\r
2030 return EFI_INVALID_PARAMETER;\r
2031 }\r
2032\r
2033 if (PciIoDevice->PciBar[BarIndex].BarType == PciBarTypeUnknown) {\r
2034 return EFI_UNSUPPORTED;\r
2035 }\r
2036\r
2037 //\r
2038 // This driver does not support setting the WRITE_COMBINE or the CACHED attributes.\r
2039 // If Attributes is not 0, then return EFI_UNSUPPORTED.\r
2040 //\r
2041 Supports = PciIoDevice->Supports & EFI_PCI_IO_ATTRIBUTE_MEMORY_CACHED & EFI_PCI_IO_ATTRIBUTE_MEMORY_WRITE_COMBINE;\r
2042\r
2043 if (Attributes != (Attributes & Supports)) {\r
2044 return EFI_UNSUPPORTED;\r
2045 }\r
2046\r
2047 //\r
2048 // Attributes must be supported. Make sure the BAR range described by BarIndex, Offset, and\r
2049 // Length are valid for this PCI device.\r
2050 //\r
2051 NonRelativeOffset = *Offset;\r
2052 Status = PciIoVerifyBarAccess (\r
2053 PciIoDevice,\r
2054 BarIndex,\r
2055 PciBarTypeMem,\r
2056 EfiPciIoWidthUint8,\r
2057 (UINT32)*Length,\r
2058 &NonRelativeOffset\r
2059 );\r
2060 if (EFI_ERROR (Status)) {\r
2061 return EFI_UNSUPPORTED;\r
2062 }\r
2063\r
2064 return EFI_SUCCESS;\r
2065}\r
2066\r
2067/**\r
2068 Test whether two Pci devices has same parent bridge.\r
2069\r
2070 @param PciDevice1 The first pci device for testing.\r
2071 @param PciDevice2 The second pci device for testing.\r
2072\r
2073 @retval TRUE Two Pci device has the same parent bridge.\r
2074 @retval FALSE Two Pci device has not the same parent bridge.\r
2075\r
2076**/\r
2077BOOLEAN\r
2078PciDevicesOnTheSamePath (\r
2079 IN PCI_IO_DEVICE *PciDevice1,\r
2080 IN PCI_IO_DEVICE *PciDevice2\r
2081 )\r
2082{\r
2083 BOOLEAN Existed1;\r
2084 BOOLEAN Existed2;\r
2085\r
2086 if (PciDevice1->Parent == PciDevice2->Parent) {\r
2087 return TRUE;\r
2088 }\r
2089\r
2090 Existed1 = PciDeviceExisted (PciDevice1->Parent, PciDevice2);\r
2091 Existed2 = PciDeviceExisted (PciDevice2->Parent, PciDevice1);\r
2092\r
2093 return (BOOLEAN)(Existed1 || Existed2);\r
2094}\r
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