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1 | /** @file\r | |
2 | \r | |
3 | Copyright (c) 2004 - 2007, Intel Corporation\r | |
4 | All rights reserved. This program and the accompanying materials\r | |
5 | are licensed and made available under the terms and conditions of the BSD License\r | |
6 | which accompanies this distribution. The full text of the license may be found at\r | |
7 | http://opensource.org/licenses/bsd-license.php\r | |
8 | \r | |
9 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
10 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
11 | \r | |
12 | Module Name:\r | |
13 | \r | |
14 | Uhci.h\r | |
15 | \r | |
16 | Abstract:\r | |
17 | \r | |
18 | The definition for UHCI driver model and HC protocol routines.\r | |
19 | \r | |
20 | Revision History\r | |
21 | \r | |
22 | \r | |
23 | **/\r | |
24 | \r | |
25 | #ifndef _UHCI_H\r | |
26 | #define _UHCI_H\r | |
27 | \r | |
28 | //\r | |
29 | // The package level header files this module uses\r | |
30 | //\r | |
31 | #include <PiDxe.h>\r | |
32 | //\r | |
33 | // The protocols, PPI and GUID defintions for this module\r | |
34 | //\r | |
35 | #include <Protocol/Usb2HostController.h>\r | |
36 | #include <Protocol/UsbHostController.h>\r | |
37 | #include <Protocol/PciIo.h>\r | |
38 | //\r | |
39 | // The Library classes this module consumes\r | |
40 | //\r | |
41 | #include <Library/DebugLib.h>\r | |
42 | #include <Library/BaseMemoryLib.h>\r | |
43 | #include <Library/UefiDriverEntryPoint.h>\r | |
44 | #include <Library/UefiBootServicesTableLib.h>\r | |
45 | #include <Library/UefiLib.h>\r | |
46 | #include <Library/BaseLib.h>\r | |
47 | #include <Library/MemoryAllocationLib.h>\r | |
48 | \r | |
49 | #include <IndustryStandard/Pci22.h>\r | |
50 | \r | |
51 | typedef struct _USB_HC_DEV USB_HC_DEV;\r | |
52 | \r | |
53 | #include "UsbHcMem.h"\r | |
54 | #include "UhciQueue.h"\r | |
55 | #include "UhciReg.h"\r | |
56 | #include "UhciSched.h"\r | |
57 | #include "UhciDebug.h"\r | |
58 | \r | |
59 | enum {\r | |
60 | //\r | |
61 | // Stall times\r | |
62 | //\r | |
63 | STALL_1_MS = 1000,\r | |
64 | STALL_1_SECOND = 1000 *STALL_1_MS,\r | |
65 | \r | |
66 | UHC_SYN_POLL = 50,\r | |
67 | FORCE_GLOBAL_RESUME_TIME = 20 *STALL_1_MS,\r | |
68 | ROOT_PORT_REST_TIME = 50 *STALL_1_MS,\r | |
69 | PORT_RESET_RECOVERY_TIME = 10 *STALL_1_MS,\r | |
70 | INTERRUPT_POLLING_TIME = 50 * 10000UL,\r | |
71 | \r | |
72 | //\r | |
73 | // UHC raises TPL to TPL_NOTIFY to serialize all its operations\r | |
74 | // to protect shared data structures.\r | |
75 | //\r | |
76 | UHCI_TPL = TPL_NOTIFY,\r | |
77 | \r | |
78 | USB_HC_DEV_SIGNATURE = EFI_SIGNATURE_32 ('u', 'h', 'c', 'i')\r | |
79 | };\r | |
80 | \r | |
81 | #pragma pack(1)\r | |
82 | typedef struct {\r | |
83 | UINT8 PI;\r | |
84 | UINT8 SubClassCode;\r | |
85 | UINT8 BaseCode;\r | |
86 | } USB_CLASSC;\r | |
87 | #pragma pack()\r | |
88 | \r | |
89 | #define UHC_FROM_USB_HC_PROTO(This) CR(This, USB_HC_DEV, UsbHc, USB_HC_DEV_SIGNATURE)\r | |
90 | #define UHC_FROM_USB2_HC_PROTO(This) CR(This, USB_HC_DEV, Usb2Hc, USB_HC_DEV_SIGNATURE)\r | |
91 | \r | |
92 | //\r | |
93 | // USB_HC_DEV support the UHCI hardware controller. It schedules\r | |
94 | // the asynchronous interrupt transfer with the same method as\r | |
95 | // EHCI: a reversed tree structure. For synchronous interrupt,\r | |
96 | // control and bulk transfer, it uses three static queue head to\r | |
97 | // schedule them. SyncIntQh is for interrupt transfer. LsCtrlQh is\r | |
98 | // for LOW speed control transfer, and FsCtrlBulkQh is for FULL\r | |
99 | // speed control or bulk transfer. This is because FULL speed contrl\r | |
100 | // or bulk transfer can reclaim the unused bandwidth. Some USB\r | |
101 | // device requires this bandwidth reclamation capability.\r | |
102 | //\r | |
103 | struct _USB_HC_DEV {\r | |
104 | UINT32 Signature;\r | |
105 | EFI_USB_HC_PROTOCOL UsbHc;\r | |
106 | EFI_USB2_HC_PROTOCOL Usb2Hc;\r | |
107 | EFI_PCI_IO_PROTOCOL *PciIo;\r | |
108 | \r | |
109 | //\r | |
110 | // Schedule data structures\r | |
111 | //\r | |
112 | UINT32 *FrameBase;\r | |
113 | UHCI_QH_SW *SyncIntQh;\r | |
114 | UHCI_QH_SW *CtrlQh;\r | |
115 | UHCI_QH_SW *BulkQh;\r | |
116 | \r | |
117 | //\r | |
118 | // Structures to maintain asynchronus interrupt transfers.\r | |
119 | // When asynchronous interrutp transfer is unlinked from\r | |
120 | // the frame list, the hardware may still hold a pointer\r | |
121 | // to it. To synchronize with hardware, its resoureces are\r | |
122 | // released in two steps using Recycle and RecycleWait.\r | |
123 | // Check the asynchronous interrupt management routines.\r | |
124 | //\r | |
125 | LIST_ENTRY AsyncIntList;\r | |
126 | EFI_EVENT AsyncIntMonitor;\r | |
127 | UHCI_ASYNC_REQUEST *Recycle;\r | |
128 | UHCI_ASYNC_REQUEST *RecycleWait;\r | |
129 | \r | |
130 | \r | |
131 | UINTN RootPorts;\r | |
132 | USBHC_MEM_POOL *MemPool;\r | |
133 | EFI_UNICODE_STRING_TABLE *CtrlNameTable;\r | |
134 | VOID *FrameMapping;\r | |
135 | };\r | |
136 | \r | |
137 | extern EFI_DRIVER_BINDING_PROTOCOL gUhciDriverBinding;\r | |
138 | extern EFI_COMPONENT_NAME_PROTOCOL gUhciComponentName;\r | |
139 | \r | |
140 | #endif\r |