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1 | /** @file\r | |
2 | \r | |
3 | The UHCI register operation routines.\r | |
4 | \r | |
5 | Copyright (c) 2007, Intel Corporation. All rights reserved.<BR>\r | |
6 | This program and the accompanying materials\r | |
7 | are licensed and made available under the terms and conditions of the BSD License\r | |
8 | which accompanies this distribution. The full text of the license may be found at\r | |
9 | http://opensource.org/licenses/bsd-license.php\r | |
10 | \r | |
11 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
12 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
13 | \r | |
14 | **/\r | |
15 | \r | |
16 | #include "Uhci.h"\r | |
17 | \r | |
18 | \r | |
19 | /**\r | |
20 | Read a UHCI register.\r | |
21 | \r | |
22 | @param PciIo The EFI_PCI_IO_PROTOCOL to use.\r | |
23 | @param Offset Register offset to USB_BAR_INDEX.\r | |
24 | \r | |
25 | @return Content of register.\r | |
26 | \r | |
27 | **/\r | |
28 | UINT16\r | |
29 | UhciReadReg (\r | |
30 | IN EFI_PCI_IO_PROTOCOL *PciIo,\r | |
31 | IN UINT32 Offset\r | |
32 | )\r | |
33 | {\r | |
34 | UINT16 Data;\r | |
35 | EFI_STATUS Status;\r | |
36 | \r | |
37 | Status = PciIo->Io.Read (\r | |
38 | PciIo,\r | |
39 | EfiPciIoWidthUint16,\r | |
40 | USB_BAR_INDEX,\r | |
41 | Offset,\r | |
42 | 1,\r | |
43 | &Data\r | |
44 | );\r | |
45 | \r | |
46 | if (EFI_ERROR (Status)) {\r | |
47 | DEBUG ((EFI_D_ERROR, "UhciReadReg: PciIo Io.Read error: %r at offset %d\n", Status, Offset));\r | |
48 | \r | |
49 | Data = 0xFFFF;\r | |
50 | }\r | |
51 | \r | |
52 | return Data;\r | |
53 | }\r | |
54 | \r | |
55 | \r | |
56 | /**\r | |
57 | Write data to UHCI register.\r | |
58 | \r | |
59 | @param PciIo The EFI_PCI_IO_PROTOCOL to use.\r | |
60 | @param Offset Register offset to USB_BAR_INDEX.\r | |
61 | @param Data Data to write.\r | |
62 | \r | |
63 | **/\r | |
64 | VOID\r | |
65 | UhciWriteReg (\r | |
66 | IN EFI_PCI_IO_PROTOCOL *PciIo,\r | |
67 | IN UINT32 Offset,\r | |
68 | IN UINT16 Data\r | |
69 | )\r | |
70 | {\r | |
71 | EFI_STATUS Status;\r | |
72 | \r | |
73 | Status = PciIo->Io.Write (\r | |
74 | PciIo,\r | |
75 | EfiPciIoWidthUint16,\r | |
76 | USB_BAR_INDEX,\r | |
77 | Offset,\r | |
78 | 1,\r | |
79 | &Data\r | |
80 | );\r | |
81 | \r | |
82 | if (EFI_ERROR (Status)) {\r | |
83 | DEBUG ((EFI_D_ERROR, "UhciWriteReg: PciIo Io.Write error: %r at offset %d\n", Status, Offset));\r | |
84 | }\r | |
85 | }\r | |
86 | \r | |
87 | \r | |
88 | /**\r | |
89 | Set a bit of the UHCI Register.\r | |
90 | \r | |
91 | @param PciIo The EFI_PCI_IO_PROTOCOL to use.\r | |
92 | @param Offset Register offset to USB_BAR_INDEX.\r | |
93 | @param Bit The bit to set.\r | |
94 | \r | |
95 | **/\r | |
96 | VOID\r | |
97 | UhciSetRegBit (\r | |
98 | IN EFI_PCI_IO_PROTOCOL *PciIo,\r | |
99 | IN UINT32 Offset,\r | |
100 | IN UINT16 Bit\r | |
101 | )\r | |
102 | {\r | |
103 | UINT16 Data;\r | |
104 | \r | |
105 | Data = UhciReadReg (PciIo, Offset);\r | |
106 | Data = (UINT16) (Data |Bit);\r | |
107 | UhciWriteReg (PciIo, Offset, Data);\r | |
108 | }\r | |
109 | \r | |
110 | \r | |
111 | /**\r | |
112 | Clear a bit of the UHCI Register.\r | |
113 | \r | |
114 | @param PciIo The PCI_IO protocol to access the PCI.\r | |
115 | @param Offset Register offset to USB_BAR_INDEX.\r | |
116 | @param Bit The bit to clear.\r | |
117 | \r | |
118 | **/\r | |
119 | VOID\r | |
120 | UhciClearRegBit (\r | |
121 | IN EFI_PCI_IO_PROTOCOL *PciIo,\r | |
122 | IN UINT32 Offset,\r | |
123 | IN UINT16 Bit\r | |
124 | )\r | |
125 | {\r | |
126 | UINT16 Data;\r | |
127 | \r | |
128 | Data = UhciReadReg (PciIo, Offset);\r | |
129 | Data = (UINT16) (Data & ~Bit);\r | |
130 | UhciWriteReg (PciIo, Offset, Data);\r | |
131 | }\r | |
132 | \r | |
133 | \r | |
134 | /**\r | |
135 | Clear all the interrutp status bits, these bits\r | |
136 | are Write-Clean.\r | |
137 | \r | |
138 | @param Uhc The UHCI device.\r | |
139 | \r | |
140 | **/\r | |
141 | VOID\r | |
142 | UhciAckAllInterrupt (\r | |
143 | IN USB_HC_DEV *Uhc\r | |
144 | )\r | |
145 | {\r | |
146 | UhciWriteReg (Uhc->PciIo, USBSTS_OFFSET, 0x3F);\r | |
147 | \r | |
148 | //\r | |
149 | // If current HC is halted, re-enable it. Host Controller Process Error\r | |
150 | // is a temporary error status.\r | |
151 | //\r | |
152 | if (!UhciIsHcWorking (Uhc->PciIo)) {\r | |
153 | DEBUG ((EFI_D_ERROR, "UhciAckAllInterrupt: re-enable the UHCI from system error\n"));\r | |
154 | Uhc->Usb2Hc.SetState (&Uhc->Usb2Hc, EfiUsbHcStateOperational);\r | |
155 | }\r | |
156 | }\r | |
157 | \r | |
158 | \r | |
159 | /**\r | |
160 | Stop the host controller.\r | |
161 | \r | |
162 | @param Uhc The UHCI device.\r | |
163 | @param Timeout Max time allowed.\r | |
164 | \r | |
165 | @retval EFI_SUCCESS The host controller is stopped.\r | |
166 | @retval EFI_TIMEOUT Failed to stop the host controller.\r | |
167 | \r | |
168 | **/\r | |
169 | EFI_STATUS\r | |
170 | UhciStopHc (\r | |
171 | IN USB_HC_DEV *Uhc,\r | |
172 | IN UINTN Timeout\r | |
173 | )\r | |
174 | {\r | |
175 | UINT16 UsbSts;\r | |
176 | UINTN Index;\r | |
177 | \r | |
178 | UhciClearRegBit (Uhc->PciIo, USBCMD_OFFSET, USBCMD_RS);\r | |
179 | \r | |
180 | //\r | |
181 | // ensure the HC is in halt status after send the stop command\r | |
182 | // Timeout is in us unit.\r | |
183 | //\r | |
184 | for (Index = 0; Index < (Timeout / 50) + 1; Index++) {\r | |
185 | UsbSts = UhciReadReg (Uhc->PciIo, USBSTS_OFFSET);\r | |
186 | \r | |
187 | if ((UsbSts & USBSTS_HCH) == USBSTS_HCH) {\r | |
188 | return EFI_SUCCESS;\r | |
189 | }\r | |
190 | \r | |
191 | gBS->Stall (50);\r | |
192 | }\r | |
193 | \r | |
194 | return EFI_TIMEOUT;\r | |
195 | }\r | |
196 | \r | |
197 | \r | |
198 | /**\r | |
199 | Check whether the host controller operates well.\r | |
200 | \r | |
201 | @param PciIo The PCI_IO protocol to use.\r | |
202 | \r | |
203 | @retval TRUE Host controller is working.\r | |
204 | @retval FALSE Host controller is halted or system error.\r | |
205 | \r | |
206 | **/\r | |
207 | BOOLEAN\r | |
208 | UhciIsHcWorking (\r | |
209 | IN EFI_PCI_IO_PROTOCOL *PciIo\r | |
210 | )\r | |
211 | {\r | |
212 | UINT16 UsbSts;\r | |
213 | \r | |
214 | UsbSts = UhciReadReg (PciIo, USBSTS_OFFSET);\r | |
215 | \r | |
216 | if ((UsbSts & (USBSTS_HCPE | USBSTS_HSE | USBSTS_HCH)) != 0) {\r | |
217 | DEBUG ((EFI_D_ERROR, "UhciIsHcWorking: current USB state is %x\n", UsbSts));\r | |
218 | return FALSE;\r | |
219 | }\r | |
220 | \r | |
221 | return TRUE;\r | |
222 | }\r | |
223 | \r | |
224 | \r | |
225 | /**\r | |
226 | Set the UHCI frame list base address. It can't use\r | |
227 | UhciWriteReg which access memory in UINT16.\r | |
228 | \r | |
229 | @param PciIo The EFI_PCI_IO_PROTOCOL to use.\r | |
230 | @param Addr Address to set.\r | |
231 | \r | |
232 | **/\r | |
233 | VOID\r | |
234 | UhciSetFrameListBaseAddr (\r | |
235 | IN EFI_PCI_IO_PROTOCOL *PciIo,\r | |
236 | IN VOID *Addr\r | |
237 | )\r | |
238 | {\r | |
239 | EFI_STATUS Status;\r | |
240 | UINT32 Data;\r | |
241 | \r | |
242 | Data = (UINT32) ((UINTN) Addr & 0xFFFFF000);\r | |
243 | \r | |
244 | Status = PciIo->Io.Write (\r | |
245 | PciIo,\r | |
246 | EfiPciIoWidthUint32,\r | |
247 | USB_BAR_INDEX,\r | |
248 | (UINT64) USB_FRAME_BASE_OFFSET,\r | |
249 | 1,\r | |
250 | &Data\r | |
251 | );\r | |
252 | \r | |
253 | if (EFI_ERROR (Status)) {\r | |
254 | DEBUG ((EFI_D_ERROR, "UhciSetFrameListBaseAddr: PciIo Io.Write error: %r\n", Status));\r | |
255 | }\r | |
256 | }\r | |
257 | \r | |
258 | \r | |
259 | /**\r | |
260 | Disable USB Emulation.\r | |
261 | \r | |
262 | @param PciIo The EFI_PCI_IO_PROTOCOL protocol to use.\r | |
263 | \r | |
264 | **/\r | |
265 | VOID\r | |
266 | UhciTurnOffUsbEmulation (\r | |
267 | IN EFI_PCI_IO_PROTOCOL *PciIo\r | |
268 | )\r | |
269 | {\r | |
270 | UINT16 Command;\r | |
271 | \r | |
272 | Command = 0;\r | |
273 | \r | |
274 | PciIo->Pci.Write (\r | |
275 | PciIo,\r | |
276 | EfiPciIoWidthUint16,\r | |
277 | USB_EMULATION_OFFSET,\r | |
278 | 1,\r | |
279 | &Command\r | |
280 | );\r | |
281 | }\r |