]>
Commit | Line | Data |
---|---|---|
1 | /** @file\r | |
2 | Task priority (TPL) functions.\r | |
3 | \r | |
4 | Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>\r | |
5 | SPDX-License-Identifier: BSD-2-Clause-Patent\r | |
6 | \r | |
7 | **/\r | |
8 | \r | |
9 | #include "DxeMain.h"\r | |
10 | #include "Event.h"\r | |
11 | \r | |
12 | /**\r | |
13 | Set Interrupt State.\r | |
14 | \r | |
15 | @param Enable The state of enable or disable interrupt\r | |
16 | \r | |
17 | **/\r | |
18 | VOID\r | |
19 | CoreSetInterruptState (\r | |
20 | IN BOOLEAN Enable\r | |
21 | )\r | |
22 | {\r | |
23 | EFI_STATUS Status;\r | |
24 | BOOLEAN InSmm;\r | |
25 | \r | |
26 | if (gCpu == NULL) {\r | |
27 | return;\r | |
28 | }\r | |
29 | \r | |
30 | if (!Enable) {\r | |
31 | gCpu->DisableInterrupt (gCpu);\r | |
32 | return;\r | |
33 | }\r | |
34 | \r | |
35 | if (gSmmBase2 == NULL) {\r | |
36 | gCpu->EnableInterrupt (gCpu);\r | |
37 | return;\r | |
38 | }\r | |
39 | \r | |
40 | Status = gSmmBase2->InSmm (gSmmBase2, &InSmm);\r | |
41 | if (!EFI_ERROR (Status) && !InSmm) {\r | |
42 | gCpu->EnableInterrupt (gCpu);\r | |
43 | }\r | |
44 | }\r | |
45 | \r | |
46 | /**\r | |
47 | Raise the task priority level to the new level.\r | |
48 | High level is implemented by disabling processor interrupts.\r | |
49 | \r | |
50 | @param NewTpl New task priority level\r | |
51 | \r | |
52 | @return The previous task priority level\r | |
53 | \r | |
54 | **/\r | |
55 | EFI_TPL\r | |
56 | EFIAPI\r | |
57 | CoreRaiseTpl (\r | |
58 | IN EFI_TPL NewTpl\r | |
59 | )\r | |
60 | {\r | |
61 | EFI_TPL OldTpl;\r | |
62 | \r | |
63 | OldTpl = gEfiCurrentTpl;\r | |
64 | if (OldTpl > NewTpl) {\r | |
65 | DEBUG ((DEBUG_ERROR, "FATAL ERROR - RaiseTpl with OldTpl(0x%x) > NewTpl(0x%x)\n", OldTpl, NewTpl));\r | |
66 | ASSERT (FALSE);\r | |
67 | }\r | |
68 | \r | |
69 | ASSERT (VALID_TPL (NewTpl));\r | |
70 | \r | |
71 | //\r | |
72 | // If raising to high level, disable interrupts\r | |
73 | //\r | |
74 | if ((NewTpl >= TPL_HIGH_LEVEL) && (OldTpl < TPL_HIGH_LEVEL)) {\r | |
75 | CoreSetInterruptState (FALSE);\r | |
76 | }\r | |
77 | \r | |
78 | //\r | |
79 | // Set the new value\r | |
80 | //\r | |
81 | gEfiCurrentTpl = NewTpl;\r | |
82 | \r | |
83 | return OldTpl;\r | |
84 | }\r | |
85 | \r | |
86 | /**\r | |
87 | Lowers the task priority to the previous value. If the new\r | |
88 | priority unmasks events at a higher priority, they are dispatched.\r | |
89 | \r | |
90 | @param NewTpl New, lower, task priority\r | |
91 | \r | |
92 | **/\r | |
93 | VOID\r | |
94 | EFIAPI\r | |
95 | CoreRestoreTpl (\r | |
96 | IN EFI_TPL NewTpl\r | |
97 | )\r | |
98 | {\r | |
99 | EFI_TPL OldTpl;\r | |
100 | EFI_TPL PendingTpl;\r | |
101 | \r | |
102 | OldTpl = gEfiCurrentTpl;\r | |
103 | if (NewTpl > OldTpl) {\r | |
104 | DEBUG ((DEBUG_ERROR, "FATAL ERROR - RestoreTpl with NewTpl(0x%x) > OldTpl(0x%x)\n", NewTpl, OldTpl));\r | |
105 | ASSERT (FALSE);\r | |
106 | }\r | |
107 | \r | |
108 | ASSERT (VALID_TPL (NewTpl));\r | |
109 | \r | |
110 | //\r | |
111 | // If lowering below HIGH_LEVEL, make sure\r | |
112 | // interrupts are enabled\r | |
113 | //\r | |
114 | \r | |
115 | if ((OldTpl >= TPL_HIGH_LEVEL) && (NewTpl < TPL_HIGH_LEVEL)) {\r | |
116 | gEfiCurrentTpl = TPL_HIGH_LEVEL;\r | |
117 | }\r | |
118 | \r | |
119 | //\r | |
120 | // Dispatch any pending events\r | |
121 | //\r | |
122 | while (gEventPending != 0) {\r | |
123 | PendingTpl = (UINTN)HighBitSet64 (gEventPending);\r | |
124 | if (PendingTpl <= NewTpl) {\r | |
125 | break;\r | |
126 | }\r | |
127 | \r | |
128 | gEfiCurrentTpl = PendingTpl;\r | |
129 | if (gEfiCurrentTpl < TPL_HIGH_LEVEL) {\r | |
130 | CoreSetInterruptState (TRUE);\r | |
131 | }\r | |
132 | \r | |
133 | CoreDispatchEventNotifies (gEfiCurrentTpl);\r | |
134 | }\r | |
135 | \r | |
136 | //\r | |
137 | // Set the new value\r | |
138 | //\r | |
139 | \r | |
140 | gEfiCurrentTpl = NewTpl;\r | |
141 | \r | |
142 | //\r | |
143 | // If lowering below HIGH_LEVEL, make sure\r | |
144 | // interrupts are enabled\r | |
145 | //\r | |
146 | if (gEfiCurrentTpl < TPL_HIGH_LEVEL) {\r | |
147 | CoreSetInterruptState (TRUE);\r | |
148 | }\r | |
149 | }\r |