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1 | /** @file\r | |
2 | Main SAL API's defined in Intel Itanium Processor Family System Abstraction\r | |
3 | Layer Specification Revision 3.2 (December 2003)\r | |
4 | \r | |
5 | Copyright (c) 2006 - 2008, Intel Corporation \r | |
6 | All rights reserved. This program and the accompanying materials \r | |
7 | are licensed and made available under the terms and conditions of the BSD License \r | |
8 | which accompanies this distribution. The full text of the license may be found at \r | |
9 | http://opensource.org/licenses/bsd-license.php \r | |
10 | \r | |
11 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r | |
12 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r | |
13 | \r | |
14 | **/\r | |
15 | \r | |
16 | #ifndef __SAL_API_H__\r | |
17 | #define __SAL_API_H__\r | |
18 | \r | |
19 | ///\r | |
20 | /// SAL return status type \r | |
21 | ///\r | |
22 | typedef UINTN EFI_SAL_STATUS;\r | |
23 | \r | |
24 | ///\r | |
25 | /// Call completed without error. \r | |
26 | ///\r | |
27 | #define EFI_SAL_SUCCESS ((EFI_SAL_STATUS) 0)\r | |
28 | ///\r | |
29 | /// Call completed without error but some information was lost due to overflow. \r | |
30 | ///\r | |
31 | #define EFI_SAL_OVERFLOW ((EFI_SAL_STATUS) 1)\r | |
32 | ///\r | |
33 | /// Call completed without error; effect a warm boot of the system to complete the update.\r | |
34 | ///\r | |
35 | #define EFI_SAL_WARM_BOOT_NEEDED ((EFI_SAL_STATUS) 2)\r | |
36 | ///\r | |
37 | /// More information is available for retrieval. \r | |
38 | ///\r | |
39 | #define EFI_SAL_MORE_RECORDS ((EFI_SAL_STATUS) 3)\r | |
40 | ///\r | |
41 | /// Not implemented.\r | |
42 | ///\r | |
43 | #define EFI_SAL_NOT_IMPLEMENTED ((EFI_SAL_STATUS) - 1)\r | |
44 | ///\r | |
45 | /// Invalid Argument.\r | |
46 | ///\r | |
47 | #define EFI_SAL_INVALID_ARGUMENT ((EFI_SAL_STATUS) - 2)\r | |
48 | ///\r | |
49 | /// Call completed without error. \r | |
50 | ///\r | |
51 | #define EFI_SAL_ERROR ((EFI_SAL_STATUS) - 3)\r | |
52 | ///\r | |
53 | /// Virtual address not registered. \r | |
54 | ///\r | |
55 | #define EFI_SAL_VIRTUAL_ADDRESS_ERROR ((EFI_SAL_STATUS) - 4)\r | |
56 | ///\r | |
57 | /// No information available. \r | |
58 | ///\r | |
59 | #define EFI_SAL_NO_INFORMATION ((EFI_SAL_STATUS) - 5)\r | |
60 | ///\r | |
61 | /// Scratch buffer required.\r | |
62 | ///\r | |
63 | #define EFI_SAL_NOT_ENOUGH_SCRATCH ((EFI_SAL_STATUS) - 9)\r | |
64 | \r | |
65 | ///\r | |
66 | /// Return registers from SAL\r | |
67 | ///\r | |
68 | typedef struct {\r | |
69 | ///\r | |
70 | /// SAL return status value in r8\r | |
71 | ///\r | |
72 | EFI_SAL_STATUS Status;\r | |
73 | ///\r | |
74 | /// SAL returned value in r9\r | |
75 | ///\r | |
76 | UINTN r9;\r | |
77 | ///\r | |
78 | /// SAL returned value in r10\r | |
79 | ///\r | |
80 | UINTN r10;\r | |
81 | ///\r | |
82 | /// SAL returned value in r11\r | |
83 | ///\r | |
84 | UINTN r11;\r | |
85 | } SAL_RETURN_REGS;\r | |
86 | \r | |
87 | /**\r | |
88 | Prototype of SAL procedures.\r | |
89 | \r | |
90 | @param Arg0 Functional identifier.\r | |
91 | The upper 32 bits are ignored and only the lower 32 bits\r | |
92 | are used. The following functional identifiers are defined:\r | |
93 | 0x01XXXXXX - Architected SAL functional group.\r | |
94 | 0x02XXXXXX to 0x03XXXXXX - OEM SAL functional group. Each OEM is\r | |
95 | allowed to use the entire range in the 0x02XXXXXX to 0x03XXXXXX range.\r | |
96 | 0x04XXXXXX to 0xFFFFFFFF - Reserved.\r | |
97 | @param Arg1 The first parameter of the architected/OEM specific SAL functions.\r | |
98 | @param Arg2 The second parameter of the architected/OEM specific SAL functions.\r | |
99 | @param Arg3 The third parameter passed to the ESAL function based\r | |
100 | @param Arg4 The fourth parameter passed to the ESAL function based\r | |
101 | @param Arg5 The fifth parameter passed to the ESAL function based\r | |
102 | @param Arg6 The sixth parameter passed to the ESAL function\r | |
103 | @param Arg7 The seventh parameter passed to the ESAL function based\r | |
104 | \r | |
105 | @return r8 Return status: positive number indicates successful,\r | |
106 | negative number indicates failure.\r | |
107 | r9 Other return parameter in r9.\r | |
108 | r10 Other return parameter in r10.\r | |
109 | r11 Other return parameter in r11.\r | |
110 | \r | |
111 | **/\r | |
112 | typedef\r | |
113 | SAL_RETURN_REGS\r | |
114 | (EFIAPI *SAL_PROC) (\r | |
115 | IN UINT64 FunctionId,\r | |
116 | IN UINT64 Arg2,\r | |
117 | IN UINT64 Arg3,\r | |
118 | IN UINT64 Arg4,\r | |
119 | IN UINT64 Arg5,\r | |
120 | IN UINT64 Arg6,\r | |
121 | IN UINT64 Arg7,\r | |
122 | IN UINT64 Arg8\r | |
123 | );\r | |
124 | \r | |
125 | //\r | |
126 | // SAL Procedure FunctionId definition\r | |
127 | //\r | |
128 | \r | |
129 | ///\r | |
130 | /// Register software code locations with SAL.\r | |
131 | ///\r | |
132 | #define EFI_SAL_SET_VECTORS 0x01000000\r | |
133 | ///\r | |
134 | /// Return Machine State information obtained by SAL.\r | |
135 | ///\r | |
136 | #define EFI_SAL_GET_STATE_INFO 0x01000001\r | |
137 | ///\r | |
138 | /// Obtain size of Machine State information.\r | |
139 | ///\r | |
140 | #define EFI_SAL_GET_STATE_INFO_SIZE 0x01000002\r | |
141 | ///\r | |
142 | /// Clear Machine State information.\r | |
143 | ///\r | |
144 | #define EFI_SAL_CLEAR_STATE_INFO 0x01000003\r | |
145 | ///\r | |
146 | /// Cause the processor to go into a spin loop within SAL.\r | |
147 | ///\r | |
148 | #define EFI_SAL_MC_RENDEZ 0x01000004\r | |
149 | ///\r | |
150 | /// Register the machine check interface layer with SAL.\r | |
151 | ///\r | |
152 | #define EFI_SAL_MC_SET_PARAMS 0x01000005\r | |
153 | ///\r | |
154 | /// Register the physical addresses of locations needed by SAL.\r | |
155 | ///\r | |
156 | #define EFI_SAL_REGISTER_PHYSICAL_ADDR 0x01000006\r | |
157 | ///\r | |
158 | /// Flush the instruction or data caches.\r | |
159 | ///\r | |
160 | #define EFI_SAL_CACHE_FLUSH 0x01000008\r | |
161 | ///\r | |
162 | /// Initialize the instruction and data caches.\r | |
163 | ///\r | |
164 | #define EFI_SAL_CACHE_INIT 0x01000009\r | |
165 | ///\r | |
166 | /// Read from the PCI configuration space.\r | |
167 | ///\r | |
168 | #define EFI_SAL_PCI_CONFIG_READ 0x01000010\r | |
169 | ///\r | |
170 | /// Write to the PCI configuration space.\r | |
171 | ///\r | |
172 | #define EFI_SAL_PCI_CONFIG_WRITE 0x01000011\r | |
173 | ///\r | |
174 | /// Return the base frequency of the platform.\r | |
175 | ///\r | |
176 | #define EFI_SAL_FREQ_BASE 0x01000012\r | |
177 | ///\r | |
178 | /// Returns information on the physical processor mapping within the platform.\r | |
179 | ///\r | |
180 | #define EFI_SAL_PHYSICAL_ID_INFO 0x01000013\r | |
181 | ///\r | |
182 | /// Update the contents of firmware blocks.\r | |
183 | ///\r | |
184 | #define EFI_SAL_UPDATE_PAL 0x01000020\r | |
185 | \r | |
186 | #define EFI_SAL_FUNCTION_ID_MASK 0x0000ffff\r | |
187 | #define EFI_SAL_MAX_SAL_FUNCTION_ID 0x00000021\r | |
188 | \r | |
189 | //\r | |
190 | // SAL Procedure parameter definitions\r | |
191 | // Not much point in using typedefs or enums because all params\r | |
192 | // are UINT64 and the entry point is common\r | |
193 | //\r | |
194 | \r | |
195 | //\r | |
196 | // Parameter of EFI_SAL_SET_VECTORS\r | |
197 | //\r | |
198 | // Vector type\r | |
199 | //\r | |
200 | #define EFI_SAL_SET_MCA_VECTOR 0x0\r | |
201 | #define EFI_SAL_SET_INIT_VECTOR 0x1\r | |
202 | #define EFI_SAL_SET_BOOT_RENDEZ_VECTOR 0x2\r | |
203 | ///\r | |
204 | /// Format of length_cs_n argument.\r | |
205 | ///\r | |
206 | typedef struct {\r | |
207 | UINT64 Length : 32;\r | |
208 | UINT64 ChecksumValid : 1;\r | |
209 | UINT64 Reserved1 : 7;\r | |
210 | UINT64 ByteChecksum : 8;\r | |
211 | UINT64 Reserved2 : 16;\r | |
212 | } SAL_SET_VECTORS_CS_N;\r | |
213 | \r | |
214 | //\r | |
215 | // Parameter of EFI_SAL_GET_STATE_INFO, EFI_SAL_GET_STATE_INFO_SIZE, and EFI_SAL_CLEAR_STATE_INFO\r | |
216 | // \r | |
217 | // Type of information\r | |
218 | //\r | |
219 | #define EFI_SAL_MCA_STATE_INFO 0x0\r | |
220 | #define EFI_SAL_INIT_STATE_INFO 0x1\r | |
221 | #define EFI_SAL_CMC_STATE_INFO 0x2\r | |
222 | #define EFI_SAL_CP_STATE_INFO 0x3\r | |
223 | \r | |
224 | //\r | |
225 | // Parameter of EFI_SAL_MC_SET_PARAMS\r | |
226 | //\r | |
227 | // Unsigned 64-bit integer value for the parameter type of the machine check interface\r | |
228 | //\r | |
229 | #define EFI_SAL_MC_SET_RENDEZ_PARAM 0x1\r | |
230 | #define EFI_SAL_MC_SET_WAKEUP_PARAM 0x2\r | |
231 | #define EFI_SAL_MC_SET_CPE_PARAM 0x3\r | |
232 | //\r | |
233 | // Unsigned 64-bit integer value indicating whether interrupt vector or\r | |
234 | // memory address is specified\r | |
235 | //\r | |
236 | #define EFI_SAL_MC_SET_INTR_PARAM 0x1\r | |
237 | #define EFI_SAL_MC_SET_MEM_PARAM 0x2\r | |
238 | \r | |
239 | //\r | |
240 | // Parameter of EFI_SAL_REGISTER_PAL_PHYSICAL_ADDR\r | |
241 | //\r | |
242 | // The encoded value of the entity whose physical address is registered\r | |
243 | //\r | |
244 | #define EFI_SAL_REGISTER_PAL_ADDR 0x0\r | |
245 | \r | |
246 | //\r | |
247 | // Parameter of EFI_SAL_CACHE_FLUSH\r | |
248 | //\r | |
249 | // Unsigned 64-bit integer denoting type of cache flush operation\r | |
250 | //\r | |
251 | #define EFI_SAL_FLUSH_I_CACHE 0x01\r | |
252 | #define EFI_SAL_FLUSH_D_CACHE 0x02\r | |
253 | #define EFI_SAL_FLUSH_BOTH_CACHE 0x03\r | |
254 | #define EFI_SAL_FLUSH_MAKE_COHERENT 0x04\r | |
255 | \r | |
256 | //\r | |
257 | // Parameter of EFI_SAL_PCI_CONFIG_READ and EFI_SAL_PCI_CONFIG_WRITE\r | |
258 | //\r | |
259 | // PCI config size\r | |
260 | //\r | |
261 | #define EFI_SAL_PCI_CONFIG_ONE_BYTE 0x1\r | |
262 | #define EFI_SAL_PCI_CONFIG_TWO_BYTES 0x2\r | |
263 | #define EFI_SAL_PCI_CONFIG_FOUR_BYTES 0x4\r | |
264 | //\r | |
265 | // The type of PCI configuration address\r | |
266 | //\r | |
267 | #define EFI_SAL_PCI_COMPATIBLE_ADDRESS 0x0\r | |
268 | #define EFI_SAL_PCI_EXTENDED_REGISTER_ADDRESS 0x1\r | |
269 | ///\r | |
270 | /// Format of PCI Compatible Address\r | |
271 | ///\r | |
272 | typedef struct {\r | |
273 | UINT64 Register : 8;\r | |
274 | UINT64 Function : 3;\r | |
275 | UINT64 Device : 5;\r | |
276 | UINT64 Bus : 8;\r | |
277 | UINT64 Segment : 8;\r | |
278 | UINT64 Reserved : 32;\r | |
279 | } SAL_PCI_ADDRESS;\r | |
280 | ///\r | |
281 | /// Format of Extended Register Address\r | |
282 | ///\r | |
283 | typedef struct {\r | |
284 | UINT64 Register : 8;\r | |
285 | UINT64 ExtendedRegister : 4;\r | |
286 | UINT64 Function : 3;\r | |
287 | UINT64 Device : 5;\r | |
288 | UINT64 Bus : 8;\r | |
289 | UINT64 Segment : 16;\r | |
290 | UINT64 Reserved : 20;\r | |
291 | } SAL_PCI_EXTENDED_REGISTER_ADDRESS;\r | |
292 | \r | |
293 | //\r | |
294 | // Parameter of EFI_SAL_FREQ_BASE\r | |
295 | //\r | |
296 | // Unsigned 64-bit integer specifying the type of clock source\r | |
297 | //\r | |
298 | #define EFI_SAL_CPU_INPUT_FREQ_BASE 0x0\r | |
299 | #define EFI_SAL_PLATFORM_IT_FREQ_BASE 0x1\r | |
300 | #define EFI_SAL_PLATFORM_RTC_FREQ_BASE 0x2\r | |
301 | \r | |
302 | //\r | |
303 | // Parameter and return value of EFI_SAL_UPDATE_PAL\r | |
304 | //\r | |
305 | // Return parameter provides additional information on the\r | |
306 | // failure when the status field contains a value of -3,\r | |
307 | // returned in r9.\r | |
308 | //\r | |
309 | #define EFI_SAL_UPDATE_BAD_PAL_VERSION ((UINT64) -1)\r | |
310 | #define EFI_SAL_UPDATE_PAL_AUTH_FAIL ((UINT64) -2)\r | |
311 | #define EFI_SAL_UPDATE_PAL_BAD_TYPE ((UINT64) -3)\r | |
312 | #define EFI_SAL_UPDATE_PAL_READONLY ((UINT64) -4)\r | |
313 | #define EFI_SAL_UPDATE_PAL_WRITE_FAIL ((UINT64) -10)\r | |
314 | #define EFI_SAL_UPDATE_PAL_ERASE_FAIL ((UINT64) -11)\r | |
315 | #define EFI_SAL_UPDATE_PAL_READ_FAIL ((UINT64) -12)\r | |
316 | #define EFI_SAL_UPDATE_PAL_CANT_FIT ((UINT64) -13)\r | |
317 | ///\r | |
318 | /// 64-byte header of update data block.\r | |
319 | ///\r | |
320 | typedef struct {\r | |
321 | UINT32 Size;\r | |
322 | UINT32 MmddyyyyDate;\r | |
323 | UINT16 Version;\r | |
324 | UINT8 Type;\r | |
325 | UINT8 Reserved[5];\r | |
326 | UINT64 FwVendorId;\r | |
327 | } SAL_UPDATE_PAL_DATA_BLOCK;\r | |
328 | ///\r | |
329 | /// Data structure pointed by parameter param_buf.\r | |
330 | /// It is a 16-byte aligned data structure in memory with a length of 32 bytes\r | |
331 | /// that describes the new firmware. This information is organized in the form\r | |
332 | /// of a linked list with each element describing one firmware component.\r | |
333 | ///\r | |
334 | typedef struct _SAL_UPDATE_PAL_INFO_BLOCK {\r | |
335 | struct _SAL_UPDATE_PAL_INFO_BLOCK *Next;\r | |
336 | struct SAL_UPDATE_PAL_DATA_BLOCK *DataBlock;\r | |
337 | UINT8 StoreChecksum;\r | |
338 | UINT8 Reserved[15];\r | |
339 | } SAL_UPDATE_PAL_INFO_BLOCK;\r | |
340 | \r | |
341 | ///\r | |
342 | /// SAL System Table Definitions\r | |
343 | ///\r | |
344 | #pragma pack(1)\r | |
345 | typedef struct {\r | |
346 | ///\r | |
347 | /// The ASCII string representation of "SST_" which confirms the presence of the table. \r | |
348 | /// \r | |
349 | UINT32 Signature;\r | |
350 | ///\r | |
351 | /// The length of the entire table in bytes, starting from offset zero and including the\r | |
352 | /// header and all entries indicated by the EntryCount field.\r | |
353 | ///\r | |
354 | UINT32 Length;\r | |
355 | ///\r | |
356 | /// The revision number of the Itanium Processor Family System Abstraction Layer\r | |
357 | /// Specification supported by the SAL implementation in binary coded decimal (BCD) format.\r | |
358 | ///\r | |
359 | UINT16 SalRevision;\r | |
360 | ///\r | |
361 | /// The number of entries in the variable portion of the table.\r | |
362 | ///\r | |
363 | UINT16 EntryCount;\r | |
364 | ///\r | |
365 | /// A modulo checksum of the entire table and the entries following this table.\r | |
366 | ///\r | |
367 | UINT8 CheckSum;\r | |
368 | ///\r | |
369 | /// Unused, must be zero.\r | |
370 | ///\r | |
371 | UINT8 Reserved[7];\r | |
372 | ///\r | |
373 | /// Version Number of the SAL_A firmware implementation in BCD format.\r | |
374 | ///\r | |
375 | UINT16 SalAVersion;\r | |
376 | ///\r | |
377 | /// Version Number of the SAL_B firmware implementation in BCD format.\r | |
378 | ///\r | |
379 | UINT16 SalBVersion;\r | |
380 | ///\r | |
381 | /// An ASCII identification string which uniquely identifies the manufacturer\r | |
382 | /// of the system hardware.\r | |
383 | ///\r | |
384 | UINT8 OemId[32];\r | |
385 | ///\r | |
386 | /// An ASCII identification string which uniquely identifies a family of\r | |
387 | /// compatible products from the manufacturer.\r | |
388 | ///\r | |
389 | UINT8 ProductId[32];\r | |
390 | ///\r | |
391 | /// Unused, must be zero.\r | |
392 | ///\r | |
393 | UINT8 Reserved2[8];\r | |
394 | } SAL_SYSTEM_TABLE_HEADER;\r | |
395 | \r | |
396 | #define EFI_SAL_ST_HEADER_SIGNATURE "SST_"\r | |
397 | #define EFI_SAL_REVISION 0x0320\r | |
398 | //\r | |
399 | // SAL System Types\r | |
400 | //\r | |
401 | #define EFI_SAL_ST_ENTRY_POINT 0\r | |
402 | #define EFI_SAL_ST_MEMORY_DESCRIPTOR 1\r | |
403 | #define EFI_SAL_ST_PLATFORM_FEATURES 2\r | |
404 | #define EFI_SAL_ST_TR_USAGE 3\r | |
405 | #define EFI_SAL_ST_PTC 4\r | |
406 | #define EFI_SAL_ST_AP_WAKEUP 5\r | |
407 | \r | |
408 | //\r | |
409 | // SAL System Type Sizes\r | |
410 | //\r | |
411 | #define EFI_SAL_ST_ENTRY_POINT_SIZE 48\r | |
412 | #define EFI_SAL_ST_MEMORY_DESCRIPTOR_SIZE 32\r | |
413 | #define EFI_SAL_ST_PLATFORM_FEATURES_SIZE 16\r | |
414 | #define EFI_SAL_ST_TR_USAGE_SIZE 32\r | |
415 | #define EFI_SAL_ST_PTC_SIZE 16\r | |
416 | #define EFI_SAL_ST_AP_WAKEUP_SIZE 16\r | |
417 | \r | |
418 | ///\r | |
419 | /// Format of Entrypoint Descriptor Entry\r | |
420 | ///\r | |
421 | typedef struct {\r | |
422 | UINT8 Type; ///< Type here should be 0\r | |
423 | UINT8 Reserved[7];\r | |
424 | UINT64 PalProcEntry;\r | |
425 | UINT64 SalProcEntry;\r | |
426 | UINT64 SalGlobalDataPointer;\r | |
427 | UINT64 Reserved2[2];\r | |
428 | } SAL_ST_ENTRY_POINT_DESCRIPTOR;\r | |
429 | \r | |
430 | ///\r | |
431 | /// Format of Platform Features Descriptor Entry\r | |
432 | ///\r | |
433 | typedef struct {\r | |
434 | UINT8 Type; ///< Type here should be 2\r | |
435 | UINT8 PlatformFeatures;\r | |
436 | UINT8 Reserved[14];\r | |
437 | } SAL_ST_PLATFORM_FEATURES;\r | |
438 | \r | |
439 | //\r | |
440 | // Value of Platform Feature List\r | |
441 | //\r | |
442 | #define SAL_PLAT_FEAT_BUS_LOCK 0x01\r | |
443 | #define SAL_PLAT_FEAT_PLAT_IPI_HINT 0x02\r | |
444 | #define SAL_PLAT_FEAT_PROC_IPI_HINT 0x04\r | |
445 | \r | |
446 | ///\r | |
447 | /// Format of Translation Register Descriptor Entry\r | |
448 | ///\r | |
449 | typedef struct {\r | |
450 | UINT8 Type; ///< Type here should be 3\r | |
451 | UINT8 TRType;\r | |
452 | UINT8 TRNumber;\r | |
453 | UINT8 Reserved[5];\r | |
454 | UINT64 VirtualAddress;\r | |
455 | UINT64 EncodedPageSize;\r | |
456 | UINT64 Reserved1;\r | |
457 | } SAL_ST_TR_DECRIPTOR;\r | |
458 | \r | |
459 | //\r | |
460 | // Type of Translation Register\r | |
461 | //\r | |
462 | #define EFI_SAL_ST_TR_USAGE_INSTRUCTION 00\r | |
463 | #define EFI_SAL_ST_TR_USAGE_DATA 01\r | |
464 | \r | |
465 | ///\r | |
466 | /// Definition of Coherence Domain Information\r | |
467 | ///\r | |
468 | typedef struct {\r | |
469 | UINT64 NumberOfProcessors;\r | |
470 | UINT64 LocalIDRegister;\r | |
471 | } SAL_COHERENCE_DOMAIN_INFO;\r | |
472 | \r | |
473 | ///\r | |
474 | /// Format of Purge Translation Cache Coherence Domain Entry\r | |
475 | ///\r | |
476 | typedef struct {\r | |
477 | UINT8 Type; ///< Type here should be 4\r | |
478 | UINT8 Reserved[3];\r | |
479 | UINT32 NumberOfDomains;\r | |
480 | SAL_COHERENCE_DOMAIN_INFO *DomainInformation;\r | |
481 | } SAL_ST_CACHE_COHERENCE_DECRIPTOR;\r | |
482 | \r | |
483 | ///\r | |
484 | /// Format of Application Processor Wake-Up Descriptor Entry\r | |
485 | ///\r | |
486 | typedef struct {\r | |
487 | UINT8 Type; ///< Type here should be 5\r | |
488 | UINT8 WakeUpType;\r | |
489 | UINT8 Reserved[6];\r | |
490 | UINT64 ExternalInterruptVector;\r | |
491 | } SAL_ST_AP_WAKEUP_DECRIPTOR;\r | |
492 | \r | |
493 | ///\r | |
494 | /// Format of Firmware Interface Table (FIT) Entry\r | |
495 | ///\r | |
496 | typedef struct {\r | |
497 | UINT64 Address;\r | |
498 | UINT8 Size[3];\r | |
499 | UINT8 Reserved;\r | |
500 | UINT16 Revision;\r | |
501 | UINT8 Type : 7;\r | |
502 | UINT8 CheckSumValid : 1;\r | |
503 | UINT8 CheckSum;\r | |
504 | } EFI_SAL_FIT_ENTRY;\r | |
505 | //\r | |
506 | // FIT Types \r | |
507 | //\r | |
508 | #define EFI_SAL_FIT_FIT_HEADER_TYPE 0x00\r | |
509 | #define EFI_SAL_FIT_PAL_B_TYPE 0x01\r | |
510 | //\r | |
511 | // Type from 0x02 to 0x0D is reserved.\r | |
512 | //\r | |
513 | #define EFI_SAL_FIT_PROCESSOR_SPECIFIC_PAL_A_TYPE 0x0E\r | |
514 | #define EFI_SAL_FIT_PAL_A_TYPE 0x0F\r | |
515 | //\r | |
516 | // OEM-defined type range is from 0x10 to 0x7E.\r | |
517 | // Here we defined the PEI_CORE type as 0x10\r | |
518 | //\r | |
519 | #define EFI_SAL_FIT_PEI_CORE_TYPE 0x10\r | |
520 | #define EFI_SAL_FIT_UNUSED_TYPE 0x7F\r | |
521 | \r | |
522 | //\r | |
523 | // FIT Entry\r | |
524 | //\r | |
525 | #define EFI_SAL_FIT_ENTRY_PTR (0x100000000 - 32) // 4GB - 24\r | |
526 | #define EFI_SAL_FIT_PALA_ENTRY (0x100000000 - 48) // 4GB - 32\r | |
527 | #define EFI_SAL_FIT_PALB_TYPE 01\r | |
528 | \r | |
529 | //\r | |
530 | // Following definitions are for Error Record Structure\r | |
531 | //\r | |
532 | \r | |
533 | ///\r | |
534 | /// Format of TimeStamp field in Record Header\r | |
535 | ///\r | |
536 | typedef struct {\r | |
537 | UINT8 Seconds;\r | |
538 | UINT8 Minutes;\r | |
539 | UINT8 Hours;\r | |
540 | UINT8 Reserved;\r | |
541 | UINT8 Day;\r | |
542 | UINT8 Month;\r | |
543 | UINT8 Year;\r | |
544 | UINT8 Century;\r | |
545 | } SAL_TIME_STAMP;\r | |
546 | ///\r | |
547 | /// Definition of Record Header\r | |
548 | ///\r | |
549 | typedef struct {\r | |
550 | UINT64 RecordId;\r | |
551 | UINT16 Revision;\r | |
552 | UINT8 ErrorSeverity;\r | |
553 | UINT8 ValidationBits;\r | |
554 | UINT32 RecordLength;\r | |
555 | SAL_TIME_STAMP TimeStamp;\r | |
556 | UINT8 OemPlatformId[16];\r | |
557 | } SAL_RECORD_HEADER;\r | |
558 | ///\r | |
559 | /// Definition of Section Header\r | |
560 | ///\r | |
561 | typedef struct {\r | |
562 | GUID Guid;\r | |
563 | UINT16 Revision;\r | |
564 | UINT8 ErrorRecoveryInfo;\r | |
565 | UINT8 Reserved;\r | |
566 | UINT32 SectionLength;\r | |
567 | } SAL_SEC_HEADER;\r | |
568 | \r | |
569 | ///\r | |
570 | /// GUID of Processor Machine Check Errors\r | |
571 | ///\r | |
572 | #define SAL_PROCESSOR_ERROR_RECORD_INFO \\r | |
573 | { \\r | |
574 | 0xe429faf1, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \\r | |
575 | }\r | |
576 | //\r | |
577 | // Bit masks for valid bits of MOD_ERROR_INFO\r | |
578 | //\r | |
579 | #define CHECK_INFO_VALID_BIT_MASK 0x1\r | |
580 | #define REQUESTOR_ID_VALID_BIT_MASK 0x2\r | |
581 | #define RESPONDER_ID_VALID_BIT_MASK 0x4\r | |
582 | #define TARGER_ID_VALID_BIT_MASK 0x8\r | |
583 | #define PRECISE_IP_VALID_BIT_MASK 0x10\r | |
584 | ///\r | |
585 | /// Definition of MOD_ERROR_INFO_STRUCT\r | |
586 | ///\r | |
587 | typedef struct {\r | |
588 | UINT64 InfoValid : 1;\r | |
589 | UINT64 ReqValid : 1;\r | |
590 | UINT64 RespValid : 1;\r | |
591 | UINT64 TargetValid : 1;\r | |
592 | UINT64 IpValid : 1;\r | |
593 | UINT64 Reserved : 59;\r | |
594 | UINT64 Info;\r | |
595 | UINT64 Req;\r | |
596 | UINT64 Resp;\r | |
597 | UINT64 Target;\r | |
598 | UINT64 Ip;\r | |
599 | } MOD_ERROR_INFO;\r | |
600 | ///\r | |
601 | /// Definition of CPUID_INFO_STRUCT\r | |
602 | ///\r | |
603 | typedef struct {\r | |
604 | UINT8 CpuidInfo[40];\r | |
605 | UINT8 Reserved;\r | |
606 | } CPUID_INFO;\r | |
607 | \r | |
608 | typedef struct {\r | |
609 | UINT64 FrLow;\r | |
610 | UINT64 FrHigh;\r | |
611 | } FR_STRUCT;\r | |
612 | //\r | |
613 | // Bit masks for PSI_STATIC_STRUCT.ValidFieldBits\r | |
614 | //\r | |
615 | #define MIN_STATE_VALID_BIT_MASK 0x1\r | |
616 | #define BR_VALID_BIT_MASK 0x2\r | |
617 | #define CR_VALID_BIT_MASK 0x4\r | |
618 | #define AR_VALID_BIT_MASK 0x8\r | |
619 | #define RR_VALID_BIT_MASK 0x10\r | |
620 | #define FR_VALID_BIT_MASK 0x20\r | |
621 | ///\r | |
622 | /// Definition of PSI_STATIC_STRUCT\r | |
623 | ///\r | |
624 | typedef struct {\r | |
625 | UINT64 ValidFieldBits;\r | |
626 | UINT8 MinStateInfo[1024];\r | |
627 | UINT64 Br[8];\r | |
628 | UINT64 Cr[128];\r | |
629 | UINT64 Ar[128];\r | |
630 | UINT64 Rr[8];\r | |
631 | FR_STRUCT Fr[128];\r | |
632 | } PSI_STATIC_STRUCT;\r | |
633 | //\r | |
634 | // Bit masks for SAL_PROCESSOR_ERROR_RECORD.ValidationBits\r | |
635 | //\r | |
636 | #define PROC_ERROR_MAP_VALID_BIT_MASK 0x1\r | |
637 | #define PROC_STATE_PARAMETER_VALID_BIT_MASK 0x2\r | |
638 | #define PROC_CR_LID_VALID_BIT_MASK 0x4\r | |
639 | #define PROC_STATIC_STRUCT_VALID_BIT_MASK 0x8\r | |
640 | #define CPU_INFO_VALID_BIT_MASK 0x1000000\r | |
641 | ///\r | |
642 | /// Definition of Processor Machine Check Error Record\r | |
643 | ///\r | |
644 | typedef struct {\r | |
645 | SAL_SEC_HEADER SectionHeader;\r | |
646 | UINT64 ValidationBits;\r | |
647 | UINT64 ProcErrorMap;\r | |
648 | UINT64 ProcStateParameter;\r | |
649 | UINT64 ProcCrLid;\r | |
650 | MOD_ERROR_INFO CacheError[15];\r | |
651 | MOD_ERROR_INFO TlbError[15];\r | |
652 | MOD_ERROR_INFO BusError[15];\r | |
653 | MOD_ERROR_INFO RegFileCheck[15];\r | |
654 | MOD_ERROR_INFO MsCheck[15];\r | |
655 | CPUID_INFO CpuInfo;\r | |
656 | PSI_STATIC_STRUCT PsiValidData;\r | |
657 | } SAL_PROCESSOR_ERROR_RECORD;\r | |
658 | \r | |
659 | ///\r | |
660 | /// GUID of Platform Memory Device Error Info\r | |
661 | ///\r | |
662 | #define SAL_MEMORY_ERROR_RECORD_INFO \\r | |
663 | { \\r | |
664 | 0xe429faf2, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \\r | |
665 | }\r | |
666 | //\r | |
667 | // Bit masks for SAL_MEMORY_ERROR_RECORD.ValidationBits\r | |
668 | //\r | |
669 | #define MEMORY_ERROR_STATUS_VALID_BIT_MASK 0x1\r | |
670 | #define MEMORY_PHYSICAL_ADDRESS_VALID_BIT_MASK 0x2\r | |
671 | #define MEMORY_ADDR_BIT_MASK 0x4\r | |
672 | #define MEMORY_NODE_VALID_BIT_MASK 0x8\r | |
673 | #define MEMORY_CARD_VALID_BIT_MASK 0x10\r | |
674 | #define MEMORY_MODULE_VALID_BIT_MASK 0x20\r | |
675 | #define MEMORY_BANK_VALID_BIT_MASK 0x40\r | |
676 | #define MEMORY_DEVICE_VALID_BIT_MASK 0x80\r | |
677 | #define MEMORY_ROW_VALID_BIT_MASK 0x100\r | |
678 | #define MEMORY_COLUMN_VALID_BIT_MASK 0x200\r | |
679 | #define MEMORY_BIT_POSITION_VALID_BIT_MASK 0x400\r | |
680 | #define MEMORY_PLATFORM_REQUESTOR_ID_VALID_BIT_MASK 0x800\r | |
681 | #define MEMORY_PLATFORM_RESPONDER_ID_VALID_BIT_MASK 0x1000\r | |
682 | #define MEMORY_PLATFORM_TARGET_VALID_BIT_MASK 0x2000\r | |
683 | #define MEMORY_PLATFORM_BUS_SPECIFIC_DATA_VALID_BIT_MASK 0x4000\r | |
684 | #define MEMORY_PLATFORM_OEM_ID_VALID_BIT_MASK 0x8000\r | |
685 | #define MEMORY_PLATFORM_OEM_DATA_STRUCT_VALID_BIT_MASK 0x10000\r | |
686 | ///\r | |
687 | /// Definition of Platform Memory Device Error Info Record\r | |
688 | ///\r | |
689 | typedef struct {\r | |
690 | SAL_SEC_HEADER SectionHeader;\r | |
691 | UINT64 ValidationBits;\r | |
692 | UINT64 MemErrorStatus;\r | |
693 | UINT64 MemPhysicalAddress;\r | |
694 | UINT64 MemPhysicalAddressMask;\r | |
695 | UINT16 MemNode;\r | |
696 | UINT16 MemCard;\r | |
697 | UINT16 MemModule;\r | |
698 | UINT16 MemBank;\r | |
699 | UINT16 MemDevice;\r | |
700 | UINT16 MemRow;\r | |
701 | UINT16 MemColumn;\r | |
702 | UINT16 MemBitPosition;\r | |
703 | UINT64 ModRequestorId;\r | |
704 | UINT64 ModResponderId;\r | |
705 | UINT64 ModTargetId;\r | |
706 | UINT64 BusSpecificData;\r | |
707 | UINT8 MemPlatformOemId[16];\r | |
708 | } SAL_MEMORY_ERROR_RECORD;\r | |
709 | \r | |
710 | ///\r | |
711 | /// GUID of Platform PCI Bus Error Info\r | |
712 | ///\r | |
713 | #define SAL_PCI_BUS_ERROR_RECORD_INFO \\r | |
714 | { \\r | |
715 | 0xe429faf4, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \\r | |
716 | }\r | |
717 | //\r | |
718 | // Bit masks for SAL_PCI_BUS_ERROR_RECORD.ValidationBits\r | |
719 | //\r | |
720 | #define PCI_BUS_ERROR_STATUS_VALID_BIT_MASK 0x1\r | |
721 | #define PCI_BUS_ERROR_TYPE_VALID_BIT_MASK 0x2\r | |
722 | #define PCI_BUS_ID_VALID_BIT_MASK 0x4\r | |
723 | #define PCI_BUS_ADDRESS_VALID_BIT_MASK 0x8\r | |
724 | #define PCI_BUS_DATA_VALID_BIT_MASK 0x10\r | |
725 | #define PCI_BUS_CMD_VALID_BIT_MASK 0x20\r | |
726 | #define PCI_BUS_REQUESTOR_ID_VALID_BIT_MASK 0x40\r | |
727 | #define PCI_BUS_RESPONDER_ID_VALID_BIT_MASK 0x80\r | |
728 | #define PCI_BUS_TARGET_VALID_BIT_MASK 0x100\r | |
729 | #define PCI_BUS_OEM_ID_VALID_BIT_MASK 0x200\r | |
730 | #define PCI_BUS_OEM_DATA_STRUCT_VALID_BIT_MASK 0x400\r | |
731 | \r | |
732 | typedef struct {\r | |
733 | UINT8 BusNumber;\r | |
734 | UINT8 SegmentNumber;\r | |
735 | } PCI_BUS_ID;\r | |
736 | ///\r | |
737 | /// Definition of Platform PCI Bus Error Info Record\r | |
738 | ///\r | |
739 | typedef struct {\r | |
740 | SAL_SEC_HEADER SectionHeader;\r | |
741 | UINT64 ValidationBits;\r | |
742 | UINT64 PciBusErrorStatus;\r | |
743 | UINT16 PciBusErrorType;\r | |
744 | PCI_BUS_ID PciBusId;\r | |
745 | UINT32 Reserved;\r | |
746 | UINT64 PciBusAddress;\r | |
747 | UINT64 PciBusData;\r | |
748 | UINT64 PciBusCommand;\r | |
749 | UINT64 PciBusRequestorId;\r | |
750 | UINT64 PciBusResponderId;\r | |
751 | UINT64 PciBusTargetId;\r | |
752 | UINT8 PciBusOemId[16];\r | |
753 | } SAL_PCI_BUS_ERROR_RECORD;\r | |
754 | \r | |
755 | ///\r | |
756 | /// GUID of Platform PCI Component Error Info\r | |
757 | ///\r | |
758 | #define SAL_PCI_COMP_ERROR_RECORD_INFO \\r | |
759 | { \\r | |
760 | 0xe429faf6, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \\r | |
761 | }\r | |
762 | //\r | |
763 | // Bit masks for SAL_PCI_COMPONENT_ERROR_RECORD.ValidationBits\r | |
764 | //\r | |
765 | #define PCI_COMP_ERROR_STATUS_VALID_BIT_MASK 0x1\r | |
766 | #define PCI_COMP_INFO_VALID_BIT_MASK 0x2\r | |
767 | #define PCI_COMP_MEM_NUM_VALID_BIT_MASK 0x4\r | |
768 | #define PCI_COMP_IO_NUM_VALID_BIT_MASK 0x8\r | |
769 | #define PCI_COMP_REG_DATA_PAIR_VALID_BIT_MASK 0x10\r | |
770 | #define PCI_COMP_OEM_DATA_STRUCT_VALID_BIT_MASK 0x20\r | |
771 | ///\r | |
772 | /// Format of PCI Component Information to identify the device\r | |
773 | ///\r | |
774 | typedef struct {\r | |
775 | UINT16 VendorId;\r | |
776 | UINT16 DeviceId;\r | |
777 | UINT8 ClassCode[3];\r | |
778 | UINT8 FunctionNumber;\r | |
779 | UINT8 DeviceNumber;\r | |
780 | UINT8 BusNumber;\r | |
781 | UINT8 SegmentNumber;\r | |
782 | UINT8 Reserved[5];\r | |
783 | } PCI_COMP_INFO;\r | |
784 | ///\r | |
785 | /// Definition of Platform PCI Component Error Info\r | |
786 | ///\r | |
787 | typedef struct {\r | |
788 | SAL_SEC_HEADER SectionHeader;\r | |
789 | UINT64 ValidationBits;\r | |
790 | UINT64 PciComponentErrorStatus;\r | |
791 | PCI_COMP_INFO PciComponentInfo;\r | |
792 | UINT32 PciComponentMemNum;\r | |
793 | UINT32 PciComponentIoNum;\r | |
794 | UINT8 PciBusOemId[16];\r | |
795 | } SAL_PCI_COMPONENT_ERROR_RECORD;\r | |
796 | \r | |
797 | ///\r | |
798 | /// Platform SEL Device Error Info\r | |
799 | ///\r | |
800 | #define SAL_SEL_DEVICE_ERROR_RECORD_INFO \\r | |
801 | { \\r | |
802 | 0xe429faf3, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \\r | |
803 | }\r | |
804 | //\r | |
805 | // Bit masks for SAL_SEL_DEVICE_ERROR_RECORD.ValidationBits\r | |
806 | //\r | |
807 | #define SEL_RECORD_ID_VALID_BIT_MASK 0x1;\r | |
808 | #define SEL_RECORD_TYPE_VALID_BIT_MASK 0x2;\r | |
809 | #define SEL_GENERATOR_ID_VALID_BIT_MASK 0x4;\r | |
810 | #define SEL_EVM_REV_VALID_BIT_MASK 0x8;\r | |
811 | #define SEL_SENSOR_TYPE_VALID_BIT_MASK 0x10;\r | |
812 | #define SEL_SENSOR_NUM_VALID_BIT_MASK 0x20;\r | |
813 | #define SEL_EVENT_DIR_TYPE_VALID_BIT_MASK 0x40;\r | |
814 | #define SEL_EVENT_DATA1_VALID_BIT_MASK 0x80;\r | |
815 | #define SEL_EVENT_DATA2_VALID_BIT_MASK 0x100;\r | |
816 | #define SEL_EVENT_DATA3_VALID_BIT_MASK 0x200;\r | |
817 | ///\r | |
818 | /// Definition of Platform SEL Device Error Info Record\r | |
819 | ///\r | |
820 | typedef struct {\r | |
821 | SAL_SEC_HEADER SectionHeader;\r | |
822 | UINT64 ValidationBits;\r | |
823 | UINT16 SelRecordId;\r | |
824 | UINT8 SelRecordType;\r | |
825 | UINT32 TimeStamp;\r | |
826 | UINT16 GeneratorId;\r | |
827 | UINT8 EvmRevision;\r | |
828 | UINT8 SensorType;\r | |
829 | UINT8 SensorNum;\r | |
830 | UINT8 EventDirType;\r | |
831 | UINT8 Data1;\r | |
832 | UINT8 Data2;\r | |
833 | UINT8 Data3;\r | |
834 | } SAL_SEL_DEVICE_ERROR_RECORD;\r | |
835 | \r | |
836 | ///\r | |
837 | /// GUID of Platform SMBIOS Device Error Info\r | |
838 | ///\r | |
839 | #define SAL_SMBIOS_ERROR_RECORD_INFO \\r | |
840 | { \\r | |
841 | 0xe429faf5, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \\r | |
842 | }\r | |
843 | //\r | |
844 | // Bit masks for SAL_SMBIOS_DEVICE_ERROR_RECORD.ValidationBits\r | |
845 | //\r | |
846 | #define SMBIOS_EVENT_TYPE_VALID_BIT_MASK 0x1\r | |
847 | #define SMBIOS_LENGTH_VALID_BIT_MASK 0x2\r | |
848 | #define SMBIOS_TIME_STAMP_VALID_BIT_MASK 0x4\r | |
849 | #define SMBIOS_DATA_VALID_BIT_MASK 0x8\r | |
850 | ///\r | |
851 | /// Definition of Platform SMBIOS Device Error Info Record\r | |
852 | ///\r | |
853 | typedef struct {\r | |
854 | SAL_SEC_HEADER SectionHeader;\r | |
855 | UINT64 ValidationBits;\r | |
856 | UINT8 SmbiosEventType;\r | |
857 | UINT8 SmbiosLength;\r | |
858 | UINT8 SmbiosBcdTimeStamp[6];\r | |
859 | } SAL_SMBIOS_DEVICE_ERROR_RECORD;\r | |
860 | \r | |
861 | ///\r | |
862 | /// GUID of Platform Specific Error Info\r | |
863 | ///\r | |
864 | #define SAL_PLATFORM_ERROR_RECORD_INFO \\r | |
865 | { \\r | |
866 | 0xe429faf7, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \\r | |
867 | }\r | |
868 | //\r | |
869 | // Bit masks for SAL_PLATFORM_SPECIFIC_ERROR_RECORD.ValidationBits\r | |
870 | //\r | |
871 | #define PLATFORM_ERROR_STATUS_VALID_BIT_MASK 0x1\r | |
872 | #define PLATFORM_REQUESTOR_ID_VALID_BIT_MASK 0x2\r | |
873 | #define PLATFORM_RESPONDER_ID_VALID_BIT_MASK 0x4\r | |
874 | #define PLATFORM_TARGET_VALID_BIT_MASK 0x8\r | |
875 | #define PLATFORM_SPECIFIC_DATA_VALID_BIT_MASK 0x10\r | |
876 | #define PLATFORM_OEM_ID_VALID_BIT_MASK 0x20\r | |
877 | #define PLATFORM_OEM_DATA_STRUCT_VALID_BIT_MASK 0x40\r | |
878 | #define PLATFORM_OEM_DEVICE_PATH_VALID_BIT_MASK 0x80\r | |
879 | ///\r | |
880 | /// Definition of Platform Specific Error Info Record\r | |
881 | ///\r | |
882 | typedef struct {\r | |
883 | SAL_SEC_HEADER SectionHeader;\r | |
884 | UINT64 ValidationBits;\r | |
885 | UINT64 PlatformErrorStatus;\r | |
886 | UINT64 PlatformRequestorId;\r | |
887 | UINT64 PlatformResponderId;\r | |
888 | UINT64 PlatformTargetId;\r | |
889 | UINT64 PlatformBusSpecificData;\r | |
890 | UINT8 OemComponentId[16];\r | |
891 | } SAL_PLATFORM_SPECIFIC_ERROR_RECORD;\r | |
892 | \r | |
893 | ///\r | |
894 | /// Union of all the possible SAL Error Record Types\r | |
895 | ///\r | |
896 | typedef union {\r | |
897 | SAL_RECORD_HEADER *RecordHeader;\r | |
898 | SAL_PROCESSOR_ERROR_RECORD *SalProcessorRecord;\r | |
899 | SAL_PCI_BUS_ERROR_RECORD *SalPciBusRecord;\r | |
900 | SAL_PCI_COMPONENT_ERROR_RECORD *SalPciComponentRecord;\r | |
901 | SAL_SEL_DEVICE_ERROR_RECORD *ImpiRecord;\r | |
902 | SAL_SMBIOS_DEVICE_ERROR_RECORD *SmbiosRecord;\r | |
903 | SAL_PLATFORM_SPECIFIC_ERROR_RECORD *PlatformRecord;\r | |
904 | SAL_MEMORY_ERROR_RECORD *MemoryRecord;\r | |
905 | UINT8 *Raw;\r | |
906 | } SAL_ERROR_RECORDS_POINTERS;\r | |
907 | \r | |
908 | #pragma pack()\r | |
909 | \r | |
910 | #endif\r |