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1 | /** @file\r | |
2 | Provides services to access PCI Configuration Space using the MMIO PCI Express window.\r | |
3 | \r | |
4 | This library is identical to the PCI Library, except the access method for performing PCI \r | |
5 | configuration cycles must be through the 256 MB PCI Express MMIO window whose base address\r | |
6 | is defined by PcdPciExpressBaseAddress.\r | |
7 | \r | |
8 | Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>\r | |
9 | This program and the accompanying materials\r | |
10 | are licensed and made available under the terms and conditions of the BSD License\r | |
11 | which accompanies this distribution. The full text of the license may be found at\r | |
12 | http://opensource.org/licenses/bsd-license.php\r | |
13 | \r | |
14 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
15 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
16 | \r | |
17 | **/\r | |
18 | \r | |
19 | #ifndef __PCI_EXPRESS_LIB_H__\r | |
20 | #define __PCI_EXPRESS_LIB_H__\r | |
21 | \r | |
22 | /**\r | |
23 | Macro that converts PCI Bus, PCI Device, PCI Function and PCI Register to an\r | |
24 | address that can be passed to the PCI Library functions.\r | |
25 | \r | |
26 | Computes an address that is compatible with the PCI Library functions. The\r | |
27 | unused upper bits of Bus, Device, Function and Register are stripped prior to\r | |
28 | the generation of the address.\r | |
29 | \r | |
30 | @param Bus PCI Bus number. Range 0..255.\r | |
31 | @param Device PCI Device number. Range 0..31.\r | |
32 | @param Function PCI Function number. Range 0..7.\r | |
33 | @param Register PCI Register number. Range 0..4095.\r | |
34 | \r | |
35 | @return The encode PCI address.\r | |
36 | \r | |
37 | **/\r | |
38 | #define PCI_EXPRESS_LIB_ADDRESS(Bus,Device,Function,Offset) \\r | |
39 | (((Offset) & 0xfff) | (((Function) & 0x07) << 12) | (((Device) & 0x1f) << 15) | (((Bus) & 0xff) << 20))\r | |
40 | \r | |
41 | /**\r | |
42 | Registers a PCI device so PCI configuration registers may be accessed after \r | |
43 | SetVirtualAddressMap().\r | |
44 | \r | |
45 | Registers the PCI device specified by Address so all the PCI configuration \r | |
46 | registers associated with that PCI device may be accessed after SetVirtualAddressMap() \r | |
47 | is called.\r | |
48 | \r | |
49 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
50 | \r | |
51 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
52 | Register.\r | |
53 | \r | |
54 | @retval RETURN_SUCCESS The PCI device was registered for runtime access.\r | |
55 | @retval RETURN_UNSUPPORTED An attempt was made to call this function \r | |
56 | after ExitBootServices().\r | |
57 | @retval RETURN_UNSUPPORTED The resources required to access the PCI device\r | |
58 | at runtime could not be mapped.\r | |
59 | @retval RETURN_OUT_OF_RESOURCES There are not enough resources available to\r | |
60 | complete the registration.\r | |
61 | \r | |
62 | **/\r | |
63 | RETURN_STATUS\r | |
64 | EFIAPI\r | |
65 | PciExpressRegisterForRuntimeAccess (\r | |
66 | IN UINTN Address\r | |
67 | );\r | |
68 | \r | |
69 | /**\r | |
70 | Reads an 8-bit PCI configuration register.\r | |
71 | \r | |
72 | Reads and returns the 8-bit PCI configuration register specified by Address.\r | |
73 | This function must guarantee that all PCI read and write operations are\r | |
74 | serialized.\r | |
75 | \r | |
76 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
77 | \r | |
78 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
79 | Register.\r | |
80 | \r | |
81 | @return The read value from the PCI configuration register.\r | |
82 | \r | |
83 | **/\r | |
84 | UINT8\r | |
85 | EFIAPI\r | |
86 | PciExpressRead8 (\r | |
87 | IN UINTN Address\r | |
88 | );\r | |
89 | \r | |
90 | /**\r | |
91 | Writes an 8-bit PCI configuration register.\r | |
92 | \r | |
93 | Writes the 8-bit PCI configuration register specified by Address with the\r | |
94 | value specified by Value. Value is returned. This function must guarantee\r | |
95 | that all PCI read and write operations are serialized.\r | |
96 | \r | |
97 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
98 | \r | |
99 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
100 | Register.\r | |
101 | @param Value The value to write.\r | |
102 | \r | |
103 | @return The value written to the PCI configuration register.\r | |
104 | \r | |
105 | **/\r | |
106 | UINT8\r | |
107 | EFIAPI\r | |
108 | PciExpressWrite8 (\r | |
109 | IN UINTN Address,\r | |
110 | IN UINT8 Value\r | |
111 | );\r | |
112 | \r | |
113 | /**\r | |
114 | Performs a bitwise OR of an 8-bit PCI configuration register with\r | |
115 | an 8-bit value.\r | |
116 | \r | |
117 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
118 | bitwise OR between the read result and the value specified by\r | |
119 | OrData, and writes the result to the 8-bit PCI configuration register\r | |
120 | specified by Address. The value written to the PCI configuration register is\r | |
121 | returned. This function must guarantee that all PCI read and write operations\r | |
122 | are serialized.\r | |
123 | \r | |
124 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
125 | \r | |
126 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
127 | Register.\r | |
128 | @param OrData The value to OR with the PCI configuration register.\r | |
129 | \r | |
130 | @return The value written back to the PCI configuration register.\r | |
131 | \r | |
132 | **/\r | |
133 | UINT8\r | |
134 | EFIAPI\r | |
135 | PciExpressOr8 (\r | |
136 | IN UINTN Address,\r | |
137 | IN UINT8 OrData\r | |
138 | );\r | |
139 | \r | |
140 | /**\r | |
141 | Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit\r | |
142 | value.\r | |
143 | \r | |
144 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
145 | bitwise AND between the read result and the value specified by AndData, and\r | |
146 | writes the result to the 8-bit PCI configuration register specified by\r | |
147 | Address. The value written to the PCI configuration register is returned.\r | |
148 | This function must guarantee that all PCI read and write operations are\r | |
149 | serialized.\r | |
150 | \r | |
151 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
152 | \r | |
153 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
154 | Register.\r | |
155 | @param AndData The value to AND with the PCI configuration register.\r | |
156 | \r | |
157 | @return The value written back to the PCI configuration register.\r | |
158 | \r | |
159 | **/\r | |
160 | UINT8\r | |
161 | EFIAPI\r | |
162 | PciExpressAnd8 (\r | |
163 | IN UINTN Address,\r | |
164 | IN UINT8 AndData\r | |
165 | );\r | |
166 | \r | |
167 | /**\r | |
168 | Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit\r | |
169 | value, followed a bitwise OR with another 8-bit value.\r | |
170 | \r | |
171 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
172 | bitwise AND between the read result and the value specified by AndData,\r | |
173 | performs a bitwise OR between the result of the AND operation and\r | |
174 | the value specified by OrData, and writes the result to the 8-bit PCI\r | |
175 | configuration register specified by Address. The value written to the PCI\r | |
176 | configuration register is returned. This function must guarantee that all PCI\r | |
177 | read and write operations are serialized.\r | |
178 | \r | |
179 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
180 | \r | |
181 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
182 | Register.\r | |
183 | @param AndData The value to AND with the PCI configuration register.\r | |
184 | @param OrData The value to OR with the result of the AND operation.\r | |
185 | \r | |
186 | @return The value written back to the PCI configuration register.\r | |
187 | \r | |
188 | **/\r | |
189 | UINT8\r | |
190 | EFIAPI\r | |
191 | PciExpressAndThenOr8 (\r | |
192 | IN UINTN Address,\r | |
193 | IN UINT8 AndData,\r | |
194 | IN UINT8 OrData\r | |
195 | );\r | |
196 | \r | |
197 | /**\r | |
198 | Reads a bit field of a PCI configuration register.\r | |
199 | \r | |
200 | Reads the bit field in an 8-bit PCI configuration register. The bit field is\r | |
201 | specified by the StartBit and the EndBit. The value of the bit field is\r | |
202 | returned.\r | |
203 | \r | |
204 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
205 | If StartBit is greater than 7, then ASSERT().\r | |
206 | If EndBit is greater than 7, then ASSERT().\r | |
207 | If EndBit is less than StartBit, then ASSERT().\r | |
208 | \r | |
209 | @param Address PCI configuration register to read.\r | |
210 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
211 | Range 0..7.\r | |
212 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
213 | Range 0..7.\r | |
214 | \r | |
215 | @return The value of the bit field read from the PCI configuration register.\r | |
216 | \r | |
217 | **/\r | |
218 | UINT8\r | |
219 | EFIAPI\r | |
220 | PciExpressBitFieldRead8 (\r | |
221 | IN UINTN Address,\r | |
222 | IN UINTN StartBit,\r | |
223 | IN UINTN EndBit\r | |
224 | );\r | |
225 | \r | |
226 | /**\r | |
227 | Writes a bit field to a PCI configuration register.\r | |
228 | \r | |
229 | Writes Value to the bit field of the PCI configuration register. The bit\r | |
230 | field is specified by the StartBit and the EndBit. All other bits in the\r | |
231 | destination PCI configuration register are preserved. The new value of the\r | |
232 | 8-bit register is returned.\r | |
233 | \r | |
234 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
235 | If StartBit is greater than 7, then ASSERT().\r | |
236 | If EndBit is greater than 7, then ASSERT().\r | |
237 | If EndBit is less than StartBit, then ASSERT().\r | |
238 | \r | |
239 | @param Address PCI configuration register to write.\r | |
240 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
241 | Range 0..7.\r | |
242 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
243 | Range 0..7.\r | |
244 | @param Value New value of the bit field.\r | |
245 | \r | |
246 | @return The value written back to the PCI configuration register.\r | |
247 | \r | |
248 | **/\r | |
249 | UINT8\r | |
250 | EFIAPI\r | |
251 | PciExpressBitFieldWrite8 (\r | |
252 | IN UINTN Address,\r | |
253 | IN UINTN StartBit,\r | |
254 | IN UINTN EndBit,\r | |
255 | IN UINT8 Value\r | |
256 | );\r | |
257 | \r | |
258 | /**\r | |
259 | Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and\r | |
260 | writes the result back to the bit field in the 8-bit port.\r | |
261 | \r | |
262 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
263 | bitwise OR between the read result and the value specified by\r | |
264 | OrData, and writes the result to the 8-bit PCI configuration register\r | |
265 | specified by Address. The value written to the PCI configuration register is\r | |
266 | returned. This function must guarantee that all PCI read and write operations\r | |
267 | are serialized. Extra left bits in OrData are stripped.\r | |
268 | \r | |
269 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
270 | If StartBit is greater than 7, then ASSERT().\r | |
271 | If EndBit is greater than 7, then ASSERT().\r | |
272 | If EndBit is less than StartBit, then ASSERT().\r | |
273 | \r | |
274 | @param Address PCI configuration register to write.\r | |
275 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
276 | Range 0..7.\r | |
277 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
278 | Range 0..7.\r | |
279 | @param OrData The value to OR with the PCI configuration register.\r | |
280 | \r | |
281 | @return The value written back to the PCI configuration register.\r | |
282 | \r | |
283 | **/\r | |
284 | UINT8\r | |
285 | EFIAPI\r | |
286 | PciExpressBitFieldOr8 (\r | |
287 | IN UINTN Address,\r | |
288 | IN UINTN StartBit,\r | |
289 | IN UINTN EndBit,\r | |
290 | IN UINT8 OrData\r | |
291 | );\r | |
292 | \r | |
293 | /**\r | |
294 | Reads a bit field in an 8-bit PCI configuration register, performs a bitwise\r | |
295 | AND, and writes the result back to the bit field in the 8-bit register.\r | |
296 | \r | |
297 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
298 | bitwise AND between the read result and the value specified by AndData, and\r | |
299 | writes the result to the 8-bit PCI configuration register specified by\r | |
300 | Address. The value written to the PCI configuration register is returned.\r | |
301 | This function must guarantee that all PCI read and write operations are\r | |
302 | serialized. Extra left bits in AndData are stripped.\r | |
303 | \r | |
304 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
305 | If StartBit is greater than 7, then ASSERT().\r | |
306 | If EndBit is greater than 7, then ASSERT().\r | |
307 | If EndBit is less than StartBit, then ASSERT().\r | |
308 | \r | |
309 | @param Address PCI configuration register to write.\r | |
310 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
311 | Range 0..7.\r | |
312 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
313 | Range 0..7.\r | |
314 | @param AndData The value to AND with the PCI configuration register.\r | |
315 | \r | |
316 | @return The value written back to the PCI configuration register.\r | |
317 | \r | |
318 | **/\r | |
319 | UINT8\r | |
320 | EFIAPI\r | |
321 | PciExpressBitFieldAnd8 (\r | |
322 | IN UINTN Address,\r | |
323 | IN UINTN StartBit,\r | |
324 | IN UINTN EndBit,\r | |
325 | IN UINT8 AndData\r | |
326 | );\r | |
327 | \r | |
328 | /**\r | |
329 | Reads a bit field in an 8-bit port, performs a bitwise AND followed by a\r | |
330 | bitwise OR, and writes the result back to the bit field in the\r | |
331 | 8-bit port.\r | |
332 | \r | |
333 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
334 | bitwise AND followed by a bitwise OR between the read result and\r | |
335 | the value specified by AndData, and writes the result to the 8-bit PCI\r | |
336 | configuration register specified by Address. The value written to the PCI\r | |
337 | configuration register is returned. This function must guarantee that all PCI\r | |
338 | read and write operations are serialized. Extra left bits in both AndData and\r | |
339 | OrData are stripped.\r | |
340 | \r | |
341 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
342 | If StartBit is greater than 7, then ASSERT().\r | |
343 | If EndBit is greater than 7, then ASSERT().\r | |
344 | If EndBit is less than StartBit, then ASSERT().\r | |
345 | \r | |
346 | @param Address PCI configuration register to write.\r | |
347 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
348 | Range 0..7.\r | |
349 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
350 | Range 0..7.\r | |
351 | @param AndData The value to AND with the PCI configuration register.\r | |
352 | @param OrData The value to OR with the result of the AND operation.\r | |
353 | \r | |
354 | @return The value written back to the PCI configuration register.\r | |
355 | \r | |
356 | **/\r | |
357 | UINT8\r | |
358 | EFIAPI\r | |
359 | PciExpressBitFieldAndThenOr8 (\r | |
360 | IN UINTN Address,\r | |
361 | IN UINTN StartBit,\r | |
362 | IN UINTN EndBit,\r | |
363 | IN UINT8 AndData,\r | |
364 | IN UINT8 OrData\r | |
365 | );\r | |
366 | \r | |
367 | /**\r | |
368 | Reads a 16-bit PCI configuration register.\r | |
369 | \r | |
370 | Reads and returns the 16-bit PCI configuration register specified by Address.\r | |
371 | This function must guarantee that all PCI read and write operations are\r | |
372 | serialized.\r | |
373 | \r | |
374 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
375 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
376 | \r | |
377 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
378 | Register.\r | |
379 | \r | |
380 | @return The read value from the PCI configuration register.\r | |
381 | \r | |
382 | **/\r | |
383 | UINT16\r | |
384 | EFIAPI\r | |
385 | PciExpressRead16 (\r | |
386 | IN UINTN Address\r | |
387 | );\r | |
388 | \r | |
389 | /**\r | |
390 | Writes a 16-bit PCI configuration register.\r | |
391 | \r | |
392 | Writes the 16-bit PCI configuration register specified by Address with the\r | |
393 | value specified by Value. Value is returned. This function must guarantee\r | |
394 | that all PCI read and write operations are serialized.\r | |
395 | \r | |
396 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
397 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
398 | \r | |
399 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
400 | Register.\r | |
401 | @param Value The value to write.\r | |
402 | \r | |
403 | @return The value written to the PCI configuration register.\r | |
404 | \r | |
405 | **/\r | |
406 | UINT16\r | |
407 | EFIAPI\r | |
408 | PciExpressWrite16 (\r | |
409 | IN UINTN Address,\r | |
410 | IN UINT16 Value\r | |
411 | );\r | |
412 | \r | |
413 | /**\r | |
414 | Performs a bitwise OR of a 16-bit PCI configuration register with\r | |
415 | a 16-bit value.\r | |
416 | \r | |
417 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
418 | bitwise OR between the read result and the value specified by\r | |
419 | OrData, and writes the result to the 16-bit PCI configuration register\r | |
420 | specified by Address. The value written to the PCI configuration register is\r | |
421 | returned. This function must guarantee that all PCI read and write operations\r | |
422 | are serialized.\r | |
423 | \r | |
424 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
425 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
426 | \r | |
427 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
428 | Register.\r | |
429 | @param OrData The value to OR with the PCI configuration register.\r | |
430 | \r | |
431 | @return The value written back to the PCI configuration register.\r | |
432 | \r | |
433 | **/\r | |
434 | UINT16\r | |
435 | EFIAPI\r | |
436 | PciExpressOr16 (\r | |
437 | IN UINTN Address,\r | |
438 | IN UINT16 OrData\r | |
439 | );\r | |
440 | \r | |
441 | /**\r | |
442 | Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit\r | |
443 | value.\r | |
444 | \r | |
445 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
446 | bitwise AND between the read result and the value specified by AndData, and\r | |
447 | writes the result to the 16-bit PCI configuration register specified by\r | |
448 | Address. The value written to the PCI configuration register is returned.\r | |
449 | This function must guarantee that all PCI read and write operations are\r | |
450 | serialized.\r | |
451 | \r | |
452 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
453 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
454 | \r | |
455 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
456 | Register.\r | |
457 | @param AndData The value to AND with the PCI configuration register.\r | |
458 | \r | |
459 | @return The value written back to the PCI configuration register.\r | |
460 | \r | |
461 | **/\r | |
462 | UINT16\r | |
463 | EFIAPI\r | |
464 | PciExpressAnd16 (\r | |
465 | IN UINTN Address,\r | |
466 | IN UINT16 AndData\r | |
467 | );\r | |
468 | \r | |
469 | /**\r | |
470 | Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit\r | |
471 | value, followed a bitwise OR with another 16-bit value.\r | |
472 | \r | |
473 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
474 | bitwise AND between the read result and the value specified by AndData,\r | |
475 | performs a bitwise OR between the result of the AND operation and\r | |
476 | the value specified by OrData, and writes the result to the 16-bit PCI\r | |
477 | configuration register specified by Address. The value written to the PCI\r | |
478 | configuration register is returned. This function must guarantee that all PCI\r | |
479 | read and write operations are serialized.\r | |
480 | \r | |
481 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
482 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
483 | \r | |
484 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
485 | Register.\r | |
486 | @param AndData The value to AND with the PCI configuration register.\r | |
487 | @param OrData The value to OR with the result of the AND operation.\r | |
488 | \r | |
489 | @return The value written back to the PCI configuration register.\r | |
490 | \r | |
491 | **/\r | |
492 | UINT16\r | |
493 | EFIAPI\r | |
494 | PciExpressAndThenOr16 (\r | |
495 | IN UINTN Address,\r | |
496 | IN UINT16 AndData,\r | |
497 | IN UINT16 OrData\r | |
498 | );\r | |
499 | \r | |
500 | /**\r | |
501 | Reads a bit field of a PCI configuration register.\r | |
502 | \r | |
503 | Reads the bit field in a 16-bit PCI configuration register. The bit field is\r | |
504 | specified by the StartBit and the EndBit. The value of the bit field is\r | |
505 | returned.\r | |
506 | \r | |
507 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
508 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
509 | If StartBit is greater than 15, then ASSERT().\r | |
510 | If EndBit is greater than 15, then ASSERT().\r | |
511 | If EndBit is less than StartBit, then ASSERT().\r | |
512 | \r | |
513 | @param Address PCI configuration register to read.\r | |
514 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
515 | Range 0..15.\r | |
516 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
517 | Range 0..15.\r | |
518 | \r | |
519 | @return The value of the bit field read from the PCI configuration register.\r | |
520 | \r | |
521 | **/\r | |
522 | UINT16\r | |
523 | EFIAPI\r | |
524 | PciExpressBitFieldRead16 (\r | |
525 | IN UINTN Address,\r | |
526 | IN UINTN StartBit,\r | |
527 | IN UINTN EndBit\r | |
528 | );\r | |
529 | \r | |
530 | /**\r | |
531 | Writes a bit field to a PCI configuration register.\r | |
532 | \r | |
533 | Writes Value to the bit field of the PCI configuration register. The bit\r | |
534 | field is specified by the StartBit and the EndBit. All other bits in the\r | |
535 | destination PCI configuration register are preserved. The new value of the\r | |
536 | 16-bit register is returned.\r | |
537 | \r | |
538 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
539 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
540 | If StartBit is greater than 15, then ASSERT().\r | |
541 | If EndBit is greater than 15, then ASSERT().\r | |
542 | If EndBit is less than StartBit, then ASSERT().\r | |
543 | \r | |
544 | @param Address PCI configuration register to write.\r | |
545 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
546 | Range 0..15.\r | |
547 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
548 | Range 0..15.\r | |
549 | @param Value New value of the bit field.\r | |
550 | \r | |
551 | @return The value written back to the PCI configuration register.\r | |
552 | \r | |
553 | **/\r | |
554 | UINT16\r | |
555 | EFIAPI\r | |
556 | PciExpressBitFieldWrite16 (\r | |
557 | IN UINTN Address,\r | |
558 | IN UINTN StartBit,\r | |
559 | IN UINTN EndBit,\r | |
560 | IN UINT16 Value\r | |
561 | );\r | |
562 | \r | |
563 | /**\r | |
564 | Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and\r | |
565 | writes the result back to the bit field in the 16-bit port.\r | |
566 | \r | |
567 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
568 | bitwise OR between the read result and the value specified by\r | |
569 | OrData, and writes the result to the 16-bit PCI configuration register\r | |
570 | specified by Address. The value written to the PCI configuration register is\r | |
571 | returned. This function must guarantee that all PCI read and write operations\r | |
572 | are serialized. Extra left bits in OrData are stripped.\r | |
573 | \r | |
574 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
575 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
576 | If StartBit is greater than 15, then ASSERT().\r | |
577 | If EndBit is greater than 15, then ASSERT().\r | |
578 | If EndBit is less than StartBit, then ASSERT().\r | |
579 | \r | |
580 | @param Address PCI configuration register to write.\r | |
581 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
582 | Range 0..15.\r | |
583 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
584 | Range 0..15.\r | |
585 | @param OrData The value to OR with the PCI configuration register.\r | |
586 | \r | |
587 | @return The value written back to the PCI configuration register.\r | |
588 | \r | |
589 | **/\r | |
590 | UINT16\r | |
591 | EFIAPI\r | |
592 | PciExpressBitFieldOr16 (\r | |
593 | IN UINTN Address,\r | |
594 | IN UINTN StartBit,\r | |
595 | IN UINTN EndBit,\r | |
596 | IN UINT16 OrData\r | |
597 | );\r | |
598 | \r | |
599 | /**\r | |
600 | Reads a bit field in a 16-bit PCI configuration register, performs a bitwise\r | |
601 | AND, and writes the result back to the bit field in the 16-bit register.\r | |
602 | \r | |
603 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
604 | bitwise AND between the read result and the value specified by AndData, and\r | |
605 | writes the result to the 16-bit PCI configuration register specified by\r | |
606 | Address. The value written to the PCI configuration register is returned.\r | |
607 | This function must guarantee that all PCI read and write operations are\r | |
608 | serialized. Extra left bits in AndData are stripped.\r | |
609 | \r | |
610 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
611 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
612 | If StartBit is greater than 15, then ASSERT().\r | |
613 | If EndBit is greater than 15, then ASSERT().\r | |
614 | If EndBit is less than StartBit, then ASSERT().\r | |
615 | \r | |
616 | @param Address PCI configuration register to write.\r | |
617 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
618 | Range 0..15.\r | |
619 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
620 | Range 0..15.\r | |
621 | @param AndData The value to AND with the PCI configuration register.\r | |
622 | \r | |
623 | @return The value written back to the PCI configuration register.\r | |
624 | \r | |
625 | **/\r | |
626 | UINT16\r | |
627 | EFIAPI\r | |
628 | PciExpressBitFieldAnd16 (\r | |
629 | IN UINTN Address,\r | |
630 | IN UINTN StartBit,\r | |
631 | IN UINTN EndBit,\r | |
632 | IN UINT16 AndData\r | |
633 | );\r | |
634 | \r | |
635 | /**\r | |
636 | Reads a bit field in a 16-bit port, performs a bitwise AND followed by a\r | |
637 | bitwise OR, and writes the result back to the bit field in the\r | |
638 | 16-bit port.\r | |
639 | \r | |
640 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
641 | bitwise AND followed by a bitwise OR between the read result and\r | |
642 | the value specified by AndData, and writes the result to the 16-bit PCI\r | |
643 | configuration register specified by Address. The value written to the PCI\r | |
644 | configuration register is returned. This function must guarantee that all PCI\r | |
645 | read and write operations are serialized. Extra left bits in both AndData and\r | |
646 | OrData are stripped.\r | |
647 | \r | |
648 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
649 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
650 | If StartBit is greater than 15, then ASSERT().\r | |
651 | If EndBit is greater than 15, then ASSERT().\r | |
652 | If EndBit is less than StartBit, then ASSERT().\r | |
653 | \r | |
654 | @param Address PCI configuration register to write.\r | |
655 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
656 | Range 0..15.\r | |
657 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
658 | Range 0..15.\r | |
659 | @param AndData The value to AND with the PCI configuration register.\r | |
660 | @param OrData The value to OR with the result of the AND operation.\r | |
661 | \r | |
662 | @return The value written back to the PCI configuration register.\r | |
663 | \r | |
664 | **/\r | |
665 | UINT16\r | |
666 | EFIAPI\r | |
667 | PciExpressBitFieldAndThenOr16 (\r | |
668 | IN UINTN Address,\r | |
669 | IN UINTN StartBit,\r | |
670 | IN UINTN EndBit,\r | |
671 | IN UINT16 AndData,\r | |
672 | IN UINT16 OrData\r | |
673 | );\r | |
674 | \r | |
675 | /**\r | |
676 | Reads a 32-bit PCI configuration register.\r | |
677 | \r | |
678 | Reads and returns the 32-bit PCI configuration register specified by Address.\r | |
679 | This function must guarantee that all PCI read and write operations are\r | |
680 | serialized.\r | |
681 | \r | |
682 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
683 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
684 | \r | |
685 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
686 | Register.\r | |
687 | \r | |
688 | @return The read value from the PCI configuration register.\r | |
689 | \r | |
690 | **/\r | |
691 | UINT32\r | |
692 | EFIAPI\r | |
693 | PciExpressRead32 (\r | |
694 | IN UINTN Address\r | |
695 | );\r | |
696 | \r | |
697 | /**\r | |
698 | Writes a 32-bit PCI configuration register.\r | |
699 | \r | |
700 | Writes the 32-bit PCI configuration register specified by Address with the\r | |
701 | value specified by Value. Value is returned. This function must guarantee\r | |
702 | that all PCI read and write operations are serialized.\r | |
703 | \r | |
704 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
705 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
706 | \r | |
707 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
708 | Register.\r | |
709 | @param Value The value to write.\r | |
710 | \r | |
711 | @return The value written to the PCI configuration register.\r | |
712 | \r | |
713 | **/\r | |
714 | UINT32\r | |
715 | EFIAPI\r | |
716 | PciExpressWrite32 (\r | |
717 | IN UINTN Address,\r | |
718 | IN UINT32 Value\r | |
719 | );\r | |
720 | \r | |
721 | /**\r | |
722 | Performs a bitwise OR of a 32-bit PCI configuration register with\r | |
723 | a 32-bit value.\r | |
724 | \r | |
725 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
726 | bitwise OR between the read result and the value specified by\r | |
727 | OrData, and writes the result to the 32-bit PCI configuration register\r | |
728 | specified by Address. The value written to the PCI configuration register is\r | |
729 | returned. This function must guarantee that all PCI read and write operations\r | |
730 | are serialized.\r | |
731 | \r | |
732 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
733 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
734 | \r | |
735 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
736 | Register.\r | |
737 | @param OrData The value to OR with the PCI configuration register.\r | |
738 | \r | |
739 | @return The value written back to the PCI configuration register.\r | |
740 | \r | |
741 | **/\r | |
742 | UINT32\r | |
743 | EFIAPI\r | |
744 | PciExpressOr32 (\r | |
745 | IN UINTN Address,\r | |
746 | IN UINT32 OrData\r | |
747 | );\r | |
748 | \r | |
749 | /**\r | |
750 | Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit\r | |
751 | value.\r | |
752 | \r | |
753 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
754 | bitwise AND between the read result and the value specified by AndData, and\r | |
755 | writes the result to the 32-bit PCI configuration register specified by\r | |
756 | Address. The value written to the PCI configuration register is returned.\r | |
757 | This function must guarantee that all PCI read and write operations are\r | |
758 | serialized.\r | |
759 | \r | |
760 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
761 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
762 | \r | |
763 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
764 | Register.\r | |
765 | @param AndData The value to AND with the PCI configuration register.\r | |
766 | \r | |
767 | @return The value written back to the PCI configuration register.\r | |
768 | \r | |
769 | **/\r | |
770 | UINT32\r | |
771 | EFIAPI\r | |
772 | PciExpressAnd32 (\r | |
773 | IN UINTN Address,\r | |
774 | IN UINT32 AndData\r | |
775 | );\r | |
776 | \r | |
777 | /**\r | |
778 | Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit\r | |
779 | value, followed a bitwise OR with another 32-bit value.\r | |
780 | \r | |
781 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
782 | bitwise AND between the read result and the value specified by AndData,\r | |
783 | performs a bitwise OR between the result of the AND operation and\r | |
784 | the value specified by OrData, and writes the result to the 32-bit PCI\r | |
785 | configuration register specified by Address. The value written to the PCI\r | |
786 | configuration register is returned. This function must guarantee that all PCI\r | |
787 | read and write operations are serialized.\r | |
788 | \r | |
789 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
790 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
791 | \r | |
792 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
793 | Register.\r | |
794 | @param AndData The value to AND with the PCI configuration register.\r | |
795 | @param OrData The value to OR with the result of the AND operation.\r | |
796 | \r | |
797 | @return The value written back to the PCI configuration register.\r | |
798 | \r | |
799 | **/\r | |
800 | UINT32\r | |
801 | EFIAPI\r | |
802 | PciExpressAndThenOr32 (\r | |
803 | IN UINTN Address,\r | |
804 | IN UINT32 AndData,\r | |
805 | IN UINT32 OrData\r | |
806 | );\r | |
807 | \r | |
808 | /**\r | |
809 | Reads a bit field of a PCI configuration register.\r | |
810 | \r | |
811 | Reads the bit field in a 32-bit PCI configuration register. The bit field is\r | |
812 | specified by the StartBit and the EndBit. The value of the bit field is\r | |
813 | returned.\r | |
814 | \r | |
815 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
816 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
817 | If StartBit is greater than 31, then ASSERT().\r | |
818 | If EndBit is greater than 31, then ASSERT().\r | |
819 | If EndBit is less than StartBit, then ASSERT().\r | |
820 | \r | |
821 | @param Address PCI configuration register to read.\r | |
822 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
823 | Range 0..31.\r | |
824 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
825 | Range 0..31.\r | |
826 | \r | |
827 | @return The value of the bit field read from the PCI configuration register.\r | |
828 | \r | |
829 | **/\r | |
830 | UINT32\r | |
831 | EFIAPI\r | |
832 | PciExpressBitFieldRead32 (\r | |
833 | IN UINTN Address,\r | |
834 | IN UINTN StartBit,\r | |
835 | IN UINTN EndBit\r | |
836 | );\r | |
837 | \r | |
838 | /**\r | |
839 | Writes a bit field to a PCI configuration register.\r | |
840 | \r | |
841 | Writes Value to the bit field of the PCI configuration register. The bit\r | |
842 | field is specified by the StartBit and the EndBit. All other bits in the\r | |
843 | destination PCI configuration register are preserved. The new value of the\r | |
844 | 32-bit register is returned.\r | |
845 | \r | |
846 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
847 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
848 | If StartBit is greater than 31, then ASSERT().\r | |
849 | If EndBit is greater than 31, then ASSERT().\r | |
850 | If EndBit is less than StartBit, then ASSERT().\r | |
851 | \r | |
852 | @param Address PCI configuration register to write.\r | |
853 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
854 | Range 0..31.\r | |
855 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
856 | Range 0..31.\r | |
857 | @param Value New value of the bit field.\r | |
858 | \r | |
859 | @return The value written back to the PCI configuration register.\r | |
860 | \r | |
861 | **/\r | |
862 | UINT32\r | |
863 | EFIAPI\r | |
864 | PciExpressBitFieldWrite32 (\r | |
865 | IN UINTN Address,\r | |
866 | IN UINTN StartBit,\r | |
867 | IN UINTN EndBit,\r | |
868 | IN UINT32 Value\r | |
869 | );\r | |
870 | \r | |
871 | /**\r | |
872 | Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and\r | |
873 | writes the result back to the bit field in the 32-bit port.\r | |
874 | \r | |
875 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
876 | bitwise OR between the read result and the value specified by\r | |
877 | OrData, and writes the result to the 32-bit PCI configuration register\r | |
878 | specified by Address. The value written to the PCI configuration register is\r | |
879 | returned. This function must guarantee that all PCI read and write operations\r | |
880 | are serialized. Extra left bits in OrData are stripped.\r | |
881 | \r | |
882 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
883 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
884 | If StartBit is greater than 31, then ASSERT().\r | |
885 | If EndBit is greater than 31, then ASSERT().\r | |
886 | If EndBit is less than StartBit, then ASSERT().\r | |
887 | \r | |
888 | @param Address PCI configuration register to write.\r | |
889 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
890 | Range 0..31.\r | |
891 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
892 | Range 0..31.\r | |
893 | @param OrData The value to OR with the PCI configuration register.\r | |
894 | \r | |
895 | @return The value written back to the PCI configuration register.\r | |
896 | \r | |
897 | **/\r | |
898 | UINT32\r | |
899 | EFIAPI\r | |
900 | PciExpressBitFieldOr32 (\r | |
901 | IN UINTN Address,\r | |
902 | IN UINTN StartBit,\r | |
903 | IN UINTN EndBit,\r | |
904 | IN UINT32 OrData\r | |
905 | );\r | |
906 | \r | |
907 | /**\r | |
908 | Reads a bit field in a 32-bit PCI configuration register, performs a bitwise\r | |
909 | AND, and writes the result back to the bit field in the 32-bit register.\r | |
910 | \r | |
911 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
912 | bitwise AND between the read result and the value specified by AndData, and\r | |
913 | writes the result to the 32-bit PCI configuration register specified by\r | |
914 | Address. The value written to the PCI configuration register is returned.\r | |
915 | This function must guarantee that all PCI read and write operations are\r | |
916 | serialized. Extra left bits in AndData are stripped.\r | |
917 | \r | |
918 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
919 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
920 | If StartBit is greater than 31, then ASSERT().\r | |
921 | If EndBit is greater than 31, then ASSERT().\r | |
922 | If EndBit is less than StartBit, then ASSERT().\r | |
923 | \r | |
924 | @param Address PCI configuration register to write.\r | |
925 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
926 | Range 0..31.\r | |
927 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
928 | Range 0..31.\r | |
929 | @param AndData The value to AND with the PCI configuration register.\r | |
930 | \r | |
931 | @return The value written back to the PCI configuration register.\r | |
932 | \r | |
933 | **/\r | |
934 | UINT32\r | |
935 | EFIAPI\r | |
936 | PciExpressBitFieldAnd32 (\r | |
937 | IN UINTN Address,\r | |
938 | IN UINTN StartBit,\r | |
939 | IN UINTN EndBit,\r | |
940 | IN UINT32 AndData\r | |
941 | );\r | |
942 | \r | |
943 | /**\r | |
944 | Reads a bit field in a 32-bit port, performs a bitwise AND followed by a\r | |
945 | bitwise OR, and writes the result back to the bit field in the\r | |
946 | 32-bit port.\r | |
947 | \r | |
948 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
949 | bitwise AND followed by a bitwise OR between the read result and\r | |
950 | the value specified by AndData, and writes the result to the 32-bit PCI\r | |
951 | configuration register specified by Address. The value written to the PCI\r | |
952 | configuration register is returned. This function must guarantee that all PCI\r | |
953 | read and write operations are serialized. Extra left bits in both AndData and\r | |
954 | OrData are stripped.\r | |
955 | \r | |
956 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
957 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
958 | If StartBit is greater than 31, then ASSERT().\r | |
959 | If EndBit is greater than 31, then ASSERT().\r | |
960 | If EndBit is less than StartBit, then ASSERT().\r | |
961 | \r | |
962 | @param Address PCI configuration register to write.\r | |
963 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
964 | Range 0..31.\r | |
965 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
966 | Range 0..31.\r | |
967 | @param AndData The value to AND with the PCI configuration register.\r | |
968 | @param OrData The value to OR with the result of the AND operation.\r | |
969 | \r | |
970 | @return The value written back to the PCI configuration register.\r | |
971 | \r | |
972 | **/\r | |
973 | UINT32\r | |
974 | EFIAPI\r | |
975 | PciExpressBitFieldAndThenOr32 (\r | |
976 | IN UINTN Address,\r | |
977 | IN UINTN StartBit,\r | |
978 | IN UINTN EndBit,\r | |
979 | IN UINT32 AndData,\r | |
980 | IN UINT32 OrData\r | |
981 | );\r | |
982 | \r | |
983 | /**\r | |
984 | Reads a range of PCI configuration registers into a caller supplied buffer.\r | |
985 | \r | |
986 | Reads the range of PCI configuration registers specified by StartAddress and\r | |
987 | Size into the buffer specified by Buffer. This function only allows the PCI\r | |
988 | configuration registers from a single PCI function to be read. Size is\r | |
989 | returned. When possible 32-bit PCI configuration read cycles are used to read\r | |
990 | from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit\r | |
991 | and 16-bit PCI configuration read cycles may be used at the beginning and the\r | |
992 | end of the range.\r | |
993 | \r | |
994 | If StartAddress > 0x0FFFFFFF, then ASSERT().\r | |
995 | If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r | |
996 | If Size > 0 and Buffer is NULL, then ASSERT().\r | |
997 | \r | |
998 | @param StartAddress Starting address that encodes the PCI Bus, Device,\r | |
999 | Function and Register.\r | |
1000 | @param Size Size in bytes of the transfer.\r | |
1001 | @param Buffer Pointer to a buffer receiving the data read.\r | |
1002 | \r | |
1003 | @return Size read data from StartAddress.\r | |
1004 | \r | |
1005 | **/\r | |
1006 | UINTN\r | |
1007 | EFIAPI\r | |
1008 | PciExpressReadBuffer (\r | |
1009 | IN UINTN StartAddress,\r | |
1010 | IN UINTN Size,\r | |
1011 | OUT VOID *Buffer\r | |
1012 | );\r | |
1013 | \r | |
1014 | /**\r | |
1015 | Copies the data in a caller supplied buffer to a specified range of PCI\r | |
1016 | configuration space.\r | |
1017 | \r | |
1018 | Writes the range of PCI configuration registers specified by StartAddress and\r | |
1019 | Size from the buffer specified by Buffer. This function only allows the PCI\r | |
1020 | configuration registers from a single PCI function to be written. Size is\r | |
1021 | returned. When possible 32-bit PCI configuration write cycles are used to\r | |
1022 | write from StartAdress to StartAddress + Size. Due to alignment restrictions,\r | |
1023 | 8-bit and 16-bit PCI configuration write cycles may be used at the beginning\r | |
1024 | and the end of the range.\r | |
1025 | \r | |
1026 | If StartAddress > 0x0FFFFFFF, then ASSERT().\r | |
1027 | If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r | |
1028 | If Size > 0 and Buffer is NULL, then ASSERT().\r | |
1029 | \r | |
1030 | @param StartAddress Starting address that encodes the PCI Bus, Device,\r | |
1031 | Function and Register.\r | |
1032 | @param Size Size in bytes of the transfer.\r | |
1033 | @param Buffer Pointer to a buffer containing the data to write.\r | |
1034 | \r | |
1035 | @return Size written to StartAddress.\r | |
1036 | \r | |
1037 | **/\r | |
1038 | UINTN\r | |
1039 | EFIAPI\r | |
1040 | PciExpressWriteBuffer (\r | |
1041 | IN UINTN StartAddress,\r | |
1042 | IN UINTN Size,\r | |
1043 | IN VOID *Buffer\r | |
1044 | );\r | |
1045 | \r | |
1046 | #endif\r |