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1 | ;------------------------------------------------------------------------------ \r | |
2 | ;\r | |
3 | ; EnableInterrupts() for ARM\r | |
4 | ;\r | |
5 | ; Copyright (c) 2006 - 2009, Intel Corporation<BR>\r | |
6 | ; Portions copyright (c) 2008-2009 Apple Inc. All rights reserved.<BR>\r | |
7 | ; All rights reserved. This program and the accompanying materials\r | |
8 | ; are licensed and made available under the terms and conditions of the BSD License\r | |
9 | ; which accompanies this distribution. The full text of the license may be found at\r | |
10 | ; http://opensource.org/licenses/bsd-license.php\r | |
11 | ;\r | |
12 | ; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
13 | ; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
14 | ;\r | |
15 | ;------------------------------------------------------------------------------\r | |
16 | \r | |
17 | EXPORT EnableInterrupts\r | |
18 | \r | |
19 | AREA Interrupt_enable, CODE, READONLY\r | |
20 | \r | |
21 | ;/**\r | |
22 | ; Enables CPU interrupts.\r | |
23 | ;\r | |
24 | ;**/\r | |
25 | ;VOID\r | |
26 | ;EFIAPI\r | |
27 | ;EnableInterrupts (\r | |
28 | ; VOID\r | |
29 | ; );\r | |
30 | ;\r | |
31 | EnableInterrupts\r | |
32 | MRS R0,CPSR\r | |
33 | BIC R0,R0,#0x80 ;Enable IRQ interrupts\r | |
34 | MSR CPSR_c,R0\r | |
35 | BX LR\r | |
36 | \r | |
37 | END\r |