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1 | /** @file\r | |
2 | Define the FIRST_SMI_HANDLER_CONTEXT structure, which is an exchange area\r | |
3 | between the SMM Monarch and the hot-added CPU, for relocating the SMBASE of\r | |
4 | the hot-added CPU.\r | |
5 | \r | |
6 | Copyright (c) 2020, Red Hat, Inc.\r | |
7 | \r | |
8 | SPDX-License-Identifier: BSD-2-Clause-Patent\r | |
9 | **/\r | |
10 | \r | |
11 | #ifndef FIRST_SMI_HANDLER_CONTEXT_H_\r | |
12 | #define FIRST_SMI_HANDLER_CONTEXT_H_\r | |
13 | \r | |
14 | //\r | |
15 | // The following structure is used to communicate between the SMM Monarch\r | |
16 | // (running the root MMI handler) and the hot-added CPU (handling its first\r | |
17 | // SMI). It is placed at SMM_DEFAULT_SMBASE, which is in SMRAM under QEMU's\r | |
18 | // "SMRAM at default SMBASE" feature.\r | |
19 | //\r | |
20 | #pragma pack (1)\r | |
21 | typedef struct {\r | |
22 | //\r | |
23 | // When ApicIdGate is MAX_UINT64, then no hot-added CPU may proceed with\r | |
24 | // SMBASE relocation.\r | |
25 | //\r | |
26 | // Otherwise, the hot-added CPU whose APIC ID equals ApicIdGate may proceed\r | |
27 | // with SMBASE relocation.\r | |
28 | //\r | |
29 | // This field is intentionally wider than APIC_ID (UINT32) because we need a\r | |
30 | // "gate locked" value that is different from all possible APIC_IDs.\r | |
31 | //\r | |
32 | UINT64 ApicIdGate;\r | |
33 | //\r | |
34 | // The new SMBASE value for the hot-added CPU to set in the SMRAM Save State\r | |
35 | // Map, before leaving SMM with the RSM instruction.\r | |
36 | //\r | |
37 | UINT32 NewSmbase;\r | |
38 | //\r | |
39 | // The hot-added CPU sets this field to 1 right before executing the RSM\r | |
40 | // instruction. This tells the SMM Monarch to proceed to polling the last\r | |
41 | // byte of the normal RAM reserved page (Post-SMM Pen).\r | |
42 | //\r | |
43 | UINT8 AboutToLeaveSmm;\r | |
44 | } FIRST_SMI_HANDLER_CONTEXT;\r | |
45 | #pragma pack ()\r | |
46 | \r | |
47 | #endif // FIRST_SMI_HANDLER_CONTEXT_H_\r |