| | 1 | /** @file\r |
| | 2 | Various register numbers and value bits based on the following publications:\r |
| | 3 | - Intel(R) datasheet 290549-001\r |
| | 4 | - Intel(R) datasheet 290562-001\r |
| | 5 | - Intel(R) datasheet 297654-006\r |
| | 6 | - Intel(R) datasheet 297738-017\r |
| | 7 | \r |
| | 8 | Copyright (C) 2015, Red Hat, Inc.\r |
| | 9 | Copyright (c) 2014, Gabriel L. Somlo <somlo@cmu.edu>\r |
| | 10 | \r |
| | 11 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
| | 12 | **/\r |
| | 13 | \r |
| | 14 | #ifndef __I440FX_PIIX4_H__\r |
| | 15 | #define __I440FX_PIIX4_H__\r |
| | 16 | \r |
| | 17 | #include <Library/PciLib.h>\r |
| | 18 | \r |
| | 19 | //\r |
| | 20 | // Host Bridge Device ID (DID) value for I440FX\r |
| | 21 | //\r |
| | 22 | #define INTEL_82441_DEVICE_ID 0x1237\r |
| | 23 | \r |
| | 24 | //\r |
| | 25 | // B/D/F/Type: 0/0/0/PCI\r |
| | 26 | //\r |
| | 27 | #define PMC_REGISTER_PIIX4(Offset) PCI_LIB_ADDRESS (0, 0, 0, (Offset))\r |
| | 28 | \r |
| | 29 | #define PIIX4_PAM0 0x59\r |
| | 30 | #define PIIX4_PAM1 0x5A\r |
| | 31 | #define PIIX4_PAM2 0x5B\r |
| | 32 | #define PIIX4_PAM3 0x5C\r |
| | 33 | #define PIIX4_PAM4 0x5D\r |
| | 34 | #define PIIX4_PAM5 0x5E\r |
| | 35 | #define PIIX4_PAM6 0x5F\r |
| | 36 | \r |
| | 37 | //\r |
| | 38 | // B/D/F/Type: 0/1/3/PCI\r |
| | 39 | //\r |
| | 40 | #define POWER_MGMT_REGISTER_PIIX4(Offset) PCI_LIB_ADDRESS (0, 1, 3, (Offset))\r |
| | 41 | \r |
| | 42 | #define PIIX4_PMBA 0x40\r |
| | 43 | #define PIIX4_PMBA_MASK (BIT15 | BIT14 | BIT13 | BIT12 | BIT11 | \\r |
| | 44 | BIT10 | BIT9 | BIT8 | BIT7 | BIT6)\r |
| | 45 | \r |
| | 46 | #define PIIX4_PMREGMISC 0x80\r |
| | 47 | #define PIIX4_PMREGMISC_PMIOSE BIT0\r |
| | 48 | \r |
| | 49 | //\r |
| | 50 | // IO ports\r |
| | 51 | //\r |
| | 52 | #define PIIX4_CPU_HOTPLUG_BASE 0xAF00\r |
| | 53 | \r |
| | 54 | #endif\r |
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