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1 | /** @file\r | |
2 | Provide constructor and GetTick for BaseRom instance of ACPI Timer Library\r | |
3 | \r | |
4 | Copyright (c) 2008 - 2012, Intel Corporation. All rights reserved.\r | |
5 | Copyright (c) 2011, Andrei Warkentin <andreiw@motorola.com>\r | |
6 | \r | |
7 | This program and the accompanying materials are licensed and made\r | |
8 | available under the terms and conditions of the BSD License which\r | |
9 | accompanies this distribution. The full text of the license may\r | |
10 | be found at http://opensource.org/licenses/bsd-license.php\r | |
11 | \r | |
12 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
13 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
14 | **/\r | |
15 | \r | |
16 | #include <Library/DebugLib.h>\r | |
17 | #include <Library/IoLib.h>\r | |
18 | #include <Library/PciLib.h>\r | |
19 | #include <OvmfPlatforms.h>\r | |
20 | \r | |
21 | /**\r | |
22 | The constructor function enables ACPI IO space.\r | |
23 | \r | |
24 | If ACPI I/O space not enabled, this function will enable it.\r | |
25 | It will always return RETURN_SUCCESS.\r | |
26 | \r | |
27 | @retval EFI_SUCCESS The constructor always returns RETURN_SUCCESS.\r | |
28 | \r | |
29 | **/\r | |
30 | RETURN_STATUS\r | |
31 | EFIAPI\r | |
32 | AcpiTimerLibConstructor (\r | |
33 | VOID\r | |
34 | )\r | |
35 | {\r | |
36 | UINT16 HostBridgeDevId;\r | |
37 | UINTN Pmba;\r | |
38 | UINT32 PmbaAndVal;\r | |
39 | UINT32 PmbaOrVal;\r | |
40 | UINTN AcpiCtlReg;\r | |
41 | UINT8 AcpiEnBit;\r | |
42 | \r | |
43 | //\r | |
44 | // Query Host Bridge DID to determine platform type\r | |
45 | //\r | |
46 | HostBridgeDevId = PciRead16 (OVMF_HOSTBRIDGE_DID);\r | |
47 | switch (HostBridgeDevId) {\r | |
48 | case INTEL_82441_DEVICE_ID:\r | |
49 | Pmba = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMBA);\r | |
50 | PmbaAndVal = ~(UINT32)PIIX4_PMBA_MASK;\r | |
51 | PmbaOrVal = PIIX4_PMBA_VALUE;\r | |
52 | AcpiCtlReg = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMREGMISC);\r | |
53 | AcpiEnBit = PIIX4_PMREGMISC_PMIOSE;\r | |
54 | break;\r | |
55 | case INTEL_Q35_MCH_DEVICE_ID:\r | |
56 | Pmba = POWER_MGMT_REGISTER_Q35 (ICH9_PMBASE);\r | |
57 | PmbaAndVal = ~(UINT32)ICH9_PMBASE_MASK;\r | |
58 | PmbaOrVal = ICH9_PMBASE_VALUE;\r | |
59 | AcpiCtlReg = POWER_MGMT_REGISTER_Q35 (ICH9_ACPI_CNTL);\r | |
60 | AcpiEnBit = ICH9_ACPI_CNTL_ACPI_EN;\r | |
61 | break;\r | |
62 | default:\r | |
63 | DEBUG ((EFI_D_ERROR, "%a: Unknown Host Bridge Device ID: 0x%04x\n",\r | |
64 | __FUNCTION__, HostBridgeDevId));\r | |
65 | ASSERT (FALSE);\r | |
66 | return RETURN_UNSUPPORTED;\r | |
67 | }\r | |
68 | \r | |
69 | //\r | |
70 | // Check to see if the Power Management Base Address is already enabled\r | |
71 | //\r | |
72 | if ((PciRead8 (AcpiCtlReg) & AcpiEnBit) == 0) {\r | |
73 | //\r | |
74 | // If the Power Management Base Address is not programmed,\r | |
75 | // then program it now.\r | |
76 | //\r | |
77 | PciAndThenOr32 (Pmba, PmbaAndVal, PmbaOrVal);\r | |
78 | \r | |
79 | //\r | |
80 | // Enable PMBA I/O port decodes\r | |
81 | //\r | |
82 | PciOr8 (AcpiCtlReg, AcpiEnBit);\r | |
83 | }\r | |
84 | \r | |
85 | return RETURN_SUCCESS;\r | |
86 | }\r | |
87 | \r | |
88 | /**\r | |
89 | Internal function to read the current tick counter of ACPI.\r | |
90 | \r | |
91 | Dynamically compute the address of the ACPI tick counter based on the\r | |
92 | properties of the underlying platform, to avoid relying on global variables.\r | |
93 | \r | |
94 | @return The tick counter read.\r | |
95 | \r | |
96 | **/\r | |
97 | UINT32\r | |
98 | InternalAcpiGetTimerTick (\r | |
99 | VOID\r | |
100 | )\r | |
101 | {\r | |
102 | UINT16 HostBridgeDevId;\r | |
103 | UINTN Pmba;\r | |
104 | \r | |
105 | //\r | |
106 | // Query Host Bridge DID to determine platform type\r | |
107 | //\r | |
108 | HostBridgeDevId = PciRead16 (OVMF_HOSTBRIDGE_DID);\r | |
109 | switch (HostBridgeDevId) {\r | |
110 | case INTEL_82441_DEVICE_ID:\r | |
111 | Pmba = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMBA);\r | |
112 | break;\r | |
113 | case INTEL_Q35_MCH_DEVICE_ID:\r | |
114 | Pmba = POWER_MGMT_REGISTER_Q35 (ICH9_PMBASE);\r | |
115 | break;\r | |
116 | default:\r | |
117 | DEBUG ((EFI_D_ERROR, "%a: Unknown Host Bridge Device ID: 0x%04x\n",\r | |
118 | __FUNCTION__, HostBridgeDevId));\r | |
119 | ASSERT (FALSE);\r | |
120 | return 0;\r | |
121 | }\r | |
122 | \r | |
123 | //\r | |
124 | // Read PMBA to read and return the current ACPI timer value.\r | |
125 | //\r | |
126 | return IoRead32 ((PciRead32 (Pmba) & ~PMBA_RTE) + ACPI_TIMER_OFFSET);\r | |
127 | }\r |