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1 | /**@file\r | |
2 | Initialize Secure Encrypted Virtualization (SEV) support\r | |
3 | \r | |
4 | Copyright (c) 2017 - 2020, Advanced Micro Devices. All rights reserved.<BR>\r | |
5 | \r | |
6 | SPDX-License-Identifier: BSD-2-Clause-Patent\r | |
7 | \r | |
8 | **/\r | |
9 | //\r | |
10 | // The package level header files this module uses\r | |
11 | //\r | |
12 | #include <IndustryStandard/Q35MchIch9.h>\r | |
13 | #include <Library/BaseMemoryLib.h>\r | |
14 | #include <Library/DebugLib.h>\r | |
15 | #include <Library/HobLib.h>\r | |
16 | #include <Library/MemEncryptSevLib.h>\r | |
17 | #include <Library/MemoryAllocationLib.h>\r | |
18 | #include <Library/PcdLib.h>\r | |
19 | #include <PiPei.h>\r | |
20 | #include <Register/Amd/Msr.h>\r | |
21 | #include <Register/Intel/SmramSaveStateMap.h>\r | |
22 | #include <Library/VmgExitLib.h>\r | |
23 | #include <ConfidentialComputingGuestAttr.h>\r | |
24 | \r | |
25 | #include "Platform.h"\r | |
26 | \r | |
27 | STATIC\r | |
28 | UINT64\r | |
29 | GetHypervisorFeature (\r | |
30 | VOID\r | |
31 | );\r | |
32 | \r | |
33 | /**\r | |
34 | Initialize SEV-SNP support if running as an SEV-SNP guest.\r | |
35 | \r | |
36 | **/\r | |
37 | STATIC\r | |
38 | VOID\r | |
39 | AmdSevSnpInitialize (\r | |
40 | VOID\r | |
41 | )\r | |
42 | {\r | |
43 | EFI_PEI_HOB_POINTERS Hob;\r | |
44 | EFI_HOB_RESOURCE_DESCRIPTOR *ResourceHob;\r | |
45 | UINT64 HvFeatures;\r | |
46 | EFI_STATUS PcdStatus;\r | |
47 | \r | |
48 | if (!MemEncryptSevSnpIsEnabled ()) {\r | |
49 | return;\r | |
50 | }\r | |
51 | \r | |
52 | //\r | |
53 | // Query the hypervisor feature using the VmgExit and set the value in the\r | |
54 | // hypervisor features PCD.\r | |
55 | //\r | |
56 | HvFeatures = GetHypervisorFeature ();\r | |
57 | PcdStatus = PcdSet64S (PcdGhcbHypervisorFeatures, HvFeatures);\r | |
58 | ASSERT_RETURN_ERROR (PcdStatus);\r | |
59 | \r | |
60 | //\r | |
61 | // Iterate through the system RAM and validate it.\r | |
62 | //\r | |
63 | for (Hob.Raw = GetHobList (); !END_OF_HOB_LIST (Hob); Hob.Raw = GET_NEXT_HOB (Hob)) {\r | |
64 | if ((Hob.Raw != NULL) && (GET_HOB_TYPE (Hob) == EFI_HOB_TYPE_RESOURCE_DESCRIPTOR)) {\r | |
65 | ResourceHob = Hob.ResourceDescriptor;\r | |
66 | \r | |
67 | if (ResourceHob->ResourceType == EFI_RESOURCE_SYSTEM_MEMORY) {\r | |
68 | MemEncryptSevSnpPreValidateSystemRam (\r | |
69 | ResourceHob->PhysicalStart,\r | |
70 | EFI_SIZE_TO_PAGES ((UINTN)ResourceHob->ResourceLength)\r | |
71 | );\r | |
72 | }\r | |
73 | }\r | |
74 | }\r | |
75 | }\r | |
76 | \r | |
77 | /**\r | |
78 | Handle an SEV-SNP/GHCB protocol check failure.\r | |
79 | \r | |
80 | Notify the hypervisor using the VMGEXIT instruction that the SEV-SNP guest\r | |
81 | wishes to be terminated.\r | |
82 | \r | |
83 | @param[in] ReasonCode Reason code to provide to the hypervisor for the\r | |
84 | termination request.\r | |
85 | \r | |
86 | **/\r | |
87 | STATIC\r | |
88 | VOID\r | |
89 | SevEsProtocolFailure (\r | |
90 | IN UINT8 ReasonCode\r | |
91 | )\r | |
92 | {\r | |
93 | MSR_SEV_ES_GHCB_REGISTER Msr;\r | |
94 | \r | |
95 | //\r | |
96 | // Use the GHCB MSR Protocol to request termination by the hypervisor\r | |
97 | //\r | |
98 | Msr.GhcbPhysicalAddress = 0;\r | |
99 | Msr.GhcbTerminate.Function = GHCB_INFO_TERMINATE_REQUEST;\r | |
100 | Msr.GhcbTerminate.ReasonCodeSet = GHCB_TERMINATE_GHCB;\r | |
101 | Msr.GhcbTerminate.ReasonCode = ReasonCode;\r | |
102 | AsmWriteMsr64 (MSR_SEV_ES_GHCB, Msr.GhcbPhysicalAddress);\r | |
103 | \r | |
104 | AsmVmgExit ();\r | |
105 | \r | |
106 | ASSERT (FALSE);\r | |
107 | CpuDeadLoop ();\r | |
108 | }\r | |
109 | \r | |
110 | /**\r | |
111 | Get the hypervisor features bitmap\r | |
112 | \r | |
113 | **/\r | |
114 | STATIC\r | |
115 | UINT64\r | |
116 | GetHypervisorFeature (\r | |
117 | VOID\r | |
118 | )\r | |
119 | {\r | |
120 | UINT64 Status;\r | |
121 | GHCB *Ghcb;\r | |
122 | MSR_SEV_ES_GHCB_REGISTER Msr;\r | |
123 | BOOLEAN InterruptState;\r | |
124 | UINT64 Features;\r | |
125 | \r | |
126 | Msr.GhcbPhysicalAddress = AsmReadMsr64 (MSR_SEV_ES_GHCB);\r | |
127 | Ghcb = Msr.Ghcb;\r | |
128 | \r | |
129 | //\r | |
130 | // Initialize the GHCB\r | |
131 | //\r | |
132 | VmgInit (Ghcb, &InterruptState);\r | |
133 | \r | |
134 | //\r | |
135 | // Query the Hypervisor Features.\r | |
136 | //\r | |
137 | Status = VmgExit (Ghcb, SVM_EXIT_HYPERVISOR_FEATURES, 0, 0);\r | |
138 | if ((Status != 0)) {\r | |
139 | SevEsProtocolFailure (GHCB_TERMINATE_GHCB_GENERAL);\r | |
140 | }\r | |
141 | \r | |
142 | Features = Ghcb->SaveArea.SwExitInfo2;\r | |
143 | \r | |
144 | VmgDone (Ghcb, InterruptState);\r | |
145 | \r | |
146 | return Features;\r | |
147 | }\r | |
148 | \r | |
149 | /**\r | |
150 | \r | |
151 | This function can be used to register the GHCB GPA.\r | |
152 | \r | |
153 | @param[in] Address The physical address to be registered.\r | |
154 | \r | |
155 | **/\r | |
156 | STATIC\r | |
157 | VOID\r | |
158 | GhcbRegister (\r | |
159 | IN EFI_PHYSICAL_ADDRESS Address\r | |
160 | )\r | |
161 | {\r | |
162 | MSR_SEV_ES_GHCB_REGISTER Msr;\r | |
163 | MSR_SEV_ES_GHCB_REGISTER CurrentMsr;\r | |
164 | \r | |
165 | //\r | |
166 | // Save the current MSR Value\r | |
167 | //\r | |
168 | CurrentMsr.GhcbPhysicalAddress = AsmReadMsr64 (MSR_SEV_ES_GHCB);\r | |
169 | \r | |
170 | //\r | |
171 | // Use the GHCB MSR Protocol to request to register the GPA.\r | |
172 | //\r | |
173 | Msr.GhcbPhysicalAddress = Address & ~EFI_PAGE_MASK;\r | |
174 | Msr.GhcbGpaRegister.Function = GHCB_INFO_GHCB_GPA_REGISTER_REQUEST;\r | |
175 | AsmWriteMsr64 (MSR_SEV_ES_GHCB, Msr.GhcbPhysicalAddress);\r | |
176 | \r | |
177 | AsmVmgExit ();\r | |
178 | \r | |
179 | Msr.GhcbPhysicalAddress = AsmReadMsr64 (MSR_SEV_ES_GHCB);\r | |
180 | \r | |
181 | //\r | |
182 | // If hypervisor responded with a different GPA than requested then fail.\r | |
183 | //\r | |
184 | if ((Msr.GhcbGpaRegister.Function != GHCB_INFO_GHCB_GPA_REGISTER_RESPONSE) ||\r | |
185 | ((Msr.GhcbPhysicalAddress & ~EFI_PAGE_MASK) != Address))\r | |
186 | {\r | |
187 | SevEsProtocolFailure (GHCB_TERMINATE_GHCB_GENERAL);\r | |
188 | }\r | |
189 | \r | |
190 | //\r | |
191 | // Restore the MSR\r | |
192 | //\r | |
193 | AsmWriteMsr64 (MSR_SEV_ES_GHCB, CurrentMsr.GhcbPhysicalAddress);\r | |
194 | }\r | |
195 | \r | |
196 | /**\r | |
197 | \r | |
198 | Initialize SEV-ES support if running as an SEV-ES guest.\r | |
199 | \r | |
200 | **/\r | |
201 | STATIC\r | |
202 | VOID\r | |
203 | AmdSevEsInitialize (\r | |
204 | VOID\r | |
205 | )\r | |
206 | {\r | |
207 | UINT8 *GhcbBase;\r | |
208 | PHYSICAL_ADDRESS GhcbBasePa;\r | |
209 | UINTN GhcbPageCount;\r | |
210 | UINT8 *GhcbBackupBase;\r | |
211 | UINT8 *GhcbBackupPages;\r | |
212 | UINTN GhcbBackupPageCount;\r | |
213 | SEV_ES_PER_CPU_DATA *SevEsData;\r | |
214 | UINTN PageCount;\r | |
215 | RETURN_STATUS PcdStatus, DecryptStatus;\r | |
216 | IA32_DESCRIPTOR Gdtr;\r | |
217 | VOID *Gdt;\r | |
218 | \r | |
219 | if (!MemEncryptSevEsIsEnabled ()) {\r | |
220 | return;\r | |
221 | }\r | |
222 | \r | |
223 | PcdStatus = PcdSetBoolS (PcdSevEsIsEnabled, TRUE);\r | |
224 | ASSERT_RETURN_ERROR (PcdStatus);\r | |
225 | \r | |
226 | //\r | |
227 | // Allocate GHCB and per-CPU variable pages.\r | |
228 | // Since the pages must survive across the UEFI to OS transition\r | |
229 | // make them reserved.\r | |
230 | //\r | |
231 | GhcbPageCount = mMaxCpuCount * 2;\r | |
232 | GhcbBase = AllocateReservedPages (GhcbPageCount);\r | |
233 | ASSERT (GhcbBase != NULL);\r | |
234 | \r | |
235 | GhcbBasePa = (PHYSICAL_ADDRESS)(UINTN)GhcbBase;\r | |
236 | \r | |
237 | //\r | |
238 | // Each vCPU gets two consecutive pages, the first is the GHCB and the\r | |
239 | // second is the per-CPU variable page. Loop through the allocation and\r | |
240 | // only clear the encryption mask for the GHCB pages.\r | |
241 | //\r | |
242 | for (PageCount = 0; PageCount < GhcbPageCount; PageCount += 2) {\r | |
243 | DecryptStatus = MemEncryptSevClearPageEncMask (\r | |
244 | 0,\r | |
245 | GhcbBasePa + EFI_PAGES_TO_SIZE (PageCount),\r | |
246 | 1\r | |
247 | );\r | |
248 | ASSERT_RETURN_ERROR (DecryptStatus);\r | |
249 | }\r | |
250 | \r | |
251 | ZeroMem (GhcbBase, EFI_PAGES_TO_SIZE (GhcbPageCount));\r | |
252 | \r | |
253 | PcdStatus = PcdSet64S (PcdGhcbBase, GhcbBasePa);\r | |
254 | ASSERT_RETURN_ERROR (PcdStatus);\r | |
255 | PcdStatus = PcdSet64S (PcdGhcbSize, EFI_PAGES_TO_SIZE (GhcbPageCount));\r | |
256 | ASSERT_RETURN_ERROR (PcdStatus);\r | |
257 | \r | |
258 | DEBUG ((\r | |
259 | DEBUG_INFO,\r | |
260 | "SEV-ES is enabled, %lu GHCB pages allocated starting at 0x%p\n",\r | |
261 | (UINT64)GhcbPageCount,\r | |
262 | GhcbBase\r | |
263 | ));\r | |
264 | \r | |
265 | //\r | |
266 | // Allocate #VC recursion backup pages. The number of backup pages needed is\r | |
267 | // one less than the maximum VC count.\r | |
268 | //\r | |
269 | GhcbBackupPageCount = mMaxCpuCount * (VMGEXIT_MAXIMUM_VC_COUNT - 1);\r | |
270 | GhcbBackupBase = AllocatePages (GhcbBackupPageCount);\r | |
271 | ASSERT (GhcbBackupBase != NULL);\r | |
272 | \r | |
273 | GhcbBackupPages = GhcbBackupBase;\r | |
274 | for (PageCount = 1; PageCount < GhcbPageCount; PageCount += 2) {\r | |
275 | SevEsData =\r | |
276 | (SEV_ES_PER_CPU_DATA *)(GhcbBase + EFI_PAGES_TO_SIZE (PageCount));\r | |
277 | SevEsData->GhcbBackupPages = GhcbBackupPages;\r | |
278 | \r | |
279 | GhcbBackupPages += EFI_PAGE_SIZE * (VMGEXIT_MAXIMUM_VC_COUNT - 1);\r | |
280 | }\r | |
281 | \r | |
282 | DEBUG ((\r | |
283 | DEBUG_INFO,\r | |
284 | "SEV-ES is enabled, %lu GHCB backup pages allocated starting at 0x%p\n",\r | |
285 | (UINT64)GhcbBackupPageCount,\r | |
286 | GhcbBackupBase\r | |
287 | ));\r | |
288 | \r | |
289 | //\r | |
290 | // SEV-SNP guest requires that GHCB GPA must be registered before using it.\r | |
291 | //\r | |
292 | if (MemEncryptSevSnpIsEnabled ()) {\r | |
293 | GhcbRegister (GhcbBasePa);\r | |
294 | }\r | |
295 | \r | |
296 | AsmWriteMsr64 (MSR_SEV_ES_GHCB, GhcbBasePa);\r | |
297 | \r | |
298 | //\r | |
299 | // The SEV support will clear the C-bit from non-RAM areas. The early GDT\r | |
300 | // lives in a non-RAM area, so when an exception occurs (like a #VC) the GDT\r | |
301 | // will be read as un-encrypted even though it was created before the C-bit\r | |
302 | // was cleared (encrypted). This will result in a failure to be able to\r | |
303 | // handle the exception.\r | |
304 | //\r | |
305 | AsmReadGdtr (&Gdtr);\r | |
306 | \r | |
307 | Gdt = AllocatePages (EFI_SIZE_TO_PAGES ((UINTN)Gdtr.Limit + 1));\r | |
308 | ASSERT (Gdt != NULL);\r | |
309 | \r | |
310 | CopyMem (Gdt, (VOID *)Gdtr.Base, Gdtr.Limit + 1);\r | |
311 | Gdtr.Base = (UINTN)Gdt;\r | |
312 | AsmWriteGdtr (&Gdtr);\r | |
313 | }\r | |
314 | \r | |
315 | /**\r | |
316 | \r | |
317 | Function checks if SEV support is available, if present then it sets\r | |
318 | the dynamic PcdPteMemoryEncryptionAddressOrMask with memory encryption mask.\r | |
319 | \r | |
320 | **/\r | |
321 | VOID\r | |
322 | AmdSevInitialize (\r | |
323 | VOID\r | |
324 | )\r | |
325 | {\r | |
326 | UINT64 EncryptionMask;\r | |
327 | RETURN_STATUS PcdStatus;\r | |
328 | \r | |
329 | //\r | |
330 | // Check if SEV is enabled\r | |
331 | //\r | |
332 | if (!MemEncryptSevIsEnabled ()) {\r | |
333 | return;\r | |
334 | }\r | |
335 | \r | |
336 | //\r | |
337 | // Check and perform SEV-SNP initialization if required. This need to be\r | |
338 | // done before the GHCB page is made shared in the AmdSevEsInitialize(). This\r | |
339 | // is because the system RAM must be validated before it is made shared.\r | |
340 | // The AmdSevSnpInitialize() validates the system RAM.\r | |
341 | //\r | |
342 | AmdSevSnpInitialize ();\r | |
343 | \r | |
344 | //\r | |
345 | // Set Memory Encryption Mask PCD\r | |
346 | //\r | |
347 | EncryptionMask = MemEncryptSevGetEncryptionMask ();\r | |
348 | PcdStatus = PcdSet64S (PcdPteMemoryEncryptionAddressOrMask, EncryptionMask);\r | |
349 | ASSERT_RETURN_ERROR (PcdStatus);\r | |
350 | \r | |
351 | DEBUG ((DEBUG_INFO, "SEV is enabled (mask 0x%lx)\n", EncryptionMask));\r | |
352 | \r | |
353 | //\r | |
354 | // Set Pcd to Deny the execution of option ROM when security\r | |
355 | // violation.\r | |
356 | //\r | |
357 | PcdStatus = PcdSet32S (PcdOptionRomImageVerificationPolicy, 0x4);\r | |
358 | ASSERT_RETURN_ERROR (PcdStatus);\r | |
359 | \r | |
360 | //\r | |
361 | // When SMM is required, cover the pages containing the initial SMRAM Save\r | |
362 | // State Map with a memory allocation HOB:\r | |
363 | //\r | |
364 | // There's going to be a time interval between our decrypting those pages for\r | |
365 | // SMBASE relocation and re-encrypting the same pages after SMBASE\r | |
366 | // relocation. We shall ensure that the DXE phase stay away from those pages\r | |
367 | // until after re-encryption, in order to prevent an information leak to the\r | |
368 | // hypervisor.\r | |
369 | //\r | |
370 | if (FeaturePcdGet (PcdSmmSmramRequire) && (mBootMode != BOOT_ON_S3_RESUME)) {\r | |
371 | RETURN_STATUS LocateMapStatus;\r | |
372 | UINTN MapPagesBase;\r | |
373 | UINTN MapPagesCount;\r | |
374 | \r | |
375 | LocateMapStatus = MemEncryptSevLocateInitialSmramSaveStateMapPages (\r | |
376 | &MapPagesBase,\r | |
377 | &MapPagesCount\r | |
378 | );\r | |
379 | ASSERT_RETURN_ERROR (LocateMapStatus);\r | |
380 | \r | |
381 | if (mQ35SmramAtDefaultSmbase) {\r | |
382 | //\r | |
383 | // The initial SMRAM Save State Map has been covered as part of a larger\r | |
384 | // reserved memory allocation in InitializeRamRegions().\r | |
385 | //\r | |
386 | ASSERT (SMM_DEFAULT_SMBASE <= MapPagesBase);\r | |
387 | ASSERT (\r | |
388 | (MapPagesBase + EFI_PAGES_TO_SIZE (MapPagesCount) <=\r | |
389 | SMM_DEFAULT_SMBASE + MCH_DEFAULT_SMBASE_SIZE)\r | |
390 | );\r | |
391 | } else {\r | |
392 | BuildMemoryAllocationHob (\r | |
393 | MapPagesBase, // BaseAddress\r | |
394 | EFI_PAGES_TO_SIZE (MapPagesCount), // Length\r | |
395 | EfiBootServicesData // MemoryType\r | |
396 | );\r | |
397 | }\r | |
398 | }\r | |
399 | \r | |
400 | //\r | |
401 | // Check and perform SEV-ES initialization if required.\r | |
402 | //\r | |
403 | AmdSevEsInitialize ();\r | |
404 | \r | |
405 | //\r | |
406 | // Set the Confidential computing attr PCD to communicate which SEV\r | |
407 | // technology is active.\r | |
408 | //\r | |
409 | if (MemEncryptSevSnpIsEnabled ()) {\r | |
410 | PcdStatus = PcdSet64S (PcdConfidentialComputingGuestAttr, CCAttrAmdSevSnp);\r | |
411 | } else if (MemEncryptSevEsIsEnabled ()) {\r | |
412 | PcdStatus = PcdSet64S (PcdConfidentialComputingGuestAttr, CCAttrAmdSevEs);\r | |
413 | } else {\r | |
414 | PcdStatus = PcdSet64S (PcdConfidentialComputingGuestAttr, CCAttrAmdSev);\r | |
415 | }\r | |
416 | \r | |
417 | ASSERT_RETURN_ERROR (PcdStatus);\r | |
418 | }\r | |
419 | \r | |
420 | /**\r | |
421 | The function performs SEV specific region initialization.\r | |
422 | \r | |
423 | **/\r | |
424 | VOID\r | |
425 | SevInitializeRam (\r | |
426 | VOID\r | |
427 | )\r | |
428 | {\r | |
429 | if (MemEncryptSevSnpIsEnabled ()) {\r | |
430 | //\r | |
431 | // If SEV-SNP is enabled, reserve the Secrets and CPUID memory area.\r | |
432 | //\r | |
433 | // This memory range is given to the PSP by the hypervisor to populate\r | |
434 | // the information used during the SNP VM boots, and it need to persist\r | |
435 | // across the kexec boots. Mark it as EfiReservedMemoryType so that\r | |
436 | // the guest firmware and OS does not use it as a system memory.\r | |
437 | //\r | |
438 | BuildMemoryAllocationHob (\r | |
439 | (EFI_PHYSICAL_ADDRESS)(UINTN)PcdGet32 (PcdOvmfSnpSecretsBase),\r | |
440 | (UINT64)(UINTN)PcdGet32 (PcdOvmfSnpSecretsSize),\r | |
441 | EfiReservedMemoryType\r | |
442 | );\r | |
443 | BuildMemoryAllocationHob (\r | |
444 | (EFI_PHYSICAL_ADDRESS)(UINTN)PcdGet32 (PcdOvmfCpuidBase),\r | |
445 | (UINT64)(UINTN)PcdGet32 (PcdOvmfCpuidSize),\r | |
446 | EfiReservedMemoryType\r | |
447 | );\r | |
448 | }\r | |
449 | }\r |