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1 | /**@file\r | |
2 | Platform PEI driver\r | |
3 | \r | |
4 | Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.<BR>\r | |
5 | Copyright (c) 2011, Andrei Warkentin <andreiw@motorola.com>\r | |
6 | \r | |
7 | This program and the accompanying materials\r | |
8 | are licensed and made available under the terms and conditions of the BSD License\r | |
9 | which accompanies this distribution. The full text of the license may be found at\r | |
10 | http://opensource.org/licenses/bsd-license.php\r | |
11 | \r | |
12 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
13 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
14 | \r | |
15 | **/\r | |
16 | \r | |
17 | //\r | |
18 | // The package level header files this module uses\r | |
19 | //\r | |
20 | #include <PiPei.h>\r | |
21 | \r | |
22 | //\r | |
23 | // The Library classes this module consumes\r | |
24 | //\r | |
25 | #include <Library/DebugLib.h>\r | |
26 | #include <Library/HobLib.h>\r | |
27 | #include <Library/IoLib.h>\r | |
28 | #include <Library/MemoryAllocationLib.h>\r | |
29 | #include <Library/PcdLib.h>\r | |
30 | #include <Library/PciLib.h>\r | |
31 | #include <Library/PeimEntryPoint.h>\r | |
32 | #include <Library/PeiServicesLib.h>\r | |
33 | #include <Library/ResourcePublicationLib.h>\r | |
34 | #include <Guid/MemoryTypeInformation.h>\r | |
35 | #include <Ppi/MasterBootMode.h>\r | |
36 | #include <IndustryStandard/Pci22.h>\r | |
37 | \r | |
38 | #include "Platform.h"\r | |
39 | #include "Cmos.h"\r | |
40 | \r | |
41 | EFI_MEMORY_TYPE_INFORMATION mDefaultMemoryTypeInformation[] = {\r | |
42 | { EfiACPIMemoryNVS, 0x004 },\r | |
43 | { EfiACPIReclaimMemory, 0x008 },\r | |
44 | { EfiReservedMemoryType, 0x004 },\r | |
45 | { EfiRuntimeServicesData, 0x024 },\r | |
46 | { EfiRuntimeServicesCode, 0x030 },\r | |
47 | { EfiBootServicesCode, 0x180 },\r | |
48 | { EfiBootServicesData, 0xF00 },\r | |
49 | { EfiMaxMemoryType, 0x000 }\r | |
50 | };\r | |
51 | \r | |
52 | \r | |
53 | EFI_PEI_PPI_DESCRIPTOR mPpiBootMode[] = {\r | |
54 | {\r | |
55 | EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,\r | |
56 | &gEfiPeiMasterBootModePpiGuid,\r | |
57 | NULL\r | |
58 | }\r | |
59 | };\r | |
60 | \r | |
61 | \r | |
62 | VOID\r | |
63 | AddIoMemoryBaseSizeHob (\r | |
64 | EFI_PHYSICAL_ADDRESS MemoryBase,\r | |
65 | UINT64 MemorySize\r | |
66 | )\r | |
67 | {\r | |
68 | BuildResourceDescriptorHob (\r | |
69 | EFI_RESOURCE_MEMORY_MAPPED_IO,\r | |
70 | EFI_RESOURCE_ATTRIBUTE_PRESENT |\r | |
71 | EFI_RESOURCE_ATTRIBUTE_INITIALIZED |\r | |
72 | EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |\r | |
73 | EFI_RESOURCE_ATTRIBUTE_TESTED,\r | |
74 | MemoryBase,\r | |
75 | MemorySize\r | |
76 | );\r | |
77 | }\r | |
78 | \r | |
79 | VOID\r | |
80 | AddReservedMemoryBaseSizeHob (\r | |
81 | EFI_PHYSICAL_ADDRESS MemoryBase,\r | |
82 | UINT64 MemorySize\r | |
83 | )\r | |
84 | {\r | |
85 | BuildResourceDescriptorHob (\r | |
86 | EFI_RESOURCE_MEMORY_RESERVED,\r | |
87 | EFI_RESOURCE_ATTRIBUTE_PRESENT |\r | |
88 | EFI_RESOURCE_ATTRIBUTE_INITIALIZED |\r | |
89 | EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |\r | |
90 | EFI_RESOURCE_ATTRIBUTE_TESTED,\r | |
91 | MemoryBase,\r | |
92 | MemorySize\r | |
93 | );\r | |
94 | }\r | |
95 | \r | |
96 | VOID\r | |
97 | AddIoMemoryRangeHob (\r | |
98 | EFI_PHYSICAL_ADDRESS MemoryBase,\r | |
99 | EFI_PHYSICAL_ADDRESS MemoryLimit\r | |
100 | )\r | |
101 | {\r | |
102 | AddIoMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));\r | |
103 | }\r | |
104 | \r | |
105 | \r | |
106 | VOID\r | |
107 | AddMemoryBaseSizeHob (\r | |
108 | EFI_PHYSICAL_ADDRESS MemoryBase,\r | |
109 | UINT64 MemorySize\r | |
110 | )\r | |
111 | {\r | |
112 | BuildResourceDescriptorHob (\r | |
113 | EFI_RESOURCE_SYSTEM_MEMORY,\r | |
114 | EFI_RESOURCE_ATTRIBUTE_PRESENT |\r | |
115 | EFI_RESOURCE_ATTRIBUTE_INITIALIZED |\r | |
116 | EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |\r | |
117 | EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |\r | |
118 | EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |\r | |
119 | EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |\r | |
120 | EFI_RESOURCE_ATTRIBUTE_TESTED,\r | |
121 | MemoryBase,\r | |
122 | MemorySize\r | |
123 | );\r | |
124 | }\r | |
125 | \r | |
126 | \r | |
127 | VOID\r | |
128 | AddMemoryRangeHob (\r | |
129 | EFI_PHYSICAL_ADDRESS MemoryBase,\r | |
130 | EFI_PHYSICAL_ADDRESS MemoryLimit\r | |
131 | )\r | |
132 | {\r | |
133 | AddMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));\r | |
134 | }\r | |
135 | \r | |
136 | \r | |
137 | VOID\r | |
138 | AddUntestedMemoryBaseSizeHob (\r | |
139 | EFI_PHYSICAL_ADDRESS MemoryBase,\r | |
140 | UINT64 MemorySize\r | |
141 | )\r | |
142 | {\r | |
143 | BuildResourceDescriptorHob (\r | |
144 | EFI_RESOURCE_SYSTEM_MEMORY,\r | |
145 | EFI_RESOURCE_ATTRIBUTE_PRESENT |\r | |
146 | EFI_RESOURCE_ATTRIBUTE_INITIALIZED |\r | |
147 | EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |\r | |
148 | EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |\r | |
149 | EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |\r | |
150 | EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE,\r | |
151 | MemoryBase,\r | |
152 | MemorySize\r | |
153 | );\r | |
154 | }\r | |
155 | \r | |
156 | \r | |
157 | VOID\r | |
158 | AddUntestedMemoryRangeHob (\r | |
159 | EFI_PHYSICAL_ADDRESS MemoryBase,\r | |
160 | EFI_PHYSICAL_ADDRESS MemoryLimit\r | |
161 | )\r | |
162 | {\r | |
163 | AddUntestedMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));\r | |
164 | }\r | |
165 | \r | |
166 | \r | |
167 | VOID\r | |
168 | MemMapInitialization (\r | |
169 | EFI_PHYSICAL_ADDRESS TopOfMemory\r | |
170 | )\r | |
171 | {\r | |
172 | //\r | |
173 | // Create Memory Type Information HOB\r | |
174 | //\r | |
175 | BuildGuidDataHob (\r | |
176 | &gEfiMemoryTypeInformationGuid,\r | |
177 | mDefaultMemoryTypeInformation,\r | |
178 | sizeof(mDefaultMemoryTypeInformation)\r | |
179 | );\r | |
180 | \r | |
181 | //\r | |
182 | // Add PCI IO Port space available for PCI resource allocations.\r | |
183 | //\r | |
184 | BuildResourceDescriptorHob (\r | |
185 | EFI_RESOURCE_IO,\r | |
186 | EFI_RESOURCE_ATTRIBUTE_PRESENT |\r | |
187 | EFI_RESOURCE_ATTRIBUTE_INITIALIZED,\r | |
188 | 0xC000,\r | |
189 | 0x4000\r | |
190 | );\r | |
191 | \r | |
192 | //\r | |
193 | // Video memory + Legacy BIOS region\r | |
194 | //\r | |
195 | AddIoMemoryRangeHob (0x0A0000, BASE_1MB);\r | |
196 | \r | |
197 | //\r | |
198 | // address purpose size\r | |
199 | // ------------ -------- -------------------------\r | |
200 | // max(top, 2g) PCI MMIO 0xFC000000 - max(top, 2g)\r | |
201 | // 0xFC000000 gap 44 MB\r | |
202 | // 0xFEC00000 IO-APIC 4 KB\r | |
203 | // 0xFEC01000 gap 1020 KB\r | |
204 | // 0xFED00000 HPET 1 KB\r | |
205 | // 0xFED00400 gap 1023 KB\r | |
206 | // 0xFEE00000 LAPIC 1 MB\r | |
207 | //\r | |
208 | AddIoMemoryRangeHob (TopOfMemory < BASE_2GB ? BASE_2GB : TopOfMemory, 0xFC000000);\r | |
209 | AddIoMemoryBaseSizeHob (0xFEC00000, SIZE_4KB);\r | |
210 | AddIoMemoryBaseSizeHob (0xFED00000, SIZE_1KB);\r | |
211 | AddIoMemoryBaseSizeHob (PcdGet32(PcdCpuLocalApicBaseAddress), SIZE_1MB);\r | |
212 | }\r | |
213 | \r | |
214 | \r | |
215 | VOID\r | |
216 | MiscInitialization (\r | |
217 | VOID\r | |
218 | )\r | |
219 | {\r | |
220 | //\r | |
221 | // Disable A20 Mask\r | |
222 | //\r | |
223 | IoOr8 (0x92, BIT1);\r | |
224 | \r | |
225 | //\r | |
226 | // Build the CPU hob with 36-bit addressing and 16-bits of IO space.\r | |
227 | //\r | |
228 | BuildCpuHob (36, 16);\r | |
229 | \r | |
230 | //\r | |
231 | // If PMREGMISC/PMIOSE is set, assume the ACPI PMBA has been configured (for\r | |
232 | // example by Xen) and skip the setup here. This matches the logic in\r | |
233 | // AcpiTimerLibConstructor ().\r | |
234 | //\r | |
235 | if ((PciRead8 (PCI_LIB_ADDRESS (0, 1, 3, 0x80)) & 0x01) == 0) {\r | |
236 | //\r | |
237 | // The PEI phase should be exited with fully accessibe PIIX4 IO space:\r | |
238 | // 1. set PMBA\r | |
239 | //\r | |
240 | PciAndThenOr32 (\r | |
241 | PCI_LIB_ADDRESS (0, 1, 3, 0x40),\r | |
242 | (UINT32) ~0xFFC0,\r | |
243 | PcdGet16 (PcdAcpiPmBaseAddress)\r | |
244 | );\r | |
245 | \r | |
246 | //\r | |
247 | // 2. set PCICMD/IOSE\r | |
248 | //\r | |
249 | PciOr8 (\r | |
250 | PCI_LIB_ADDRESS (0, 1, 3, PCI_COMMAND_OFFSET),\r | |
251 | EFI_PCI_COMMAND_IO_SPACE\r | |
252 | );\r | |
253 | \r | |
254 | //\r | |
255 | // 3. set PMREGMISC/PMIOSE\r | |
256 | //\r | |
257 | PciOr8 (PCI_LIB_ADDRESS (0, 1, 3, 0x80), 0x01);\r | |
258 | }\r | |
259 | }\r | |
260 | \r | |
261 | \r | |
262 | VOID\r | |
263 | BootModeInitialization (\r | |
264 | )\r | |
265 | {\r | |
266 | EFI_STATUS Status;\r | |
267 | \r | |
268 | Status = PeiServicesSetBootMode (BOOT_WITH_FULL_CONFIGURATION);\r | |
269 | ASSERT_EFI_ERROR (Status);\r | |
270 | \r | |
271 | Status = PeiServicesInstallPpi (mPpiBootMode);\r | |
272 | ASSERT_EFI_ERROR (Status);\r | |
273 | }\r | |
274 | \r | |
275 | \r | |
276 | VOID\r | |
277 | ReserveEmuVariableNvStore (\r | |
278 | )\r | |
279 | {\r | |
280 | EFI_PHYSICAL_ADDRESS VariableStore;\r | |
281 | \r | |
282 | //\r | |
283 | // Allocate storage for NV variables early on so it will be\r | |
284 | // at a consistent address. Since VM memory is preserved\r | |
285 | // across reboots, this allows the NV variable storage to survive\r | |
286 | // a VM reboot.\r | |
287 | //\r | |
288 | VariableStore =\r | |
289 | (EFI_PHYSICAL_ADDRESS)(UINTN)\r | |
290 | AllocateAlignedRuntimePages (\r | |
291 | EFI_SIZE_TO_PAGES (2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize)),\r | |
292 | PcdGet32 (PcdFlashNvStorageFtwSpareSize)\r | |
293 | );\r | |
294 | DEBUG ((EFI_D_INFO,\r | |
295 | "Reserved variable store memory: 0x%lX; size: %dkb\n",\r | |
296 | VariableStore,\r | |
297 | (2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize)) / 1024\r | |
298 | ));\r | |
299 | PcdSet64 (PcdEmuVariableNvStoreReserved, VariableStore);\r | |
300 | }\r | |
301 | \r | |
302 | \r | |
303 | VOID\r | |
304 | DebugDumpCmos (\r | |
305 | VOID\r | |
306 | )\r | |
307 | {\r | |
308 | UINTN Loop;\r | |
309 | \r | |
310 | DEBUG ((EFI_D_INFO, "CMOS:\n"));\r | |
311 | \r | |
312 | for (Loop = 0; Loop < 0x80; Loop++) {\r | |
313 | if ((Loop % 0x10) == 0) {\r | |
314 | DEBUG ((EFI_D_INFO, "%02x:", Loop));\r | |
315 | }\r | |
316 | DEBUG ((EFI_D_INFO, " %02x", CmosRead8 (Loop)));\r | |
317 | if ((Loop % 0x10) == 0xf) {\r | |
318 | DEBUG ((EFI_D_INFO, "\n"));\r | |
319 | }\r | |
320 | }\r | |
321 | }\r | |
322 | \r | |
323 | \r | |
324 | /**\r | |
325 | Perform Platform PEI initialization.\r | |
326 | \r | |
327 | @param FileHandle Handle of the file being invoked.\r | |
328 | @param PeiServices Describes the list of possible PEI Services.\r | |
329 | \r | |
330 | @return EFI_SUCCESS The PEIM initialized successfully.\r | |
331 | \r | |
332 | **/\r | |
333 | EFI_STATUS\r | |
334 | EFIAPI\r | |
335 | InitializePlatform (\r | |
336 | IN EFI_PEI_FILE_HANDLE FileHandle,\r | |
337 | IN CONST EFI_PEI_SERVICES **PeiServices\r | |
338 | )\r | |
339 | {\r | |
340 | EFI_PHYSICAL_ADDRESS TopOfMemory;\r | |
341 | \r | |
342 | DEBUG ((EFI_D_ERROR, "Platform PEIM Loaded\n"));\r | |
343 | \r | |
344 | DebugDumpCmos ();\r | |
345 | \r | |
346 | TopOfMemory = MemDetect ();\r | |
347 | \r | |
348 | InitializeXen ();\r | |
349 | \r | |
350 | ReserveEmuVariableNvStore ();\r | |
351 | \r | |
352 | PeiFvInitialization ();\r | |
353 | \r | |
354 | MemMapInitialization (TopOfMemory);\r | |
355 | \r | |
356 | MiscInitialization ();\r | |
357 | \r | |
358 | BootModeInitialization ();\r | |
359 | \r | |
360 | return EFI_SUCCESS;\r | |
361 | }\r |